Method for improving fatigue life of lead-free welding spot of vehicle-mounted CIS chip under warm impulse load

Abstract

The invention discloses a method for improving fatigue life of a lead-free welding spot of a vehicle-mounted CIS (Contact Image Sensor) chip under a temperature impact load, which comprises the following steps of: 1, simulating a current system design parameter, and determining the fatigue life of the welding spot in an original design scheme under the temperature impact load as a reference value for optimizing a verification result; 2, welding spot morphology structure parameters are optimized, and an optimization result is verified through simulation; 3, corresponding parameters are designed according to the optimization result of the welding spot morphology structure; 4, improving thermal attribute parameters of the PCB, and simulating and verifying an optimization result; 5, optimizing a locking structure of the PCBA board of the system, and simulating and verifying an optimization result; and step 6, preparing an optimization scheme sample, and performing actual measurement verification.

Description

Technical Field

[0001] The present invention belongs to the field of improvement and optimization of the fatigue life of lead-free solder joints under temperature shock loads, relates to the field of chip packaging reliability, and particularly relates to a method for improving the fatigue life of lead-free solder joints of vehicle-mounted CIS chips under temperature shock loads. Background Art

[0002] Electronic products are continuously evolving towards miniaturization, integration, and multifunctionality. The electronic packaging within them is also advancing towards higher density and miniaturization. Reliability is crucial for these products, and premature failure can severely impact the user experience. In the automotive sector, failure of critical automotive electronics can threaten the safety of people and property. Automotive electronics operate in extremely harsh environments, with typical operating temperatures ranging from -40°C to 85°C. They are also subject to external loads such as humidity, dust, vibration, and shock. Research shows that over 60% of automotive electronics failures occur at the solder joints of electronic component packages, and most are fatigue failures. Further analysis of the failure causes reveals that over half are attributable to temperature. To meet the fatigue life reliability requirements for package solder joints, current automotive chips often use underfill, but this significantly increases production costs.

[0003] Therefore, there is a need for a method and process that can improve the fatigue life of lead-free solder joints of automotive CIS chips under thermal shock loads. According to this optimization method, the fatigue life of solder joints can be greatly improved based on the original design scheme, and the optimization cost can be reduced. This method improves the fatigue life of solder joints from multiple aspects, including solder joint morphology and structure, PCB board material properties, and PCBA board system locking structure, comprehensively improving the fatigue life of solder joints. Currently, there is no systematic solution that can improve the fatigue life of lead-free solder joints of automotive CIS chips under thermal shock loads from multiple dimensions.

[0004] An existing method for predicting the thermal fatigue life of laminated solder joints based on a convolutional neural network (Guilin University of Electronic Technology. A method for predicting the thermal fatigue life of laminated solder joints based on a convolutional neural network: CN202410919711.2[P].2024-10-15.) provides a method for predicting the thermal fatigue life of laminated solder joints based on a convolutional neural network. This method analyzes the different morphological factors that affect the thermal fatigue life of laminated solder joints, establishes a test group of Cartesian product combinations for simulation, evaluates the fatigue life of dangerous solder joints, and finally establishes a mapping relationship between the morphological factors of laminated solder joints and the thermal cycle life of laminated solder joints to predict the thermal fatigue life of laminated solder joints with different morphologies. This method predicts the thermal fatigue life of solder joints with different morphologies, focusing on the prediction method of solder joint thermal fatigue life, but does not study the optimization method of solder joint thermal fatigue life. Summary of the Invention

[0005] In view of the current lack of optimization solutions for the fatigue life of lead-free solder joints on automotive chips, and to at least optimize the current results to a certain extent, the purpose of the present invention is to provide a method and process for improving the fatigue life of lead-free solder joints on automotive CIS chips under thermal shock loads. The current system design parameters are simulated to determine the fatigue life of the solder joints in the original design under thermal shock loads as a reference value for the optimization verification results; the solder joint morphology and structural parameters are optimized and the optimization results are verified through simulation; the corresponding parameters are designed based on the optimization results of the solder joint morphology and structure; the thermal property parameters of the PCB board are improved and the optimization results are verified through simulation; the locking structure of the system PCBA board is optimized and the optimization results are verified through simulation; and the optimization solution samples are prepared and verified by actual measurement. The fatigue life of the solder joints is improved by three aspects: the solder joint morphology and structure, the PCB board properties, and the system locking and fixing structure.

[0006] The present invention is achieved through at least one of the following technical solutions.

[0007] The method for improving the fatigue life of lead-free solder joints of an on-board CIS chip under thermal shock load comprises the following steps:

[0008] Step 1: Perform solder joint fatigue life simulation on the current single-board system consisting of an on-board CIS chip, lead-free solder joints, and a PCB board. Use the fatigue life prediction model to determine the fatigue life of the solder joints under temperature shock loads under the current design parameters, and use this fatigue life as a reference value for the optimization verification result.

[0009] Step 2: Optimize the topographical and structural parameters of the solder joints and verify the optimization results through simulation;

[0010] Step 3: According to the optimization results of the solder joint morphology structure, the corresponding manufacturing parameters are set so that the final solder joint structure is similar to the optimization results in step 2;

[0011] Step 4: Adjust the thermal property parameters of the PCB board and verify the optimization results through simulation;

[0012] Step 5: Optimize the locking structure of the system PCBA board and verify the optimization results through simulation;

[0013] Step 6: Prepare samples of the optimized solution and conduct actual measurement verification.

[0014] Furthermore, in step 1, the current design parameters include the structural dimensions, material parameters, and bolt locking structure of each component; the structural dimensions of each component include the structural dimensions of the PCB board, the structural dimensions of the chip, and the structural dimensions of the solder joint; the material parameters include density, Young's modulus, Poisson's ratio, thermal expansion coefficient, specific heat capacity, and thermal conductivity; the bolt locking structure includes the number of bolts and the bolt locking position.

[0015] Furthermore, in step 1, in the process of establishing the solder joint fatigue life simulation prediction model, in order to obtain a more accurate solder joint fatigue life, the structural dimension model of the solder joint needs to measure the solder joint structural parameters of the actual sample. The measurement can be carried out by three-dimensional scanning or slicing to measure the three-dimensional structural parameters of the solder joint.

[0016] Furthermore, in step 1, since the lead-free solder joints will exhibit viscoplastic material characteristics under temperature shock loads, the Anand viscoplastic constitutive model needs to be added to describe the material properties of the lead-free solder joints.

[0017] Furthermore, the temperature shock load in step 1 refers to the temperature load to which the single board system is subjected in the temperature shock test chamber; and the fatigue life refers to the accelerated fatigue life under the temperature load in the temperature shock test chamber.

[0018] Furthermore, the fatigue life prediction model is a Darveaux model. Based on the Darveaux model, the fatigue life results of the solder joints can be obtained using COMSOL multi-physics field simulation software.

[0019] Furthermore, in step 2, the optimized solder joint morphology and structural parameters include the upper diameter of the solder joint at the contact surface between the solder joint and the chip, the lower diameter of the solder joint at the contact surface between the solder joint and the PCB board, the maximum diameter of the solder joint, and the height of the solder joint;

[0020] Based on the solder joint morphology structure in step 1, single-factor and multi-factor analysis is performed on the solder joint morphology structure size to obtain the optimal morphology structure parameters, and the optimization results are verified by simulation comparison of the solder joint fatigue life before and after optimization.

[0021] Furthermore, in step 3, the manufacturing parameters include the size of the PCB end pad and the steel mesh parameters in the SMT process corresponding to the pad.

[0022] Furthermore, in step 4, the thermal property parameters of different PCB materials are compared, and a PCB material with a high glass transition temperature and a low thermal expansion coefficient is selected to reduce the thermal mismatch between the PCB and the chip.

[0023] Furthermore, in step 5, the locking structure of the system PCBA board is optimized by exploring the effects of different bolt locking positions and numbers on the fatigue life of the solder joints through simulation, and obtaining a locking structure scheme with a long solder joint fatigue life, thereby reducing the influence of the mechanical stress generated by the bolt locking structure on the fatigue life of the solder joints.

[0024] Compared with the existing technology, the beneficial effects of the present invention are:

[0025] This invention gradually improves solder joint fatigue life through multi-dimensional optimization, focusing on three aspects: solder joint topography and structure, PCB substrate material properties, and the system's mounting and fixing methods. This optimization also considers cost, minimizing costs while ensuring solder joint fatigue life. This solution can be used not only for automotive CIS chips but also for other chip types. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention.

[0027] Figure 1 This is a flow chart of a method for improving fatigue life of lead-free solder joints of automotive chips under temperature shock loads according to an embodiment of the present invention;

[0028] Figure 2 1 is a simulation model of the original design scheme and a schematic diagram of the simulation results of lead-free solder joints in an embodiment of the present invention;

[0029] Figure 3 1 is a schematic cross-sectional view of the solder joint structure of a CIS chip in a CSP package in an embodiment of the present invention;

[0030] Figure 4 is a cross-sectional view of a solder joint of a manufactured sample optimized for solder joints in an embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of simulation results after solder joint optimization in an embodiment of the present invention;

[0032] Figure 6 2 is a schematic diagram of simulation results after further optimizing the thermal expansion coefficient of the PCB substrate in an embodiment of the present invention;

[0033] Figure 7 1. It is a schematic diagram comparing the optimized locking scheme and the original locking scheme in an embodiment of the present invention and comparing simulation results;

[0034] Figure 8 3 is a schematic diagram of the simulation results of the fatigue life of the solder joint after the final comprehensive optimization in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0036] In the description of the present invention, it should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. The terms "first", "second", etc. in the specification and claims and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Descriptions of orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0037] In the description of the present invention, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0038] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0039] The method of improving the fatigue life of lead-free solder joints of an on-board CIS chip under warm shock loads of the present application is further described below with reference to specific embodiments and drawings.

[0040] like Figure 1 As shown, the method of improving the fatigue life of lead-free solder joints of an on-board CIS chip under a thermal shock load in this embodiment includes the following steps:

[0041] Step 1: Perform solder joint fatigue life simulation on the current single-board system consisting of an on-board CIS chip, lead-free solder joints, and a PCB board. Use a fatigue life prediction model to determine the fatigue life of the solder joints under temperature shock loads under current design parameters, and use this fatigue life as a reference value for the optimization verification result. The temperature shock load refers to the temperature load to which the single-board system is subjected in a temperature shock test chamber. The fatigue life refers to the accelerated fatigue life under the action of the temperature load in the temperature shock test chamber.

[0042] The fatigue life prediction model is the Darveaux model. Based on the Darveaux model, the fatigue life results of the solder joints can be obtained using COMSOL multi-physics simulation software. In the process of establishing the solder joint fatigue life simulation prediction model, in order to obtain a more accurate solder joint fatigue life, the structural dimension model of the solder joint needs to measure the solder joint structural parameters of the actual sample. The measurement can be performed by three-dimensional scanning or slicing to measure the three-dimensional structural parameters of the solder joint. Because lead-free solder joints will exhibit viscoplastic material characteristics under temperature shock loads, in addition to density, Young's modulus, Poisson's ratio, thermal expansion coefficient, specific heat capacity, and thermal conductivity, the material properties of the solder joints also need to be described by adding the Anand viscoplastic constitutive model.

[0043] The current design parameters include the structural dimensions, material parameters, and bolt locking structure of each component; the structural dimensions of each component include the structural dimensions of the PCB board, the structural dimensions of the chip, and the structural dimensions of the solder joints; the material parameters include density, Young's modulus, Poisson's ratio, thermal expansion coefficient, specific heat capacity, and thermal conductivity; the bolt locking structure includes the number of bolts and the bolt locking position.

[0044] Step 2: Optimize the topographical and structural parameters of the solder joints and verify the optimization results through simulation;

[0045] According to the current system structure (based on the solder joint morphology structure in step 1), single-factor and multi-factor analysis is performed on the solder joint morphology structure size to obtain the optimal morphology structure parameters, and the optimization results are verified by simulation comparison of the solder joint fatigue life before and after optimization.

[0046] Step 3: Based on the optimization results of the solder joint morphology structure, design corresponding manufacturing parameters so that the final solder joint structure is similar to the optimization result in step 2; as an embodiment, the manufacturing parameters include the PCB end pad size and the steel mesh parameters in the SMT process corresponding to the pad.

[0047] Step 4: Adjust the thermal properties of the PCB and verify the optimization results through simulation. The thermal properties of the PCB are designed to improve the thermal expansion coefficient of the PCB and reduce the thermal mismatch between the PCB and the chip. Specifically, the PCB material's glass transition temperature and thermal expansion coefficient are comprehensively considered. A PCB material with a high glass transition temperature and a low thermal expansion coefficient is selected to improve the thermal expansion coefficient and reduce the thermal mismatch between the PCB and the chip.

[0048] Step 5: Optimize the locking structure of the system PCBA board and verify the optimization results through simulation;

[0049] The locking structure of the optimized system PCBA board is to explore the influence of different bolt locking positions and locking numbers on the fatigue life of the solder joints through simulation, and obtain a locking structure scheme with higher solder joint fatigue life, which reduces the influence of mechanical stress generated by the bolt locking structure on the fatigue life of the solder joints, aiming to reduce the influence of external mechanical stress on the fatigue life of the solder joints.

[0050] Step 6: Prepare samples of the optimized solution and conduct actual measurement verification.

[0051] As a specific embodiment, the method of this embodiment for improving the fatigue life of lead-free solder joints of an on-board CIS chip under a warm shock load includes the following steps:

[0052] Step 1: Simulate the current system to obtain the fatigue life of lead-free solder joints under current parameters and determine the simplified simulation model such as Figure 2 As shown in (a), the thermal expansion coefficient (CTE) of the PCB is 18ppm / K, and the final solder joint fatigue life simulation result is 224 times. Figure 2 (b) shown.

[0053] Step 2: Optimize the morphology of the solder joint. The cross-sectional diagram of the solder joint is as follows: Figure 3 As shown, this CIS chip is a CSP packaged chip, and PCB pad 2 is a non-solder mask defined pad (NSMD) structure. The upper diameter of solder joint 1 is D1, the maximum diameter of the solder joint is D2, and the height of the solder joint is H. The dimensions below the solder joint are determined by the pad: the upper diameter of the pad is L1, the thickness of the pad is h, and the lower diameter of the pad is L2. Single-factor and multi-factor orthogonal experiments were conducted to determine the optimal solder joint structure for this object.

[0054] Step 3: To create an optimized solder joint structure, the PCB end pad size and the corresponding steel mesh size are designed. After preparing the sample, the cross-sectional dimensions of the solder joint are measured. The morphological structure slices of the solder joints before and after optimization are shown as follows: Figure 4 After further measuring its parameters, the model is remodeled and the simulation results are shown in (a) and (b). Figure 5 shown.

[0055] Step 4: Optimize the PCB board parameters based on the price and thermal property parameters of the PCB board, and select a substrate with a thermal expansion coefficient closer to that of the CIS chip base material. After optimization, take the PCB CTE = 12ppm / K. The optimization simulation results are as follows: Figure 6 shown.

[0056] Step 5: Optimize the locking and fixing method of the PCBA board. The locking methods before and after optimization are as follows: Figure 7As shown in (a) and (b), the bolt locking method used before optimization is two bolts at the diagonal corners of the PCB, and the bolt locking method used after optimization is four bolts at the four corners of the PCB. The optimized four-bolt locking method can balance the external mechanical stress, reduce the impact of external stress on the solder joints, and significantly increase the fatigue life of the solder joints. The final optimized simulation results are shown in Figure 1. Figure 8 shown.

[0057] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A method for improving the fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads, characterized in that: The following steps are involved: Step 1: Perform solder joint fatigue life simulation on the current single-board system consisting of an on-board CIS chip, lead-free solder joints, and a PCB board. Use the fatigue life prediction model to determine the fatigue life of the solder joints under temperature shock loads under the current design parameters, and use this fatigue life as a reference value for the optimization verification result. Step 2: Optimize the topographical and structural parameters of the solder joints and verify the optimization results through simulation; Step 3: According to the optimization results of the solder joint morphology structure, the corresponding manufacturing parameters are set so that the final solder joint structure is similar to the optimization results in step 2; Step 4: Adjust the thermal property parameters of the PCB board and verify the optimization results through simulation; Step 5: Optimize the locking structure of the system PCBA board and verify the optimization results through simulation; Step 6: Prepare samples of the optimized solution and conduct actual measurement verification.

2. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 1, characterized in that: In step 1, the current design parameters include the structural dimensions, material parameters, and bolt locking structure of each component; the structural dimensions of each component include the structural dimensions of the PCB board, the structural dimensions of the chip, and the structural dimensions of the solder joints; the material parameters include density, Young's modulus, Poisson's ratio, thermal expansion coefficient, specific heat capacity, and thermal conductivity; and the bolt locking structure includes the number of bolts and the bolt locking position.

3. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 2, characterized in that: In step 1, in the process of establishing the solder joint fatigue life simulation prediction model, in order to obtain a more accurate solder joint fatigue life, the structural dimension model of the solder joint needs to measure the solder joint structural parameters of the actual sample. The measurement can be carried out by three-dimensional scanning or slicing to measure the three-dimensional structural parameters of the solder joint.

4. The method for improving fatigue life of lead-free solder joints of an on-board CIS chip under thermal shock load according to claim 2, wherein: In step 1, since lead-free solder joints exhibit viscoplastic material characteristics under temperature shock loads, the Anand viscoplastic constitutive model needs to be added to describe the material properties of lead-free solder joints.

5. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 2, characterized in that: The temperature shock load mentioned in step 1 refers to the temperature load to which the single board system is subjected in the temperature shock test chamber; the fatigue life refers to the accelerated fatigue life under the temperature load in the temperature shock test chamber.

6. The method for improving fatigue life of lead-free solder joints of an on-board CIS chip under thermal shock loads according to claim 2, wherein: The fatigue life prediction model is the Darveaux model. Based on the Darveaux model, the fatigue life results of the solder joints can be obtained using COMSOL multi-physics field simulation software.

7. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 1, characterized in that: In step 2, the optimized solder joint morphology and structural parameters include the upper diameter of the solder joint where the solder joint contacts the chip, the lower diameter of the solder joint where the solder joint contacts the PCB, the maximum diameter of the solder joint, and the height of the solder joint. Based on the solder joint morphology structure in step 1, single-factor and multi-factor analysis is performed on the solder joint morphology structure size to obtain the optimal morphology structure parameters, and the optimization results are verified by simulation comparison of the solder joint fatigue life before and after optimization.

8. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 1, characterized in that: In step 3, the manufacturing parameters include the size of the PCB end pad and the steel mesh parameters in the SMT process corresponding to the pad.

9. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 1, characterized in that: In step 4, the thermal properties of different PCB materials are compared, and a PCB material with a high glass transition temperature and a low thermal expansion coefficient is selected to reduce the thermal mismatch between the PCB and the chip.

10. The method for improving fatigue life of lead-free solder joints of vehicle-mounted CIS chips under thermal shock loads according to claim 1, characterized in that: In step 5, the locking structure of the system PCBA board is optimized by exploring the effects of different bolt locking positions and numbers on the fatigue life of the solder joints through simulation, and obtaining a locking structure scheme with a long solder joint fatigue life, thereby reducing the impact of mechanical stress generated by the bolt locking structure on the fatigue life of the solder joints.

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