All-digital closed-loop simulation verification system based on MicroBlaze soft core Bayer image processing FPGA

Abstract

The invention relates to the technical field of FPGA (Field Programmable Gate Array) simulation verification, in particular to an all-digital closed-loop simulation verification system based on a MicroBlaze soft core Bayer image processing FPGA, which comprises an image data generation module for processing an original image to obtain a test image data set; the simulated detector module is used for receiving configuration parameters configured by the FPGA and sending time sequence signal flow data obtained by converting the test image data set to the FPGA; the imitation storage chip module responds to a storage control signal of the FPGA, receives address data and write-in data and returns read-out data; the MicroBlaze soft core simulation module drives an FPGA (Field Programmable Gate Array) to process the time sequence signal flow data to obtain a simulation image; the image processing module processes the test image data set to generate first result data; the simulation data downloading module receives and processes the simulation image to obtain second result data; the result comparison module compares the second result data with the first result data. By means of the MicroBlaze soft core simulation module, a specific hardware platform does not need to be built, and the dynamic interaction function and the operation performance of the soft core and the FPGA are effectively verified.

Description

Technical Field

[0001] The present invention relates to the field of FPGA simulation verification technology, and in particular to a full-digital closed-loop simulation verification system, equipment and storage medium based on a MicroBlaze soft-core Bayer image processing FPGA. Background Art

[0002] The MicroBlaze soft-core FPGA implements a system that integrates hardware and software logic on an FPGA. The FPGA portion primarily includes peripheral sensors, communication and storage interface units, and signal processing units. The soft-core portion includes algorithm programs and an operating system. The required functions are implemented through the hardware logic within the FPGA and the software code within the MicroBlaze processor. The MicroBlaze soft-core Bayer image processing FPGA implements interface modules such as detectors, memory chips, serial port instructions, and data downlinks through the FPGA, while the soft-core portion implements functions such as the Bayer image processing algorithm. This system features a tight integration of hardware and software logic, and its testing and verification methods differ from traditional software testing and standard FPGA verification.

[0003] Currently, simulation verification of MicroBlaze soft-core Bayer image processing FPGAs is still primarily based on physical hardware testing or simulation of individual modules. Physical hardware testing is costly and difficult to detect and locate faults. Simulation of individual modules also makes it difficult to effectively verify the entire system. Furthermore, for complex image processing algorithms, existing technologies still suffer from problems such as limited test image data, insufficient accuracy, low efficiency, and insufficient reliability.

[0004] Therefore, the present invention proposes a fully digital closed-loop simulation and verification system based on a MicroBlaze soft-core Bayer image processing FPGA. By establishing a MicroBlaze soft-core simulation module and an FPGA external interface module, this system effectively verifies the dynamic interaction and operational performance between the soft-core and FPGA, eliminating the need for a dedicated hardware platform. Furthermore, it facilitates the configuration of abnormal operating conditions and simplifies fault location. Furthermore, it can generate targeted test image datasets, improving verification accuracy, efficiency, and reliability. Summary of the Invention

[0005] The purpose of the present invention is to solve the shortcomings of the prior art and provide a full digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA, including an image data generation module, a simulated detector module, a simulated storage chip module, a MicroBlaze soft-core simulation module, an image processing module, a simulated clock reset module, a simulated serial port instruction module, a simulated data download module 8 and a result comparison module; The image data generation module is used to perform processing including image cropping, noise addition, compression, sorting, and shifting on the original image to obtain a test image dataset, and output the test image dataset to the simulated detection module; The simulated detector module simulates the detector chip, is used to receive the SPI configuration parameters, clock configuration parameters and power supply configuration parameters configured by the FPGA, and sends the detector clock, temperature data and the timing signal stream data converted from the test image data set to the FPGA; The imitation memory chip module is used to respond to the storage control signal of the FPGA, receive address data and write data, and return read data; The MicroBlaze soft core simulation module loads the Bayer image processing firmware, drives the FPGA to process the timing signal stream data to obtain a simulation image, and sends it to the simulation data download module 8; The image processing module is used to process the test image data set to generate first result data; The simulated clock reset module is used to simulate the crystal oscillator and reset circuit to provide an adjustable clock signal and a reset signal for the FPGA; The simulated serial port instruction module is used to simulate the serial port timing, send serial port remote control instructions and receive serial port telemetry data; The simulation data download module 8 receives and processes the simulation image to obtain second result data, and synchronously transmits the second result data to the result comparison module; The result comparison module is used to compare the second result data with the first result data to verify the correctness of the FPGA processing function.

[0006] Preferably, the image data generating module includes: An image cropping unit, configured to set cropping parameters including the coordinates of the image's starting point, and the image's height and width, and to crop the original image according to the cropping parameters; The noise injection unit supports the generation of noise test patterns by superimposing at least one noise type, including Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, exponential noise, and uniform noise; Bayer compression unit, converts the noise test pattern into a Bayer image in RGGB, GRBG, BGGR, or GBRG format according to the Bayer compression type The data reconstruction unit obtains the test image data set according to the settings including the sorting mode and the shifting mode of the Bayer image.

[0007] Preferably, the simulated detector module includes: A multi-channel asynchronous transmission unit reads the test image data set into the stack of the simulated detector module, generates a frame address signal, a row address signal, and a column address signal under a corresponding timing according to the received FPGA drive signal and the clock configuration parameters, and transmits the test image data set in the stack to the FPGA in a multi-channel manner according to the generated frame address signal, row address signal, and column address signal in the memory of the simulated detector module. At the same time, a delay parameter for each channel output is set to simulate an abnormal situation in which the image data output is not synchronized; The SPI configuration interface unit is used to receive configuration data including X coordinates, Y coordinates, image size, exposure time, gain parameters, and detector mode sent by the FPGA, select information including the coordinate position of the detector image, image size, detector exposure time, and detector channel mode according to the configuration data, and the SPI interface sets the real-time temperature parameters of the detector according to the set temperature requirements and sends the set real-time temperature data to the FPGA; The timing monitoring unit is used to monitor whether the interface timing meets the timing parameter requirements of the chip manual.

[0008] Preferably, the imitation memory chip module includes: A read / write operation unit for realizing reading and writing of image data in a manner including word-by-word and page-by-page; an erase unit for performing operations including block erase or sector erase; The address parsing unit is used to send an enable signal and address data according to the FPGA, and jump to the corresponding storage operation function after making a judgment based on the address data, so as to store the intermediate data and result data of the image processing.

[0009] Preferably, the MicroBlaze soft core simulation module includes: A binary file loading and simulation operation unit is used to load the image processing module, compile the Bayer image program code into an ELF file executable by the Microblaze soft core, and simulate the soft core's instruction fetch, decoding, execution and write-back processes to achieve simulation operation; A dynamic interaction unit is used to receive the timing signal stream data transmitted by the FPGA logic part through the AXI4 bus interface during the simulation process, and send the processed data results to the DMA controller of the FPGA logic. The DMA controller transmits the processed results to the simulation data download module 8. When the FPGA logic completes data writing, the data ready interrupt of the soft core is triggered, and when the soft core processing is completed, the data read interrupt of the FPGA logic is triggered; A fault injection unit, which simulates faults including a soft core abnormal interrupt fault and a soft core running memory space insufficient fault by modifying the ELF file or dynamically adjusting simulation environment parameters; Time performance analysis unit, which records the timestamps of key events during the soft core operation, including interrupt response delay, algorithm processing cycle and bus transmission time; Generate a performance report based on timestamp data, and count the worst-case execution time (WCET), interrupt delay jitter, and bus utilization indicators to evaluate whether the software core timeliness meets the design requirements.

[0010] Preferably, the image processing module includes: Performing image denoising on the test image data set using a median filter or a mean filter algorithm; Generate RGB image according to Bayer image decompression algorithm; The RGB image is restored to obtain the first result data, and the first result data is sent to the result comparison module.

[0011] Preferably, the serial port emulation instruction module includes: First, according to the serial communication protocol, the information including the frame header, command word, data word, and check code is framed, and then the start bit, check bit, and stop bit are added byte by byte. The framed data is sent to the FPGA through the serial-to-parallel conversion function according to the serial protocol at a preset transmission rate. At the same time, abnormal conditions including frame header error, command code error, check code error, start bit loss, stop bit loss, check bit loss, communication interruption, and baud rate deviation are simulated; The serial port telemetry data returned by the FPGA is received at a preset transmission rate, and a telemetry data frame is obtained after determining the start bit, check bit and stop bit.

[0012] Preferably, the result comparison module includes: Converting the second result data and the first result data into the same pixel matrix format; Calculate PSNR, SSIM indicators and pixel difference maps; Mark error areas and generate visual comparison reports.

[0013] Based on the same concept, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes a module of a fully digital closed-loop simulation verification system based on a MicroBlaze soft-core Bayer image processing FPGA as described in any one of the embodiments.

[0014] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the module of the full-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA as described in any of the embodiments.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a fully digital verification platform through an image data generation module, a detector simulation module, a storage chip simulation module, a MicroBlaze soft-core simulation module, an image processing module, a clock reset simulation module, a serial port instruction simulation module, a data download simulation module, and a result comparison module. Without the need to build a specific hardware platform, the platform can effectively verify the correctness and stability of the FPGA under different working conditions, greatly reducing the cost of simulation verification. The present invention verifies the correctness of the soft-core and FPGA interaction function through the simulation results of the MicroBlaze soft-core simulation module, and verifies the correctness of the FPGA's image acquisition and processing function in the hardware joint test. At the same time, the abnormal working condition setting is convenient, and the simulation waveforms of all signals can be observed in real time, making fault location relatively easy. The present invention can perform parameterized simulation of test image data sets and verification of image processing algorithms through the image data generation module and image processing module. At the same time, the serial port instruction simulation module and the storage chip simulation module can realize simulation verification of the correctness of functions such as remote control instruction injection, telemetry data reception and storage chip reading and writing. The present invention can generate a test image data set in a targeted manner through an image data generation module, thereby improving the accuracy, efficiency and reliability of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those skilled in the art by reading the following detailed description of the preferred embodiment.The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the invention.

[0017] Figure 1 This is a structural diagram of the fully digital closed-loop simulation verification system based on the MicroBlaze soft-core Bayer image processing FPGA of the present invention; Figure 2 This is a flow chart of the fully digital closed-loop simulation verification method based on the MicroBlaze soft-core Bayer image processing FPGA of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Obviously, the embodiments described are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0019] Those skilled in the art will understand that, unless otherwise specified, the singular forms "a," "an," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] First embodiment See also Figure 1 As shown, the fully digital closed-loop simulation verification system based on the MicroBlaze soft-core Bayer image processing FPGA provided in this embodiment is used to provide a closed-loop real-time simulation working environment for the FPGA. The system can realize interactive simulation of the soft-core and the FPGA, and at the same time verify abnormal working conditions that cannot be realized in the ground hardware joint test, and provide pixel-level error analysis for the FPGA image processing algorithm part. It includes an image data generation module 1, a detector simulation module 2, a storage chip simulation module 3, a MicroBlaze soft-core simulation module 4, an image processing module 5, a clock reset simulation module 6, a serial port instruction simulation module 7, a data download simulation module 8 and a result comparison module 9. Specifically, in this embodiment, the system is written in System Verilog code to provide a closed-loop working environment for the FPGA. The image data generation module 1 is used to process the original image including image cropping, noise addition, compression, sorting, and shifting to obtain a test image dataset, and output the test image dataset to the imitation detection module and the image processing module 5; The imitation detector module 2 simulates the detector chip, is used to receive the SPI configuration parameters, clock configuration parameters and power supply configuration parameters configured by the FPGA, and sends the detector clock, temperature data and the timing signal flow data converted from the test image data set to the FPGA; The imitation memory chip module 3 is used to respond to the storage control signal of the FPGA, receive address data and write data, and return read data; The MicroBlaze soft-core simulation module 4 loads the Bayer image processing firmware, drives the FPGA to process the timing signal stream data to obtain a simulated image, and sends it to the simulated data download module 8 to realize the simulation operation of the soft-core and the code on it. Specifically, in this embodiment, it is used to load the Bayer image algorithm binary file converted by the image processing module 5 to realize the dynamic interactive operation between the soft-core and the FPGA; Image processing module 5, used to process the test image data set, generate first result data, and realize dynamic interactive operation between the soft core and the FPGA; The simulated clock reset module 6 is used to simulate the crystal oscillator and reset circuit to provide an adjustable clock signal and reset signal for the FPGA. Specifically, in this embodiment, the simulated crystal oscillator provides a stable clock signal for the MicroBlaze soft core simulation module 4 and sets the clock frequency of the clock signal as required. The simulated reset circuit provides a reset signal for the MicroBlaze soft core simulation module 4 and sets whether the reset signal is a high-level reset or a low-level reset as required. At the same time, an abnormal test of the glitch signal is performed; The serial port instruction simulation module 7 is used to simulate the serial port timing, send serial port remote control instructions and receive serial port telemetry data; The simulation data download module 8 receives and processes the simulation image to obtain the second result data, and synchronously transmits it to the result comparison module 9. Specifically, in this embodiment, the simulation image downloaded by the FPGA is received, and the data signal is correctly analyzed and received; The result comparison module 9 is used to compare the second result data with the first result data, so as to verify the correctness of the MicroBlaze soft-core Bayer image processing FPGA function.

[0021] Preferably, the image data generating module 1 includes: The image cropping unit is used to set cropping parameters including the image starting point coordinates, image height and width, and to crop the original image according to the cropping parameters; The noise injection unit supports the generation of noise test patterns by superimposing at least one noise type, including Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, exponential noise, and uniform noise; Bayer compression unit, which converts the noise test pattern into Bayer image in RGGB, GRBG, BGGR, GBRG format according to the Bayer compression type The data reconstruction unit obtains a test image data set according to the settings including the sorting mode and the shifting mode of the Bayer image. Specifically, in this embodiment, the order of rows and columns of the image is rearranged according to the requirements and converted into hexadecimal and then shifted.

[0022] Preferably, the imitation detector module 2 includes: The multi-channel asynchronous transmission unit reads the test image data set into the stack of the simulated detector module 2, and generates a frame address signal, a row address signal, and a column address signal under the corresponding timing according to the received FPGA drive signal and clock configuration parameters. The image data in the memory of the simulated detector module 2 is sequentially sent to the FPGA in multiple channels according to the generated frame address signal, row address signal, and column address signal. At the same time, the delay parameters of each channel output are set to simulate the abnormal situation of asynchronous image data output; The SPI configuration interface unit is used to receive configuration data sent by the FPGA, including X-coordinates, Y-coordinates, image size, exposure time, gain parameters, and detector mode. It selects information about the detector image, including coordinate position, image size, detector exposure time, and detector channel mode, based on the configuration data. The SPI interface also sets the real-time temperature parameters of the detector based on the set temperature requirements and sends the set real-time temperature data to the FPGA. The timing monitoring unit is used to monitor whether the interface timing meets the timing parameter requirements of the chip manual.

[0023] Preferably, the imitation memory chip module 3 includes: A read / write operation unit for realizing reading and writing of image data in a manner including word-by-word and page-by-page; an erase unit for performing operations including block erase or sector erase; The address parsing unit is used to send an enable signal and address data according to the FPGA, and jump to the corresponding storage operation function after making a judgment based on the address data, so as to store the intermediate data and result data of the image processing.

[0024] Preferably, the MicroBlaze soft core simulation module 4 includes: The binary file loading and simulation operation unit is used to load the image processing module 5 to compile the Bayer image program code into an ELF file executable by the Microblaze soft core, and simulate the soft core's instruction fetch, decoding, execution and write-back process to achieve simulation operation; The dynamic interaction unit is used to receive the timing signal stream data transmitted by the FPGA logic part through the AXI4 bus interface during the simulation process, and send the processed data results to the DMA controller of the FPGA logic. The DMA controller transmits the processed results to the simulation data download module 8. When the FPGA logic completes data writing, the data ready interrupt of the soft core is triggered. When the soft core processing is completed, the data read interrupt of the FPGA logic is triggered. The fault injection unit simulates faults including soft core abnormal interrupt faults and insufficient soft core running memory space faults by modifying ELF files or dynamically adjusting simulation environment parameters; Time performance analysis unit, which records the timestamps of key events during the soft core operation, including interrupt response delay, algorithm processing cycle and bus transmission time; Generate a performance report based on timestamp data, and count the worst-case execution time (WCET), interrupt delay jitter, and bus utilization indicators to evaluate whether the software core timeliness meets the design requirements.

[0025] Preferably, the image processing module 5 includes: Perform image denoising on the test image dataset using median filtering or mean filtering algorithm; Generate RGB image according to Bayer image decompression algorithm; The RGB image is restored to obtain first result data, and the first result data is sent to the result comparison module 9.

[0026] Preferably, the imitation serial port instruction module 7 includes: First, the information including the frame header, command word, data word, and check code is framed according to the serial communication protocol. Then, the start bit, check bit, and stop bit are added byte by byte. The framed data is sent to the FPGA through the serial-to-parallel conversion function at the preset transmission rate according to the serial protocol. At the same time, abnormal conditions including frame header error, command code error, check code error, start bit loss, stop bit loss, check bit loss, communication interruption, and baud rate deviation are simulated. The serial port telemetry data returned by the FPGA is received at a preset transmission rate, and the telemetry data frame is obtained after determining the start bit, check bit, and stop bit.

[0027] Preferably, the result comparison module 9 includes: Converting the second result data and the first result data into the same pixel matrix format; Calculate PSNR, SSIM indicators and pixel difference maps; Mark error areas and generate visual comparison reports.

[0028] Second embodiment See also Figure 2 As shown, this embodiment provides a full digital closed-loop simulation verification method based on a MicroBlaze soft-core Bayer image processing FPGA, which is used to execute the system in the first embodiment, including the following steps: Step 1: Construct the image data generation module 1, the simulated detector module 2, the simulated storage chip module 3, the MicroBlaze soft core simulation module 4, the image processing module 5, the simulated clock reset module 6, the simulated serial port instruction module 7, the simulated data download module 8 and the result comparison module 9.

[0029] Step 2: Convert the image processing algorithm in the image processing module 5 into a binary file that can be recognized by the MicroBlaze soft core, and load and run the binary file through the soft core.

[0030] Step 3: In the simulated clock reset module 6, according to the actual working clock frequency and reset requirements of the FPGA, set the clock signal and reset signal to 100 MHz and a low level with a delay greater than 1 us, respectively.

[0031] Step 4: The image data generation module 1 generates a Bayer test image that meets the required size (1024*1024 pix). Then, according to the simulation verification requirements, the parameters including noise type, Bayer compression type, sorting method, and shifting method are set to generate test images including Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, exponential noise, and uniform noise. Then, compressed images including RGGB, GRBG, BGGR, and GBRG are generated. Then, the image row and column order is rearranged according to the requirements and converted to hexadecimal before shifting. Step 5: The test image data set generated in step 4 is transmitted to the simulated detector module 2 and the image processing module 5 at the same time.

[0032] Step 6: Based on the remote control commands sent by the simulated serial port command module 7, the MicroBlaze soft-core Bayer image processing FPGA 10 reads and processes the test image data from the simulated detector module 2 according to a predetermined sequence. The processed intermediate data is stored in the simulated storage chip module 3, allowing the MicroBlaze soft-core Bayer image processing FPGA 10 to read and write data at any time. The processed result data is then transmitted to the simulated data download module 8.

[0033] Step 7: Image processing module 5 processes the test image dataset generated in step 4. First, image segmentation and image denoising are performed. By applying threshold segmentation to the original image, the bright and dark background areas of the original image are filtered out to reduce the impact of stray light on the image. Subsequently, image denoising is performed on the resulting image, using different filtering methods to reduce the impact of noise. Finally, the preprocessed Bayer image is decompressed and restored to an RGB image.

[0034] Step 8: The result data received by the simulated data download module 8 in step 6 and the result data processed by the image processing module 5 in step 7 are transmitted to the result comparison module 9. In this module, the restored RGB image data is compared in detail to verify the correctness of the image processing function, thus providing a reference for design.

[0035] Third embodiment In some embodiments of the present application, a computer device is also provided, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes a module of a fully digital closed-loop simulation verification system based on a MicroBlaze soft-core Bayer image processing FPGA as described in any one of the first embodiments.

[0036] The present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the module of the fully digital closed-loop simulation verification system based on the MicroBlaze soft-core Bayer image processing FPGA as described in any one of the first embodiments.

[0037] It can be understood that, for the aforementioned all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA, if it is implemented in the form of software function modules and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0038] Computer-readable storage media may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0039] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A fully digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA, characterized by: include: Image data generation module, detector simulation module, storage chip simulation module, MicroBlaze soft core simulation module, image processing module, clock reset simulation module, serial port instruction simulation module, data download simulation module and result comparison module; The image data generation module is used to perform processing including image cropping, noise addition, compression, sorting, and shifting on the original image to obtain a test image dataset, and output the test image dataset to the simulated detection module; The simulated detector module simulates the detector chip, is used to receive the SPI configuration parameters, clock configuration parameters and power supply configuration parameters configured by the FPGA, and sends the detector clock, temperature data and the timing signal stream data converted from the test image data set to the FPGA; The imitation memory chip module is used to respond to the storage control signal of the FPGA, receive address data and write data, and return read data; The MicroBlaze soft core simulation module loads the Bayer image processing firmware, drives the FPGA to process the timing signal stream data to obtain a simulation image, and sends it to the simulation data download module; The image processing module is used to process the test image data set to generate first result data; The simulated clock reset module is used to simulate the crystal oscillator and reset circuit to provide an adjustable clock signal and a reset signal for the FPGA; The simulated serial port instruction module is used to simulate the serial port timing, send serial port remote control instructions and receive serial port telemetry data; The simulation data download module receives and processes the simulation image to obtain second result data, and synchronously transmits the second result data to the result comparison module; The result comparison module is used to compare the second result data with the first result data.

2. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 1 is characterized in that: The image data generation module includes: An image cropping unit, configured to set cropping parameters including the coordinates of the image's starting point, and the image's height and width, and to crop the original image according to the cropping parameters; The noise injection unit supports the generation of noise test patterns by superimposing at least one noise type, including Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, exponential noise, and uniform noise; Bayer compression unit, converts the noise test pattern into a Bayer image in RGGB, GRBG, BGGR, or GBRG format according to the Bayer compression type The data reconstruction unit obtains the test image data set according to the setting parameters including the sorting mode and the shifting mode of the Bayer image.

3. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 2, characterized in that: The imitation detector module includes: A multi-channel asynchronous transmission unit reads the test image data set into the stack of the simulated detector module, generates a frame address signal, a row address signal, and a column address signal under a corresponding timing according to the received FPGA drive signal and the clock configuration parameters, and transmits the test image data set in the stack to the FPGA in a multi-channel manner according to the generated frame address signal, row address signal, and column address signal in the memory of the simulated detector module. At the same time, a delay parameter for each channel output is set to simulate an abnormal situation in which the image data output is not synchronized; The SPI configuration interface unit is used to receive configuration data including X coordinates, Y coordinates, image size, exposure time, gain parameters, and detector mode sent by the FPGA, select information including the coordinate position of the detector image, image size, detector exposure time, and detector channel mode according to the configuration data, and the SPI interface sets the real-time temperature parameters of the detector according to the set temperature requirements and sends the set real-time temperature data to the FPGA; The timing monitoring unit is used to monitor whether the interface timing meets the timing parameter requirements of the chip manual.

4. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 3 is characterized in that: The imitation memory chip module includes: A read / write operation unit for realizing reading and writing of image data in a manner including word-by-word and page-by-page; an erase unit for performing operations including block erase or sector erase; The address parsing unit is used to send an enable signal and address data according to the FPGA, and jump to the corresponding storage operation function after making a judgment based on the address data, so as to store the intermediate data and result data of the image processing.

5. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 4, characterized in that: The MicroBlaze soft core simulation module includes: A binary file loading and simulation operation unit is used to load the image processing module, compile the Bayer image program code into an ELF file executable by the Microblaze soft core, and simulate the soft core's instruction fetch, decoding, execution and write-back processes to achieve simulation operation; A dynamic interaction unit is configured to receive the timing signal stream data transmitted by the FPGA logic part via the AXI4 bus interface during the simulation process, and send the processed data results to the DMA controller of the FPGA logic. The DMA controller transmits the processed results to the simulation data download module. When the FPGA logic completes data writing, the data ready interrupt of the soft core is triggered. When the soft core processing is completed, the data read interrupt of the FPGA logic is triggered. A fault injection unit, which simulates faults including a soft core abnormal interrupt fault and a soft core running memory space insufficient fault by modifying the ELF file or dynamically adjusting simulation environment parameters; Time performance analysis unit, which records the timestamps of key events during the soft core operation, including interrupt response delay, algorithm processing cycle and bus transmission time; Generate a performance report based on timestamp data, and count the worst-case execution time (WCET), interrupt delay jitter, and bus utilization indicators to evaluate whether the software core timeliness meets the design requirements.

6. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 5, characterized in that: The image processing module includes: Performing image denoising on the test image data set using a median filter or a mean filter algorithm; Generate RGB image according to Bayer image decompression algorithm; The RGB image is restored to obtain the first result data, and the first result data is sent to the result comparison module.

7. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 6, characterized in that: The simulated serial port instruction module includes: First, according to the serial communication protocol, the information including the frame header, command word, data word, and check code is framed, and then the start bit, check bit, and stop bit are added byte by byte. The framed data is sent to the FPGA through the serial-to-parallel conversion function according to the serial protocol at a preset transmission rate. At the same time, abnormal conditions including frame header error, command code error, check code error, start bit loss, stop bit loss, check bit loss, communication interruption, and baud rate deviation are simulated; The serial port telemetry data returned by the FPGA is received at a preset transmission rate, and a telemetry data frame is obtained after determining the start bit, check bit and stop bit.

8. The all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to claim 7, wherein the result comparison module comprises: Converting the second result data and the first result data into the same pixel matrix format; Calculate PSNR, SSIM indicators and pixel difference maps; Mark error areas and generate visual comparison reports.

9. A computer device, characterized in that: The system comprises a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes a module of a fully digital closed-loop simulation verification system based on a MicroBlaze soft-core Bayer image processing FPGA as described in any one of claims 1 to 8.

10. A storage medium storing computer-readable instructions, characterized in that: When the computer-readable instructions are executed by one or more processors, the one or more processors execute the module of the all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA according to any one of claims 1 to 8.

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