Mask pattern edge compensation correction method, system, medium and computer device

Abstract

The present application relates to the technical field of semiconductor manufacturing, and specifically provides a mask layout pattern edge compensation correction method, comprising the steps of: constructing a training data set; training a deep learning model based on the training data set; obtaining a target mask design pattern, determining a set of open circuit position coordinates of the target mask design pattern based on a historical defect database and / or optical proximity correction simulation of a lithography imaging model; inputting the target mask design pattern, the set of open circuit position coordinates, lithography machine model parameters and optical model physical constraint parameters into an open circuit analysis model respectively, and outputting an open circuit probability distribution map of the target mask design pattern and a pattern edge correction rule; and inputting the target mask design pattern, the open circuit probability distribution map and the pattern edge correction rule into a lithography imaging model to generate a corrected mask design pattern. The method breaks through the limitations of traditional correction, significantly improves the mask correction accuracy and reduces the open circuit risk in chip production.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and specifically to a method, system, medium, and computer equipment for edge compensation and correction of mask patterns. Background Technology

[0002] With the rapid development of Ultra Large Scale Integration (ULSI), integrated circuit manufacturing processes have become increasingly complex and sophisticated. Photolithography is a driving force behind this development and is one of the most complex technologies. Compared to other individual manufacturing technologies, advancements in photolithography are of paramount importance to the development of integrated circuits. Before the photolithography process begins, the design pattern is first copied onto a photomask using specialized equipment. Then, a photolithography machine copies the pattern from the photomask onto the silicon wafer used to produce the chip. However, as design dimensions continue to shrink, approaching or even falling below the wavelength of light used in the photolithography process, diffraction and interference effects become increasingly pronounced. This leads to severe distortion of the actual lithographic pattern relative to the pattern on the photomask, ultimately resulting in a pattern on the silicon wafer that differs from the design pattern. This phenomenon is known as the Optical Proximity Effect (OPE).

[0003] Under the influence of Optical Proximity Effect (OPE), diffraction during photolithography can cause blurred edges or shortened linetips in the design pattern, indirectly leading to pinholes. Pinholes in the design pattern can cause functional failures in the final manufactured chip. To address this, Optical Proximity Correction (OPC) is typically introduced to adjust the edge shape of the mask pattern to resolve pinholes. However, insufficient OPC can leave pinholes unresolved. Alternatively, OPC can suffer from accumulated errors due to the correction algorithm. For example, when relying on an empirical rule base, if the mutual influence between adjacent patterns is not adequately anticipated, the corrected linewidth may gradually deviate from the target value due to insufficient or excessive compensation for the proximity effect, forming potential pinhole regions.

[0004] Based on this, the present invention provides a method, system, medium, and computer device for edge compensation and correction of mask graphics to solve the above problems. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention provides a method, system, medium, and computer device for edge compensation and correction of mask pattern, so as to solve the problems in the prior art.

[0006] One embodiment of the present invention provides a method for edge compensation and correction of a photomask pattern, comprising the following steps:

[0007] Construct a training dataset, which includes multiple sets of historical mask design graphics and corresponding sets of open circuit location coordinates, lithography machine model parameters matching each set of historical masks, and physical constraint parameters of the optical model;

[0008] The deep learning model is trained based on the training dataset to obtain the trained circuit breaker analysis model.

[0009] Obtain the target mask design pattern, and based on the historical defect database and / or optical proximity effect correction simulation of the lithography imaging model, determine the set of open circuit location coordinates that may occur at the edge of the target mask design pattern after silicon wafer exposure.

[0010] Input the target mask design pattern and its corresponding set of open circuit location coordinates, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained open circuit analysis model, and output the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules.

[0011] The target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules are input into the photolithography imaging model to generate the corrected mask design pattern.

[0012] By employing the aforementioned approach, a deep learning model is trained using a multi-dimensional training dataset that integrates historical mask design patterns, lithography machine parameters, and optical physical constraints. This enables the deep learning model to predict the risk of open circuits in the mask pattern during lithography and automatically generate correction schemes. The dynamic generation of quantized correction rules using a lithography imaging model overcomes the inherent limitations of traditional OPC, which relies on manual rule iteration. Simulation verification of the correction results using the lithography imaging model effectively solves problems such as pattern deformation and linewidth deviation caused by light diffraction, preventing error propagation. This method overcomes the limitations of traditional manual correction, significantly improves mask correction accuracy, and reduces the risk of open circuits in chip manufacturing.

[0013] In one embodiment, the historical defect database contains optical proximity effect correction parameters for several mask design patterns, as well as location data of the pattern edges where breaks occur during optical proximity effect correction.

[0014] By adopting the above scheme, using the optical proximity effect correction parameters of several historical mask design patterns, as well as the location data of the broken circuits at the edges of several mask design patterns during optical proximity effect correction, a reference can be provided for the compensation and correction of the target mask design pattern. This makes it easier to find out which position is most likely to be broken during compensation and correction, so as to make targeted corrections at that position.

[0015] In one embodiment, the step of obtaining the target mask design pattern and determining the set of open circuit location coordinates where an open circuit may occur at the edge of the pattern after silicon wafer exposure, based on a historical defect database and / or optical proximity effect correction simulation of the photolithography imaging model, specifically includes:

[0016] Obtain the target mask design pattern and the optical proximity effect correction parameters of the target mask design pattern;

[0017] The optical proximity effect correction parameters of the obtained target mask design pattern are matched with the optical proximity effect correction parameters of several mask design patterns in the historical defect database.

[0018] Based on the matching results, obtain the open circuit locations of several mask design patterns with matching values ​​greater than a preset threshold during silicon wafer exposure.

[0019] The open circuit locations of all the obtained mask design patterns that appear during silicon wafer exposure are integrated to obtain a set of open circuit location coordinates. This set of open circuit location coordinates is then used as the set of open circuit location coordinates that may occur in the target mask design pattern after silicon wafer exposure.

[0020] By adopting the above scheme, the target mask design pattern and its optical proximity effect correction parameters are matched with the optical proximity effect correction parameters of several mask design patterns in the historical defect database. One or more historical mask design patterns with matching values ​​exceeding a certain value are found. Furthermore, the open circuit locations of all the found historical mask design patterns during silicon wafer exposure are integrated, and the integrated set of open circuit location coordinates is the location where the target mask design pattern may experience an open circuit during exposure. This enables the prediction of open circuit risk of mask pattern during photolithography.

[0021] In one embodiment, after the step of matching the optical proximity correction parameters of the acquired target mask design pattern with the optical proximity correction parameters of several mask design patterns in a historical defect database, the method further includes:

[0022] Based on the matching results, if the matching value is less than the preset threshold, the optical proximity effect correction parameters of the obtained target mask design pattern are input into the lithography imaging model to simulate the optical proximity effect correction.

[0023] Based on the simulation results, several open circuit locations are obtained where the target mask design pattern may be broken at the edge of the pattern after exposure on the silicon wafer. These open circuit locations are then used as a set of open circuit location coordinates.

[0024] By adopting the above scheme, when the matching value is less than a certain value, the optical proximity effect correction simulation is performed on the target mask design pattern. The simulation simulates several open circuit locations that may occur at the edge of the pattern after silicon wafer exposure. Then, the simulated locations are used as the set of open circuit location coordinates. This avoids the situation where there is no mask design pattern in the historical defect database that matches the target mask design pattern, thus making it impossible to predict the open circuit risk of the mask pattern during photolithography.

[0025] In one embodiment, the step of inputting the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern specifically includes:

[0026] Based on the circuit breaker probability distribution map, the target mask design pattern is divided into a high circuit breaker risk area, a circuit breaker risk area, and a low circuit breaker risk area.

[0027] Based on the graphic edge correction rules, the risk levels are sequentially ranked from high to low to generate phased correction graphics. When each phase correction is completed, the light intensity gradient distribution of the current correction graphic is simulated by a photolithography imaging model. If the error between the current correction graphic and the adjacent region exceeds a preset threshold, the correction of the next phase is stopped and the correction rules of the current phase are adjusted back until the error between the current correction graphic and the adjacent region is within the preset threshold range.

[0028] Once all stages of correction are completed, the corrected mask design drawing is generated and output.

[0029] By adopting the above scheme, the target mask design pattern is divided into high, medium, and low open-circuit risk regions. Then, corrections are performed sequentially from high to low risk levels. Through risk grading and phased correction strategies, high open-circuit risk regions are prioritized, and error propagation in adjacent regions is verified in real time. The corrected light intensity gradient distribution is dynamically simulated using a photolithography imaging model. When errors in adjacent regions exceed limits, subsequent corrections are immediately stopped, and the current rules are adjusted retrospectively to ensure the stability of local corrections and compatibility with the global process window. This effectively solves the error accumulation problem caused by traditional single-step global corrections. Through a closed-loop iterative mechanism of "correction-verification-backtracking," it avoids secondary defects caused by over-correction of high open-circuit risk regions and prevents resource waste caused by premature adjustments in low-risk regions, significantly improving mask correction efficiency.

[0030] In one embodiment, the step of generating phased corrected graphics based on the graphic edge correction rules in descending order of risk level further includes the following step:

[0031] a) Based on the circuit breaker probability distribution map, identify the high circuit breaker risk area and the adjacent area of ​​the high circuit breaker risk area in the circuit breaker probability distribution map of the target mask design pattern;

[0032] b) Based on the aforementioned graphic edge correction rules, offset correction is performed on the edges of high-risk circuit breaker areas;

[0033] c) Simulate the light intensity distribution in the adjacent areas of the corrected high-risk area for circuit breakage using a photolithographic imaging model;

[0034] d) If the line width error of adjacent areas exceeds the preset threshold, the offset in the correction rule is dynamically adjusted, and steps b) to c) are repeated until the cumulative error of all adjacent areas is less than the tolerance range.

[0035] By adopting the above scheme, based on the division of high, medium, and low circuit breaker risk areas, the scheme accurately locates the high circuit breaker risk area and its adjacent areas, prioritizes the offset correction of the edges of the high circuit breaker risk area, and uses a photolithographic imaging model to verify the light intensity distribution and linewidth error of the adjacent areas in real time. When an error exceeding the limit is detected, the offset in the correction rule is dynamically adjusted and iteratively corrected until the cumulative error of the adjacent areas converges to the safe tolerance range. This scheme, through the synergistic mechanism of "local priority correction - global error suppression," avoids the overcompensation problem caused by global synchronous correction in traditional methods, and effectively suppresses the error chain diffusion caused by optical proximity effect through dynamic offset calibration.

[0036] In one embodiment, after the step of inputting the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern, the method further includes the following step:

[0037] The modified mask design pattern is solved in reverse based on the photolithography imaging model. The optimal pattern of the target mask is generated by minimizing the open circuit probability and linewidth error after silicon wafer exposure through an optimization algorithm.

[0038] The optimal graph is used as the optimization training set to optimize the circuit breaker analysis model.

[0039] By adopting the above scheme, the accuracy and adaptability of the correction are improved through a closed-loop self-optimization mechanism. Optical distortion is accurately compensated through the inverse solution of the photolithography imaging model, which directly reduces the risk of open circuit and linewidth error after silicon wafer exposure. At the same time, the optimized pattern is used as training data to optimize the open circuit analysis model, thereby improving the open circuit risk prediction capability of the open circuit analysis model.

[0040] This application also relates to a mask graphic edge compensation and correction system, including:

[0041] The data acquisition module is used to construct a training dataset, which includes multiple sets of historical mask design graphics and corresponding sets of open circuit location coordinates, lithography machine model parameters matching each set of historical masks, and physical constraint parameters of the optical model.

[0042] The model training module is used to train the deep learning model based on the training dataset to obtain the trained circuit breaker analysis model.

[0043] The open circuit pre-analysis module is used to acquire the target mask design pattern and, based on the historical defect database and / or the optical proximity effect correction simulation of the lithography imaging model, determine the set of open circuit location coordinates that may occur at the edge of the target mask design pattern after silicon wafer exposure.

[0044] The parameter correction analysis module is used to input the target mask design pattern and its corresponding set of open circuit position coordinates, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained open circuit analysis model, and output the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules.

[0045] The compensation and correction module is used to input the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern.

[0046] By employing the aforementioned approach, a deep learning model is trained using a multi-dimensional training dataset that integrates historical mask design patterns, lithography machine parameters, and optical physical constraints. This enables the deep learning model to predict the risk of open circuits in the mask pattern during lithography and automatically generate correction schemes. The dynamic generation of quantized correction rules using a lithography imaging model overcomes the inherent limitations of traditional OPC, which relies on manual rule iteration. Simulation verification of the correction results using the lithography imaging model effectively solves problems such as pattern deformation and linewidth deviation caused by light diffraction, preventing error propagation. This method overcomes the limitations of traditional manual correction, significantly improves mask correction accuracy, and reduces the risk of open circuits in chip manufacturing.

[0047] This application also relates to a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described mask pattern edge compensation and correction method.

[0048] This application also relates to a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described mask graphic edge compensation and correction method.

[0049] The mask pattern edge compensation and correction method, system, medium, and computer equipment provided in the above embodiments have the following beneficial effects:

[0050] 1. A deep learning model is trained by constructing a multi-dimensional training dataset that integrates historical mask design patterns, lithography machine parameters, and optical physical constraints. This enables the deep learning model to predict the risk of open circuits in the mask pattern during lithography and automatically generate correction schemes. Combined with a lithography imaging model, quantitative correction rules are dynamically generated, overcoming the inherent limitations of traditional OPC which relies on manual rule iteration. The correction results are simulated and verified using the lithography imaging model, effectively solving problems such as pattern deformation and linewidth deviation caused by light diffraction and avoiding error propagation. This method overcomes the limitations of traditional manual correction, significantly improves mask correction accuracy, and reduces the risk of open circuits in chip manufacturing.

[0051] 2. By matching the target mask design pattern and its optical proximity effect correction parameters with the optical proximity effect correction parameters of several mask designs in the historical defect database, one or more historical mask designs with matching values ​​exceeding a certain value are found. Furthermore, the open circuit locations of all the found historical mask designs during silicon wafer exposure are integrated, and the integrated set is the open circuit location coordinate set. All positions in this open circuit location coordinate set are the locations where the target mask design pattern may experience open circuits during exposure, thereby enabling the prediction of open circuit risks during photolithography.

[0052] 3. By dividing the target mask design pattern into high, medium, and low open-circuit risk regions, and then correcting them in stages from high to low risk, a risk-based, staged correction strategy is adopted. High-risk open-circuit regions are prioritized, and error propagation in adjacent regions is verified in real time. The corrected light intensity gradient distribution is dynamically simulated using a photolithography imaging model. When an error in an adjacent region exceeds the limit, subsequent corrections are immediately stopped, and the current rules are adjusted retrospectively to ensure the stability of local corrections and compatibility with the global process window. This effectively solves the error accumulation problem caused by traditional single-step global corrections. Through a closed-loop iterative mechanism of "correction-verification-backtracking," it avoids secondary defects caused by over-correction of high-risk open-circuit regions and prevents resource waste caused by premature adjustments in low-risk regions, significantly improving mask correction efficiency.

[0053] 4. Based on the division of high, medium, and low circuit breaker risk areas, this method accurately locates the high circuit breaker risk area and its adjacent areas, prioritizing edge offset correction for the high circuit breaker risk area. A photolithographic imaging model is then used to verify the light intensity distribution and linewidth errors of adjacent areas in real time. When an error exceeds the limit, the offset in the correction rule is dynamically adjusted and iteratively corrected until the cumulative error in adjacent areas converges to a safe tolerance range. This scheme, through a synergistic mechanism of "local priority correction - global error suppression," avoids the overcompensation problem caused by global synchronous correction in traditional methods, and effectively suppresses the error chain propagation caused by optical proximity effects through dynamic offset calibration. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0055] Figure 1 A flowchart of a mask pattern edge compensation and correction method provided in an embodiment of the present invention;

[0056] Figure 2 This is a flowchart illustrating step S50 of a mask pattern edge compensation and correction method provided in an embodiment of the present invention.

[0057] Figure 3 This is a flowchart illustrating step S51 of a mask pattern edge compensation and correction method provided in an embodiment of the present invention.

[0058] Figure 4This is a schematic diagram illustrating the probability of an open circuit occurring at the edge of the target mask design pattern in an embodiment of the present invention;

[0059] Figure 5 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0061] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0062] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0063] Reference Figure 1 One embodiment of the present invention provides a method for edge compensation and correction of a mask pattern, comprising the steps of:

[0064] S10. Construct a training dataset, which includes multiple sets of historical mask design graphics and corresponding sets of open circuit location coordinates, lithography machine model parameters matching each set of historical masks, and physical constraint parameters of the optical model.

[0065] S20. Train the deep learning model based on the training dataset to obtain the trained circuit breaker analysis model.

[0066] S30. Obtain the target mask design pattern, and based on the historical defect database and / or the optical proximity effect correction simulation of the lithography imaging model, determine the set of open circuit location coordinates that may occur at the edge of the target mask design pattern after silicon wafer exposure.

[0067] S40. Input the target mask design pattern and its corresponding set of open circuit position coordinates, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained open circuit analysis model, and output the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules.

[0068] S50. Input the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern.

[0069] In this embodiment, as described in steps S10-S20 above, the multiple sets of historical mask design patterns in the constructed training dataset are pre-collected data / parameters corresponding to several mask design patterns that are similar / approximate in design, and data / parameters corresponding to several masks that are the same / similar / approximate in manufacturing process. The corresponding set of open circuit location coordinates is compiled from the open circuit locations of each mask design pattern that were exposed to silicon wafers during exposure, and these open circuit locations are integrated into coordinate locations to form the open circuit location coordinate set. The lithography machine model parameters matched with each set of historical masks are the lithography machines selected when the corresponding mask is exposed; the physical constraint parameters of the optical model matched with each set of historical masks are the parameters for optical proximity effect correction of the corresponding mask design pattern. The collected data are preprocessed (e.g., data cleaning, missing value handling, data normalization, etc.); the preprocessed data are integrated into a training dataset for subsequent training of the deep learning model. The deep learning model can employ any of the following: Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), or Generative Adversarial Network (GAN). By utilizing the training dataset, the deep learning model learns the mapping relationship between the physical constraints of the mask design pattern, lithography machine parameters, and optical model, and the coordinates of the broken circuit location and the adjustment parameters of the pattern edge, in order to obtain a trained broken circuit analysis model. This model is used to predict the risk of broken circuits in the mask pattern during lithography and output the corresponding correction scheme.

[0070] In this embodiment, as described in step S30 above, the target mask design pattern is the mask design pattern that requires optical proximity correction. The historical defect database is constructed by compiling the open circuit locations of several pre-collected mask designs that are similar / approximate in design during silicon wafer exposure, as well as the correction parameters during optical proximity correction. The acquired target mask design pattern is matched with the mask design patterns in the historical defect database using a similarity algorithm. Simultaneously, optical proximity correction (OPC) simulation of the lithography imaging model is used, or only optical proximity correction simulation of the lithography imaging model is used (to obtain simulated patterns to view all possible open circuit locations) to determine the set of open circuit location coordinates that may occur at the edge of the target mask design pattern after silicon wafer exposure.

[0071] For the simulation of optical proximity effect correction in photolithographic imaging models, computer-aided software tools (OPC software) known in the art for use in OPC can be used to simulate the exposure of the target mask design pattern. These software programs can have preset simulation exposure rules, which can be modified by those skilled in the art. This application does not limit the specific simulation exposure rules.

[0072] In this embodiment, as described in step S40 above, the acquired target mask design pattern is input into the open circuit analysis model. Simultaneously, the corresponding open circuit location coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters are input into the trained open circuit analysis model. The trained open circuit analysis model, based on the "matrix design pattern, lithography machine parameters, and optical model physical constraint parameters to open circuit location coordinates and pattern edge adjustment parameters" learned during the training phase, outputs the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules. Figure 4 The diagram shown illustrates the probability of a broken circuit occurring at the edge of the target mask design pattern.

[0073] For example, the circuit breaker analysis model uses a convolutional neural network;

[0074] I. Input includes the following data:

[0075] The target mask design graphic (2D / 3D graphic data, such as GDSII format), the set of open circuit location coordinates generated in step S30 (the set of open circuit location coordinate points that may cause an open circuit), the lithography machine model parameters (such as numerical aperture NA, illumination mode, light source wavelength, etc.); and the physical constraint parameters of the optical model (such as the frequency domain coefficients of the Hopkins diffraction equation and the resist model parameters).

[0076] II. Output Mechanism:

[0077] (1) Generation of the probability distribution map of circuit closure.

[0078] Feature extraction: Use convolutional neural networks (CNNs) to extract spatial features of the design graphics (such as line width, spacing, corner shape, etc.) and generate high-dimensional feature maps.

[0079] Coordinate attention mechanism: The coordinates of the circuit breaker location in step S30 are encoded as spatial attention weights (e.g., through a graph neural network or coordinate encoding layer) to enhance the model's attention to areas with high circuit breaker risk.

[0080] Probabilistic prediction: The feature map is mapped to the open circuit probability value (0-1) of each pixel through a classification layer (such as an activation function), forming a probability distribution in the form of a heatmap.

[0081] (2) Generation of graphic edge correction rules.

[0082] Physical constraint fusion: The lithography machine parameters (such as NA) and optical model parameters (such as Hopkins equation coefficients) are input into the fully connected layer to generate physical feature vectors, which are then fused with the graphic features.

[0083] Regression network: Predicts the offset (Δx, Δy) of each edge point or the insertion rules (such as position and width) of the sub-resolution auxiliary graph (SRAF) through regression layers.

[0084] Rule encoding: Correction rules can be represented as structured data.

[0085] Example output: If the model detects that an edge is prone to breakage due to insufficient photoresist coverage, it may generate the rule: "Offset edge L1 outward by 1.5nm"; if the spacing between adjacent patterns is too small, it may insert SRAF to improve the light intensity distribution.

[0086] In this embodiment, as described in step S50 above, the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules are input into the photolithography imaging model. Based on the open circuit probability distribution map and pattern edge correction rules output by the open circuit analysis model, the photolithography imaging model corrects the target mask design pattern and generates the corrected mask design pattern.

[0087] In one embodiment, the historical defect database in step S30 includes optical proximity effect correction parameters for several mask design patterns, and location data of open circuits appearing at the edges of several mask design patterns during optical proximity effect correction. Further, step S30 specifically includes the following steps:

[0088] S31. Obtain the target mask design pattern and the optical proximity effect correction parameters of the target mask design pattern;

[0089] S32. Match the optical proximity effect correction parameters of the obtained target mask design pattern with the optical proximity effect correction parameters of several mask design patterns in the historical defect database.

[0090] S33A. Based on the matching results, obtain the open circuit locations of several mask design patterns with matching values ​​greater than a preset threshold during silicon wafer exposure.

[0091] S34A. Integrate all the open circuit locations that appear during silicon wafer exposure of the obtained mask design patterns to obtain a set of open circuit location coordinates. Use the obtained set of open circuit location coordinates as the set of open circuit location coordinates that may occur after silicon wafer exposure of the target mask design pattern.

[0092] After step S32, the following is also included:

[0093] S33B. Based on the matching results, if the matching value is less than the preset threshold, the optical proximity effect correction parameters of the obtained target mask design pattern are input into the lithography imaging model to simulate the optical proximity effect correction.

[0094] S34B. Based on the simulation results, several open circuit locations are obtained where the target mask design pattern may be broken at the edge of the pattern after exposure on the silicon wafer. The obtained open circuit locations are used as a set of open circuit location coordinates.

[0095] In this embodiment, the purpose of obtaining the target mask design pattern is to obtain the optical proximity effect correction parameters of the target mask design pattern to be corrected. The obtained optical proximity effect correction parameters of the target mask design pattern are matched with the optical proximity effect correction parameters of several mask design patterns in the historical defect database using a similarity algorithm (such as cosine similarity). Assuming a preset threshold of 80%, based on the matching results, if there are 10 historical mask design patterns with a matching value greater than 80% with the target mask design pattern, the open circuit positions that appear in these 10 mask design patterns during silicon wafer exposure are extracted and integrated to obtain a set of open circuit position coordinates. This set of open circuit position coordinates is the set of open circuit position coordinates that may occur in the target mask design pattern after silicon wafer exposure. Based on the matching results, there were no historical mask designs with a matching value greater than 80% with the target mask design. At this point, the optical proximity correction effect of the photolithography imaging model was used to correct and simulate the target mask design to obtain the exposure simulation pattern of the target mask design. This determined the possible open circuit locations at the edges of the target mask design after silicon wafer exposure. The open circuit locations were converted into coordinate locations and integrated into a set of open circuit location coordinates, which were then used as input data for the subsequent open circuit analysis model to output an open circuit probability distribution map.

[0096] Reference Figure 2 In one embodiment, step S50 specifically includes:

[0097] S51. Based on the circuit breaker probability distribution map, the target mask design pattern is divided into a high circuit breaker risk area, a circuit breaker risk area, and a low circuit breaker risk area.

[0098] S52. Based on the graphic edge correction rules, generate phased correction graphics in descending order of risk level; wherein, when each phase correction is completed, the light intensity gradient distribution of the current correction graphic is simulated by the photolithography imaging model. If the error between the current correction graphic and the adjacent area exceeds a preset threshold, stop the correction of the next phase and backtrack to adjust the correction rules of the current phase until the error between the current correction graphic and the adjacent area is within the preset threshold range.

[0099] S53. When all stages of correction are completed, generate and output the corrected mask design drawing.

[0100] In this embodiment, based on the circuit breaker probability distribution map output by the circuit breaker analysis model, the target mask design pattern is then divided into high circuit breaker risk areas, low circuit breaker risk areas, and low circuit breaker risk areas, such as... Figure 4 As shown, it is assumed that areas with a risk probability below 50% are classified as low-risk open-circuit regions, areas with a risk probability between 50% and 80% are classified as open-circuit regions, and areas with a risk probability greater than 80% are classified as high-risk open-circuit regions. Then, using OPC software based on a photolithography imaging model, the target mask design pattern is corrected in stages according to the risk level from high to low, based on the pattern edge correction rules. The corrected pattern is then generated in stages. By prioritizing the processing of high-risk open-circuit regions, error propagation caused by simultaneous global correction can be avoided.

[0101] In the process of correcting according to risk level (in stages), the correction will only proceed to the next stage if the current stage is deemed satisfactory. For example, if the correction is currently targeting a high-risk area for circuit breakage, the correction for the high-risk area for circuit breakage will not proceed immediately upon completion. Instead, the light intensity gradient distribution of the current corrected pattern will be simulated using a photolithographic imaging model. The simulation results will be used to determine whether the current stage of correction is satisfactory. This is because error propagation may occur during the correction process, and this step aims to prevent error propagation and accumulation, which could lead to new potential circuit breakage areas. If the error between the current corrected pattern and the adjacent area exceeds a preset threshold, it will be determined that the conditions for proceeding to the next stage are not met, and the process will revert to the current stage for further adjustment until the error between the current corrected pattern and the adjacent area falls within the preset threshold range before proceeding to the next stage of correction.

[0102] The preset thresholds for error can be: linewidth error not exceeding ±5% of the target linewidth, and light intensity gradient change rate less than 10% / nm.

[0103] The adjustment rules for backtracking can be as follows: adjust the edge offset in the opposite direction of the error, and reduce or increase the insertion density of the sub-resolution auxiliary graphics (SRAF).

[0104] Only when the corrections at each stage are satisfactory will the corrected mask design graphic be generated and output.

[0105] Reference Figure 3 In one embodiment, step S52 further includes the step of:

[0106] a) Based on the circuit breaker probability distribution map, identify the high circuit breaker risk area and the adjacent area of ​​the high circuit breaker risk area in the circuit breaker probability distribution map of the target mask design pattern;

[0107] b) Based on the aforementioned graphic edge correction rules, offset correction is performed on the edges of high-risk circuit breaker areas;

[0108] c) Simulate the light intensity distribution in the adjacent areas of the corrected high-risk area for circuit breakage using a photolithographic imaging model;

[0109] d) If the line width error of adjacent areas exceeds the preset threshold, the offset in the correction rule is dynamically adjusted, and steps b) to c) are repeated until the cumulative error of all adjacent areas is less than the tolerance range.

[0110] In this embodiment, based on the open circuit probability distribution map output by the open circuit analysis model, the target mask design pattern is divided into high open circuit risk regions, medium open circuit risk regions, and low open circuit risk regions. The high open circuit risk regions and their adjacent regions are then identified. The definition of adjacent regions involves extending a certain range outward from the high-risk region (e.g., twice the resolution of the lithography machine, or 6nm at the 3nm node) to ensure coverage of the influence range of optical proximity effects. After correcting the high open circuit risk regions according to the edge correction rules output by the open circuit analysis model, the light intensity distribution of the adjacent regions of the corrected high open circuit risk regions is simulated using a lithography imaging model to avoid new lithography distortions caused by local corrections. For example, "during correction, extending the line edges of the high-risk regions outward by 2nm to enhance the linewidth may lead to a reduction in the spacing between adjacent regions, causing new open circuit risks." When the linewidth error of the adjacent region is detected to exceed the preset threshold, the offset in the correction rule is dynamically adjusted according to the light intensity distribution result simulated by the photolithography imaging model. Then, steps b) to c) are repeated until the cumulative error of all adjacent regions converges to the safe tolerance range, thereby suppressing the error chain diffusion caused by the optical proximity effect.

[0111] S52. Based on the graphic edge correction rules, generate phased correction graphics in descending order of risk level; wherein, when each phase correction is completed, the light intensity gradient distribution of the current correction graphic is simulated by the photolithography imaging model. If the error between the current correction graphic and the adjacent area exceeds a preset threshold, stop the correction of the next phase and backtrack to adjust the correction rules of the current phase until the error between the current correction graphic and the adjacent area is within the preset threshold range.

[0112] Further, as needed, in step S52, the error between the current corrected pattern and the adjacent region includes edge placement error (EPE) (Edge placement error = actual edge position - target edge position, used to reflect the degree of edge offset after photolithography), and satisfies the following condition:

[0113] S521. For all high-risk areas with completed corrections and their adjacent areas, as well as the target area and its adjacent areas in the current correction phase, calculate the edge placement error value between the actual position and the target position of each graphic edge.

[0114] S522. If the absolute value of the edge placement error exceeds the first preset threshold (e.g., ±3nm) or the gradient change rate of the edge placement error value in the adjacent area is greater than the second preset threshold (e.g., 5% / nm), it is determined that the error exceeds the limit. For example, if the absolute value of the edge placement error exceeds ±3nm, or the gradient change rate of the edge placement error value in the adjacent area is greater than 5% / nm, it is determined that the error exceeds the limit.

[0115] S523. Adjust the edge offset in the correction rule so that the corrected edge placement error value meets the first preset threshold and the gradient change rate meets the second preset threshold.

[0116] In this embodiment, step S521 not only detects the error in the current operating area but also tracks the stability of historically corrected areas to avoid secondary defects in other areas caused by local corrections. In step S522, a gradient change rate threshold is used to identify drastic fluctuations in light intensity distribution (such as edge abrupt changes caused by lithographic proximity effects), thus blocking the error propagation chain in advance. Overall, through a dual-threshold dynamic detection and closed-loop adjustment mechanism, the edge placement error (EPE) and light intensity gradient changes in the corrected area and adjacent areas can be accurately monitored. When the absolute value of EPE or the gradient change rate exceeds the limit, the offset is dynamically adjusted in the reverse direction until the error converges, effectively blocking the error propagation chain and improving linewidth uniformity.

[0117] In one embodiment, after step S50, the following step is further included:

[0118] S60. Based on the photolithography imaging model, the modified mask design pattern is solved in reverse. The probability of open circuit and linewidth error after silicon wafer exposure are minimized by the optimization algorithm to generate the optimal pattern of the target mask.

[0119] S70. Use the optimal graph as the optimization training set to optimize the circuit breaker analysis model.

[0120] In this embodiment, the accuracy and adaptability of the correction are improved by a closed-loop self-optimization mechanism. Optical distortion is accurately compensated by the inverse solution of the photolithography imaging model, which directly reduces the risk of open circuit and linewidth error after silicon wafer exposure. At the same time, the optimized pattern is used as training data to optimize the open circuit analysis model, thereby improving the open circuit risk prediction capability of the open circuit analysis model.

[0121] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0122] In one embodiment, a mask pattern edge compensation and correction system is provided, which corresponds to the mask pattern edge compensation and correction method described in the above embodiments. The mask pattern edge compensation and correction system includes:

[0123] The data acquisition module is used to construct a training dataset, which includes multiple sets of historical mask design graphics and corresponding sets of open circuit location coordinates, lithography machine model parameters matching each set of historical masks, and physical constraint parameters of the optical model.

[0124] The model training module is used to train the deep learning model based on the training dataset to obtain the trained circuit breaker analysis model.

[0125] The open circuit pre-analysis module is used to acquire the target mask design pattern and, based on the historical defect database and / or the optical proximity effect correction simulation of the lithography imaging model, determine the set of open circuit location coordinates that may occur at the edge of the target mask design pattern after silicon wafer exposure.

[0126] The parameter correction analysis module is used to input the target mask design pattern and its corresponding set of open circuit position coordinates, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained open circuit analysis model, and output the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules.

[0127] The compensation and correction module is used to input the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern.

[0128] Specific limitations regarding a mask image edge compensation and correction system can be found in the above description of a mask image edge compensation and correction method, and will not be repeated here. Each module in the aforementioned mask image edge compensation and correction system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0129] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows. Figure 5 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores mask design graphic data, performs data processing, and conducts data analysis. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a mask graphic edge compensation and correction method.

[0130] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a mask graphic edge compensation correction method.

[0131] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements a mask graphic edge compensation and correction method.

[0132] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0133] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0134] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for edge compensation and correction of a photomask pattern, characterized in that, Including the following steps: Construct a training dataset, which includes multiple sets of historical mask design graphics and corresponding sets of open circuit location coordinates, lithography machine model parameters matching each set of historical masks, and physical constraint parameters of the optical model; The deep learning model is trained based on the training dataset to obtain the trained circuit breaker analysis model. The target mask design pattern is obtained, and based on the historical defect database and / or the optical proximity effect correction simulation of the lithography imaging model, the set of coordinates of the break-circuit positions that may occur at the edge of the target mask design pattern after silicon wafer exposure is determined; the historical defect database contains optical proximity effect correction parameters for several mask design patterns, as well as location data of break-circuit positions at the edge of several mask design patterns when optical proximity effect correction is performed. Input the target mask design pattern and its corresponding set of open circuit position coordinates, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained open circuit analysis model, and output the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules. The target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules are input into the photolithography imaging model to generate the corrected mask design pattern.

2. The mask pattern edge compensation and correction method as described in claim 1, characterized in that, The step of obtaining the target mask design pattern and determining the set of open circuit location coordinates that may occur at the edge of the pattern after silicon wafer exposure, based on the optical proximity effect correction simulation of the historical defect database and / or the photolithography imaging model, specifically includes: Obtain the target mask design pattern and the optical proximity effect correction parameters of the target mask design pattern; The optical proximity effect correction parameters of the obtained target mask design pattern are matched with the optical proximity effect correction parameters of several mask design patterns in the historical defect database. Based on the matching results, obtain the open circuit locations of several mask design patterns with matching values ​​greater than a preset threshold during silicon wafer exposure. The open circuit locations of all the obtained mask design patterns that appear during silicon wafer exposure are integrated to obtain a set of open circuit location coordinates. This set of open circuit location coordinates is then used as the set of open circuit location coordinates that may occur in the target mask design pattern after silicon wafer exposure.

3. The mask pattern edge compensation and correction method as described in claim 2, characterized in that, After the step of matching the optical proximity effect correction parameters of the obtained target mask design pattern with the optical proximity effect correction parameters of several mask design patterns in the historical defect database, the method further includes: Based on the matching results, if the matching value is less than the preset threshold, the optical proximity effect correction parameters of the obtained target mask design pattern are input into the lithography imaging model to simulate the optical proximity effect correction. Based on the simulation results, several open circuit locations are obtained where the target mask design pattern may be broken at the edge of the pattern after exposure on the silicon wafer. These open circuit locations are then used as a set of open circuit location coordinates.

4. The mask pattern edge compensation and correction method as described in claim 1, characterized in that, The step of inputting the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern specifically includes: Based on the circuit breaker probability distribution map, the target mask design pattern is divided into a high circuit breaker risk area, a circuit breaker risk area, and a low circuit breaker risk area. Based on the graphic edge correction rules, the risk levels are sequentially ranked from high to low to generate phased correction graphics. When each phase correction is completed, the light intensity gradient distribution of the current correction graphic is simulated by a photolithography imaging model. If the error between the current correction graphic and the adjacent region exceeds a preset threshold, the correction of the next phase is stopped and the correction rules of the current phase are adjusted back until the error between the current correction graphic and the adjacent region is within the preset threshold range. Once all stages of correction are completed, the corrected mask design drawing is generated and output.

5. The mask pattern edge compensation and correction method as described in claim 4, characterized in that, The step of generating phased corrected graphics based on the graphic edge correction rules in descending order of risk level further includes the following steps: a) Based on the circuit breaker probability distribution map, identify the high circuit breaker risk area and the adjacent area of ​​the high circuit breaker risk area in the circuit breaker probability distribution map of the target mask design pattern; b) Based on the aforementioned graphic edge correction rules, offset correction is performed on the edges of high-risk circuit breaker areas; c) Simulate the light intensity distribution in the adjacent areas of the corrected high-risk area for circuit breakage using a photolithographic imaging model; d) If the line width error of adjacent areas exceeds the preset threshold, the offset in the correction rule is dynamically adjusted, and steps b) to c) are repeated until the cumulative error of all adjacent areas is less than the tolerance range.

6. The mask pattern edge compensation and correction method as described in claim 1, characterized in that, After the step of inputting the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern, the method further includes the following steps: The modified mask design pattern is solved in reverse based on the photolithography imaging model. The optimal pattern of the target mask is generated by minimizing the open circuit probability and linewidth error after silicon wafer exposure through an optimization algorithm. The optimal graph is used as the optimization training set to optimize the circuit breaker analysis model.

7. A mask pattern edge compensation and correction system, used to implement the steps of the mask pattern edge compensation and correction method as described in any one of claims 1-6, characterized in that, include: The data acquisition module is used to construct a training dataset, which includes multiple sets of historical mask design graphics and corresponding sets of open circuit location coordinates, lithography machine model parameters matching each set of historical masks, and physical constraint parameters of the optical model. The model training module is used to train the deep learning model based on the training dataset to obtain the trained circuit breaker analysis model. The open circuit pre-analysis module is used to acquire the target mask design pattern and, based on the historical defect database and / or the optical proximity effect correction simulation of the lithography imaging model, determine the set of open circuit location coordinates where an open circuit may occur at the edge of the target mask design pattern after silicon wafer exposure; the historical defect database contains optical proximity effect correction parameters for several mask design patterns, as well as location data of open circuits appearing at the edge of several mask design patterns during optical proximity effect correction; The parameter correction analysis module is used to input the target mask design pattern and its corresponding set of open circuit position coordinates, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained open circuit analysis model, and output the open circuit probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules. The compensation and correction module is used to input the target mask design pattern, the open circuit probability distribution map, and the pattern edge correction rules into the photolithography imaging model to generate the corrected mask design pattern.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the mask graphic edge compensation and correction method as described in any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the mask graphic edge compensation and correction method as described in any one of claims 1-6.

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