Semiconductor device with multiple passivation materials at bonding surface

Abstract

The present disclosure relates to a semiconductor device having a plurality of passivation materials at a bonding surface. The semiconductor device assembly includes a semiconductor substrate having a plurality of die locations where a plurality of semiconductor dies are implemented, scribe regions interleaved between the plurality of die locations, and a peripheral region proximate a periphery of the semiconductor substrate. A first passivation material is disposed at the plurality of die locations, and a second passivation material is disposed at the scribe line region and the peripheral region. The first passivation material and the second passivation material implement a bonding surface of the semiconductor device assembly.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor device components, and more particularly, to semiconductor devices having multiple passivation materials at bonding surfaces. Background Art

[0002] Wafer bonding is a wafer-level packaging technology that can be used to form semiconductor device assemblies. During wafer bonding, two semiconductor wafers are brought into contact with each other at their respective bonding surfaces. Interconnects can be formed between the wafers. Similarly, dielectric materials at each respective wafer can be bonded to mechanically couple the two semiconductor wafers. During bonding, moisture can become trapped at the bond line between the two wafers and create gaps. These gaps can reduce the bond strength between the two semiconductor wafers or, in some cases, break the interconnects between the wafers, potentially rendering the semiconductor devices implemented on the wafers inoperable. Summary of the Invention

[0003] In one aspect, the present disclosure provides a semiconductor device component comprising: a semiconductor substrate comprising: a first surface; a plurality of die locations, at which a plurality of semiconductor dies are implemented; scribe line regions, which are staggered between the plurality of die locations; and a peripheral region, which is located near the periphery of the semiconductor substrate and surrounds the plurality of die locations; a first passivation material, which is disposed at the first surface and vertically aligned with the plurality of die locations; and a second passivation material, which is disposed at the first surface and vertically aligned with the scribe lines and the peripheral region, the second passivation material being different from the first passivation material, wherein the first passivation material and the second passivation material implement a bonding surface of the semiconductor device component.

[0004] On the other hand, the present disclosure provides a method comprising: providing a semiconductor substrate comprising: a first side, a plurality of die locations for implementing a plurality of semiconductor dies, scribe line regions interlaced between the plurality of die locations, and a peripheral region located near the periphery of the semiconductor substrate and surrounding the plurality of die locations; placing a first passivation material at the first side and vertically aligned with the plurality of die locations; and placing a second passivation material at the first side and vertically aligned with the scribe line regions and the peripheral region, the second passivation material being different from the first passivation material, wherein the first passivation material and the second passivation material are exposed to implement a bonding surface.

[0005] In another aspect, the present disclosure provides a semiconductor wafer comprising: a first surface; a plurality of die locations at which a plurality of semiconductor dies are implemented; scribe line regions that are staggered between the plurality of die locations; a peripheral region that is located near the periphery of the semiconductor wafer and surrounds the plurality of die locations; and a passivation material layer disposed at the first surface, the passivation material layer comprising a first passivation material vertically aligned with the plurality of die locations and a second passivation material vertically aligned with the scribe line regions and the peripheral region, the second passivation material being different from the first passivation material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Simplified schematic cross-sectional views of semiconductor device components including a semiconductor substrate having multiple passivation materials are illustrated in accordance with embodiments of the present technology.

[0007] Figure 2 Simplified schematic partial plan view illustrating a semiconductor substrate having multiple passivation materials in accordance with an embodiment of the present technology.

[0008] Figure 3-9 Simplified schematic cross-sectional views illustrating a series of operations for assembling a semiconductor device in accordance with an embodiment of the present technology.

[0009] Figure 10 A schematic diagram illustrating a system including a semiconductor device according to an embodiment of the present technology is shown.

[0010] Figure 11 A method for assembling a semiconductor device according to an embodiment of the present technology is described. DETAILED DESCRIPTION

[0011] Semiconductor devices are integrated into many devices to implement memory cells, processor circuits, imager devices, and other functional features. As more applications for semiconductor devices are discovered, designers are tasked with creating improved devices that can perform greater numbers of operations per second, store greater amounts of data, or operate with higher levels of security. Improvements in packaging have enabled multiple semiconductor dies to be assembled into a single package to implement a single packaged device with increased functionality. To implement this improved device while limiting the increase in package footprint, semiconductor dies can be stacked on top of each other.

[0012] Typically, to form a stacked semiconductor device, two semiconductor wafers, each implementing multiple dies, may be bonded such that the respective dies on each of the wafers are coupled to one another. The bonding process may include forming interconnects between contacts at the respective semiconductor dies on each wafer and bonding a passivation layer (e.g., of a dielectric material) at the respective bonding surfaces of the wafers. Typically, the bonding process must be controlled to ensure that the wafers are free of contaminants that, when present on the bonding surfaces, could create voids (e.g., unbonded portions of the bonding surfaces of the wafers). If the voids are large enough, they could weaken the bond between the semiconductor wafers to the point of failure or cause the interconnects between the bonded semiconductor dies to separate and short, rendering the dies inoperable.

[0013] Limiting contamination at the bonding surface can be difficult, in part because contaminants can be generated by various steps in the bonding process. For example, the bonding process may involve hydrating the bonding surfaces of semiconductor wafers and contacting the wafers in a high-temperature or high-pressure environment. The wafers may be bonded along a bonding wave that propagates from the center to the edge of the wafer. As the bonding wave propagates, moisture may be pushed toward the edge of the wafer, where pressure drops. Consequently, moisture may condense at the edge of the wafer, and this condensation can create voids along the bonding interface.

[0014] Furthermore, contaminants may be generated by fusion bonding of semiconductor wafers. In some cases, fusion bonding between the passivation layers of the wafers can generate moisture that can accumulate at the bonding surface. As a specific example, fusion bonding between Si-OH groups in the passivation layers of the wafers can generate moisture at the bonding surface. If the moisture cannot diffuse through the passivation layer, it can form gaps between the wafers.

[0015] In order to solve these problems, etc., an embodiment of the present technology provides a semiconductor substrate having a plurality of passivation materials implemented at the bonding surface. For example, a passivation material with high bonding energy can be used to implement a portion of the bonding surface so that the bonding member formed with similar materials has a higher bonding strength. Therefore, higher bonding strength can reduce the gaps that occur due to separation of the semiconductor substrate at the bonding interface. On the other hand, this passivation material may be inconsistent with the passivation material used for other assembly processes (for example, a passivation material for insulating a through-hole). This inconsistency may reduce the predictability and yield of the assembly process. Therefore, some areas on the bonding surface may benefit from being implemented with a certain passivation material, even if the passivation material has a lower bonding strength.

[0016] The present technology utilizes the benefits of two passivation materials by implementing a first passivation material (e.g., a passivation material that is consistent with other passivation materials used during assembly) in the active area of a semiconductor substrate where the semiconductor die (e.g., multiple die locations) are implemented, and implementing a second passivation material in the scribe line areas and other undeveloped areas on the semiconductor substrate. As a result, the active areas where passivation material is present for manufacturing and assembling the semiconductor die can include consistent passivation material, thereby improving yield. In addition, the second passivation material can be used to form stronger bonds outside the active areas and in some locations where voids are most likely to occur (e.g., at the edges of the substrate), thereby reducing the occurrence of voids without creating inconsistencies with other passivation materials at the active areas. Thus, the present technology achieves embodiments of improved semiconductor devices with improved yield.

[0017] Figure 1 A simplified schematic cross-sectional view of a semiconductor device assembly 100 including a semiconductor substrate 102 having multiple passivation materials is illustrated in accordance with an embodiment of the present technology. The semiconductor substrate 102 may include a wafer-level, strip-level, or panel-level substrate. The semiconductor substrate 102 may include a semiconductor material such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate.

[0018] A plurality of semiconductor dies 104 are implemented at a semiconductor substrate 102. The semiconductor substrate 102 may be attached to a carrier substrate (e.g., a wafer). As illustrated, the semiconductor substrate 102 implements a semiconductor die 104-1 and a semiconductor die 104-2 (generally referred to as semiconductor die 104). The semiconductor die 104 may be of any type. For example, the semiconductor die may be a memory die, such as a dynamic random access memory (DRAM) die, a NAND die, or the like. Alternatively or in addition, the semiconductor die 104 may include a logic die. The semiconductor die 104 may be implemented at different lateral locations on the semiconductor substrate 102. The semiconductor die 104 includes transistors, capacitors, resistors, and other circuitry (not shown) that is connected to a back-end wiring layer (not shown). The back-end wiring layer may include traces, lines, vias, and other connection circuitry that provides connectivity to the semiconductor die 104.

[0019] Semiconductor substrate 102 includes an active area 106 (e.g., multiple die locations), a scribe line region 108, and a peripheral region 110. Semiconductor die 104 are implemented at active area 106. Scribe line regions 108 are located between semiconductor die 104 outside of active area 106. For example, scribe line regions 108 may be staggered between multiple die locations. In this manner, scribe line regions 108 may provide locations where semiconductor substrate 102 may be sawed to singulate semiconductor die 104. Peripheral region 110 is similarly located outside active area 106. Peripheral region 110 may correspond to the periphery of semiconductor substrate 102 (e.g., near the substrate edge) and surround semiconductor die 104.

[0020] A passivation layer may be disposed above the back-end wiring layer at the surface 112 (e.g., the front side) of the semiconductor substrate 102. The passivation layer may insulate the circuitry disposed on the semiconductor substrate 102 and provide a bonding surface for additional semiconductor dies. For example, the passivation layer may be used to form a hybrid or fused bond with the passivation layer of the additional semiconductor device. Thus, in some cases, contact pads may be disposed in the passivation layer to implement interconnects between the bonded semiconductor dies. Alternatively or in addition, the passivation layer may be a continuous layer, and the interconnects may be implemented between the bonded semiconductor dies by drilling vias directly through the passivation layer to the back-end wiring layer.

[0021] The passivation layer may include a variety of passivation materials (e.g., dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxide, etc.). As illustrated, passivation material 114 is disposed at active area 106, and passivation material 116 is disposed at scribe line area 108 and peripheral area 110. For example, the lateral position of passivation material 114 corresponds to the lateral position of active area 106, and the lateral position of passivation material 116 corresponds to the lateral position of scribe line area 108 and peripheral area 110. In this manner, passivation material 114 may be vertically aligned with active area 106, and passivation material 116 may be vertically aligned with scribe line area 108 and peripheral area 110. For example, the perimeter of passivation material 114 may be vertically aligned with the perimeter of active area 104 (e.g., at each of the die locations), and passivation material 116 may be vertically aligned with the perimeter of scribe line area 108 and peripheral area 110. In this manner, passivation material 114 may extend across active area 106, and passivation material 116 may extend from the periphery of semiconductor die 104. In some embodiments, active area 106, scribe line area 108, or peripheral area 110 may include multiple passivation materials (e.g., the same as or different from passivation material 114 and passivation material 116). Passivation material 114 and passivation material 116 may be different passivation materials.

[0022] In various aspects, passivation material 116 has a higher bonding energy than passivation material 114. In this way, the bond formed between passivation material 116 and the same material can have a higher bonding strength than the bond formed between passivation material 114 and the same material. In this way, the occurrence of voids at passivation material 116 can be limited. Passivation material 114 can correspond to the insulating material used in other assembly processes. For example, passivation material 114 can correspond to the passivation material used to insulate the through-holes extending between the bonded semiconductor dies. Therefore, passivation material 114 can be implemented at the active area to provide continuity with the passivation material used to insulate the through-holes present in the active area. As a specific example, passivation material 114 includes silicon oxide, silicon carbon oxide or any other dielectric, and passivation material 116 includes silicon carbon nitride, a dielectric material deposited by a high aspect ratio process (HARP dielectric) or any other dielectric.

[0023] Figure 2 A simplified schematic partial plan view of a semiconductor substrate 200 having multiple passivation materials according to an embodiment of the present technology is illustrated. The semiconductor substrate 200 includes semiconductor dies 202 implemented at different lateral locations of the semiconductor substrate 200. The semiconductor dies 202 can be spaced apart from each other so that the semiconductor dies 202 can be singulated from each other by sawing at scribe line regions therebetween. Figure 2 2 illustrates that additional semiconductor devices can be attached to a bonding surface 204 of the semiconductor substrate 200. A passivation layer is disposed at the semiconductor substrate 200 to implement the bonding surface 204. The passivation layer includes a passivation material 206 in locations corresponding to the semiconductor die 202 (e.g., in the active area) and a passivation material 208 in locations outside the semiconductor die 202 (e.g., in the scribe line area and the peripheral area).

[0024] The present disclosure now turns to a series of steps for manufacturing a semiconductor device assembly according to an embodiment of the present technology. Specifically, Figure 3-9 A simplified schematic cross-sectional view illustrating a series of operations for assembling a semiconductor device according to an embodiment of the present technology. For ease of description, the operations are described with respect to a specific embodiment. However, operations may be performed with respect to Figure 3-9 The operations are described to assemble semiconductor devices according to other embodiments.

[0025] from Figure 3Initially, at stage 300, a semiconductor substrate 302 including semiconductor die 304-1 and semiconductor die 304-2 (collectively referred to as semiconductor die 304) is provided. Semiconductor substrate 302 includes active regions 306 implementing semiconductor die 304, scribe line regions 308 between semiconductor die 304, and peripheral regions 310 surrounding semiconductor die 304. Active regions 306, scribe line regions 308, and peripheral regions 310 constitute different portions of a surface 312 (e.g., a front side) of semiconductor substrate 302.

[0026] Passivation material 314 is disposed at surface 312 of semiconductor substrate 302 by any number of techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), dispensing, oxidation, spin coating, and / or other suitable techniques. Passivation material 314 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxide carbon, etc. Passivation material 314 may correspond to a dielectric material used to insulate circuit systems formed during other assembly processes. As specific examples, passivation material 314 may include silicon oxide or silicon oxide carbon. Passivation material 314 may be disposed across the entire surface 312 (e.g., at active area 306, scribe line area 308, and peripheral area 310). Portions of passivation material 314 may then be removed to implement passivation material 314 only at portions of surface 312, such as Figure 4 As described in .

[0027] Next turn Figure 4 At stage 400, portions of the passivation material 314 are removed to expose the semiconductor substrate 302. The passivation material 314 may be removed at the scribe line areas 308 and the peripheral areas 310. Thus, the passivation material 314 may be disposed only at locations corresponding to the active areas 306 of the semiconductor die 304. The portions of the passivation material 314 corresponding to the scribe line areas 308 and the peripheral areas 310 may be removed by any number of techniques, such as using plasma etching, wet etching, chemical mechanical planarization (CMP), drilling, or other suitable techniques. Although described in two operations in which the passivation material 314 is disposed over the entire surface 312 of the semiconductor substrate 302 and then selectively removed, in other embodiments, the passivation material 314 may be selectively disposed in locations corresponding to the active areas 306.

[0028] Next turn Figure 5, at stage 500, a passivation material 316 is disposed at the surface 312 of the semiconductor substrate 302 and over the passivation material 314 by any number of techniques, such as CVD, PVD, dispensing, oxidation, spin coating, and / or other suitable techniques. The passivation material 316 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxide, etc. The passivation material 316 may correspond to a dielectric material having a high bonding energy. As a specific example, the passivation material 316 may include silicon carbonitride or a HARP dielectric. The passivation material 316 may have a higher bonding energy than the passivation material 314. The passivation material 316 may be disposed at the surface 312 (e.g., at the active area 306, the scribe area 308, and the peripheral area 310) and over the passivation material 314. Portions of the passivation material 316 may then be removed to expose the passivation material 314 and the remaining passivation material 316 at the bonding surface, such as Figure 6 As described in .

[0029] Next turn Figure 6 At stage 600, a portion of passivation material 316 is removed to expose passivation material 314 and remaining passivation material 316. For example, passivation material 316 disposed above passivation material 314 may be removed to expose passivation material 314 corresponding to active area 306 of semiconductor die 304, and to expose passivation material 316 at scribe line area 308 and peripheral area 310. Passivation material 316 may be removed by any number of techniques, such as using plasma etching, wet etching, CMP, drilling, or other suitable techniques. In some cases, passivation material 316 is removed by CMP. In various aspects, CMP may remove a portion of passivation material 314 to form a planar bonding surface implemented using passivation material 314 and passivation material 316. Although illustrated in two operations where passivation material 316 is disposed over surface 312 of semiconductor substrate 302 and passivation material 314 and then selectively removed, in other embodiments, passivation material 316 may be selectively disposed in locations corresponding to scribe line region 308 and peripheral region 310 .

[0030] Next turn Figure 7 At stage 700, semiconductor substrate 302 is bonded to semiconductor substrate 702. Semiconductor substrate 702 may be implemented similarly to semiconductor substrate 302. For example, semiconductor substrate 702 includes semiconductor die 704-1 and semiconductor die 704-2 (collectively referred to as semiconductor die 704) implemented at active area 706, scribe line region 708 between semiconductor die 704, and peripheral region 710 surrounding semiconductor die 704.

[0031] Semiconductor substrate 302 and semiconductor substrate 702 may be bonded at a bonding interface 712. In various aspects, semiconductor substrate 702 may include a passivation material 714 and a passivation material 716 that implement a bonding surface that bonds with the bonding surface of semiconductor substrate 302. Passivation material 714 may be disposed at active area 706, and passivation material 716 may be disposed at scribe line area 708 and peripheral area 710. Passivation material 714 may be the same material as passivation material 314, and passivation material 716 may be the same material as passivation material 316. Semiconductor substrate 302 and semiconductor substrate 702 may be aligned such that semiconductor die 304 and semiconductor die 704 are aligned. In this manner, passivation material 314 may bond with passivation material 714, and passivation material 316 may bond with passivation material 716 at bonding interface 712.

[0032] The bond may be formed by mixing or fusion bonding. In various aspects, semiconductor die 304 and semiconductor die 704 may be bonded in a front-to-back arrangement such that the front of semiconductor die 304 faces the back of semiconductor die 704. Passivation material 316 and passivation material 716 may comprise a passivation material having a high bonding energy. As a result, it may be difficult to separate semiconductor substrate 302 and semiconductor substrate 702 at bonding interface 712, thereby reducing the occurrence of voids, particularly at the substrate edges where passivation material 316 and passivation material 716 are present and where voids are more likely to occur.

[0033] Next turn Figure 8 At stage 800, circuitry 802-1 and circuitry 802-2 (collectively, circuitry 802) at semiconductor die 704 are coupled to circuitry 804-1 and circuitry 804-2 (collectively, circuitry 804) at semiconductor die 304 via respective through-silicon vias 806-1 (TSVs) and 806-2 (collectively, TSVs 806). TSVs 806 may provide connectivity to enable the transmission of signaling between semiconductor die 704 and semiconductor die 304. Circuitry 802 and circuitry 804 may include functional circuitry (e.g., transistors, diodes, capacitors, resistors, etc.) or connection circuitry (e.g., traces, lines, vias, etc.) implemented at semiconductor die 704 and semiconductor die 304, respectively. Circuitry 802 may be disposed at semiconductor die 704 before or after coupling semiconductor die 704 to semiconductor die 304.

[0034] TSV 806 can be implemented in a TSV-first, TSV-middle, or TSV-last process. In various aspects, TSV 806 is implemented in a TSV-last process. For example, semiconductor die 704 can be bonded to semiconductor die 304, and a through-hole can be created through semiconductor substrate 702. The through-hole can be created by etching, drilling, or any other process. The through-hole can extend through semiconductor substrate 702 (e.g., at active area 706), passivation material 714, and passivation material 314. In various aspects, the through-hole can extend completely to the back-end wiring layer of semiconductor die 304 where circuit system 804 is located. In this way, there is no need to form metal-metal interconnects at the bonding interface 712. Conductive material can be placed in the through-hole to implement TSV 806. The conductive material can be placed via dispensing, CVD, PVD, plating, electroless plating, or any other suitable technique. In some cases, passivation material can be placed on the wall of the through-hole to insulate TSV 806. In various aspects, this passivation material may be the same as passivation material 714 to maintain consistency, which may improve yield and predictability.

[0035] Next turn Figure 9 At stage 900, a semiconductor die stack 902 is singulated and packaged. The singulated semiconductor die stack 902 may include semiconductor dies (eg, Figure 8 The semiconductor die stack 902 may be singulated by sawing the substrate between the semiconductor dies at scribe line regions.

[0036] The semiconductor die stack 902 can then be packaged into a semiconductor device. The semiconductor die stack 902 is attached to a package-level substrate 904 (e.g., a printed circuit board (PCB), an interposer, a semiconductor substrate, another semiconductor die). The semiconductor die stack 902 includes one or more external contact pads 906 that are coupled to circuitry at the semiconductor die stack 902 through connecting circuitry (e.g., traces, wires, vias, etc.). Connection structures 908 (e.g., solder, conductive posts, etc.) can be formed between the contact pads 906 and contacts (not shown) at the package-level substrate 904 to enable electrical signaling to be passed between the semiconductor die stack 902 and the package-level substrate 904. The package-level substrate 904 can further include package-level contact pads (not shown) that provide external connectivity (e.g., power, ground, and input / output (I / O) signals) to the semiconductor die stack 902 through solder balls 910 or other connection structures. Traces, lines, vias, and other electrical connection structures in the package-level substrate 904 may electrically connect the package-level contact pads to the contact pads at the upper surface of the package-level substrate 904 .

[0037] An underfill material 912 (e.g., capillary underfill) may be provided between the semiconductor die stack 902 and the package-level substrate 904 to provide electrical insulation for the connection structure 908 and structurally support the device. The semiconductor die stack 902 and the package-level substrate 904 may be at least partially encapsulated by an encapsulation material 914 (e.g., a molding resin compound, etc.) to prevent electrical contact therewith and to provide mechanical strength and protection for the components.

[0038] Although the semiconductor device assembly has been illustrated and described in the foregoing example embodiments as including semiconductor dies of a particular configuration, in other embodiments, the assembly may include semiconductor dies of a different configuration. For example, the semiconductor device assembly described in any of the foregoing examples may be implemented mutatis mutandis with, for example, additional semiconductor dies in a semiconductor die stack or multiple semiconductor die stacks. Any additional semiconductor die or semiconductor die stack may be coupled to the other dies in the assembly using similar techniques as described for semiconductor die stack 902.

[0039] According to one aspect of the present disclosure, Figure 1-9 The semiconductor devices described in the components of the present disclosure may be memory dies, such as DRAM dies, NAND memory dies, NOR memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, and the like. In embodiments where multiple dies are provided in a single component, the semiconductor device may include memory dies of the same type (e.g., two NANDs, two DRAMs, etc.) or memory dies of different types (e.g., one DRAM and one NAND, etc.). For example, the semiconductor device may be a 3D NAND or 3D DRAM device. According to another aspect of the present disclosure, the semiconductor dies of the components illustrated and described above may be logic dies (e.g., a controller die, a processor die, etc.), or a mix of logic and memory dies (e.g., a memory controller die and a memory die controlled by it). For example, the semiconductor device may include multiple stacks of logic dies and memory dies (e.g., DRAMs, NANDs, etc.) coupled thereto.

[0040] References Figure 1-9 Any of the described semiconductor devices and semiconductor device components may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is Figure 10 1. The system 1000 is schematically shown in FIG. The system 1000 may include a semiconductor device component 1002 (e.g., a discrete semiconductor device), a power supply 1004, a driver 1006, a processor 1008, and / or other subsystems or components 1010. The semiconductor device component 1002 may include the same subsystems or components as described above with reference to FIG. Figure 1-9 The features of the semiconductor device components described are generally similar features. The resulting system 1000 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, a representative system 1000 may include, but is not limited to, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, and a digital audio player), a computer, a vehicle, an appliance, or other product. The components of system 1000 can be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). The components of system 1000 can also include remote devices and any of a wide variety of computer-readable media.

[0041] Figure 11 A method 1100 for assembling a semiconductor device according to an embodiment of the present technology is described. Although described with a specific configuration, one or more operations of the method 1100 may be omitted, repeated, or reorganized. In addition, the method 1100 may include Figure 11 Other operations not described herein, such as operations detailed in one or more other methods described herein.

[0042] At 1102, a semiconductor substrate is provided. The semiconductor substrate includes a first side, a plurality of die locations implementing a plurality of semiconductor dies, scribe line regions interleaved between the plurality of semiconductor dies, and a peripheral region located near a periphery of the semiconductor substrate and surrounding the plurality of die locations. In some cases, the substrate is a semiconductor wafer.

[0043] At 1104, a first passivation material is disposed at a first side of the semiconductor substrate in a position vertically aligned with the active area (e.g., along an axis perpendicular to the first side of the semiconductor substrate). In some cases, the first passivation material may be disposed only at a plurality of die locations. In other cases, the first passivation material is disposed across the entire first surface, and portions of the first passivation material are removed to leave only portions corresponding to the plurality of die locations. The first passivation material may comprise an insulating material, such as a dielectric material. In various aspects, the first passivation material may comprise the same dielectric material as that used to insulate through-substrate TSVs. For example, the first passivation material may comprise silicon oxide or silicon oxidized carbon. As a result, the TSV formation process and other assembly processes may be more predictable and produce a higher yield.

[0044] At 1106, a second passivation material is placed at a first side in positions corresponding to the scribe line area and the peripheral area. In some cases, the second passivation material may be placed only in the scribe line area and the peripheral area. In other cases, the first passivation material spans the exposed portion of the first surface and is placed above the first passivation material. The second passivation material can then be thinned to expose the first passivation material and a bonding surface is implemented, which has the first passivation material at multiple die positions and the second passivation material at the scribe line area and the peripheral area. The second passivation material may include an insulating material, such as a dielectric material. In various aspects, the second passivation material may have a higher bonding energy than the first passivation material. For example, the second passivation material may include silicon carbonitride or a HARP dielectric. Therefore, the bonded parts between semiconductor substrates using the second passivation material may be more difficult to separate, and the occurrence of gaps can be limited.

[0045] Once the passivation material is applied to the semiconductor substrate, the semiconductor substrate can be coupled to another semiconductor substrate that implements a similar passivation material. The coupled substrate can couple to corresponding dies on the substrate. Furthermore, the scribe lines can be aligned during coupling. The substrates can be coupled via the passivation material, for example, by fusion or hybrid bonding.

[0046] Once bonded, the semiconductor substrate and the additional semiconductor substrate can be sawed at the scribe line regions. Sawing the wafer can singulate individual semiconductor die stacks that can be packaged into various electronic devices. In some cases, sawing the semiconductor substrate can remove the scribe line regions and peripheral regions, leaving only the semiconductor dies bonded via the first passivation material. Thus, the techniques disclosed herein can improve reliability in the semiconductor bonding process (e.g., by limiting the occurrence of voids and maintaining consistency in the assembly process) while minimizing changes in the resulting semiconductor devices.

[0047] Several embodiments of semiconductor devices and specific details of associated systems and methods are described above. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. Furthermore, unless the context indicates otherwise, conventional semiconductor fabrication techniques may be used to form the structures disclosed herein. Materials may be deposited, for example, using dispensing, CVD, PVD, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, CMP, drilling, or other suitable techniques.

[0048] The technology disclosed herein relates to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. In addition, the term "semiconductor device" may refer to a finished device or to a component or other structure at various processing stages before becoming a finished device. Depending on the context of use, the term "substrate" may refer to a structure that supports an electronic component (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die for die stacking or three-dimensional integration (3DI) applications.

[0049] The devices including memory devices discussed herein can be formed on a semiconductor substrate or die, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be an SOI substrate, such as SOG or SOP, or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0050] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing a function may also be physically located at various locations, including distribution such that parts of the function are implemented at different physical locations.

[0051] As used herein, "or," including as used in the claims, as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0052] As used herein, the terms "vertical," "horizontal," "upper," "lower," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figures. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, over / below, up / down, and left / right may be interchanged depending on the orientation.

[0053] It should be understood from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Specifically, in the foregoing description, many specific details have been discussed to provide a thorough and inspiring description of embodiments of the present invention. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other cases, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid confusing other aspects of the technology. In general, it should be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may be within the scope of the present invention.

Claims

1. A semiconductor device assembly comprising: A semiconductor substrate comprising: a first surface; a plurality of die sites at which a plurality of semiconductor dies are implemented; scribe line regions that intersect between the plurality of die locations; and a peripheral region located near a periphery of the semiconductor substrate and surrounding the plurality of die locations; a first passivation material disposed at the first surface and vertically aligned with the plurality of die locations; and a second passivation material disposed at the first surface and vertically aligned with the scribe line and the peripheral region, the second passivation material being different from the first passivation material, The first passivation material and the second passivation material are implemented on the bonding surface of the semiconductor device component. 2 . The semiconductor device assembly of claim 1 , wherein a bonding energy of the second passivation material is higher than a bonding energy of the first passivation material. The semiconductor device assembly of claim 1 , wherein the first passivation material comprises silicon oxide. The semiconductor device assembly of claim 1 , wherein the first passivation material comprises silicon carbon oxide. The semiconductor device assembly of claim 1 , wherein the second passivation material comprises silicon carbonitride.

6. The semiconductor device assembly of claim 1, wherein the second passivation material comprises a high aspect ratio process (HARP) dielectric.

7. A method comprising: Providing a semiconductor substrate comprising: a first side, a plurality of die locations implementing a plurality of semiconductor dies, scribe line regions interleaved between the plurality of die locations, and a peripheral region located near a periphery of the semiconductor substrate and surrounding the plurality of die locations; disposing a first passivation material at the first side and vertically aligned with the plurality of die locations; and disposing a second passivation material at the first side and vertically aligned with the scribe line region and the peripheral region, the second passivation material being different from the first passivation material, The first passivation material and the second passivation material are exposed to implement a bonding surface. 8 . The method of claim 7 , further comprising planarizing the first passivation material and the second passivation material to expose the first passivation material and the second passivation material at the bonding surface.

9. The method according to claim 7, further comprising: disposing the first passivation material at the first side and in vertical alignment with the plurality of die sites, the scribe line region, and the peripheral region; as well as A portion of the first passivation material vertically aligned with the scribe line region and the peripheral region is removed such that the first passivation material is vertically aligned with the plurality of die locations.

10. The method according to claim 9, further comprising: disposing the second passivation material at the first side and over the first passivation material; as well as A portion of the second passivation material disposed over the first passivation material is removed such that the first passivation material is exposed at the bonding surface and the second passivation material is vertically aligned with the scribe line region and the peripheral region.

11. The method according to claim 7, further comprising: providing a second semiconductor substrate comprising: a second side, a second plurality of die locations corresponding to the plurality of die locations, a second scribe line region corresponding to the scribe line region, and a second peripheral region corresponding to the peripheral region; disposing a third passivation material at the second side and vertically aligned with the second plurality of die locations, wherein the third passivation material and the first passivation material are the same material; disposing a fourth passivation material at the second side and vertically aligned with the second scribe line region and the second peripheral region, wherein the fourth passivation material and the second passivation material are the same material, wherein the third passivation material and the fourth passivation material are exposed to implement a second bonding surface; and The semiconductor substrate and the second semiconductor substrate are coupled at the bonding surface and the second bonding surface such that the first passivation material is coupled with the third passivation material and the second passivation material is coupled with the fourth passivation material.

12. The method according to claim 11, wherein: A back-end line layer of a first semiconductor die of the plurality of semiconductor dies is disposed at the first side; and The method further comprises: creating an opening through the second semiconductor substrate, the first passivation material, and the third passivation material to expose the back-end wiring layer of the first semiconductor die; and Conductive material is disposed in the opening to implement a via coupled with the back end wiring layer of the first semiconductor die.

13. The method according to claim 11, further comprising: The semiconductor substrate, the second semiconductor substrate, the second passivation material, and the fourth passivation material are sawed at the scribe line region and the second scribe line region to singulate each of the plurality of semiconductor dies.

14. The method of claim 7, wherein a bonding energy of the second passivation material is higher than a bonding energy of the first passivation material. The method of claim 7 , wherein the first passivation material comprises silicon oxide. The method of claim 7 , wherein the second passivation material comprises silicon carbonitride.

17. A semiconductor wafer comprising: a first surface; a plurality of die sites at which a plurality of semiconductor dies are implemented; scribe line regions that intersect between the plurality of die locations; a peripheral region located near a periphery of the semiconductor wafer and surrounding the plurality of die locations; as well as A passivation material layer is disposed at the first surface, the passivation material layer including a first passivation material vertically aligned with the plurality of die locations and a second passivation material vertically aligned with the scribe line region and the peripheral region, the second passivation material being different from the first passivation material. The semiconductor wafer of claim 17 , wherein a bonding energy of the second passivation material is higher than a bonding energy of the first passivation material. The semiconductor wafer of claim 17 , wherein the first passivation material comprises silicon oxide.

20. The semiconductor wafer of claim 17, wherein the second passivation material comprises silicon carbonitride.

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