Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the semiconductor package are provided. The semiconductor package includes: an intermediate line layer including a first connection pad extending in a horizontal direction; a plurality of first chips stacked on the first connection pads and spaced apart from the first connection pads, the plurality of first chips being electrically connected to the first connection pads through first bonding wires; the plurality of second chips are stacked on the plurality of first chips, and the plurality of second chips are electrically connected to the first connecting pads through second bonding wires; a molding layer encapsulating the intermediate circuit layer, the plurality of first chips, the first bonding wires, the plurality of second chips and the second bonding wires; a redistribution layer on the molding layer; and a first via formed in the molding layer by a broken second bonding wire among the second bonding wires and electrically connecting the plurality of first chips and the plurality of second chips to the redistribution layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips stacked therein. Background Art

[0002] A semiconductor package includes an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, a semiconductor package is formed by mounting the semiconductor chip on a printed circuit board and electrically connecting the semiconductor chip using bonding wires or bumps. With the development of the electronics industry, semiconductor packages may be required to achieve high-capacity characteristics. Furthermore, as electronic products have become smaller, the demand for smaller semiconductor packages has increased.

[0003] However, in existing semiconductor packages, when multiple stacked semiconductor chips are connected by leads, the leads occupy a large amount of space in the horizontal direction. Especially for stacked structures with flip-chip and wire bonding processes, there is a possibility of short circuits occurring between wires that are tilted to one side or between leads.

[0004] Therefore, there is a need to provide a semiconductor package with improved characteristics. Summary of the Invention

[0005] In order to solve the above problems, the present disclosure provides a semiconductor package and a method of manufacturing the semiconductor package.

[0006] According to one aspect of the present disclosure, a semiconductor package is provided, which includes: an intermediate circuit layer, including a first connection pad extending in a horizontal direction, the first connection pad including an upper surface and a lower surface opposite to each other in a vertical direction; a plurality of first chips, stacked on one side of the upper surface of the first connection pad and spaced apart from the first connection pad in the horizontal direction, the plurality of first chips being electrically connected to the first connection pad through a first bonding wire; a plurality of second chips, stacked on the plurality of first chips on one side of the lower surface of the first connection pad, the plurality of second chips being electrically connected to the first connection pad through a second bonding wire; a molding layer, encapsulating the intermediate circuit layer, the plurality of first chips, the first bonding wire, the plurality of second chips and the second bonding wire; a redistribution layer, arranged on the lower surface of the molding layer; and a first via, formed in the molding layer by a disconnected second bonding wire among the second bonding wires, and electrically connecting the plurality of first chips and the plurality of second chips to the redistribution layer.

[0007] According to some embodiments of the present disclosure, the disconnected second bonding wire may include a first portion and a second portion. The first portion may form a first portion of the first via. The second portion may form a second portion of the first via. The first and second portions of the first via may electrically connect the first connection pad and a bottommost second chip of the plurality of second chips to the redistribution layer, respectively.

[0008] According to some embodiments of the present disclosure, the semiconductor package may further include a second via. The second via may be formed in the mold layer by a disconnected third bonding wire. The disconnected third bonding wire may include a third portion and a fourth portion, the third portion may form a first portion of the second via, and the fourth portion may form a second portion of the second via.

[0009] According to some embodiments of the present disclosure, the semiconductor package may further include a third chip. The third chip may be disposed on one side of the lower surface of the first connection pad and may be spaced apart from the plurality of second chips in the horizontal direction. The third chip may be electrically connected to the redistribution layer through the second portion of the second via.

[0010] According to some embodiments of the present disclosure, the intermediate wiring layer may further include a second connection pad. The second connection pad may extend in the horizontal direction, the second connection pad and the first connection pad may be on opposite sides of the plurality of first chips along the horizontal direction, and the second connection pad may be electrically connected to the redistribution layer through the second via.

[0011] According to some embodiments of the present disclosure, an upper surface of each of the first connection pad, the second connection pad, and the third chip may be at the same level as an upper surface of an uppermost second chip of the plurality of second chips.

[0012] According to some embodiments of the present disclosure, the plurality of first chips may be stacked with their active surfaces facing upward to form a stepped structure. The plurality of second chips may be stacked with their active surfaces facing downward and their side surfaces aligned with each other. The third chip may be arranged horizontally between the second connection pads and the plurality of second chips with its active surface facing downward.

[0013] According to some embodiments of the present disclosure, the uppermost second chip among the plurality of second chips may contact the lower surface of the first connection pad.

[0014] According to some embodiments of the present disclosure, an end portion of the disconnected second bonding wire and an end portion of the disconnected third bonding wire may be respectively exposed to the mold layer and electrically connected to the redistribution layer.

[0015] According to some embodiments of the present disclosure, the mold layer includes: a first mold layer encapsulating the plurality of first chips and the first bonding wires on the upper surface of the first connection pad; and a second mold layer encapsulating the plurality of second chips, the third chip, the third bonding wires, the second bonding wires, the first vias, and the second vias on the lower surface of the first connection pad. The intermediate wiring layer may be vertically disposed at an interface between the first and second mold layers.

[0016] According to some embodiments of the present disclosure, the first mold layer and the second mold layer may include different materials and / or have different thicknesses from each other.

[0017] According to some embodiments of the present disclosure, the semiconductor package may further include: an external connection terminal disposed on a lower surface of the redistribution layer and electrically connected to the intermediate wiring layer through the first via and the second via.

[0018] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package is provided, the method comprising: providing an intermediate circuit layer on a substrate, the intermediate circuit layer comprising first connection pads extending in a horizontal direction, the first connection pads comprising an upper surface and a lower surface opposite to each other in a vertical direction; stacking a plurality of first chips on the substrate on one side of the upper surface of the first connection pads, and electrically connecting the plurality of first chips to the first connection pads via a plurality of first bonding wires; forming a first mold layer to encapsulate the plurality of first chips and the plurality of first bonding wires on one side of the upper surface of the first connection pads; removing an upper portion of the first mold layer so that a first bonding wire among the plurality of first bonding wires is disconnected to form a first via hole; removing the first mold layer The method comprises the following steps: inverting the structure obtained after forming the upper part of the first connection pad by molding the upper portion of the first molding layer, removing the substrate, so that the lower surface of the first connection pad faces upward and is exposed to the first molding layer; stacking a plurality of second chips on the plurality of first chips on one side of the lower surface of the first connection pad, and electrically connecting the plurality of second chips to the first connection pad through a plurality of second bonding wires; forming a second molding layer to encapsulate the plurality of second chips and the plurality of second bonding wires on one side of the lower surface of the first connection pad, wherein the intermediate circuit layer is arranged on the interface between the first molding layer and the second molding layer; and arranging a redistribution layer on the first molding layer, so that the plurality of first chips and the plurality of second chips are electrically connected to the redistribution layer through the first vias.

[0019] According to some embodiments of the present disclosure, the disconnected first bonding wire may include a first portion and a second portion, wherein the first portion may form a first portion of the first via, and the second portion may form a second portion of the first via. The first portion and the second portion of the first via may electrically connect the first connection pad and a lowermost second chip of the plurality of second chips to the redistribution layer, respectively.

[0020] According to some embodiments of the present disclosure, the intermediate wiring layer may further include a second connection pad. The second connection pad may extend in the horizontal direction, and the second connection pad and the first connection pad are arranged on opposite sides of the plurality of first chips along the horizontal direction.

[0021] According to some embodiments of the present disclosure, a third chip may be disposed on the substrate on one side of the upper surface of the first connection pad, and the third chip may be electrically connected to the second connection pad via a third bonding wire. The third chip may be spaced apart from the plurality of first chips in the horizontal direction.

[0022] According to some embodiments of the present disclosure, while removing the upper portion of the first mold layer, the third bonding wire may be disconnected to form a second via. The disconnected third bonding wire may include a third portion and a fourth portion, the third portion may form the first portion of the second via, and the fourth portion may form the second portion of the second via.

[0023] According to some embodiments of the present disclosure, the step of disposing the redistribution layer on the first mold layer may further include electrically connecting the second connection pad and the third chip to the redistribution layer through the first portion and the second portion of the second via, respectively.

[0024] According to some embodiments of the present disclosure, after removing the substrate, an upper surface of each of the first connection pads, the second connection pads, and the third chip may be located at the same level as an upper surface of an uppermost first chip among the plurality of first chips.

[0025] According to some embodiments of the present disclosure, when arranging the plurality of first chips, the plurality of first chips may be stacked with their active surfaces facing upward and their side surfaces aligned with each other. When arranging the plurality of second chips, the plurality of second chips may be stacked with their active surfaces facing upward and forming a stepped structure. When arranging the third chip, the third chip may be arranged horizontally between the second connection pads and the plurality of first chips with its active surface facing upward.

[0026] According to some embodiments of the present disclosure, the method may further include: providing an external connection terminal on a lower surface of the redistribution layer, such that the external connection terminal is electrically connected to the intermediate line layer through the first via and the second via.

[0027] According to some embodiments of the present disclosure, an end portion of the disconnected first bonding wire and an end portion of the disconnected third bonding wire may be respectively exposed to the first mold layer and electrically connected to a redistribution layer.

[0028] According to some embodiments of the present disclosure, the first mold layer and the second mold layer may include different materials and / or have different thicknesses from each other.

[0029] According to some embodiments of the present disclosure, the uppermost first chip of the plurality of first chips may contact the upper surface of the first connection pad, and the plurality of second chips may be spaced apart from the first connection pad in the horizontal direction.

[0030] According to some example embodiments, a semiconductor package includes: an intermediate wiring layer having a first connection pad and a second connection pad, each extending in a first direction; a plurality of first chips on a first surface side of the intermediate wiring layer and between the first connection pad and the second connection pad, the plurality of first chips being electrically connected to the first connection pads through a plurality of first bonding wires; a plurality of second chips on a second surface side of the intermediate wiring layer, the second surface side being opposite to the first surface side, and the plurality of second chips being electrically connected to the first connection pads through a plurality of second bonding wires; and a first molding layer encapsulating the plurality of second chips on the first surface side of the intermediate wiring layer. a chip and the plurality of first bonding wires; a second mold layer encapsulating the plurality of second chips and the plurality of second bonding wires on one side of the second surface of the intermediate wiring layer; a redistribution layer on the second mold layer; a first via at least partially defined by a second bonding wire among the plurality of second bonding wires in the second mold layer, the first via electrically connecting the plurality of second chips to the redistribution layer; a second via at least partially defined by a third bonding wire in the second mold layer; and a third chip on one side of the second surface of the intermediate wiring layer and spaced apart from the plurality of second chips, the third chip electrically connected to the redistribution layer through the second via.

[0031] According to some example embodiments, the second bonding wire includes a first portion and a second portion, the first portion defining a first portion of the first via, the second portion defining a second portion of the first via, the first portion of the second bonding wire electrically connecting the first connection pad to the redistribution layer, and the second portion of the second bonding wire electrically connecting the second chip of the plurality of second chips to the redistribution layer.

[0032] According to some example embodiments, the first connection pad and the second connection pad are on opposite sides of the plurality of first chips, and the second connection pad is electrically connected to the redistribution layer through a second via.

[0033] According to some example embodiments, the plurality of first chips are stacked to have a stepped structure with active surfaces facing upward, the plurality of second chips are stacked with side surfaces aligned with each other with active surfaces facing downward, and a third chip is between the second connection pad and the plurality of second chips with an active surface facing downward. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects and features of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings.

[0035] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0036] Figure 2 is a cross-sectional view of a semiconductor package according to a comparative example.

[0037] Figure 3 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0038] Figures 4 to 7 are cross-sectional views of intermediate structures corresponding to intermediate steps of a method for fabricating a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Hereinafter, example embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. However, the example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the exemplary embodiments to those skilled in the art. The present invention is not limited to the above-described embodiments, and various variations and modifications may be made without departing from the scope of the invention.

[0040] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "on" may be used herein to describe the relationship of one element to other elements as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings were turned over, an element previously described as "below" or "beneath" another element would then be oriented "above" the other element.

[0041] It will be understood that although the terms "first," "second," "third," "fourth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below could be termed the second element without departing from the teachings of the present disclosure.

[0042] Additionally, it will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.

[0043] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0044] Reference Figure 1 The semiconductor package 10 may include: an intermediate circuit layer 100, a plurality of first chips 200-1, 200-2 and 200-3 (collectively referred to as first chips 200), a plurality of second chips 300-1, 300-2 and 300-3 (collectively referred to as second chips 300), a molding layer 400, a redistribution layer 500 and / or a first via 713.

[0045] The middle line layer 100 may include a first connection pad 110 and a second connection pad 120 extending in the horizontal direction DR1, the first connection pad 110 and the second connection pad 120 may each include an upper surface and a lower surface opposite to each other in the vertical direction DR2, and the second connection pad 120 may be spaced apart from the first connection pad 110 in the horizontal direction DR1.

[0046] The plurality of first chips 200 may be stacked vertically on one side of the upper surface of the first connection pad 110 so that the active surfaces of the plurality of first chips 200 face upward, and the plurality of first chips 200 are stacked to form a stepped structure. Here, the “upper surface side” of the first connection pad 110 refers to the upper space above the upper surface of the first connection pad 110. The plurality of first chips 200 may be spaced apart from the first connection pad 110 in the horizontal direction DR1. The plurality of first chips 200 may be electrically connected to the first connection pad 110 through the first bonding wire 210. The second connection pad 120 and the first connection pad 110 may be arranged on opposite sides of the plurality of first chips 200. In another embodiment, Figure 1 Unlike what is shown in FIG, a plurality of first chips 200 may be stacked on one side of the upper surface of the first connection pad 110 in alignment with each other.

[0047] A plurality of second chips 300 can be vertically stacked on the plurality of first chips 200 on one side of the lower surface of the first connection pad 110, so that the active surfaces of the plurality of second chips 300 face downward (for example, in the negative DR2 direction), and the side surfaces (or ends) of the plurality of second chips 300 can be aligned with each other. Here, the "lower surface side" of the first connection pad 110 refers to the lower space below the lower surface of the first connection pad 110. The lower space and the upper space can be axially symmetrical with respect to a straight line along which the first connection pad 110 and the second connection pad 120 extend in the horizontal direction DR1. The plurality of second chips 300 can be electrically connected to the first connection pad 110 through the second bonding wire 310. In an embodiment, the uppermost second chip among the plurality of second chips 300 (for example, the second chip 300-1 closest to the plurality of first chips 200) can contact the lower surface of the first connection pad 110. In another embodiment, Figure 1 Unlike what is shown in , the plurality of second chips 300 may be vertically stacked on the plurality of first chips 200 in a stair structure.

[0048] In embodiments, the plurality of first chips 200 and second chips 300 may include the same or different types of semiconductor chips (such as DRAM chips and NAND chips).

[0049] The mold layer 400 may encapsulate the intermediate circuit layer 100, the plurality of first chips 200, the first bonding wires 210, the plurality of second chips 300, and / or the second bonding wires 310. In an embodiment, the mold layer 400 may include a first mold layer 410 and a second mold layer 420. The first mold layer 410 may encapsulate the plurality of first chips 200 and the first bonding wires 210 on the upper surface side of the first connection pad 110. The second mold layer 420 may encapsulate the plurality of second chips 300, the second bonding wires 310, and the first vias 713 on the lower surface side of the first connection pad 110. The intermediate circuit layer 100 may be disposed at the interface between the first mold layer 410 and the second mold layer 420 and may be completely encapsulated by the first mold layer 410 and the second mold layer 420.

[0050] The first and second mold layers 410 and 420 may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide resin), or a mixture of a thermosetting resin or a thermoplastic resin with an inorganic filler. In embodiments, the first and second mold layers 410 and 420 may include different materials. For example, the second mold layer 420 may include a material having greater rigidity than the first mold layer 410. In another embodiment, the first and second mold layers 410 and 420 may have different thicknesses. For example, the thickness of the first mold layer 410 may be greater than the thickness of the second mold layer 420. In semiconductor packages according to embodiments, by providing first and second mold layers 410 and 420 having different thicknesses and / or comprising different materials, overall warpage of the semiconductor package may be reduced or minimized.

[0051] The redistribution layer 500 may be provided on the lower surface of the mold layer 400. The redistribution layer 500 may be provided as a single layer or a multilayer structure. Although not shown, the redistribution layer 500 may be included in the substrate. Although not shown, the redistribution layer 500 may include a plurality of wiring patterns, a plurality of vias, and an interlayer insulating layer.

[0052] In the mold layer 400, a first via 713 may be formed by a disconnected second bond wire 311 among the second bond wires 310. The first via 713 may electrically connect the plurality of first chips 200 and the plurality of second chips 300 to the redistribution layer 500. In an embodiment, the disconnected second bond wire 311 may be the lowermost second bond wire among the second bond wires 310 (e.g., the bond wire furthest from the intermediate wiring layer 100 in the negative DR2 direction). In an embodiment, the disconnected second bond wire 311 may include a first portion 311A and a second portion 311B. The first portion 311A may form a first part of the first via 713, and the second portion 311B may form a second part of the first via 713. The first portion formed by the first portion 311A and the second portion formed by the second portion 311B may electrically connect the first connection pad 110 and the lowermost second chip 300-3 among the plurality of second chips 300 to the redistribution layer 500, respectively. In this case, the plurality of second chips 300 can be connected to the redistribution layer 500 via the second bonding wires 310, the first connection pads 110, and the second portion formed by the second portion 311B. In addition, the lowermost second chip 300-3 among the plurality of second chips 300 can be connected to the redistribution layer 500 through the first portion of the first via 713, and the second chips 300-1 and 300-2 among the plurality of second chips 300 can be connected to the redistribution layer 500 via the second bonding wires 310, the first connection pads 110, and the second portion of the first via 713.

[0053] In an embodiment, the semiconductor package 10 may further include a third chip 600. The third chip 600 may be a controller chip, but is not limited thereto. On the lower surface side of the first connection pad 110, the third chip 600 may be arranged between the second connection pad 120 and the plurality of second chips 300 with the active surface facing downward, and spaced apart from the plurality of second chips 300 in the horizontal direction DR1.

[0054] The semiconductor package 10 may further include a second via 711. The second via 711 may be formed in the mold layer 400 by the disconnected third bonding wire 611. The disconnected third bonding wire 611 may include a third portion 611A and a fourth portion 611B. The third portion 611A may form a first portion of the second via 711, and the fourth portion 611B may form a second portion of the second via 711. The second connection pad 120 of the intermediate wiring layer 100 may be electrically connected to the redistribution layer 500 via the first portion of the second via 711. The third chip 600 may be electrically connected to the redistribution layer 500 via the second portion of the second via 711.

[0055] In an embodiment, an upper surface of each of the first connection pad 110 , the second connection pad 120 , and the third chip 600 may be located at the same level as an upper surface of the uppermost second chip 300 - 1 among the plurality of second chips 300 .

[0056] In an embodiment, ends of the disconnected second bonding wire 311 (e.g., the first portion 311A and the second portion 311B) and ends of the disconnected third bonding wire 611 (e.g., the third portion 611A and the fourth portion 611B) may be respectively exposed to the mold layer 400 at the same level (e.g., may be exposed from the lower surface of the second mold layer 420 at the same level) and electrically connected to the redistribution layer 500 disposed on the mold layer 400.

[0057] In addition, in an embodiment, the semiconductor package 10 may further include a plurality of external connection terminals 700 disposed on the lower surface of the redistribution layer 500. The external connection terminals 700 may be electrically connected to the intermediate line layer 100 through the first via hole 713 and the second via hole 711. Figure 1 As shown, the first portion 311A, the second portion 311B, the third portion 611A, and the fourth portion 611B may each be connected to a corresponding external connection terminal 700. The external connection terminal 700 may also electrically connect the semiconductor package 10 to an external device.

[0058] Figure 2 2 is a cross-sectional view of a semiconductor package according to a comparative example. Hereinafter, the distinguishing features of the semiconductor package 20 according to the comparative example and the semiconductor package 10 according to the embodiment of the present disclosure will be mainly described.

[0059] Reference Figure 2 , the semiconductor package 20 may include Figure 1 The first chip 200, the second chip 300, the third chip 600, the first bonding wires 210, the second bonding wires 310, the redistribution layer 500, and the external connection terminals 700 in the semiconductor package 10 shown are the first chip 200a, the second chip 300a, the third chip 600a, the first bonding wires 210a, the second bonding wires 310a, the redistribution layer 500a, and the external connection terminals 700. In addition, unlike the semiconductor package 10, the semiconductor package 20 may further include a substrate SUB, bumps BP, an underfill resin CUF, a first spacer SP1, and a second spacer SP2.

[0060] The first spacer SP1 and the second spacer SP2 may be spaced apart from each other and disposed on the substrate SUB. The first chip 200a and the second chip 300a may be vertically stacked on the first spacer SP1 and the second spacer SP2 so that the active surfaces face upward, and the first chip 200a and the second chip 300a form a stepped structure. The first chip 200a may be electrically connected to the substrate SUB via a first bonding wire 210a, and the second chip 300a may be electrically connected to the substrate SUB via a second bonding wire 310a.

[0061] The third chip 600a can be electrically connected to the substrate SUB through the bumps BP in a flip-chip manner between the first spacer SP1 and the second spacer SP2. The bumps BP can be fixed by an underfill resin CUF, which can fill or occupy the space between and adjacent to the bumps BP.

[0062] The mold layer 400 a encapsulates the first chip 200 a , the second chip 300 a , the third chip 600 a , the first bonding wires 210 a , the second bonding wires 310 a , the first spacers SP1 , the second spacers SP2 , and the underfill resin CUF on the substrate SUB.

[0063] exist Figure 2 In the semiconductor package 20 shown in FIG, the third chip 600a is encapsulated using an underfill process, which increases the difficulty of the process and prevents the semiconductor package 20 from being reduced to the desired size. In addition, since the chips are all disposed on the substrate SUB, the gap between the bonding wires 210a and 310a used for electrical connection is too small, increasing the risk of short circuits between the bonding wires.

[0064] In the semiconductor package 10 according to the example embodiment of the present disclosure, the first chip 200 and the second chip 300 are arranged on opposite sides of the middle wiring layer 100 in the vertical direction, which can reduce the number of bonding wires of the first bonding wire 210 and the second bonding wire 310, thereby preventing short circuits between the bonding wires.

[0065] Furthermore, in the semiconductor package 10 according to the exemplary embodiment of the present disclosure, by using the disconnected second bonding wire 311 and the disconnected third bonding wire 611 to form the first via 713 and the second via 711, respectively, the intermediate wiring layer 100 can be directly electrically connected to the redistribution layer 500. As a result, the structure and manufacturing process complexity of the semiconductor package can be simplified.

[0066] Furthermore, using disconnected bond wires for electrical connections can reduce manufacturing costs compared to other connection structures, such as through-silicon vias or solder bumps.

[0067] Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present disclosure will be described. Figure 3 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figures 4 to 7 are cross-sectional views of intermediate structures corresponding to intermediate steps of a method for fabricating a semiconductor package according to an embodiment of the present disclosure.

[0068] Figures 3 to 7 The manufacturing method according to some embodiments of the present disclosure is shown. Figure 1 In the following description, when the device is inverted, reference is made to Figure 1 The upper and lower surfaces described will be referred to as the lower and upper surfaces, respectively, or the first element will be referred to as the second element in the process sequence. It is understood that additional embodiments of the method may be Figure 3 Additional operations may be provided before, during, and after the operations in the process, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable, or two or more operations may be performed simultaneously.

[0069] Reference Figure 3 and Figure 4 An intermediate wiring layer 100 may be provided on a substrate SUB_1 (operation S1). Intermediate wiring layer 100 may include a first connection pad 110 and a second connection pad 120 extending in a horizontal direction DR1. First connection pad 110 may include an upper surface and a lower surface opposing each other in a vertical direction DR2. Second connection pad 120 may be spaced apart from first connection pad 110 in the horizontal direction DR1. In embodiments, substrate SUB_1 may be a carrier substrate or a support substrate.

[0070] On the upper surface side of the first connection pad 110, a plurality of second chips 300-1, 300-2 and 300-3 (collectively referred to as second chips 300) may be vertically stacked on the substrate SUB_1 with the active surface facing upward (operation S2). Here, the second chip 300-1 (e.g., Figure 4 The lowermost second chip in the substrate SUB_1 may contact the upper surface of the first connection pad 110. In an embodiment, the plurality of second chips 300 may have side surfaces aligned with one another, and each second chip 300 may be configured to be electrically connected to the first connection pad 110 via corresponding second bonding wires 310-1, 300-2, and 300-3 (collectively referred to as second bonding wires 310). The second connection pad 120 may be provided on or adjacent to a side of the substrate SUB_1 opposite to the side including the plurality of second chips 300. In another embodiment, the plurality of second chips 300 may be vertically stacked in a stepped structure on the substrate SUB_1.

[0071] Furthermore, a third chip 600 may be disposed on the substrate SUB_1 on the upper surface side of the second connection pad 120 (operation S3). The third chip 600 may have an active surface facing upward and may be configured to be electrically connected to the second connection pad 120 via a third bonding wire 611. The third chip 600 may be spaced apart from the plurality of second chips 300 in the horizontal direction DR1 and arranged between the second connection pad 120 and the plurality of second chips 300.

[0072] Subsequently, a second molding process may be performed to form a second molding layer 420 (operation S4 ). The second molding layer 420 may encapsulate (eg, completely encapsulate) the plurality of second chips 300 , the third chip 600 , the second bonding wires 310 , and the third bonding wires 611 on the upper surface side of the first connection pads 110 .

[0073] Reference Figure 3 and Figure 5 , and continue to refer to Figure 4 , the upper portion of the second mold layer 420 may be removed by a planarization process such as grinding or chemical mechanical polishing (operation S5). As a result, the second bonding wire 310-3 among the second bonding wires 310 may be disconnected to form the first via hole 713, and the third bonding wire 611 may be disconnected to form the second via hole 711. In an embodiment, the second bonding wire 310-3 among the second bonding wires 310 may be the disconnected second bonding wire 311. The ends of the disconnected second bonding wire 311 and the ends of the disconnected third bonding wire 611 may be exposed to the surface of the second mold layer 420 (e.g., Figure 5In an embodiment, the disconnected second bonding wire 311 may include a first portion 311A and a second portion 311B. The first portion 311A may form a first portion in the first via 713, and the second portion 311B may form a second portion in the first via 713. The disconnected third bonding wire 611 may include a third portion 611A and a fourth portion 611B. The third portion 611A may form a first portion in the second via 711, and the fourth portion 611B may form a second portion in the second via 711.

[0074] like Figure 5 As shown in FIG, the structure obtained in operation S4 can be inverted and the substrate SUB_1 can be removed (operation S6). The surfaces of the first connection pad 110 and the second connection pad 120 can be (relative to their Figure 4 The upper surface of each of the first connection pads 110, the second connection pads 120, and the third chip 600 may be disposed at the same level as the upper surface of the second chip 300-1 among the plurality of second chips 300 after removing the substrate SUB_1.

[0075] Reference Figure 3 and Figure 6 , on the lower surface side of the first connection pad 110, a plurality of first chips 200 may be vertically stacked in a stepped structure on the plurality of second chips 300 (operation S7). Here, the plurality of first chips 200 may be spaced apart from the first connection pad 110 in the horizontal direction DR1. The plurality of first chips 200 may be configured (with respect to their Figure 6 The first connection pad 110 is electrically connected to the first connection pad 110 through the first bonding wire 210 in a manner that the active surface faces downward.

[0076] Subsequently, a first molding process may be performed to form a first mold layer 410 (operation S8). The first mold layer 410 may encapsulate the plurality of first chips 200 and the first bonding wires 210 on one side of the upper surface of the first connection pads 110. In embodiments, the intermediate circuit layer 100 may be disposed at the interface between the first mold layer 410 and the second mold layer 420. The first and second mold layers 410, 420 may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), or a mixture of a thermosetting resin or a thermoplastic resin with an inorganic filler. The first and second mold layers 410, 420 may include different materials and / or different thicknesses. Furthermore, the first and second mold layers 410, 420 may reduce overall warpage of the semiconductor package.

[0077] A redistribution layer 500 may be provided on the second mold layer 420 (S9). In an embodiment, the plurality of second chips 300 and the plurality of first chips 200 may be electrically connected to the redistribution layer 500 through the first vias 713 (e.g., the first portion of the first via 713 and the second portion of the first via 713 formed by the disconnected second bonding wires 311) and the first connection pads 110, and the second connection pads 120 and the third chip 600 may be electrically connected to the redistribution layer 500 through the second vias 711 (e.g., the first portion of the second via 711 and the second portion of the second via 711 formed by the disconnected third bonding wires 611), respectively.

[0078] Reference Figure 3 and Figure 7 , external connection terminals 700 may be provided on the lower surface of the redistribution layer 500 (operation S10). The external connection terminals 700 may be electrically connected to the intermediate wiring layer 100 through first vias 713 formed by the disconnected second bonding wires 311 and second vias 711 formed by the disconnected third bonding wires 611, respectively. For example, the external connection terminals 700 may be electrically connected to the first connection pads 110 of the intermediate wiring layer 100 through the first vias 713, and may be electrically connected to the second connection pads 120 of the intermediate wiring layer 100 through the second vias 711.

[0079] To summarize and review, in the semiconductor package according to the embodiments of the present disclosure, by arranging multiple first chips and multiple second chips on the upper and lower sides of the intermediate wiring layer (e.g., on opposite sides of the intermediate wiring layer), the number of leads used for electrical connection can be reduced, thereby preventing short circuits in the leads and improving the reliability of the semiconductor package. Furthermore, by providing vias formed by disconnected bonding wires, the intermediate wiring layer can be directly connected to the redistribution layer, thereby simplifying the structure and process complexity of the semiconductor package. Compared to other connection structures (such as through-silicon vias or solder bumps), the disconnected leads used for electrical connection in the semiconductor package according to the embodiments of the present disclosure can reduce manufacturing costs.

[0080] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor package, comprising: an intermediate circuit layer, comprising a first connection pad extending in a horizontal direction, wherein the first connection pad comprises an upper surface and a lower surface opposite to each other in a vertical direction; a plurality of first chips stacked on one side of the upper surface of the first connection pad and spaced apart from the first connection pad in the horizontal direction, the plurality of first chips being electrically connected to the first connection pad through first bonding wires; a plurality of second chips stacked on the plurality of first chips on one side of the lower surface of the first connection pad, the plurality of second chips being electrically connected to the first connection pad via second bonding wires; a molding layer encapsulating the intermediate circuit layer, the plurality of first chips, the first bonding wires, the plurality of second chips, and the second bonding wires; a redistribution layer disposed on the lower surface of the molding layer; as well as A first via is formed in the mold layer by a disconnected second bonding wire among the second bonding wires and electrically connects the plurality of first chips and the plurality of second chips to the redistribution layer.

2. The semiconductor package according to claim 1, wherein The disconnected second bonding wire includes a first portion and a second portion, the first portion forming a first portion of the first via hole in the first via hole, the second portion forming a second portion of the first via hole in the first via hole, and The first portion of the first vias and the second portion of the first vias electrically connect the first connection pad and the bottommost second chip of the plurality of second chips to the redistribution layer, respectively.

3. The semiconductor package according to claim 1, wherein The semiconductor package further includes a second via hole, and The second via is formed in the mold layer by a disconnected third bonding wire, the disconnected third bonding wire includes a third portion and a fourth portion, the third portion forms a first portion of the second via in the second via, and the fourth portion forms a second portion of the second via in the second via.

4. The semiconductor package according to claim 3, wherein The semiconductor package also includes a third chip, which is arranged on one side of the lower surface of the first connection pad and is spaced apart from the plurality of second chips in the horizontal direction. The third chip is electrically connected to the redistribution layer through the second portion of the second vias in the second vias.

5. The semiconductor package according to claim 4, wherein The middle circuit layer further includes a second connection pad, and wherein the second connection pad extends in the horizontal direction, The second connection pads and the first connection pads are on opposite sides of the plurality of first chips along the horizontal direction, and The second connection pad is electrically connected to the redistribution layer through the second via.

6. A method for manufacturing a semiconductor package, comprising: Disposing an intermediate circuit layer on the substrate, the intermediate circuit layer including a first connection pad extending in a horizontal direction, the first connection pad including an upper surface and a lower surface opposite to each other in a vertical direction; On one side of the upper surface of the first connection pad, a plurality of first chips are stacked on the substrate, and the plurality of first chips are electrically connected to the first connection pad through a plurality of first bonding wires; forming a first molding layer to encapsulate the plurality of first chips and the plurality of first bonding wires on one side of the upper surface of the first connection pad; removing an upper portion of the first molding layer so that at least one first bonding wire among the plurality of first bonding wires is disconnected to form a first via hole; inverting the resulting structure obtained after removing the upper portion of the first mold layer, removing the substrate, so that the lower surface of the first connection pad faces upward and is exposed to the first mold layer; On one side of the lower surface of the first connection pad, stacking a plurality of second chips on the plurality of first chips, and electrically connecting the plurality of second chips to the first connection pad through a plurality of second bonding wires; forming a second molding layer to encapsulate the plurality of second chips and the plurality of second bonding wires on one side of the lower surface of the first connection pad, wherein the intermediate circuit layer is provided on an interface between the first molding layer and the second molding layer; as well as A redistribution layer is disposed on the first mold layer, such that the plurality of first chips and the plurality of second chips are electrically connected to the redistribution layer through the first vias.

7. The method according to claim 6, wherein: The disconnected first bonding wire includes a first portion and a second portion, the first portion forming a first portion of the first via hole in the first via hole, the second portion forming a second portion of the first via hole in the first via hole, and The first portion of the first vias and the second portion of the first vias electrically connect the first connection pad and the bottommost second chip of the plurality of second chips to the redistribution layer, respectively.

8. The method according to claim 6, in, The middle circuit layer further includes a second connection pad, and The second connection pads extend in the horizontal direction, and the first connection pads and the second connection pads are arranged on opposite sides of the plurality of first chips along the horizontal direction.

9. The method according to claim 8, further comprising: A third chip is provided on the substrate on the upper surface side of the first connection pad and is electrically connected to the second connection pad through a third bonding wire. The third chip is spaced apart from the plurality of first chips in the horizontal direction.

10. The method according to claim 9, in, while removing the upper portion of the first mold layer, disconnecting the third bonding wire to form a second via hole, and The disconnected third bonding wire includes a third portion and a fourth portion, the third portion forms a first portion of the second via hole in the second via hole, and the fourth portion forms a second portion of the second via hole in the second via hole.

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