Switching stage for a switched mode power supply, SMPS and corresponding method

Abstract

A switching stage of a switched mode power supply (SMPS), the switching stage comprising: a switching element comprising a GaN transistor connected in series with a metal oxide semiconductor (MOS) field effect transistor (FET), thereby defining an intermediate node between the GaN transistor and the MOSFET; a controller arranged to drive a gate terminal of the MOSFET based on a pulse width modulation (PWM) input signal, where the controller comprises a first switching circuit arranged to provide a low ohmic path between the intermediate node and the gate terminal of the MOSFET, and a control circuit arranged to provide a low ohmic path between the intermediate node and the gate terminal of the MOSFET, the control circuit is arranged for controlling the switching circuit based on the PWM input signal.

Description

Technical Field

[0001] The present disclosure relates generally to the field of switched mode power supplies (SMPS), and more particularly to an improved method for driving a gate terminal of a switching element. Background Art

[0002] A conventional boost power factor correction (PFC) converter is a component in power electronics designed to improve the power factor and efficiency of a power supply. Power factor correction can be important in power consumption, especially in applications with non-linear loads, to minimize reactive power and improve overall power utilization.

[0003] In a typical boost PFC converter, the circuit consists of components such as a boost topology, a transformer (and / or inductor), and a controller IC. The primary goal is to shape the input current waveform to be in phase with the input voltage, thereby improving the power factor. This is achieved by operating the boost converter, which increases the input voltage to the required level and shapes the current waveform.

[0004] Transformer T1 in the conventional setup plays a special role. It not only provides isolation between the input and output, but also serves as a means of supplying power to the controller IC. The transformer's secondary winding provides the power rail for the controller IC, ensuring its proper operation.

[0005] Current sensing in traditional designs uses a resistor specifically designed to measure the current in the circuit. The current measured is usually the current flowing through the converter's switching element, a metal oxide semiconductor (MOS) field effect transistor (FET).

[0006] This information can be important for a feedback loop in the controller IC to adjust the duty cycle of the switching element, thereby increasing the power delivered to the load.

[0007] The gate drive strength of the switching element is controlled by the gate resistor. Proper adjustment of this resistor ensures efficient switching and minimizes losses in the power stage. It also affects the overall performance and reliability of the PFC circuit.

[0008] To address the growing demand for power density, industry trends are shifting toward innovative solutions. One notable change involves replacing bulky transformers with low-profile inductors. This reduces the overall size and weight of the PFC converter, meeting the needs of applications where space is at a premium.

[0009] Furthermore, advances in sensing technology have introduced lossless sense FETs, eliminating the need for resistors to sense current. This improves efficiency and reduces losses in PFC circuits, contributing to improved overall performance.

[0010] One disadvantage of the aforementioned controller ICs is that they can cause various types of electromagnetic interference (EMI). Another disadvantage concerns the efficiency of the corresponding SMPS. Summary of the Invention

[0011] It would be advantageous to implement a switching stage of a switched mode power supply SMPS that overcomes at least some of the above-mentioned disadvantages.It would further be advantageous to implement a corresponding SMPS and a method for operating such a switching stage.

[0012] In a first aspect of the present disclosure, there is provided a switching stage of a switched mode power supply (SMPS), the switching stage comprising:

[0013] a switching element comprising a GaN transistor connected in series with a metal oxide semiconductor (MOS) field effect transistor (FET), thereby defining an intermediate node (Vm) between the GaN transistor and the MOSFET;

[0014] - a controller arranged to drive the gate terminal of the MOSFET based on a pulse width modulated PWM input signal;

[0015] The controller comprises:

[0016] - a first switching circuit ("M2") arranged to provide a low-ohmic path between the intermediate node and the gate terminal of the MOSFET;

[0017] - a control circuit ("state machine") arranged for controlling the switching circuit based on the PWM input signal.

[0018] To better understand the concepts presented in this disclosure, let's first examine in more detail a conventional controller used to drive the gate terminal of a switching element in a switch-mode power supply. The controller is powered by a supply voltage and controls the gate terminal of a MOSFET based on a pulse-width modulated (PWM) input signal. When the PWM signal is high, the corresponding gate terminal receives a high signal, initiating conduction in the switching element. Conversely, a low PWM signal results in a low signal at the gate terminal, causing the switching element to cease conduction.

[0019] The switching element, typically a MOSFET, can have a gate-source capacitance. During periods of high PWM signals, this capacitance is charged. Once the voltage across the gate-source capacitance exceeds a threshold voltage, the MOSFET enters the "on" or conducting state. The threshold voltage is the minimum value required to establish a conducting channel between the MOSFET's source and drain terminals.

[0020] The inventors have discovered that conventional controllers can generate electromagnetic interference (EMI) during the charging of the gate-source capacitor. The EMI problem is related to the charging profile, specifically the rate of change of the voltage (dv / dt) and / or current (di / dt) supplied to the gate-source capacitor.

[0021] Furthermore, the inventors have noticed that during the on-time of the MOSFET, the parasitic capacitance at the switch node of the switch mode power supply SMPS is undesirably dissipated in the channel of the switching element. In this case, the switch node is usually connected to the drain of the switching element.

[0022] The present disclosure proposes a solution to more efficiently utilize the energy stored in the parasitic capacitance at the switch node. Traditionally, current through the GaN transistor begins (and the stored energy discharges) only when the MOSFET's gate terminal reaches a threshold voltage, signaling the MOSFET to transition to the on-state.

[0023] The present disclosure proposes introducing a low-ohmic path between the intermediate node and the gate terminal of the MOSFET, facilitated by a first switching circuit. This arrangement enables the energy stored in the parasitic capacitance to effectively charge the gate-source capacitance of the MOSFET, improving the use of the stored energy and mitigating EMI issues during the charging process.

[0024] In an example, the switch stage further comprises:

[0025] - Snubber capacitor (Cx);

[0026] - rectifying means (Dx) connected between the intermediate node and the buffer capacitor such that the buffer capacitor is charged from the intermediate node;

[0027] a voltage regulator (LDO) connected to the buffer capacitor and arranged to provide a supply voltage;

[0028] The controller further comprises:

[0029] - a second switching circuit ("M1") arranged to provide a low-ohmic path between the supply voltage and the gate terminal of the MOSFET of the switching element;

[0030] Wherein the control circuit is further arranged for controlling the second switching circuit ("M1") based on the voltage level of the intermediate node and based on the PWM input signal.

[0031] The voltage regulator can be used in a controller to implement various functions in the controller.

[0032] The controller in an SMPS plays a role in regulating the flow of energy in the power system and can be implemented using a variety of electronic components. Microcontrollers (MCUs) are commonly used, offering programmability and flexibility through their integrated CPU and memory. For applications requiring high-speed signal processing and complex control algorithms, digital signal processors (DSPs) may be preferred. Field-programmable gate arrays (FPGAs) offer the flexibility to customize digital circuit implementations, making them suitable for applications such as boost converters with specific control requirements.

[0033] The embodiments disclosed above may be beneficial because the power required for converter operation is drawn from the intermediate node. No additional, separate power supply branch is required to power the controller.

[0034] Energy can be harvested from the intermediate node and stored in a buffer capacitor. Whenever the voltage at the intermediate node is above a certain threshold, energy can be harvested. A rectifying device, such as a diode, ensures that power flows in one direction: from the intermediate node to the buffer capacitor.

[0035] One of the advantages of the SMPS is that it no longer requires a transformer. In the prior art, a transformer is typically used, with the secondary side of the transformer being used to power the controller. The primary side of the transformer acts as an inductor, for example, in a boost converter.

[0036] According to the above, by extracting power from the intermediate node, the implementation of the transformer is alleviated.

[0037] The second switching circuit is arranged to provide a low-ohmic path between the supply voltage and the gate terminal of the MOSFET of the switching element. This allows the gate-source capacitance of the MOSFET of the switching element to charge. In this case, the charging is obtained from the supply voltage provided by the voltage regulator.

[0038] Therefore, the second switching circuit is arranged to utilize the supply voltage obtained from the voltage regulator to charge the gate-source capacitance of the MOSFET of the switching element, and the first switching circuit is arranged to utilize the voltage at the intermediate node, i.e. the charge present in the parasitic capacitance of the switching node of the SMPS, to charge the gate-source capacitance of the MOSFET of the switching element.

[0039] The control circuit may be arranged for controlling the second switching circuit based on a voltage level of the intermediate node and based on the PWM input signal.

[0040] For example, the controller may comprise a first comparator ("comp1") arranged to compare the voltage at the intermediate node with a predefined first reference voltage, wherein the control circuit is arranged to control the second switching circuit ("M1") based on the comparison.

[0041] Therefore, the comparator will determine whether the voltage at the intermediate node will drop below a predefined first reference value.If this is the case, the controller can activate or enable the second switching circuit.

[0042] In a specific example, the first switching circuit includes:

[0043] - a first control MOSFET ("M2"), wherein a drain terminal of said first control MOSFET is connected to said intermediate node, and wherein a source terminal of said first control MOSFET is connected to said gate terminal of said MOSFET of said switching element.

[0044] It should be noted that the body terminal of the first control MOSFET may be connected to ground.

[0045] In another example, the second switching circuit includes:

[0046] - a second control MOSFET ("M1"), wherein a source terminal of said second control MOSFET is connected to said supply voltage, and wherein a drain terminal of said second control MOSFET is connected to said gate terminal of said MOSFET of said switching element.

[0047] In yet another example, a control circuit ("state machine") is further arranged for controlling the first switching circuit based on the PWM input signal and based on a voltage level at the gate terminal of the MOSFET of the switching element.

[0048] In another example, the control circuit further includes:

[0049] - a second comparator ("Comp2") arranged for comparing the voltage level at the gate terminal of the MOSFET of the switching element with a predefined second reference voltage, wherein the control circuit is arranged for controlling the first switching circuit based on the PWM input signal and based on the comparison.

[0050] In a second aspect of the present disclosure, a switched mode power supply (SMPS) is provided, comprising a switching stage according to any of the preceding examples.

[0051] It should be noted that the advantages as explained with respect to the first aspect of the disclosure, ie the switching stage of the switched mode power supply, also apply to the second aspect of the disclosure, ie the switched mode power supply.

[0052] SMPS, or switched-mode power supplies, encompass different types of power converters, each designed for a specific application. Among them is the flyback converter, which utilizes a transformer to store and transfer energy during the switching cycle. A boost converter boosts the input voltage to produce a higher output voltage. A buck converter steps down the input voltage to produce a lower output voltage, often used for voltage regulation. A forward converter uses a transformer to operate with continuous energy transfer during both the on and off cycles. A resonant converter uses a resonant component for soft switching, reducing losses and improving efficiency.

[0053] In a third aspect of the present disclosure, there is provided a method of operating a switch stage according to any of the preceding examples, wherein the method comprises the following steps:

[0054] - The switching circuit is controlled by the control circuit based on the PWM input signal.

[0055] In an example, the controlling step includes:

[0056] - enabling the switching circuit by the control circuit such that the switching circuit provides the low-ohmic path between the intermediate node and the gate terminal of the MOSFET after a transition of the PWM input signal.

[0057] In another example, the method further comprises the steps of:

[0058] The second switching circuit is controlled by the control circuit based on the voltage of the intermediate node and based on the PWM input signal.

[0059] In yet another example, the controller further includes a first comparator ("comp1"), wherein the method further includes the steps of:

[0060] - comparing, by said first comparator ("comp1"), said voltage at said intermediate node with a predefined first reference voltage,

[0061] And wherein the controlling step comprises:

[0062] - controlling the second switching circuit ("M1") by the control circuit based on the comparison.

[0063] In a fourth aspect of the present disclosure, there is provided a computer program product comprising a computer-readable medium having instructions stored thereon, which, when executed by a controller of a switched mode power supply (SMPS), causes the SMPS to implement a method according to any of the examples provided above.

[0064] In the drawings, similar components and / or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a dash and a second reference number, the second reference number being used to distinguish the similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number, regardless of the second reference number.

[0065] The above and other aspects of the disclosure will be apparent from and elucidated with reference to the examples described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 An exemplary prior art cascode GaN device is shown.

[0067] Figure 2 shows a block diagram of a switch mode power supply (SMPS) having a switching stage according to the present disclosure;

[0068] Figure 3 shows a further block diagram of a switch mode power supply SMPS having a switching stage according to the present disclosure;

[0069] Figure 4 shows yet another block diagram of an SMPS having a switching stage according to the present disclosure;

[0070] Figure 5 Shown is the corresponding Figure 3 A timing diagram of the concepts shown in . DETAILED DESCRIPTION

[0071] It should be noted that in the description of the drawings, like reference numerals refer to like like components performing like substantially similar functions.

[0072] A more detailed description will be given with reference to specific examples, some of which are illustrated in the accompanying drawings so that the features of the present disclosure can be more fully understood. It should be noted that the drawings illustrate only typical examples and, therefore, should not be considered to limit the scope of the claimed subject matter. The drawings are incorporated to facilitate understanding of the present disclosure and are therefore not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading the description in conjunction with the accompanying drawings.

[0073] The following description above provides only preferred exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of the preferred exemplary embodiments will provide those skilled in the art with an enabling description for implementing the preferred exemplary embodiments of the present disclosure, and it should be understood that various changes may be made to the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the present disclosure.

[0074] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise," "comprising," and the like are to be interpreted in an inclusive sense, and not in an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to." As used herein, the terms "connected," "coupled," or any variations thereof, mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, electromagnetic, or a combination thereof. Additionally, the words "herein," "on," "below," and words of similar meaning, when used in this application, refer to this application as a whole and not to any particular portion of this application. Where the context permits, words using the singular or plural in the detailed description may also include the plural or singular, respectively. The word "or" referring to a list of two or more items encompasses all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

[0075] These and other changes can be made to the technology in view of the following detailed description. Although the specification describes certain examples of the present technology and describes the expected best mode, no matter how detailed the specification appears, the technology can be practiced in many ways. The details of the system can vary considerably in its specific implementation and still be covered by the technology disclosed herein. As mentioned above, the specific terms used when describing certain features or aspects of the present technology should not be regarded as implying that the term is redefined in this article to be limited to any specific characteristics, features or aspects of the technology associated with the term. In general, unless the detailed description part explicitly defines such terms, the terms used in the appended claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification. Therefore, the actual scope of the present technology covers not only the disclosed examples, but also all equivalent ways of practicing or realizing the technology under the claims.

[0076] Figure 1 An exemplary prior art cascode GaN device is shown. Figure 1A depletion-mode gallium nitride (d-GaN) HEMT is shown with a die-to-die connection to a silicon MOSFET located on top of the GaN HEMT. Since the gate and source of the GaN device are individually connected to the source and drain of the MOSFET in a cascode configuration, the GaN device can be turned off indirectly by turning off the MOSFET device.

[0077] In the device shown, when the GaN device is indirectly turned off by turning off the MOSFET device, the midpoint voltage Vmid-node reaches the absolute value of the GaN threshold voltage VTH (eg, -20V) because Vmid-node = -VGS (of the GaN device).

[0078] Due to package parasitic impedances and capacitance mismatch between the cascode GaN and MOSFET devices, the Vmid-node often experiences overshoot, which can degrade the reliability of the GaN gate. To reduce this reliability degradation, a large capacitor CX is typically integrated into the MOSFET die to mitigate the midpoint voltage overshoot during the off period and also reduce the risk of unwanted cascode turn-on events due to oscillations across the cascode voltage.

[0079] However, during the turn-on transient, the energy stored in capacitor CX is dissipated directly across the MOSFET channel, and if all these settings need to be added, the benefits brought by the GaN device are reduced.

[0080] Therefore, there is a trade-off between reducing overshoot and reducing power loss. A larger capacitor CX results in reduced VM overshoot, but increases the required chip size and increases power loss.

[0081] Furthermore, since the leakage current of a GaN device in the off state is typically higher than that of a MOSFET, a bleeder resistor RX is integrated into the MOSFET die to absorb the GaN leakage current, which undesirably compromises efficiency.

[0082] Figure 2 A modified design for the gate driver circuit in a switched-mode power supply (SMPS) is disclosed, with the goal of improving efficiency and performance. In this design, the energy dissipated during the MOSFET's on-time is offset by energy harvesting from an intermediate node VM, which represents the voltage at a specific point in the circuit.

[0083] This energy harvesting is facilitated by the use of a diode DX and a capacitor CX. The diode ensures energy flows in one direction, and the capacitor accumulates and stores this energy on a cycle-by-cycle basis. Furthermore, the design incorporates current sensing by measuring the MOSFET drain-to-source voltage, VDS, during the channel's on-state, expressed as VDS = RDSON * IDS.

[0084] This measurement provides information about the current flowing through the MOSFET.

[0085] This design offers several advantages over conventional SMPS designs, including higher power density, increased power efficiency, and lower hardware costs. Specifically, the elimination of certain components, such as resistors and transformers for current sensing, offsets the additional cost associated with adding additional GaN devices to the design.

[0086] Overall, this modified design represents an improved approach to SMPS gate driver circuits compared to conventional designs, aiming to optimize energy usage, introduce current sensing functionality, and achieve higher power density at reduced hardware cost.

[0087] Figure 2 Despite the advancements in the cascode GaN module depicted in Figure 3, there are still three potential areas for improvement. First, there is susceptibility to electromagnetic interference (EMI) issues, which is attributed to uncontrollable factors such as di / dt and dv / dt during the switching process. These uncontrollable variables can lead to unwanted EMI issues, indicating the need for mitigation strategies in the design.

[0088] Secondly, there is a problem related to the energy dissipation in Cpar when the inductor current iL1 is positive and the input pulse width modulation (PWM) signal goes high. In this scenario, the energy stored in Cpar is undesirably dissipated across the GaN and MOSFET channels during the turn-on phase of the cascode GaN.

[0089] In this case, Cpar covers the accumulated parasitic capacitance at the switching node Vsw. Addressing this issue can be important for improving energy usage and minimizing losses during switching transitions.

[0090] Third, the negative inductor current iL, combined with the high PWM signal, requires fast turn-on of the MOSFET to mitigate the losses associated with the MOSFET body diode rectification. Therefore, the efficiency of the cascode GaN module depends on the MOSFET's fast response under these specific conditions. Enhanced control and management of these aspects can contribute to overall improvements in the performance and reliability of cascode GaN modules.

[0091] Now refer to Figure 3 .

[0092] The present disclosure is designed to cater to both logic-level (LL) and standard-level (SL) gate metal-oxide-semiconductor field-effect transistor (MOSFET) applications, with particular attention paid to minimizing gate drive losses, especially in the case of LL gate MOSFETs. The MOSFETs and GaN in the system have voltage ratings of 30V and 650V, respectively.

[0093] exist Figure 3 In [1], a block diagram outlines the proposed low-EMI, self-driven GaN concept in a boost power factor correction (PFC) configuration. Here, the body of transistor M2 is connected to ground, a strategy used to disable reverse conduction of its body diode. This connection increases the threshold voltage as the MOSFET gate voltage, VG, increases. Notably, this configuration leverages the characteristics of common complementary metal oxide semiconductor (CMOS) technology.

[0094] According to the present disclosure, a first switching circuit is arranged for providing a low-ohmic path between the intermediate node and the gate terminal of the MOSFET. In this case, the first switching circuit is implemented as a MOSFET M2.

[0095] According to the present disclosure, a second switching circuit is arranged for providing a low-ohmic path between the supply voltage and the gate terminal of the MOSFET of the switching element. In this case, the second switching circuit is implemented as a MOSFET M1.

[0096] refer to Figure 4 .Apart from Figure 3 In addition to the embodiment shown in FIG, an additional diode D1 is placed in series with MOSFET M2 to ensure that there is no conductive path from node Vg to node Vm.

[0097] Figure 5 The principle of the proposed low EMI gate drive is discussed in depth. The conventional gate drive profile and the proposed gate drive profile are represented by MOSFET VGS1 and VGS2 respectively.

[0098] The corresponding GaN drain-to-source currents are denoted as IDS1 and IDS2. When the inductor current iL1 is positive and the input pulse width modulation PWM signal goes high, ie at the switching point, the energy in Cpar is effectively recycled to charge the MOSFET gate CGS.

[0099] This approach prevents energy from being dissipated in the MOSFET channel and instead redirects it through a specific current path involving the main FET's CPAR, GaN, M2, and CGS. As a result, the GaN drain-to-source current, IDS2, undergoes a change at the very beginning of the gate transition, rather than waiting for VG to reach the MOSFET threshold voltage. This modification results in smaller di / dt values, which helps mitigate EMI and reduces switching ringing.

[0100] As VG increases, the M2 source-to-body voltage VSB also increases, resulting in an increase in M2's threshold voltage and channel on-resistance. The intentional design choice of increasing RON_M2 results in a lower charging current, designed to extend the plateau duration. This intentional extension results in a lower dv / dt value, further contributing to EMI mitigation and reduced switching ringing.

[0101] Furthermore, consider the scenario when the intermediate node VM drops from high to low, triggering the state machine to turn on M1. This process quickly charges VG to the final determined value (e.g., 5V), thereby minimizing the high Ron conduction loss. Compared to the conventional blue curve VGS1, as shown by Figure 4 As shown in the curve VGS2 in Figure 3, the adaptive method of the gate driver, that is, the controller, achieves a shorter MOSFET on-time while maintaining smaller di / dt and dv / dt values.

[0102] For negative inductor current iL1 and low intermediate node VM due to body diode conduction, once the input PWM goes high, MOSFET turn-on speed becomes very important to minimize the body diode rectification loss. In this scenario, the comparator COMP1 of the proposed gate driver directly triggers the state machine to turn on M1 by skipping the turn-on of M2, ensuring fast MOSFET turn-on.

[0103] Furthermore, the proposed gate driver, i.e., controller, can be easily configured with senseFET for achieving accurate current sensing functionality, eliminating the need for RSNS. Furthermore, the adaptive gate drive approach eliminates the necessity of gate resistors. Essentially, Figure 3 The embodiments shown in FIG solve this problem by significantly enhancing EMI performance and self-driving capability. Figure 2 any shortcomings.

[0104] By studying the drawings, the disclosure and the appended claims, those skilled in the art can understand and implement other variations to the disclosed embodiments when practicing the claimed invention. The provided drawings and descriptions of the embodiments of the invention are illustrations and explanations of the core of the invention and should not be considered to limit the invention thereto. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are cited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any figure signs in the claims should not be interpreted as limiting their scope.

Claims

1. A switching stage of a switch mode power supply (SMPS), the switching stage comprising: - a switching element comprising a GaN transistor connected in series with a metal oxide semiconductor (MOS) field effect transistor (FET), thereby defining an intermediate node between the GaN transistor and the MOSFET; - a controller arranged to drive the gate terminal of the MOSFET based on a pulse width modulated PWM input signal; The controller comprises: - a first switching circuit arranged to provide a low-ohmic path between the intermediate node and the gate terminal of the MOSFET; - a control circuit arranged for controlling the switching circuit based on the PWM input signal.

2. The switch stage according to claim 1 , wherein the switch stage further comprises: - snubber capacitors; - a rectifying device connected between the intermediate node and the buffer capacitor so that the buffer capacitor is charged from the intermediate node; a voltage regulator connected to the buffer capacitor and arranged to provide a supply voltage; The controller further comprises: - a second switching circuit arranged to provide a low-ohmic path between the supply voltage and the gate terminal of the MOSFET of the switching element; Wherein the control circuit is further arranged to control the second switching circuit based on the voltage level of the intermediate node and based on the PWM input signal.

3. The switching stage of claim 2 , wherein the controller further comprises: - a first comparator arranged for comparing the voltage at the intermediate node with a predefined first reference voltage, wherein the control circuit is arranged for controlling the second switching circuit based on the comparison.

4. The switching stage according to claim 1 , wherein the first switching circuit comprises: - a first control MOSFET, wherein a drain terminal of the first control MOSFET is connected to the intermediate node, and wherein a source terminal of the first control MOSFET is connected to the gate terminal of the MOSFET of the switching element.

5. The switching stage of claim 4, wherein the body terminal of the first control MOSFET is connected to ground.

6. The switching stage according to any of the preceding claims, and at least according to claim 2, wherein the second switching circuit comprises: - a second control MOSFET, wherein a source terminal of the second control MOSFET is connected to the supply voltage, and wherein a drain terminal of the second control MOSFET is connected to the gate terminal of the MOSFET of the switching element.

7. The switching stage according to any of the preceding claims, wherein the control circuit is further arranged for controlling the first switching circuit based on the PWM input signal and on a voltage level at the gate terminal of the MOSFET of the switching element.

8. The switching stage of claim 7 , wherein the control circuit further comprises: - a second comparator arranged for comparing the voltage level at the gate terminal of the MOSFET of the switching element with a predefined second reference voltage, wherein the control circuit is arranged for controlling the switching circuit based on the PWM input signal and based on the comparison.

9. A switched mode power supply (SMPS) comprising a switching stage according to any one of the preceding claims.

10. The SMPS according to claim 9, wherein the SMPS is any one of the following: - Flyback converter; -Boost converter; - Buck converter; - forward converter; -Resonant converter.

11. A method of operating a switching stage according to any one of claims 1 to 8, wherein the method comprises the following steps: - The switching circuit is controlled by the control circuit based on the PWM input signal.

12. The method of claim 11, wherein the controlling step comprises: - enabling the switching circuit by the control circuit such that the switching circuit provides the low-ohmic path between the intermediate node and the gate terminal of the MOSFET after a transition of the PWM input signal.

13. The method according to any one of claims 11 to 12 in combination with claim 2, wherein the method further comprises the following steps: The second switching circuit is controlled by the control circuit based on the voltage of the intermediate node and based on the PWM input signal.

14. The method of claim 13, wherein the controller further comprises a first comparator, wherein the method further comprises the steps of: - comparing, by said first comparator, said voltage at said intermediate node with a predefined first reference voltage, And wherein the controlling step comprises: - controlling the second switching circuit by the control circuit based on the comparison.

15. A computer program product comprising a computer readable medium having instructions stored thereon, which, when executed by a controller of a switched mode power supply (SMPS), cause the SMPS to implement the method according to any one of claims 11 to 14.

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