Control method, device, equipment and product for dual three-level inverter

Abstract

This invention discloses a control method, apparatus, device, and product for a dual three-level inverter, comprising: acquiring the zero-sequence current and midpoint potential of the dual three-level inverter during operation; traversing all selectable clamping combinations and calculating the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter; selecting the clamping combination corresponding to the opposite directions of the zero-sequence voltage and zero-sequence current, and the opposite directions of the midpoint current and midpoint potential, as the selected clamping combination for the first and second three-level inverters. This invention can select appropriate clamping combinations for the first and second three-level inverters, achieving zero-sequence current suppression and midpoint potential balance in the dual three-level inverter, improving the output performance of the dual three-level inverter, and simultaneously reducing the number of switching operations of the dual three-level inverter, thereby reducing switching losses.

Description

Technical Field

[0001] This invention belongs to the field of dual three-level inverters, and in particular relates to a control method, device, equipment and product for a dual three-level inverter. Background Technology

[0002] Dual three-level inverters for permanent magnet synchronous motors are driven by two three-level inverters, so they have high flexibility, strong fault tolerance and high DC voltage utilization, and are widely used in new energy electric vehicles and aerospace fields.

[0003] Dual three-level inverters have the advantages of reduced cost and simple system structure because the two inverters only need to share one power supply. However, the disadvantage is that the direct connection of the two inverters sharing one power supply will create a zero-sequence path and generate zero-sequence current. Therefore, there is a need to suppress the zero-sequence current. At the same time, it is also necessary to deal with the problem of the potential balance at the midpoint of the dual three-level inverter. Summary of the Invention

[0004] In view of this, the present invention aims to overcome the deficiencies in the prior art and proposes a control method, device, equipment and product for a dual three-level inverter.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0006] In a first aspect, the present invention discloses a control method for a dual three-level inverter, the dual three-level inverter comprising a first three-level inverter and a second three-level inverter, including:

[0007] Obtain the zero-sequence current and midpoint potential of the dual three-level inverter during operation;

[0008] Iterate through all the possible clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding zero-sequence voltage and midpoint current of the dual three-level inverter.

[0009] The clamping combinations corresponding to the opposite directions of zero-sequence voltage and zero-sequence current, and the opposite directions of midpoint current and midpoint potential, are selected as the clamping combinations for the first three-level inverter and the second three-level inverter.

[0010] In one embodiment of the present invention, all selectable clamping combinations when the first three-level inverter and the second three-level inverter output AC voltage are traversed, and the corresponding generated dual three-level inverter zero-sequence voltage and dual three-level inverter midpoint current are calculated, including: the dual three-level inverter zero-sequence voltage is the difference between the zero-sequence voltage generated by the first three-level inverter and the zero-sequence voltage generated by the second three-level inverter; the dual three-level inverter midpoint current is the difference between the midpoint current generated by the first three-level inverter and the midpoint current generated by the second three-level inverter.

[0011] In one embodiment of the present invention, all optional clamping combinations include: all clamping combinations where one phase is fixed to an optional clamp when the first three-level inverter outputs the required AC voltage and one phase is fixed to an optional clamp when the second three-level inverter outputs the required AC voltage.

[0012] In one embodiment of the present invention, the zero-sequence voltage generated by the first three-level inverter is the average zero-sequence voltage generated by the first three-level inverter within one carrier cycle; the zero-sequence voltage generated by the second three-level inverter is the average zero-sequence voltage generated by the second three-level inverter within one carrier cycle.

[0013] In one embodiment of the present invention, the average zero-sequence voltage of the first three-level inverter is the average value of the voltage values ​​of the switching states of the zero vector, one vector, and two vectors of the first three-level inverter at the DC side midpoint and the corresponding operating time during one carrier cycle; the average zero-sequence voltage of the second three-level inverter is the average value of the voltage values ​​of the switching states of the zero vector, one vector, and two vectors of the second three-level inverter at the DC side midpoint and the corresponding operating time during one carrier cycle.

[0014] In one embodiment of the present invention, the midpoint current generated by the first three-level inverter is the average midpoint current of the first three-level inverter within one carrier cycle, and the midpoint current generated by the second three-level inverter is the average midpoint current of the second three-level inverter within one carrier cycle.

[0015] In a second aspect, the present invention discloses a control device for a dual three-level inverter, the device comprising:

[0016] The acquisition module is used to acquire the zero-sequence current and midpoint potential in the dual three-level inverter during operation; the dual three-level inverter consists of a first three-level inverter and a second three-level inverter;

[0017] The calculation module is used to traverse all selectable clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding zero-sequence voltage and midpoint current of the dual three-level inverter.

[0018] The selection module is used to select the clamping combination when the zero-sequence voltage and zero-sequence current are opposite in positive and negative directions, and the midpoint current and midpoint potential are opposite in positive and negative directions, as the clamping combination selected for the first three-level inverter and the second three-level inverter.

[0019] Thirdly, the present invention discloses an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the above-described method.

[0020] Fourthly, the present invention discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0021] Fifthly, the present invention discloses a computer program product, including a computer program that is executed by a processor using the above-described method.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] This invention discloses a control method, apparatus, device, and product for a dual three-level inverter, comprising: acquiring the zero-sequence current and midpoint potential of the dual three-level inverter during operation; traversing all selectable clamping combinations when the first and second three-level inverters output the required AC voltage, and calculating the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter; selecting the clamping combination corresponding to the opposite directions of the zero-sequence voltage and zero-sequence current, and the opposite directions of the midpoint current and midpoint potential, as the selected clamping combination for the first and second three-level inverters. This invention discloses a control method, apparatus, device, and product for a dual three-level inverter, which can select appropriate clamping combinations for the first and second three-level inverters to achieve zero-sequence current suppression and midpoint potential balance in the dual three-level inverter, improve the output performance of the dual three-level inverter, and simultaneously reduce the number of switching operations of the dual three-level inverter, thereby reducing switching losses. Attached Figure Description

[0024] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0025] In the attached diagram:

[0026] Figure 1 This is a schematic diagram of a control method for a dual three-level inverter according to an embodiment of the present invention;

[0027] Figure 2This is a schematic diagram of a dual three-level inverter according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the three-level space vector diagram of the three-level inverter according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of a control device for a dual three-level inverter according to an embodiment of the present invention;

[0030] Figure 5 This invention relates to a control electronic device for a dual three-level inverter. Detailed Implementation

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0032] In the description of this invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0034] In the description of this invention, it should be further noted that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0035] Dual three-level inverters offer advantages such as reduced cost and simpler system structure because both inverters share a single power supply. However, a drawback is that the direct connection of the two inverters sharing a power supply creates a zero-sequence path, generating zero-sequence current. Therefore, it's necessary to suppress this zero-sequence current and address the issue of midpoint potential balance. This invention discloses a control method, device, equipment, and product for a dual three-level inverter. By selecting a suitable clamping combination for the first and second three-level inverters, it achieves zero-sequence current suppression and midpoint potential balance in the dual three-level inverter, improving its output performance. Simultaneously, it reduces the number of switching operations, thereby decreasing switching losses.

[0036] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0037] In one embodiment of the present invention, such as Figure 1 and Figure 2 As shown, a control method for a dual three-level inverter is provided. The method includes:

[0038] Step S101: The dual three-level inverter consists of a first three-level inverter and a second three-level inverter. The zero-sequence current and midpoint potential in the dual three-level inverter are obtained when the dual three-level inverter is running.

[0039] Step S102: Traverse all selectable clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter.

[0040] In this embodiment, all selectable clamping combinations when the first three-level inverter and the second three-level inverter output AC voltage are traversed, and the corresponding generated dual three-level inverter zero-sequence voltage and dual three-level inverter midpoint current are calculated, including: the dual three-level inverter zero-sequence voltage is the difference between the zero-sequence voltage generated by the first three-level inverter and the zero-sequence voltage generated by the second three-level inverter; the dual three-level inverter midpoint current is the difference between the midpoint current generated by the first three-level inverter and the midpoint current generated by the second three-level inverter.

[0041] In this embodiment, based on 180-degree decoupling, the following relationship exists:

[0042] ;

[0043] in, V ref It is the synthesized voltage vector of a dual three-level inverter system. V ref1It is the synthesized voltage vector of the first three-level inverter. V ref2 It is the synthesized voltage vector of the second-three level inverter;

[0044] Furthermore, the zero-sequence voltage of the dual three-level inverter has the following relationship:

[0045] ;

[0046] in, It is the zero-sequence voltage of a dual three-level inverter; It is the zero-sequence voltage generated by the first three-level inverter; It is the zero-sequence voltage generated by the second-three level inverter;

[0047] Furthermore, the following relationship exists:

[0048] ;

[0049] in, It is the midpoint current of a dual three-level inverter; It is the midpoint current generated by the first three-level inverter; It is the midpoint current generated by the second-three level inverter;

[0050] Step S103: Select the clamping combination corresponding to the zero-sequence voltage and zero-sequence current having opposite positive and negative directions, and the midpoint current and midpoint potential having opposite positive and negative directions, as the clamping combination selected for the first three-level inverter and the second three-level inverter.

[0051] Furthermore, exemplarily, the following relationship is known to exist:

[0052] ;

[0053] in, This indicates the zero-sequence current of a dual three-level inverter. This indicates the zero-sequence voltage of a dual three-level inverter;

[0054] Therefore, when the selected clamping combination makes the zero-sequence voltage and zero-sequence current have opposite positive and negative directions, it is possible to control the zero-sequence current. inhibition;

[0055] For example, the following relationship is known to exist:

[0056] ;

[0057] in, This indicates the neutral point potential of a dual three-level inverter. This indicates the midpoint current of a dual three-level inverter;

[0058] Therefore, when the selected clamping combination is such that the midpoint current and the midpoint potential are in opposite directions, it is possible to achieve control over the midpoint potential. The balancing effect;

[0059] In the previous embodiment, in another embodiment of the present invention, the zero-sequence voltage generated by the first three-level inverter is the average zero-sequence voltage generated by the first three-level inverter within one carrier cycle; the zero-sequence voltage generated by the second three-level inverter is the average zero-sequence voltage generated by the second three-level inverter within one carrier cycle.

[0060] In the previous embodiment, in another embodiment of the present invention, the average zero-sequence voltage of the first three-level inverter is the average value of the voltage values ​​of the switching states of the zero vector, one vector, and two vectors of the first three-level inverter at the DC side midpoint and the corresponding operating time within one carrier cycle; the average zero-sequence voltage of the second three-level inverter is the average value of the voltage values ​​of the switching states of the zero vector, one vector, and two vectors of the second three-level inverter at the DC side midpoint and the corresponding operating time within one carrier cycle.

[0061] In this embodiment, for example, the following relationships exist:

[0062] ;

[0063] in, This indicates the zero-sequence voltage of a dual three-level inverter; This represents one carrier cycle; T 0 、T 1 as well as T 2 V represents the duration of action of the zero vector, the first vector, and the second vector within one carrier cycle; 0x 、 V 1x 、V 2x These are the voltages at the DC side midpoint for the zero-vector, one-vector, and two-vector switching states of the current inverter x (x=1, 2; x=1 is the first three-level inverter, x=2 is the second three-level inverter);

[0064] For example, V 11 When V is a vector ONN state, 11 = - ;

[0065] For example, when inverter 1 generates vectors in the first and second minor sectors of the first major sector, the following relationship exists:

[0066] ;

[0067] in, This represents one carrier cycle; =max( A , B , C ), =mid( A , B , C ), =min( A , B , C ), , as well as These represent taking the maximum, median, and minimum values, respectively. A , B , C It is the A, B, and C three-phase reference voltage of any inverter.

[0068] In the previous embodiment, in another embodiment of the present invention, the midpoint current generated by the first three-level inverter is the average midpoint current of the first three-level inverter within one carrier cycle, and the midpoint current generated by the second three-level inverter is the average midpoint current of the second three-level inverter within one carrier cycle.

[0069] For example, the following relationship exists.

[0070] ;

[0071] in, This indicates the midpoint current of a dual three-level inverter; It is the DC-side voltage of a dual three-level inverter; yes Can represent Three phases, It is the first three-level inverter in Phase reference voltage, It is a second- or third-level inverter in The phase reference voltage can be obtained from the motor system through the double closed-loop control section; It is corresponding Phase current;

[0072] In the previous embodiment, in another embodiment of the present invention, all optional clamping combinations include: all clamping combinations where one phase is fixed to an optional clamp when the first three-level inverter outputs the required AC voltage and one phase is fixed to an optional clamp when the second three-level inverter outputs the required AC voltage.

[0073] For example, such as Figure 3 As shown in Table 1, the voltage vector synthesized by the first three-level inverter and the second three-level inverter is combined with all clamping states existing in the first major sector (sectors 1 and 2) and the fourth major sector (sectors 1 and 2), respectively. The corresponding zero-sequence voltage and midpoint current positive and negative states are then calculated.

[0074] Table 1 shows the zero-sequence voltage and midpoint current status in sub-sectors 1 and 2 of the first major sector.

[0075]

[0076] In Table 1, "+" indicates that the current zero-sequence voltage or midpoint current is positive, "-" indicates that the current zero-sequence voltage or midpoint current is negative, "\" indicates that the positive or negative state of the zero-sequence voltage in this small sector is not unique, and "0" indicates that the midpoint current in the current combination is zero.

[0077] Furthermore, the clamping combination corresponding to the zero-sequence voltage and zero-sequence current having opposite positive and negative directions, and the midpoint current and midpoint potential having opposite positive and negative directions, is selected as the clamping combination for the first three-level inverter and the second three-level inverter.

[0078] Furthermore, based on the above clamping combinations, the clamping combinations can be further screened according to the following criteria: the zero-sequence voltage or midpoint current is the same in both sectors 1 and 2 (adjacent sectors), and does not contain "\" or "0". At the same time, combinations with excessively large calculated zero-sequence voltages are excluded. The clamping combinations in Table 2 are then obtained as the clamping combinations to be retained for the first and second three-level inverters.

[0079] Table 2 shows the zero-sequence voltage and midpoint current states corresponding to the inverter clamping state.

[0080]

[0081] In this embodiment, based on the positive and negative states of the zero-sequence current and the midpoint potential in the current system, the zero-sequence current is used as the horizontal axis and the midpoint potential as the vertical axis. According to the obtained positive and negative states, the system is divided into four quadrants. For the current situation of the zero-sequence current and the midpoint potential, the two inverters respectively select the corresponding clamping states with suppression and balancing effects to suppress and balance the zero-sequence current and the midpoint potential.

[0082] Similarly, when the voltage vector synthesized by the first three-level inverter and the second three-level inverter is in other large sectors, the above process can be followed to select appropriate clamping combinations for the first three-level inverter and the second three-level inverter, thereby suppressing the zero-sequence current and balancing the midpoint potential of the dual three-level inverter. At the same time, since both the first three-level inverter and the second three-level inverter are clamped, the number of switching operations of the dual three-level inverter is reduced, thereby reducing switching losses.

[0083] Compared with traditional methods for suppressing zero-sequence current, this invention does not introduce additional third harmonics into the current.

[0084] like Figure 4 As shown, the present invention also discloses a control device for a dual three-level inverter, comprising:

[0085] The acquisition module 401 is used to acquire the zero-sequence current and midpoint potential in the dual three-level inverter during operation; the dual three-level inverter consists of a first three-level inverter and a second three-level inverter;

[0086] The calculation module 402 is used to traverse all the selectable clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter.

[0087] Selection module 403 is used to select the clamping combination corresponding to the zero-sequence voltage and zero-sequence current having opposite positive and negative directions, and the midpoint current and midpoint potential having opposite positive and negative directions, as the clamping combination selected for the first three-level inverter and the second three-level inverter.

[0088] The present invention also discloses an electronic device, such as Figure 5 The diagram shows an embodiment of an electronic device applicable to the control of a dual three-level inverter described above.

[0089] The electronic device 50 of this embodiment includes a processor 501, which can perform various appropriate actions and processes according to a program stored in ROM 502 or a program loaded from storage portion 508 into RAM 503. The processor 501 may include, for example, a general-purpose microprocessor, an instruction set processor and / or related chipsets and / or dedicated microprocessors, etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of the present invention.

[0090] RAM 503 stores various programs and data required for the operation of electronic device 50. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 502 and / or RAM 503. It should be noted that programs may also be stored in one or more memories other than ROM 502 and RAM 503, and processor 501 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in one or more memories.

[0091] According to an embodiment of the present invention, the electronic device 50 may further include an I / O interface 505, which is also connected to the bus 504. The electronic device 50 may also include one or more of the following components connected to the I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube, liquid crystal display, and speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card and a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 5010 is also connected to the I / O interface 505 as needed. A removable medium 5011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 5010 as needed so that computer programs read from it can be installed into the storage section 508 as needed.

[0092] The present invention also provides a computer-readable storage medium.

[0093] The computer-readable storage medium may be included in the electronic device / apparatus system described in the above embodiments; or it may exist independently and not assembled into the electronic device / apparatus. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of the present invention.

[0094] According to embodiments of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples include, but are not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, portable compact disk read-only memory (CDROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this invention, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0095] Embodiments of the present invention also include a computer program product.

[0096] The computer program product includes a computer program containing program code for performing the methods provided in the embodiments of the present invention. When the computer program product is run on an electronic device, the program code is used to enable the electronic device to implement the methods provided in the embodiments of the present invention.

[0097] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0098] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written using any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages. Programming languages ​​include, but are not limited to, Java, C++, Python, C, or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device.

[0099] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features recited in the various embodiments and / or claims of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not expressly stated in the present invention. In particular, the features described in the various embodiments and / or claims of this invention can be combined and / or combined in various ways without departing from the spirit and teachings of this invention. All such combinations and / or combinations fall within the scope of this invention.

[0100] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Without departing from the scope of the invention, various substitutions and modifications can be made by those skilled in the art, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A control method for a dual three-level inverter, characterized in that, The dual three-level inverter consists of a first three-level inverter and a second three-level inverter, and the method includes: Obtain the zero-sequence current and midpoint potential of the dual three-level inverter during operation; Traverse all possible clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter. The clamping combination corresponding to the zero-sequence voltage and the zero-sequence current being opposite in positive and negative directions, and the midpoint current and the midpoint potential being opposite in positive and negative directions, is selected as the clamping combination for the first three-level inverter and the second three-level inverter. All the optional clamping combinations include: all clamping combinations where one phase is fixed to one optional clamp when the first three-level inverter outputs the required AC voltage, and where one phase is fixed to one optional clamp when the second three-level inverter outputs the required AC voltage; The step of iterating through all selectable clamping combinations when outputting AC voltages from the first and second three-level inverters, and calculating the corresponding zero-sequence voltage and midpoint current of the dual three-level inverter, includes: the zero-sequence voltage of the dual three-level inverter being the difference between the zero-sequence voltage generated by the first three-level inverter and the zero-sequence voltage generated by the second three-level inverter; and the midpoint current of the dual three-level inverter being the difference between the midpoint current generated by the first three-level inverter and the midpoint current generated by the second three-level inverter. The zero-sequence voltage generated by the first three-level inverter is the average zero-sequence voltage generated by the first three-level inverter within one carrier cycle; the zero-sequence voltage generated by the second three-level inverter is the average zero-sequence voltage generated by the second three-level inverter within one carrier cycle.

2. The control method for a dual three-level inverter according to claim 1, characterized in that, The average zero-sequence voltage of the first three-level inverter is the average of the product of the voltage values ​​of the switching states of the zero vector, one vector, and two vectors of the first three-level inverter at the DC side midpoint and the corresponding operating time within one carrier cycle; the average zero-sequence voltage of the second three-level inverter is the average of the product of the voltage values ​​of the switching states of the zero vector, one vector, and two vectors of the second three-level inverter at the DC side midpoint and the corresponding operating time within one carrier cycle.

3. The control method for a dual three-level inverter according to claim 1, characterized in that, The midpoint current generated by the first three-level inverter is the average midpoint current of the first three-level inverter within one carrier cycle, and the midpoint current generated by the second three-level inverter is the average midpoint current of the second three-level inverter within one carrier cycle.

4. A control device for a dual three-level inverter, characterized in that: The device includes: The acquisition module is used to acquire the zero-sequence current and midpoint potential of the dual three-level inverter during operation; the dual three-level inverter consists of a first three-level inverter and a second three-level inverter; The calculation module is used to traverse all selectable clamping combinations when the first three-level inverter and the second three-level inverter output the required AC voltage, and calculate the corresponding zero-sequence voltage and midpoint current of the dual three-level inverter. The selection module is used to select the clamping combination corresponding to the zero-sequence voltage and the zero-sequence current having opposite positive and negative directions, and the midpoint current and the midpoint potential having opposite positive and negative directions, as the clamping combination selected by the first three-level inverter and the second three-level inverter; all selectable clamping combinations include: all clamping combinations where one phase is fixed to one selectable clamp when the first three-level inverter outputs the required AC voltage and where one phase is fixed to one selectable clamp when the second three-level inverter outputs the required AC voltage; The difference calculation submodule is used to calculate the corresponding generated zero-sequence voltage and midpoint current of the dual three-level inverter; The average zero-sequence voltage calculation subunit is used to calculate the average zero-sequence voltage generated by the first three-level inverter within one carrier cycle as the zero-sequence voltage generated by the first three-level inverter, and to calculate the average zero-sequence voltage generated by the second three-level inverter within one carrier cycle as the zero-sequence voltage generated by the second three-level inverter.

5. An electronic device, characterized in that, include: One or more processors; A storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method of any one of claims 1 to 3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that... When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 3.

7. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the method described in any one of claims 1 to 3.

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