Multi-path amplifier circuit and method

Abstract

The present disclosure relates to a multi-path amplifier circuit and method comprising a first amplification path and a second amplification path coupled in parallel for an input voltage, the first path comprises a first amplifier stage, a second amplifier stage, and a notch filter located between a first node coupled to the second amplifier stage and a second node coupled to an output of the first amplifier stage, and a control unit, the control unit is configured to open the first path and couple the first node to the second node through the unity gain amplifier for a first duration after detecting a change in the common mode of the input voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French patent application No. 2401382, filed on February 13, 2024, which is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to multipath amplifier circuits and methods of operating the same. Background Art

[0004] Low voltage measurements (for example, in motor supply current measurements) can be disturbed when the common mode of the low voltage changes abruptly. Summary of the Invention

[0005] There is a need to reduce the interference time during sudden changes in the common mode of the voltage.

[0006] One embodiment overcomes some or all of the disadvantages of known multi-path amplifier circuits.

[0007] One embodiment provides a multi-path amplifier circuit, comprising:

[0008] first and second amplification paths for an input voltage coupled in parallel, the first path comprising a first amplifier stage, a second amplifier stage, and a notch filter between a first node coupled to the second amplifier stage and a second node coupled to an output of the first amplifier stage;

[0009] The control unit is configured to, after detecting a change in a common mode of the input voltage, open the first path and couple the first node to the second node through a unity gain amplifier for a first duration.

[0010] One embodiment provides a method for operating a multipath amplifier circuit comprising first and second amplification paths of an input voltage coupled in parallel,

[0011] The first path includes a first amplifier stage, a second amplifier stage, and a notch filter between a first node coupled to the second amplifier stage and a second node coupled to an output of the first amplifier stage;

[0012] The method comprises, after detecting a change in the common mode of the input voltage, operating a control unit for a first duration:

[0013] Open the first path, and

[0014] The first node is coupled to the second node through a unity gain amplifier.

[0015] In one embodiment, the second path is used when the frequency of the input voltage is higher than a first frequency, and wherein the first path is used when the frequency of the input voltage is lower than the first frequency.

[0016] In one embodiment, the first amplifier stage is configured to compensate for an offset voltage present at its input.

[0017] In one embodiment, the first amplifier stage includes a first amplifier coupled with a first shaping circuit configured to modulate an input voltage of the first amplifier and a second shaping circuit configured to demodulate an output voltage of the first amplifier.

[0018] In one embodiment, the unity gain amplifier is configured to achieve offset compensation of its input voltage.

[0019] In one embodiment, the unity gain amplifier is configured to replicate an input voltage offset of the second amplifier stage on the second node with an offset less than or equal to 50 μV during the first time duration.

[0020] In one embodiment, the unity gain amplifier comprises:

[0021] an amplifier stage, an output of the amplifier stage being configured to be coupled to the second node,

[0022] First and second differential amplifier circuits are configured to sequentially measure and compensate for their respective voltage offsets.

[0023] In one embodiment, the first and second differential amplifier circuits each include:

[0024] a respective first input terminal coupled to the second node,

[0025] a respective second input terminal coupled to the first node, and

[0026] The respective output terminals are coupled to the input nodes of the amplifier stages.

[0027] In one embodiment, the detection of the change in the common mode of the input voltage is achieved by a detector of the rising edge and / or the falling edge of the common mode of the input voltage.

[0028] In one embodiment, the amplifier circuit comprises:

[0029] a fourth amplifier coupling an output node of the amplifier circuit to an output of the second amplifier stage; and

[0030] A first capacitive element couples the output node to an output of the second amplifier stage.

[0031] In one embodiment, the second capacitive element couples the second node to an output node of the amplifier circuit.

[0032] In one embodiment, the second node is coupled to a third capacitive element.

[0033] One embodiment provides an electronic current determination device comprising a measuring resistor and an amplifier circuit as described above, wherein an input voltage of the amplifier circuit is taken between two terminals of the resistor.

[0034] One embodiment provides a control system for a motor, the control system comprising the motor and the apparatus as described above implemented on at least one power phase of the motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0036] Figure 1 schematically illustrates an example of a motor system to which the embodiments are applicable;

[0037] Figure 2 According to an example, schematically illustrated Figure 1 The circuit of the system shown in;

[0038] Figure 3 Schematically illustrates a method according to an embodiment Figure 1 The circuit of the system shown in;

[0039] Figure 4 Schematically illustrates Figure 3 The circuit shown in;

[0040] Figure 5 Pictured Figure 4 A timing diagram of the operation of the circuit shown in FIG;

[0041] Figure 6 The diagram shows a Figure 3 The circuit shown in;

[0042] Figure 7 The diagram shows a Figure 3 The circuit shown in;

[0043] Figure 8 The diagram shows a Figure 3 The circuit shown in;

[0044] Figure 9 The diagram shows a Figure 3 The circuit shown in;

[0045] Figure 10 The diagram shows a Figure 9 The circuit shown in;

[0046] Figure 11 The diagram shows a Figure 9 The circuit shown in;

[0047] Figure 12 The diagram shows when using Figure 3 When the circuit shown in Figure 1 A timing diagram of the operation of the circuit shown in ; and

[0048] Figure 13 A motor system according to one embodiment is schematically illustrated. DETAILED DESCRIPTION

[0049] Similar features in the various figures are denoted by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0050] For clarity, only operations and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0051] Unless otherwise indicated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0052] In the following disclosure, unless otherwise indicated, when reference is made to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or to relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.) or to orientation qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the figures.

[0053] Unless otherwise specified, the expressions "around," "approximately," "substantially," and "about" mean within 10% or 10°, and preferably within 5% or 5°.

[0054] Figure 1 An example of a motor system to which the embodiment is applicable is schematically illustrated.

[0055] In the example shown, the motor 108 (M) is powered by at least one phase 104 through a resistor 106 (RSHUNT) of very low value. By measuring the voltage INP-INM present across this resistor 106, the value of the current flowing through the motor 108 can be deduced.

[0056] In the example shown, amplifier circuit 109 is coupled (preferably, connected) across resistor 106 to amplify voltage INP-INM, eg, with a gain greater than 10 at output OM-OP.

[0057] Amplifier circuit 109 includes a resistor 105 having a value of R for coupling node IP to a terminal of resistor 106 coupled to motor 108. Amplifier circuit 109 also includes a resistor 107 having a value of R for coupling node IM to a terminal of resistor 106 receiving a phase intended for motor 108. Resistor 111 and a further resistor 103 (each having a value of G*R, where G is the gain) couple node IP to output OM and node IM to output OP, respectively.

[0058] In the example shown, one input terminal (denoted as "-") of amplifier circuit 102 is coupled (preferably connected) to node IP to receive potential VIP, and the other input terminal (denoted as "+") is coupled (preferably connected) to node IM to receive potential VIM. Amplifier circuit 102 receives clock signals Clk1 and Clk2 and voltage VNEG from operation unit 113 (REF). One output terminal (denoted as "+") of circuit 102 is coupled to output terminal OM, and the other output terminal (denoted as "-") of circuit 102 is coupled to output terminal OP.

[0059] Figure 2 Schematically illustrates an example Figure 1 The circuit of the system shown in . In particular, Figure 2 Pictured Figure 1 The circuits 113 and 102 shown in FIG.

[0060] In the example shown, the circuit 113 includes a voltage rail that receives a voltage VCC. The voltage rail is coupled (preferably connected) to:

[0061] a low dropout (LDO) regulator circuit 223 that generates a regulated voltage VREG that is distributed to an oscillator 225 (OSC), a clock signal generator 227 (Clk Generator), and a negative charge pump circuit 229 (Negative Charge Pump) that generates a voltage VNEG; and

[0062] Voltage generator circuit 231 (bias and reference).

[0063] In the example shown, oscillator 225 provides signal Fclk to circuit 227 to generate signals Clk1 and Clk2. For example, signal Clk2 has a frequency half that of Clk1.

[0064] Circuit 102 includes, for example, a positive voltage generating block 217 (positive power supply) coupled (preferably connected) to terminals INP, INM of resistor 106 and to voltage rail VCC as inputs, and delivers voltage VCMP as output.

[0065] The circuit 102 includes first and second paths 201, 202 for amplifying the voltage between nodes IP and IM. Each path includes a channel dedicated to processing the potential VIP received at the node IP and another channel dedicated to processing the potential VIM received at the node IM.

[0066] For clarity, in the rest of this article, a single node will refer to nodes at the same level on two channels of the same path.

[0067] In the example shown, two paths are coupled in parallel between nodes IP and IM and nodes N4M and N4P. First path 201 includes a first amplifier 216 (gm1), coupled to a first shaping circuit 218 (chopper modulator) and a ground-referenced second shaping circuit 220 (chopper demodulator). The voltage present between the two channels of the first path at the output of amplifier 216 is VOM-VOP. These two shaping circuits receive a clock signal Clk1 and are configured to cancel voltage offsets present at the inputs of amplifier 216. First shaping circuit 218 has inputs coupled (preferably connected) to nodes IP and IM, and second shaping circuit 220 has outputs coupled (preferably connected) to nodes NVOMI and NVOPI. In one example, first amplifier 216 receives voltages VCMP, VCC, and VNEG, and is also coupled (preferably connected) to ground.

[0068] In one example, the nodes NVOMI, NVOPI are capacitive nodes, ie, the capacitor C3 couples the two channels of the first path at the nodes NVOMI, NVOPI.

[0069] In the example shown, notch filter 212 (notch filter) couples nodes NVOMF, NVOPF coupled to amplifier 226 (gm2) with nodes NVOMI, NVOPI. Notch filter 212 receives, for example, signal Clk2. Signal Clk1 has a frequency of, for example, several hundred kHz or even several MHz.

[0070] The shaping circuit is configured to perform chopping, a continuous-time modulation technique that does not cause noise aliasing. The input voltages VIP and VIM to the shaping circuit 218 first pass through the shaping circuit 218, which is driven by the signal Clk1. The modulated signal at the output of the circuit 218 is then amplified by its own input offset. The ripple caused by the voltage offset at the input of the amplifier circuit 216 is filtered by the notch filter 212, thereby obtaining a constant voltage NVOMF-NVOPF between the two channels.

[0071] The amplifier 226 receives, for example, a voltage VCC and is also coupled (preferably connected) to ground. The amplifier is coupled (preferably connected) to nodes N4M, N4P as an output.

[0072] In the example shown, a ground-referenced feedback circuit 224 (CM feedback) couples the amplifier 216 to nodes NVOMI, NVOPI, referenced to ground. The feedback circuit 224 is configured to allow the common mode of the output of the amplifier 216 to be adjusted around a given fixed voltage.

[0073] Second path 202 includes amplifier 230 (gm4) coupling nodes IP and IM with nodes N4M and N4P. Amplifier 230 receives voltages VCMP, VCC, and VNEG and is also coupled (preferably connected) to ground. The components of circuits 218, 220, and 212 allow for accurate amplification, but are limited in frequency to the input signal. Therefore, second path 202 is primarily used for input signal frequencies above 100 kHz. Conversely, for input signal frequencies below 100 kHz, the first path is primarily used.

[0074] In one example, amplifier circuit 102 includes a fourth amplifier 228 (gm3) coupling output nodes OM, OP of circuit 102 with the output of amplifier 226 (i.e., nodes N4M, N4P). Amplifier 228 receives, for example, voltage VCC and is also coupled (preferably connected) to ground.

[0075] Circuit 102 also includes a capacitive element of value C2 coupling nodes OM, OP with nodes N4M, N4P, respectively, for each channel.

[0076] Circuit 102 also includes a capacitive element having a value of C1 coupling nodes NVOMI, NVOPI with nodes OM, OP, respectively, for each channel.

[0077] In the case of a motor, the common mode of the voltage present on phase 104 may vary greatly, for example between 0 and 120 V, and by up to about 50 V in ten nanoseconds. Such common mode variations are also found on IP-IM (i.e., on voltage VIP-VIM). However, during a sudden common mode variation, Figure 2 The output OM-OP of the illustrated circuit changes before returning to a more stable value. The time it takes to return to a voltage value within ±0.5% of the value before the sudden change in common mode is greater than 5 μs. This recovery time is relatively long due to, for example, speed limitations imposed by the sampling implemented by circuit 212.

[0078] It is necessary to reduce this recovery time, for example, to a time close to the order of μs.

[0079] To this end, the embodiment provides that the amplifier circuit comprises a control unit configured to open the first path 201 for a first duration after detecting a common-mode change of the input voltage.

[0080] This allows, once a change in common mode is detected, the signal to completely pass through the second path, which is faster than the first path, during the on-time of the first path, thereby shortening the recovery time.

[0081] In one embodiment, the voltage offset at the input of amplifier 226 is stored during the opening of the first path. This allows for a further increase in the speed of the recovery time.

[0082] Figure 3 Schematically illustrates Figure 1 The circuit of the system shown in . In particular, Figure 3 Examples of circuit 113 and another amplifier circuit 300 are illustrated.

[0083] In the example shown, circuit 113 is connected to Figure 2 The circuit shown in is similar, except that a signal having the frequency FOSC of oscillator 225 is available to circuit 113 .

[0084] In the example shown, the circuit 300 is connected to Figure 2 , except that circuit 300 includes a control unit 321 (logic), a detector 310 for rising and / or falling edge changes in the common mode of voltages INP-INM, and a unity gain amplifier 320 (AZ BUF). Detector 310 is coupled (preferably connected) to an input of control unit 321. Control unit 321 is coupled (preferably connected) to unity gain amplifier 320, filter 212, and circuit 220.

[0085] When circuit 310 detects a rising or falling edge on the common mode of voltage INP-INM, i.e., when a rising or falling edge is detected simultaneously at both terminals INP and INM, signal EDGE_DET changes state. Depending on the state of signal EDGE_DET, and based on signal FOSC and / or clock signal CLK from clock signal generator 227, control unit 321 generates and changes the states of signals AZ, MASKON, NOTCH, NOTCHB, CHOP, and CHOPB. Signals AZ and MASKON control unity gain amplifier 320, signals NOTCH and NOTCHB control filter 212, and signals CHOP and CHOPB control shaping circuits 218 and 220. Signal CHOPB is the inverse of signal CHOP, and signal NOTCHB is the inverse of signal NOTCH.

[0086] After the detector 310 detects a change in the common mode of the input voltage, the signal EDGE_DET changes state, and the control unit 321 responsively opens the first path 201, i.e., opens the circuit 220 and / or the filter 212 for a first duration. To this end, during this first duration (also referred to as the masking duration), the signals NOTCH and / or CHOP—and accordingly, the signals CHOPB and NOTCHB—are maintained.

[0087] In response to the detector 310 detecting a change in the common mode of the input voltage, the control unit 321 may also change the states of the signals AZ and MASKON during a first duration (e.g., a few microseconds) such that the output of the unity-gain amplifier 320 is connected to the nodes NVOMI, NVOPI. Thus, when the first path is open, the unity-gain amplifier 320 stores or copies the voltage offset of the second amplifier stage 216 on the capacitor nodes NVOMI, NVOPI and feeds it back to the nodes NVOMI, NVOPI during the first duration. This allows for reduced recovery time during a change in the common mode of the input voltage by restarting from the voltage offset that existed before the first path was opened.

[0088] Figure 4 Schematically illustrates Figure 3 The circuit shown in .

[0089] In particular, Figure 4 Circuits 212 , 220 , and 320 of circuit 300 are illustrated.

[0090] In the example shown, the circuit 220 comprises: a switch 401 controlled by a signal CHOP and coupling a channel receiving the potential VOM to a node NVOMI;

[0091] a switch 403 controlled by a signal CHOPB and coupling a channel receiving the potential VOM to a node NVOPI;

[0092] a switch 402 controlled by a signal CHOP and coupling a channel receiving a potential VOP to a node NVOPI; and

[0093] A switch 408 is controlled by a signal CHOPB and couples the channel receiving the potential VOP to a node NVOMI.

[0094] exist Figure 4 In the example shown in , circuit 212 includes:

[0095] A capacitor 420 coupling the node N1CN to the node N1CP, a capacitor 421 coupling the node N2CN to the node N2CP, and a capacitor 426 coupling two channels of the nodes NVOMF and NVOPF;

[0096] a switch 409 controlled by signal NOTCH and coupling node NVOMI to node N1CN;

[0097] a switch 416 controlled by signal NOTCHB and coupling node NVOMF to node N1CN;

[0098] a switch 411 controlled by signal NOTCHB and coupling node NVOMI to node N2CN;

[0099] a switch 413 controlled by signal NOTCH and coupling node NVOMF to node N2CN;

[0100] a switch 407 controlled by signal NOTCH and coupling node NVOPI to node N1CP;

[0101] a switch 414 controlled by signal NOTCHB and coupling node NVOPF to node N1CP;

[0102] a switch 405 controlled by signal NOTCHB and coupling node NVOPI to node N2CP;

[0103] A switch 412 is controlled by signal NOTCH and couples node NVOPF to node N2CP.

[0104] exist Figure 4In the example shown in FIG, the input of unity-gain amplifier 320 is coupled to a first node (NVOMF, NVOPF), and the output of unity-gain amplifier 320 is coupled to a second node (NVOMI, NVOPI). Circuit 320 includes two unity-gain amplifier stages 450 and 460, each of which operates on a channel of a first path. Switch 440, controlled by signal MASKON, couples unity-gain amplifier stage 450 to node NVOPI. Unity-gain amplifier stage 450 is further coupled (preferably, connected) to node NVOPF. Switch 462, controlled by signal MASKON, couples unity-gain amplifier stage 460 to node NVOMI. Unity-gain amplifier stage 460 is further coupled (preferably, connected) to node NVOMF.

[0105] Figure 5 The diagram shows Figure 4 The timing diagram of the operation of the circuit shown in FIG. In particular, Figure 5 The example shown in FIG. 1 illustrates changes in the common mode INP / INM, the signal EDGE_DET, the signal MASKON, the signal CHOP, and the signal NOTCH over time.

[0106] Before time t1 , the common mode INP / INM is at 0V, the signals EDGE_DET and MASKON are low, and the signals CHOP and NOTCH form a square wave signal with a duty cycle of 50%, and the frequency of the signal CHOP is twice the frequency of the signal NOTCH.

[0107] At time t1 , the common mode voltage INP / INM suddenly changes with a rising edge from 0 V to 48 V. This causes a pulse in signal EDGE_DET, causing signal MASKON to go high and signals CHOP and NOTCH to go low until time t2 .

[0108] At time t2, signal MASKON returns to low, and the oscillations of signals CHOP and NOTCH resume.

[0109] At time t3 after time t2, the common mode INP / INM suddenly returns to 0V with a falling edge, resulting in a pulse being generated on the EDGE_DET signal, setting the MASKON signal high and setting the CHOP and NOTCH signals low until time t4. At time t2, the MASKON signal returns to low, and the oscillation of the CHOP and NOTCH signals resumes.

[0110] Signal AZ is not present Figure 5 , but has the same frequency as signal NOTCH, except that it is not maintained during the masking time during which signal NOTCH is maintained.

[0111] Figure 6The diagram shows a Figure 3 In particular, Figure 6 The functionality of circuit 321 for generating signals NOTCH, NOTCHB, CHOP, CHOPB, and AZ is illustrated.

[0112] Circuit 321 includes a first circuit having a flip-flop 617 (FF) (e.g., D-type) that receives a signal FOSC at a clock input CK. The output Q of flip-flop 617 is coupled to the clock input CK of another D-type flip-flop 619. The data input D of flip-flop 619 is coupled to the inverting output QB of another D-type flip-flop 618. The clock input CK of flip-flop 618 is coupled to the data input D and inverting output QB of flip-flop 617. The data input D of flip-flop 618 is coupled to the output Q of flip-flop 619 and the data input D of an LD-type flip-flop 620. The signal state at the output Q of flip-flop 620 is the state of signal CHOP. The input GN of flip-flop 620 is configured to receive the signal HOLDON2. For example, when HOLDON2 is high, the signal HOLDON2 maintains the output state Q regardless of the signal state at the input D. In other words, signal HOLDON2 enables or disables circuit 220 depending on its state. The inverting output QB of flip-flop 619 is coupled to the data input D of an LD-type flip-flop 623. The state of the signal at the output Q of flip-flop 623 is the state of signal CHOPB. The input GN of flip-flop 623 is configured to receive signal HOLDON2. The output Q of flip-flop 618 is coupled to the input of an AND-type logic gate 625, the other input of which is configured to receive signal HOLDOFF, which enables or disables circuit 212 depending on its state. The output of logic gate 625 is coupled to the clock input CK of a D-type flip-flop, the data input D of which is looped back to its inverting output QB. The state of signal NOTCH is found at the output Q of flip-flop 626, while the state of signal NOTCHB is found at the inverting output QB of flip-flop 626.

[0113] Circuit 321 includes a second circuit comprising a D-type flip-flop 627 having a data input terminal D coupled to an inverting output terminal QB thereof, and a clock input terminal of the flip-flop configured to receive a signal CLK. The state of the signal outputted at an output terminal Q of the flip-flop 627 is the state of the signal AZ.

[0114] The flip-flops 617 , 618 , 619 , 626 , and 627 are configured to receive a reset signal RSTB.

[0115] Circuit 321 includes a third circuit, which includes an AND-type logic gate 613 configured to receive the state of a signal CLK and the state of a signal CNTON as inputs. The output of logic gate 614 is coupled to the clock input CK of a D-type flip-flop 614, whose data input D is looped back to its inverting output QB. The signal at the Q output of flip-flop 614 is referred to as A0, and the signal at the inverting output QB is referred to as A0B. The third circuit also includes two additional flip-flops 615 and 616, similar to flip-flop 614. The clock input of flip-flop 615 is coupled to the Q output of flip-flop 614, and the clock input CK of flip-flop 616 is coupled to the output of flip-flop 615. The signal at the Q output of flip-flop 615 is referred to as A1, and the signal at the inverting output QB of the flip-flop is referred to as A1B. The signal at the Q output of flip-flop 616 is referred to as A2, and the signal at the inverting output QB of the flip-flop is referred to as A2B.

[0116] The flip-flops 614 , 615 , and 616 are configured to receive a reset signal RSTCNTB.

[0117] Circuit 321 includes a fourth circuit comprising logic gates 636 and 637, each configured to perform an AND-type logic function on signals A2, A1, A0B and A2, A1B, A0, respectively. The respective outputs of logic gates 636 and 637 are coupled to the input of logic gate 638, which is configured to perform an OR-type logic function on the outputs of logic gates 636 and 637. The output CNTONB of logic gate 638 is coupled to inverter 628, the output of which provides a signal CNTON. The output of logic gate 638 is also coupled to input D of a D-type flip-flop 640, whose clock input CK is configured to receive a signal CLK inverted by inverter 639. The output Q of flip-flop 640 provides a signal HOLDOFF and is coupled to input D of another D-type flip-flop 642, whose clock input is configured to receive the signal CLK. The inverting output terminal QB of the flip-flop 642 provides a signal HOLDON2 and is coupled to two serially connected inverters 631 and 632 to provide a signal MASKON.

[0118] Circuit 321 also includes a fifth circuit having an inverter 631 configured to receive the signal EDGE_DET and coupled (preferably connected) to an input of an AND-type logic gate 632, which receives the signal RSTB at another input. The output of logic gate 632 is the signal RSTCNTB.

[0119] Figure 7 The diagram shows a Figure 3 In particular, Figure 7 An example embodiment of a circuit 310 for detecting a rising edge of a common-mode voltage between INP and INM is illustrated.

[0120] In the example shown, capacitor 720 couples node INM to node ND1 , and another capacitor 721 couples node INM to node ND2 .

[0121] The illustrated example includes a first branch 723 having a resistor 710 coupling node ND1 to ground GND, three series-connected diodes 712, 717, and 719 coupling node ND1 to ground, and a diode 708 positioned inversely relative to diodes 712, 717, and 719, with its cathode coupled to node ND1 and its anode coupled to ground. The illustrated example also includes a second branch 722, which is similar to the first branch 723, but with node ND2 replacing node ND1.

[0122] Node ND1 is coupled (preferably connected) to the control node of NMOS transistor 726, and node ND2 is coupled (preferably connected) to the control node of NMOS transistor 724. The conduction node of transistor 724 is coupled (preferably connected) to ground, and the conduction node of transistor 726 is coupled (preferably connected) to node NTH1. Transistors 724 and 726 share a common conduction node.

[0123] In the example shown, transistor 728 is coupled (preferably connected) to voltage rail VCC via resistor 725. Transistor 728 has a conduction node coupled (preferably connected) to node NTH1 and a control node coupled (preferably connected) to flip-flop 730 (such as a Schmitt trigger). The control node of transistor 728 receives voltage VREG. Amplifier 730 is also coupled (preferably connected) to node NTH1 as an input and is referenced to ground. The output of amplifier 730 is signal EDGE_DET.

[0124] When rising edges are detected simultaneously on INM and INP, this produces a pulse on signal EDGE_DET at the output of amplifier 730 .

[0125] Figure 8 The diagram shows a Figure 3 In particular, Figure 8 An example embodiment of circuit 310 is illustrated to detect a falling edge of the common-mode voltage between INP and INM.

[0126] In the example shown, capacitor 821 couples node INM to node ND3 , and another capacitor 828 couples node INM to node ND4 .

[0127] The illustrated example includes a first branch 820 having a resistor 810 coupling node ND3 to voltage rail VCC, three series-connected diodes 812, 817, and 819 coupling node ND1 to voltage rail VCC, and a diode 808 positioned inversely relative to diodes 812, 817, and 819, with its cathode coupled to voltage rail VCC and its anode coupled to node ND3. The illustrated example also includes a second branch 822 that is similar to first branch 820, but with node ND4 replacing node ND3.

[0128] Node ND3 is coupled (preferably connected) to the control node of PMOS transistor 826, and node ND4 is coupled (preferably connected) to the control node of PMOS transistor 823. The conduction node of transistor 823 is coupled (preferably connected) to voltage rail VCC, and the conduction node of transistor 826 is coupled (preferably connected) to node NTH2 via PMOS transistor 828. Transistors 826 and 823 share a common conduction node.

[0129] The illustrated example includes another branch 832 having: a resistor 830 coupling node NTH2 to ground; three series-connected diodes 823, 824, 825 coupling node NTH2 to ground; and a diode 835 positioned opposite diodes 823, 824, 825, with its cathode connected to node NTH2 and its anode coupled to ground.

[0130] In the example shown, a flip-flop 840 (such as a Schmitt trigger) is coupled (preferably connected) to the node NTH2 as an input and is referenced to ground. The flip-flop 840 also receives a voltage VREG. The output of the flip-flop 840 is a signal EDGE_DET.

[0131] When falling edges are detected simultaneously on INM and INP, this produces a pulse on signal EDGE_DET at the output of flip-flop 840 .

[0132] Figure 9 The diagram shows a Figure 3 In particular, Figure 9 An embodiment of circuit 320 is illustrated.

[0133] In the example shown, unity gain amplifier 320 includes amplifier stage 930 (AVOUT) whose output node NVOUT is configured to be coupled to node NVOMI or NVOPI via respective switch 440 or 462. Amplifier stage 930 is coupled (preferably connected) to voltage rail VREG and referenced to ground.

[0134] Amplifier 320 also includes first and second differential amplifier circuits 924 and 926 (AZ AV1), whose respective input nodes IM are coupled to nodes NVOMI and NVOPI, respectively, and whose respective other input nodes IP are coupled to nodes NVOMF and NVOPF, respectively. The respective output nodes OM of amplifier circuits 924 and 926 are coupled to the same input node NVINT of amplifier stage 930 (AVOUT). Circuits 924 and 926 are coupled (preferably connected) to voltage rail VREG and referenced to ground, and are configured to receive the states of signals AZ and AZB, with AZB being the inverse of signal AZ. Circuits 924 and 926 receive signals AZ and AZB in opposite ways and are therefore used sequentially. As one of the two circuits is used to output the subsequent voltage on VOUT, the other measures its input voltage offset so that it can subsequently compensate for it. The alternating use of circuits 924 and 926 is performed at the frequency of signal AZ.

[0135] Figure 10 The diagram shows a Figure 9 The circuit shown in .

[0136] In particular, Figure 10 An example embodiment of circuit 930 is illustrated.

[0137] In the example shown, capacitor 1024 couples node NVINT to node NVOUT, while capacitor 1030 couples node NVOUT to ground. Node NVINT is also coupled (preferably connected) to the control node of NMOS transistor 1026, one conduction node of which is coupled (preferably connected) to ground, while the other conduction node of the transistor is coupled (preferably connected) to node NVOUT. PMOS transistor 1020 (whose control node is controlled by voltage VBP) couples node NVOUT to voltage rail VREG.

[0138] Figure 11 The diagram shows a Figure 9 In particular, Figure 11 An embodiment of circuits 924 , 926 is shown.

[0139] In the example shown, nodes IP and IM are coupled to node NC0 via switch 1102 controlled by signal AZ and switch 1104 controlled by signal AZB, respectively.

[0140] Voltage rail VREG is coupled to ground through two PMOS transistors 1110, 1128 and two NMOS transistors 1124, 1122 coupled in series. Transistors 1128 and 1124 have a common conduction node referred to as NC6.

[0141] PMOS transistor 1112 (whose control node is configured to receive voltage VBP) couples voltage rail VREG to node NC3. A PMOS transistor 1114 and an NMOS transistor 1120, connected in series, couple node NC3 to ground. A PMOS transistor 1116 and an NMOS transistor 1118, connected in series, also couple node NC3 to ground. Transistor control node 1116 is configured to receive a signal present on IP, and transistor control node 1114 is configured to be coupled (preferably, connected) to node NC0. The control node of transistor 1122 is coupled (preferably, connected) to the control node of transistor 1120.

[0142] Voltage rail VREG is also coupled to ground via two PMOS transistors 1132 and 1130, and two NMOS transistors 1134 and 1136, connected in series. The control node of transistor 1136 is coupled (preferably connected) to the control node of transistor 1118; the control node of transistor 1134 is coupled (preferably connected) to the control node of transistor 1124; the control node of transistor 1130 is coupled (preferably connected) to transistor control node 1128; and the control node of transistor 1132 is coupled (preferably connected) to the control node of transistor 1110. Conduction node NC2, common to transistors 1130 and 1134, is coupled (preferably connected) to node NC1, which is the control node of transistor 1132. Conduction node NC5, common to transistors 1120 and 1114, is coupled (preferably connected) to the control node of transistor 1122. Conduction node NC4, common to transistors 1118 and 1116, is coupled (preferably connected) to the control node of transistor 1118.

[0143] A PMOS transistor 1138 controlled by a signal VPB couples the node NC9 to the voltage rail VREG. A PMOS transistor 1140 couples the node NC5 to the node NC9. A PMOS transistor 1142 couples the node NC4 to the node NC9.

[0144] The control node of transistor 1140 is coupled to node NVINT via switch 1160 controlled by signal AZ. The control node of transistor 1140 is also coupled to ground via resistor 1139 in series with capacitor 1143.

[0145] The control node NC7 of transistor 1142 is coupled to ground via a resistor 1152 in series with a capacitor 1162. The control node of transistor 1142 is also coupled to node NVINT via a switch 1150 controlled by signal AZ in series with a switch 1154 controlled by signal AZB. Switch 1150 is also coupled (preferably connected) to a conduction node NC6 common to transistors 1124 and 1128.

[0146] Figure 12 The diagram shows when using Figure 3 When the circuit shown in Figure 3 The timing diagram of the operation of the circuit shown in FIG. In particular, Figure 12 The output voltage OM-OP of the amplifier circuit 300 and the common mode voltage between INP and INM are illustrated.

[0147] Before time t'1, the common mode voltage INM / INP is 0V, and the output voltage is stable at 3.5V.

[0148] At time t'1, the common-mode voltage INM / INP suddenly rises to 48V, causing output voltage instability and temporary overshoot.

[0149] At time t'2, 1.3 μs after time t'1, the output voltage returns to within ±0.5% of the value before the common-mode voltage INM / INP changed. Figure 2 Compared to the recovery time of the circuit 102 shown in Figure 3 The circuit 300 shown in FIG. 3 improves the recovery time.

[0150] Figure 13 A motor system according to one embodiment is schematically illustrated. The system comprises a control circuit which supplies three phases to a motor 108. The current flowing through each phase is measured, for example, by means of a resistor 106, across which a circuit 300 is connected.

[0151] The control circuit comprises three parallel branches, for example, coupling the voltage rail VM to ground. Each branch comprises two power transistors, respectively designated 1302, 1312; 1304, 1306; 1308, 1310. The conduction node shared by the transistors of the same branch is coupled (preferably connected) to one of the motor phases.

[0152] To measure the current in each branch, resistor 106 is inserted between transistor 1312 and ground, and / or between transistor 1306 and ground, and / or between transistor 1310 and ground. Then, a circuit similar to circuit 109 and circuit 300 is connected across each resistor 106.

[0153] This control circuit enables accurate current measurement even during voltage variations of the individual phases.

[0154] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations. In particular, even in Figure 3In the embodiment, the unity gain amplifier 320 is associated with the detector 310 and the control unit 321. However, those skilled in the art may also conceive of implementing only the detector and the control unit 321. Figure 7 and 8 Detection of rising and falling edges is described in , and the detector 310 may also include these two circuits.

[0155] Finally, based on the functional description provided above, the practical implementation of the embodiments and variants described herein is within the capabilities of a person skilled in the art. In particular, with respect to the amplifier stage formed by circuits 216, 218, 220 and configured to compensate for the offset voltage present at its input, circuits 218 and 220 can be replaced by components having automatic compensation (autozeroing) of the input voltage offset.

Claims

1. A multipath amplifier circuit, comprising: a first amplification path for the input voltage, the first amplification path comprising a first amplifier stage, a second amplifier stage, and a notch filter between a first node coupled to the second amplifier stage and a second node coupled to an output of the first amplifier stage; as well as a second amplification path for the input voltage, the second amplification path coupled in parallel with the first amplification path; The first amplifier stage is configured to, after detecting a change in the common mode of the input voltage, open the first amplification path and couple the first node to the second node through a unity gain amplifier for a first duration.

2. The multi-path amplifier circuit according to claim 1, wherein the multi-path amplifier circuit is configured to use the second amplification path in response to a frequency of the input voltage being higher than a first frequency, and to use the first amplification path in response to a frequency of the input voltage being lower than the first frequency. 3 . The multi-path amplifier circuit of claim 1 , wherein the first amplifier stage is configured to compensate for an offset voltage present at its input.

4. The multi-path amplifier circuit of claim 3 , wherein the first amplifier stage comprises a first amplifier coupled to a first shaping circuit and a second shaping circuit, the first shaping circuit being configured to modulate a first input voltage of the first amplifier and the second shaping circuit being configured to demodulate an output voltage of the first amplifier. 5 . The multi-path amplifier circuit according to claim 1 , wherein the unity-gain amplifier is configured to achieve offset compensation of its input voltage. 6 . The multipath amplifier circuit of claim 5 , wherein the unity-gain amplifier is configured to copy an input voltage offset of the second amplifier stage onto the second node during the first duration, wherein the second offset is less than or equal to 50 μV.

7. The multi-path amplifier circuit according to claim 5, wherein the unity gain amplifier comprises: a third amplifier stage having an output coupled to the second node; as well as The first differential amplifier circuit and the second differential amplifier circuit are configured to sequentially measure and compensate for their respective voltage offsets.

8. The multi-path amplifier circuit according to claim 7, wherein the first differential amplifier circuit and the second differential amplifier circuit each comprise: a respective first input terminal coupled to the second node; a respective second input terminal coupled to the first node; as well as A respective output terminal is coupled to an input node of the third amplifier stage. 9 . The multi-path amplifier circuit according to claim 1 , further comprising a detector that performs detection of a change in the common mode of the input voltage by detecting a rising edge and / or a falling edge of the common mode of the input voltage.

10. The multi-path amplifier circuit according to claim 1, further comprising: a fourth amplifier coupling an output node of the multipath amplifier circuit to an output of the second amplifier stage; as well as A first capacitive element couples the output node to an output of the second amplifier stage.

11. The multi-path amplifier circuit of claim 10, further comprising a second capacitive element coupling the second node to an output node of the multi-path amplifier circuit.

12. The multi-path amplifier circuit of claim 1, wherein the second node is coupled to a third capacitive element.

13. The multi-path amplifier circuit of claim 1, wherein an input terminal of the unity gain amplifier is coupled to the first node, and an output terminal of the unity gain amplifier is coupled to the second node.

14. A method for operating a multipath amplifier circuit, the multipath amplifier circuit having a first amplification path and a second amplification path coupled in parallel to an input voltage, the first amplification path having a first amplifier stage, a second amplifier stage, and a notch filter located between a first node coupled to the second amplifier stage and a second node coupled to an output terminal of the first amplifier stage, the method comprising: detecting a change in a common mode of the input voltage for a first duration; as well as After detecting a change in common mode: opening the first amplification path by a control unit of the multi-path amplifier circuit; as well as The first node is coupled to the second node by the control unit through a unity gain amplifier.

15. The method according to claim 14, further comprising: using a second amplification path by the multi-path amplifier circuit in response to the frequency of the input voltage being higher than the first frequency; as well as In response to the frequency of the input voltage being lower than the first frequency, the first amplification path is used by the multi-path amplifier circuit.

16. The method of claim 14, further comprising compensating, by the first amplifier stage, for an offset voltage present at its input.

17. The method of claim 16, wherein the first amplifier stage comprises a first amplifier coupling the first shaping circuit to the second shaping circuit, and the method further comprises: modulating a first input voltage of the first amplifier by a first shaping circuit; as well as The output voltage of the first amplifier is demodulated by the second shaping circuit.

18. The method according to claim 14, further comprising implementing offset compensation of an input voltage thereof by a unity gain amplifier. 19 . The method of claim 14 , wherein detecting a change in the common mode of the input voltage comprises detecting, by a detector, a rising edge and / or a falling edge of the common mode of the input voltage.

20. A system comprising: a measuring resistor having two terminals; as well as A multipath amplifier circuit comprising: a first amplification path for an input voltage taken between two terminals of the measuring resistor, the first amplification path comprising a first amplifier stage, a second amplifier stage, and a notch filter between a first node coupled to the second amplifier stage and a second node coupled to an output of the first amplifier stage; and a second amplification path for the input voltage, the second amplification path being coupled in parallel with the first amplification path; The first amplifier stage is configured to, after detecting a change in the common mode of the input voltage, open the first amplification path and couple the first node to the second node through a unity gain amplifier for a first duration.

21. The system of claim 20, further comprising a motor, wherein the measuring resistor is disposed in series in a line on a power phase of the motor.

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