Protective treatment for semiconductor manufacturing apparatus surfaces

Abstract

Semiconductor fabrication component fabrication methods are described. In an embodiment, a method includes forming a first layer on a surface of a semiconductor fabrication component. The first layer is characterized by a porosity of greater than or about 0.01 vol.%. The method further includes depositing a second layer on the first layer, wherein the second layer is characterized by a porosity of less than or about 20 vol.%. Processed semiconductor fabrication components are also described. In an embodiment, a treated component includes a first layer formed in a surface of a semiconductor fabrication component, where the first layer is characterized by a porosity of greater than or about 0.01 vol.%, and a second layer positioned on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol.%.

Description

Technical Field

[0001] The present invention relates to protective coatings on components of semiconductor manufacturing equipment that are subject to large and rapid temperature changes. In an embodiment, the protective layer includes a first layer incorporated into a surface of the component and a second layer formed on the first layer.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims U.S. patent application No. 17 / 981,394, filed on November 5, 2022, all of which is incorporated by reference into this application. Background Art

[0004] Semiconductor manufacturing processes typically include operations in which semiconductor substrates, such as semiconductor wafers, are raised to elevated temperatures and cooled to lower temperatures. In most manufacturing processes, there is a thermal budget for these operations that sets a maximum heating temperature that cannot be exceeded without risking thermal damage to structures on the substrate. The selection of semiconductor manufacturing equipment components that come into thermal contact with the substrate is determined, in part, by their ability to raise and lower the substrate to precise temperatures during manufacturing operations.

[0005] Conventional manufacturing components that contact substrates typically include ceramic materials that are stable and inert during manufacturing operations. These ceramics produce minimal contamination of the substrate and do not react with corrosive species, such as reactive halogens, oxides, and nitrides, which are produced during many semiconductor manufacturing and cleaning operations. Unfortunately, these ceramic materials often have low thermal conductivity, which prevents them from quickly changing the temperature of adjacent substrates. Low thermal conductivity can keep substrates at elevated temperatures for extended periods and cause operations that exceed the thermal budget. Low thermal conductivity also increases the time it takes to complete a thermal cycle, which can reduce the productivity of the manufacturing system. These and other problems of conventional manufacturing components are addressed by the present invention. Summary of the Invention

[0006] Embodiments of the present invention include methods for preparing semiconductor manufacturing components. In one embodiment, the method includes forming a first layer on a surface of the semiconductor manufacturing component. The first layer is characterized by a porosity of greater than or about 0.01 vol.%. The method further includes depositing a second layer on the first layer, wherein the second layer is characterized by a porosity of less than or about 20 vol.%.

[0007] In additional embodiments, the first layer may be characterized by a thickness greater than or about 0.01 μm. In further embodiments, the first layer may be formed on the surface of the semiconductor manufacturing component by an anodization technique selected from the group consisting of anodic aluminum oxidation, anodic titanium oxidation, barrier thick oxidation, and plasma electrolytic oxidation. In yet additional embodiments, the second layer may be characterized by a thickness less than or about 10 μm. In still further embodiments, the second layer may comprise a metal, a metal boride, a metal carbide, a metal nitride, a metal oxide, a metal fluoride, a metal oxyfluoride, or M1 x M2 y M3 z C a B b N c O d F e , wherein M1, M2, and M3 are each metal, and wherein x, y, z, a, b, c, d, and e are greater than or equal to 0. In further embodiments, the second layer may comprise a metal selected from the group consisting of aluminum, yttrium, erbium, scandium, zirconium, and magnesium. In further embodiments, the semiconductor manufacturing component may comprise aluminum. In still further embodiments, the surface of the semiconductor manufacturing component is a surface on a panel or heater assembly operable to be incorporated into a semiconductor manufacturing chamber.

[0008] Additional embodiments of the present invention include methods for processing a semiconductor manufacturing component. In one embodiment, the method includes forming a first layer in a surface of the semiconductor manufacturing component, wherein the first layer includes a grain structure characterized by an amorphous, polycrystalline, crystalline, or mixed phase. The method further includes depositing a second layer on the first layer, wherein the second layer is characterized by an amorphous, polycrystalline, crystalline, or mixed phase grain structure. In some embodiments, the second layer is also characterized by a higher hardness than the first layer.

[0009] In further embodiments, the first layer is characterized by a thickness of greater than or about 0.01 μm. In additional embodiments, the first layer is formed on the surface of the semiconductor fabricated component by plasma electrolytic oxidation. In still further embodiments, the second layer is characterized by a thickness of less than or about 1 μm. In yet additional embodiments, the second layer is formed on the first layer by atomic layer deposition. In further embodiments, the second layer comprises a metal oxide, a metal fluoride, or a metal oxyfluoride.

[0010] A further embodiment of the present invention includes a semiconductor manufacturing component. In one embodiment, the component comprises a surface of the semiconductor manufacturing component. The component further comprises a first layer formed in the surface of the semiconductor manufacturing component, wherein the first layer is characterized by a porosity of greater than or about 0.01 vol.%. The component also comprises a second layer positioned on the first layer, wherein the second layer is characterized by a porosity of less than or about 20 vol.%.

[0011] In further embodiments, the surface of the semiconductor manufacturing component comprises aluminum. In yet further embodiments, the first layer is characterized by a thickness of greater than or about 50 μm, and further wherein the first layer is characterized by an amorphous grain structure. In additional embodiments, the second layer is characterized by a thickness of less than or about 10 μm, and further wherein the second layer is characterized by a crystalline grain structure. In further embodiments, the second layer comprises a metal oxide, a metal fluoride, a metal oxyfluoride, a metal nitride, a metal oxynitride, a metal carbide, a metal oxycarbide, a metal boride, or a stoichiometric mixture of the foregoing. In still further embodiments, the semiconductor manufacturing component may be a panel or heater assembly operable to be incorporated into a semiconductor manufacturing chamber.

[0012] The present invention provides several benefits over conventional semiconductor manufacturing components that do not include a protective layer or have a single protective layer. When these conventional semiconductor manufacturing components include an unprotected metal surface in contact with a semiconductor substrate, such as a semiconductor wafer, they are susceptible to contamination of the substrate by metal from the surface. When the surface is protected by a single protective layer, such as a metal oxide layer deposited on the surface by atomic layer deposition (ALD), the difference in thermal expansion properties between the protective layer and the surface of the component generates large thermal stresses that can lead to cracking and displacement of the protective layer. The present invention addresses this problem by forming a first layer in the surface of the semiconductor manufacturing component that reduces the thermal stress experienced by a second layer deposited on the first layer. The second layer can be characterized by lower porosity, higher crystallinity, and higher hardness than the first layer, which helps prevent contaminants from migrating in either direction between the substrate processing area of the manufacturing chamber and the metal in the surface of the protected semiconductor manufacturing component. These and other embodiments of the present method and components, and their many advantages and features, are described in more detail in conjunction with the following specification and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A further understanding of the nature and advantages of the present invention may be realized by referring to the remainder of the specification and the drawings, in which the same reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sub-label is associated with a reference numeral and follows a hyphen to denote one of multiple similar components. When a reference numeral is made without specifying the presence of a sub-label, then all such multiple similar components are intended to be referred to.

[0014] Figure 1 A flowchart with selected operations is shown of an example method of processing a manufactured part in accordance with an embodiment of the present invention.

[0015] Figure 2 A simplified cross-sectional view showing a surface of a manufactured component with a protective layer according to an embodiment of the present invention.

[0016] Figure 3A A simplified cross-sectional view showing a surface of a manufactured component with a first layer of a protective layer according to an embodiment of the present invention.

[0017] Figure 3B A simplified cross-sectional view showing the surface of a manufactured component with first and second layers of protective layers according to an embodiment of the present invention.

[0018] Figure 4 A simplified cross-sectional view of a semiconductor manufacturing pedestal including a surface with a protective layer is shown in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Many semiconductor manufacturing processes require rapid temperature changes in substrates, such as semiconductor wafers. These processes involve rapidly increasing the substrate temperature to facilitate deposition or curing of materials on the substrate. These processes also involve rapidly decreasing the substrate temperature to keep manufacturing operations within the thermal budget. To achieve these rapid temperature changes in the substrate, the thermal conductivity of the materials used to make components of the manufacturing equipment is increased. These materials include metals and metal alloys, materials with high thermal conductivity, and more.

[0020] Manufacturing components from metal presents numerous challenges, including the potential for metal contamination of the substrate. Component manufacturers have addressed these challenges by depositing protective layers on surfaces of the component that are in direct contact with or in close proximity to the substrate. For example, a thin protective layer of inert material can be deposited on the component surface to prevent metallic species from migrating from the surface to the substrate. The protective layer can also prevent reactive species found in the manufacturing chamber from migrating to the metal component surface and causing component corrosion. In further embodiments, the protective layer can be made of a dielectric material that also prevents plasma arcing between plasma-generating equipment in the manufacturing chamber and the coated metal surface of the component.

[0021] Unfortunately, many conventional protective layers consist of a single, thin coating with a significantly different coefficient of thermal expansion than the underlying metal surface. When components experience rapid temperature changes, the different expansion rates create severe mechanical stresses on the protective layer. Within a relatively short number of thermal cycles, the protective layer can begin to crack, flake, and delaminate from the underlying metal surface. This increases the amount of contaminants that can migrate between the metal surface and the substrate, creating conductive paths for the plasma arc. Refurbishing or replacing components with damaged protective layers can result in significant chamber downtime.

[0022] The present invention solves these and other problems of conventional protective layers by forming a protective layer comprising at least one intermediate layer between the surface of the component and the outer layer directly exposed to the substrate. In embodiments, the at least one intermediate layer may be formed in the surface of the component by, for example, anodizing techniques. The intermediate layer may be characterized by a higher porosity and a lower crystallinity than the outer layer. In embodiments, the one or more intermediate layers reduce the mechanical stresses generated on the outer layer during rapid temperature changes in the component. The more amorphous structure of the intermediate layer also reduces and closes pathways for contaminants to migrate between the metal surface of the component and the substrate. In further embodiments, the intermediate layer is complemented by an outer layer characterized by a lower porosity, a higher crystallinity, and increased corrosion resistance to reactive species in the chamber processing zone. The combination of the intermediate layer and the outer layer provides a multi-layer protective layer that can protect metal-containing components for significantly more processing cycles than conventional single-layer protective layers.

[0023] Figure 1 A flow chart is shown with selected operations in a method 100 for preparing a fabricated part with multiple protective layers according to an embodiment of the present invention. The method 100 may or may not include one or more operations before the method begins, including molding, embossing, machining, polishing, cleaning, or any other operations that may be performed before the operations are performed. The method may include optional operations that may or may not be explicitly related to some embodiments of the method according to the present invention. The method 100 describes operations to prepare the surface of the fabricated part, as shown Figure 2 A portion of one of the components 200 is shown as Figure 3A - Another of the components 300 in B, and shown as Figure 4 The other of the base member 402. It should be appreciated that Figure 2-4 Only partial diagrammatic views with limited detail are illustrated. In further embodiments not shown, the example component and protective layer structures may contain additional layers, regions, and materials, have aspects shown in the figures, and alternative structural and material aspects, which may still benefit from any aspect of the present invention.

[0024] Method 100 includes providing a manufacturing component at operation 105. In one embodiment, the manufacturing component processed by the present method may include a faceplate, a heating assembly, a wafer holder, a susceptor, and the like. In a further embodiment, the manufacturing component includes a component that contacts or supports and positions a substrate (e.g., a semiconductor wafer) in a manufacturing process chamber. In yet further embodiments, the manufacturing component is operable for use in an erosive processing environment where the component is frequently exposed to highly reactive chemicals, such as halogen species (e.g., chlorine-containing species, fluorine-containing species), oxide species, and nitride species, among others. In yet additional embodiments, the manufacturing component is operable for exposure to frequent ion bombardment.

[0025] like Figure 2 As shown in FIG, layer 205 represents a portion of fabricated component 200 in which a first layer 210 of a protective layer is formed. In an embodiment, fabricated component 200 includes layer 205 having one or more surfaces of a material characterized by increased thermal conductivity that allows for faster temperature changes in a substrate in thermal contact with the component. In additional embodiments, the material may be characterized by a thermal conductivity greater than or about 25 W / (m·K), greater than or about 50 W / (m·K), greater than or about 75 W / (m·K), greater than or about 100 W / (m·K), greater than or about 125 W / (m·K), greater than or about 150 W / (m·K), greater than or about 175 W / (m·K), greater than or about 200 W / (m·K), or greater.

[0026] As described above, many materials with increased thermal conductivity that may be incorporated into a manufactured component may also be characterized by an increased coefficient of thermal expansion. In embodiments, the material used to form one or more surfaces of the manufactured component may be characterized by a linear coefficient of thermal expansion greater than or about 10x10 -6 / ℃, greater than or about 11x10 -6 / ℃, greater than or about 12x10 -6 / ℃, greater than or about 13x10 -6 / ℃, greater than or about 14x10 -6 / ℃, greater than or about 15x10 -6 / ℃, greater than or about 16x10 -6 / ℃, greater than or about 17x10 -6 / ℃, greater than or about 18x10 -6 / ℃, greater than or about 19x10 -6 / ℃, greater than or about 20x10 -6 / °C, or greater. In further embodiments, the fabricated component includes one or more metal-containing surfaces. In additional embodiments, the metal-containing surface of layer 205 may include one or more metals selected from the group consisting of aluminum, iron, copper, nickel, and titanium, among others.

[0027] Method 100 may further include forming a first layer (e.g., first layer 210) in a surface of a layer (e.g., layer 205) of the component being manufactured at operation 110. In one embodiment, a portion of the surface of layer 205 of the component being manufactured may be incorporated into the first layer during operation 110. In yet further embodiments, first layer 210 may be formed by an anodization technique that forms an anodized layer in the surface of layer 205. In yet further embodiments, the anodization technique may be selected from the group consisting of anodic aluminum oxidation, anodic titanium oxidation, barrier thick oxidation, and plasma electrolytic oxidation, among others. In additional embodiments, first layer 210 may be characterized by a thickness greater than or about 0.01 μm, a thickness greater than or about 1 μm, a thickness greater than or about 10 μm, a thickness greater than or about 25 μm, a thickness greater than or about 30 μm, a thickness greater than or about 35 μm, a thickness greater than or about 40 μm, a thickness greater than or about 45 μm, a thickness greater than or about 50 μm, or greater.

[0028] In one embodiment, the first layer 210 can be characterized as being more porous and more amorphous than the subsequently deposited second layer 215. In additional embodiments, the increased porosity of the first layer 210 provides a mechanical stress buffer for the second layer 215 by having a coefficient of thermal expansion (CTE) intermediate between the component surface layer 205 and the second layer. In further embodiments, the more amorphous grain structure of the first layer 210 provides fewer channels extending from the surface layer 205 through the first layer to the second layer 215. Fewer of these channels provides less opportunity for metal contaminants to migrate from the surface layer 205 through the first layer 210, and less opportunity for reactive species from the processing chamber to migrate to the surface layer. Furthermore, the reduced number of long channels in the first layer 210 results in less plasma arcing between the plasma region in the processing chamber and the conductive metal on the surface layer 205.

[0029] In additional embodiments, the first layer 210 may be characterized by a porosity of greater than or about 0.01 vol.% of the total volume of the layer. In further embodiments, the first layer 210 may be characterized by a porosity of greater than or about 0.1 vol.%, greater than or about 0.5 vol.%, greater than or about 1 vol.%, greater than or about 2 vol.%, greater than or about 3 vol.%, greater than or about 4 vol.%, greater than or about 5 vol.%, or greater. In further embodiments, the first layer 210 may be characterized as an amorphous or polycrystalline layer. In still further embodiments, the first layer 210 may be characterized by an average crystallinity of less than or about 50%, less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, or less. In yet further embodiments, the first layer 210 may be characterized by a coefficient of linear thermal expansion less than the CTE of the material in the surface layer 205. In embodiments, the first layer 210 can be characterized by a reduced CTE that is less than or about 90%, less than or about 80%, less than or about 70%, less than or about 60%, less than or about 50%, or less than the CTE of the material in the surface layer 205. In further embodiments, the first layer 210 can be characterized by a CTE that is greater than the CTE of the second layer 215. In additional embodiments, the first layer 210 can be characterized by a CTE that is greater than or about 50%, greater than or about 60%, greater than or about 90%, greater than or about 80%, greater than or about 90%, or greater than the CTE of the second layer 215.

[0030] In further embodiments, the first layer 210 may include one or more metals selected from the group consisting of aluminum, iron, copper, nickel, titanium, and chromium, etc. In additional embodiments, the first layer 210 may include at least one oxide of the one or more metals, such as aluminum oxide (Al2O3) or titanium oxide (TiO2), etc.

[0031] In some embodiments, forming the first layer of the protective layer in operation 110 may include anodizing the surface of the metal-containing component with plasma electrolytic oxidation (PEO). Figure 3AA portion of a metal-containing component 302 is shown with a first layer 304 of exposed surfaces incorporated into the component by PEO. In one embodiment, the PEO operation includes exposing one or more surfaces of the metal-containing component 302 to an electrolyte solution while applying a bias voltage to the component. In additional embodiments, the electrolyte solution may be an alkaline aqueous solution characterized by a pH greater than 7, greater than or about 8, greater than or about 9, greater than or about 10, or greater. In further embodiments, the electrolyte solution may include one or more dissolved salts of alkali metal hydroxides and alkaline earth metal hydroxides, etc. In further embodiments, the voltage applied to the component during the PEO operation may be greater than or about 200 volts, greater than or about 250 volts, greater than or about 300 volts, greater than or about 350 volts, greater than or about 400 volts, greater than or about 450 volts, greater than or about 500 volts, or greater.

[0032] In one embodiment, the first layer 304 formed of PEO may include a plurality of cracks, as shown by crack 306, which are formed during the anodizing process. In a further embodiment, crack 306 may extend from the top surface of the first layer downward to the surface of the metal-containing component 302. If exposed, crack 306 may provide a path for contaminants and plasma arcing. As discussed below, the plurality of cracks, including crack 306, are sealed by a second layer 308 to prevent contaminant migration and plasma arcing.

[0033] The method 100 may further include depositing a second layer (e.g., second layer 215, 308) on the first layer (e.g., first layer 210) at operation 115. The second layer 215 may have a lower porosity than the first layer 210. The lower porosity of the second layer 215 may hinder the migration of contaminants between the surface of the layer 205 and a substrate (not shown) contacting the component 200. In embodiments, the second layer 215 may be characterized by a porosity of less than or about 20 vol.%, less than or about 15 vol.%, less than or about 10 vol.%, less than or about 5 vol.%, less than or about 1 vol.%, less than or about 0.1 vol.%, less than or about 0.05 vol.%, less than or about 0.001 vol.%, or less. Figure 3B As shown in FIG, the second layer 308 may also fill cracks 306 in the first layer 304 formed of PEO to prevent contaminant migration and plasma arcing during substrate processing operations.

[0034] In one embodiment, the second layer may include one or more metals, metal borides, metal carbides, metal oxides, metal nitrides, metal oxynitrides, metal fluorides, metal oxyfluorides, metal fluoronitrides, and metal fluorooxynitrides, among others. In a further embodiment, the second layer may include one or more materials represented by the following formula: x MNy 、MO x N y MF z 、MO x F z 、MO x N y F z , wherein M represents one or more metals selected from the group consisting of Al, Y, Er, Sc, Zr, Ni, Cr, Mg, Ti, Ta, and W, and wherein x, y, and z may include integers from 1 to 6. In further embodiments, M represents one or more rare earth elements. In still further embodiments, the second layer may include one or more materials selected from the group consisting of AlO3, AlF3, AlF3-MgF2, and the like. In still further embodiments, the second layer may include one or more materials represented by the following formula: M1 x M2 y M3 z C a B b N c O d F e , wherein M1, M2, and M3 are each metals, and wherein x, y, z, a, b, c, d, and e are each greater than or equal to 0. In further embodiments, x, y, z, a, b, c, d, and e are each greater than 0. In yet additional embodiments, the metals M1, M2, and M3 are each individually selected from the group consisting of Al, Y, Er, Sc, Zr, Ni, Cr, Mg, Ti, Ta, and W, among others.

[0035] In further embodiments, the second layer may have increased corrosion resistance compared to the first layer formed in the component surface. In still further embodiments, the corrosion resistance may include the second layer's resistance to reaction with one or more reactive species contacting the second layer. In embodiments, these reactive species may include oxygen-containing species and halogen-containing species such as chlorine-containing species and fluorine-containing species, among others. In further embodiments, the corrosion resistance may include a slower etch rate when the second layer is exposed to the one or more reactive species. In still further embodiments, the second layer may be characterized by an increased corrosion resistance compared to the first layer, as measured by a slower etch rate, of greater than or about 10%, greater than or about 25%, greater than or about 50%, greater than or about 75%, greater than or about 100%, or greater.

[0036] In additional embodiments, the second layer 215 comprising a metal oxide can be deposited using an ALD process comprising alternating exposure of the substrate to a first precursor and a second precursor. In additional embodiments, the first precursor can be a metal-containing precursor and the second precursor can be an oxygen-containing precursor. ALD processes can be advantageously performed if the substrate exhibits a non-planar topography due to the conformal nature of the ALD process. ALD processes are also suitable for deposition on substantially planar surfaces.

[0037] In further embodiments, the ALD deposition of the metal oxide second layer 215 may include depositing a metal oxide material on the first layer 210. In further embodiments, the metal oxide material may include one or more of aluminum oxide, lanthanum oxide, hafnium oxide, yttrium oxide, zirconium oxide, and cerium oxide, among others. In additional embodiments, the metal oxide material may be deposited by alternating exposure of the first layer 210 to a first metal-containing precursor and a second oxygen-containing precursor. In embodiments, the first metal-containing precursor may include one or more precursors such as (tert-butylimido)tris(diethylamido)tantalum (TBTDET), tetrakis(diethylamido)titanium (TDEAT), tetrakis(dimethylamino)titanium (TDMAT), tetrakis(ethylmethylamido)titanium (TEMAT), trimethyl The second oxygen-containing precursor may include a metal-containing precursor such as aluminum (TMA), pentakis(dimethylamino)tantalum(V) (PDMAT), tetrakis(dimethylamido)hafnium (Hf(NMe2)4)(TDMAH)), tetrakis(dimethylamido)zirconium (Zr(NMe2)4)(TDMAZ)), [Ce(thd)4], [Ce(thd)3phen], [Ce(Cp)3], [Ce(CpMe)3], [Ce(iprCp)3], and the like. In further embodiments, the second oxygen-containing precursor may include one or more of nitrous oxide (N2O), oxygen (O2), ozone (O3), steam (H2O), carbon monoxide (CO), carbon dioxide (CO2), and the like.

[0038] In additional embodiments, the component including the first layer 210 can be heated during deposition of the second layer 215. In still further embodiments, the component can be heated to greater than or about 100° C., greater than or about 150° C., greater than or about 200° C., greater than or about 250° C., greater than or about 300° C., greater than or about 350° C., greater than or about 400° C., or greater.

[0039] In one embodiment, the first metal-containing precursor for the second layer 215 may be flowed into the processing chamber at a flow rate of greater than or about 200 sccm, greater than or about 400 sccm, greater than or about 600 sccm, greater than or about 800 sccm, greater than or about 1000 sccm, or greater. In additional embodiments, the first metal-containing precursor is introduced into the processing chamber with a carrier gas such as an inert gas such as nitrogen. In yet additional embodiments, the first precursor is pulsed into the processing chamber. As used herein, the word "pulsed" is intended to refer to an amount of a particular compound being intermittently or non-continuously introduced into a reaction zone of the processing chamber. In one embodiment, as a result of the pulsing of the first precursor, a monolayer of the first precursor may be formed on the substrate. In further embodiments, the first metal-containing precursor can be pulsed into the processing chamber for a duration of greater than or about 100 milliseconds (ms), greater than or about 200 ms, greater than or about 300 ms, greater than or about 400 ms, greater than or about 500 ms, greater than or about 600 ms, greater than or about 700 ms, greater than or about 800 ms, greater than or about 900 ms, greater than or about 1000 ms, or greater. In still further embodiments, the first metal-containing precursor can be heated to a temperature greater than or about 25° C., greater than or about 50° C., greater than or about 75° C., greater than or about 100° C., greater than or about 125° C., or greater.

[0040] In further embodiments, a purge operation can be performed before flowing the second oxygen-containing precursor into the processing chamber. In further embodiments, the purge operation can include flowing a purge gas into the processing chamber after reducing or stopping the supply of the first metal-containing precursor to the substrate. In further embodiments, the purge process can include pulsing a purge gas, such as argon or nitrogen, into the processing chamber for a duration greater than or about 0.5 seconds, greater than or about 1 second, greater than or about 2.5 seconds, greater than or about 5 seconds, greater than or about 7.5 seconds, greater than or about 10 seconds, or greater.

[0041] In further embodiments, the second oxygen-containing precursor may be pulsed into the processing chamber for a duration of greater than or about 0.15 seconds, greater than or about 0.5 seconds, greater than or about 1 second, greater than or about 2.5 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 15 seconds, greater than or about 20 seconds, greater than or about 25 seconds, greater than or about 30 seconds, or greater. In further embodiments, the second oxygen-containing precursor may be flowed into the processing chamber at a flow rate of greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 200 sccm, greater than or about 400 sccm, greater than or about 600 sccm, greater than or about 800 sccm, greater than or about 1000 sccm, or greater. In yet further embodiments, the second oxygen-containing precursor may be heated to greater than or about 20° C., greater than or about 25° C., greater than or about 30° C., or greater. In embodiments, a plasma is generated in the processing chamber while the second oxygen-containing precursor is flowing into the processing chamber. In a further embodiment, the plasma may be generated by applying RF power to a plasma generator, such as an ICP coil assembly or a CCP assembly. For example, the RF generator may apply RF power between about 100 W and about 300 W, such as about 200 W, and a frequency of about 13.56 MHz to the ICP coil assembly or the CCP assembly.

[0042] In yet additional embodiments, another purge process can be performed after the pulse of the second oxygen-containing precursor. The second purge process can be performed to remove any residual second precursor from the processing chamber. Similar to the purge process used for the first metal-containing precursor, the additional purge process can include pulsing a purge gas, such as argon, into the processing chamber for a duration greater than or about 0.5 seconds, greater than or about 1 second, greater than or about 2.5 seconds, greater than or about 5 seconds, greater than or about 7.5 seconds, greater than or about 10 seconds, or greater.

[0043] In some embodiments, pulsing the first metal-containing precursor and the second oxygen-containing precursor into the process chamber may be a cycle, and the cycle may include first and second purges after flowing the first precursor into the process chamber and after flowing the second precursor into the process chamber. In other embodiments, the cycle is repeated to grow the metal oxide layer. The number of cycles is based on the final thickness of the final metal oxide layer. In some embodiments, the growth rate of the metal oxide layer may be greater than or about / Cycle, greater than or approximately / Cycle, greater than or approximately / Cycle, greater than or approximately / Cycle, greater than or approximately / Cycle, greater than or approximately / cycle, or greater. For example, the growth rate of the metal oxide layer can be about Depending on the precursor materials utilized, the final thickness of the metal oxide layer can be less than or about 1 μm, less than or about 0.9 μm, less than or about 0.8 μm, less than or about 0.7 μm, less than or about 0.6 μm, less than or about 0.5 μm, less than or about 0.4 μm, less than or about 0.3 μm, less than or about 0.2 μm, less than or about 0.1 μm, or less.

[0044] In an additional embodiment, the second layer 215 comprising a metal nitride can be deposited using an ALD process comprising alternating exposure of the substrate to a first precursor and a second precursor. In an additional embodiment, the first precursor can be a metal-containing precursor and the second precursor can be a nitrogen-containing precursor. If the substrate exhibits a non-planar topography, the ALD process can be advantageously performed due to its conformal nature. The ALD process is also suitable for deposition on substantially planar surfaces.

[0045] In further embodiments, the first metal-containing precursor may include any suitable metal-containing precursor for forming metal nitride films, such as aluminum, titanium, tantalum, and the like. In one embodiment, the first metal-containing precursor is selected from the group consisting of (tert-butylimido)tris(diethylamido)tantalum (TBTDET), tetrakis(diethylamido)titanium (TDEAT), tetrakis(dimethylamino)titanium (TDMAT), tetrakis(ethylmethylamido)titanium (TEMAT), trimethylaluminum (TMA), pentakis(dimethylamino)tantalum(V) (PDMAT), and combinations thereof. In some embodiments, the metal-containing precursor is free of fluorine. In further embodiments, the second nitrogen-containing precursor may include ammonia (NH3), hydrazine (N2H4), methylhydrazine (CH3(NH)NH2), dimethylhydrazine (C2H8N2), tertiary butylhydrazine (C4H 12 N2), phenylhydrazine (C6H8N2), azoisobutane (C4H8N2), ethylazide (CH3N3), and the like.

[0046] In additional embodiments, the second layer 215 comprising a metal oxyfluoride or metal nitride fluoride may be deposited using an ALD process comprising alternating exposure of the substrate to a first precursor, a second precursor, and a third precursor. In additional embodiments, the first precursor may be a metal-containing precursor, the second precursor may be an oxygen- and / or nitrogen-containing precursor, and the third precursor may be a fluorine-containing precursor. In yet additional embodiments, the metal oxyfluoride or metal nitride fluoride layer may be deposited using ALD using alternating exposures of a first metal-containing precursor and a second fluoride-containing oxide and / or nitrogen-containing fluoride precursor. In embodiments, if the substrate exhibits a non-planar topography, the ALD process may be advantageously performed due to the conformal nature of the ALD process. The ALD process is also suitable for deposition on substantially planar surfaces.

[0047] Figure 4 A heating pedestal 400 is shown including a substrate holder 402 including multiple protective layers according to an embodiment of the present invention. A substrate 404 is placed in direct contact with the substrate holder 402 during one or more substrate processing operations. These operations may include increasing and decreasing the temperature of the substrate during one or more processing operations. The substrate holder 402 includes one or more metals, such as aluminum, with higher thermal conductivity than conventional ceramic materials to facilitate more rapid temperature changes in the substrate 404 during processing operations. Multiple protective layers (not shown) positioned between the substrate 404 and the metal surface of the substrate holder 402 prevent contaminants in the holder (including the metal used to make the holder) from migrating to the substrate. The protective layers also reduce plasma arcing between the substrate holder 402 and the plasma during operations that generate the plasma.

[0048] It should be understood that the substrate holder 402 includes a multi-layer protective coating according to embodiments of the present invention, but any of many types of substrate processing components may include a protective coating. Additional substrate processing components include faceplates and heater elements, among others. The multi-layer protective coating provides several advantages to the components, including increased corrosion resistance and increased hardness, reduced amounts of metal contaminants in substrates contacting the components, and reduced rates of plasma arcing during plasma operation, among other advantages.

[0049] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative architectures, and equivalents may be used without departing from the spirit of the embodiments. Furthermore, several well-known processes and components have not been described to avoid unnecessarily obscuring the present invention. Therefore, the foregoing description should not be construed as limiting the scope of the present invention.

[0050] When a numerical range is provided, unless the context clearly dictates otherwise, it is understood that each intervening value, to the tenth of the unit of the lower limit, between the upper and lower limits of the range is also expressly disclosed. Any stated or unstated intervening value in a stated range and any narrower range between any other stated or intervening value in the stated range are encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in that range, and subject to any expressly excluded limits in the stated range, ranges with any, none, or all of the limits in the smaller ranges are also encompassed. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0051] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a process" includes a plurality of such processes and reference to "the pixel structure" includes reference to one or more pixel structures and equivalents thereof known to those skilled in the art, and so forth.

[0052] Furthermore, the words “comprise,” “comprising,” “include,” “including,” and “includes,” when used in this specification and in the claims that follow, are intended to indicate the presence of stated features, integers, components, or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, actions, or groups.

Claims

1. A method for preparing a semiconductor manufacturing component, comprising: forming a first layer on a surface of the semiconductor fabrication component, wherein the first layer is characterized by a porosity of greater than or about 0.01 vol. %; and A second layer is deposited on the first layer, wherein the second layer is characterized by a porosity of less than or about 20 vol. %. 2 . The method of claim 1 , wherein the first layer is characterized by a thickness greater than or about 0.01 μm.

3. The method of claim 1, wherein the first layer is formed on the surface by an anodization technique selected from the group consisting of anodic aluminum oxidation, anodic titanium oxidation, barrier thick oxidation, and plasma electrolytic oxidation. The method of claim 1 , wherein the second layer is characterized by a thickness of less than or about 10 μm.

5. The method of claim 4, wherein the second layer comprises a metal, a metal boride, a metal carbide, a metal nitride, a metal oxide, a metal fluoride, a metal oxyfluoride, or M1 x M2 y M3 z C a B b N c O d F e , wherein M1, M2, and M3 are independently metals, and wherein x, y, z, a, b, c, d, and e are greater than or equal to 0.

6. The method of claim 5, wherein the second layer comprises a metal selected from the group consisting of aluminum, yttrium, erbium, scandium, zirconium, and magnesium. The method of claim 1 , wherein the surface in the semiconductor fabrication component comprises aluminum.

8. The method of claim 1, wherein the surface in the semiconductor manufacturing component is a surface on a panel or heater assembly operable to be incorporated into a semiconductor manufacturing chamber.

9. A method of processing a semiconductor manufacturing component, the method comprising: forming a first layer in a surface of the semiconductor fabrication component, wherein the first layer comprises a grain structure characterized by an amorphous, polycrystalline, crystalline, or mixed phase; and A second layer is deposited on the first layer, wherein the second layer is characterized by an amorphous, polycrystalline, crystalline, or mixed-phase grain structure.

10. The method of claim 9, wherein the first layer is characterized by a thickness greater than or about 0.01 μm. The method of claim 9 , wherein the first layer is formed on the surface by plasma electrolytic oxidation.

12. The method of claim 9, wherein the second layer is characterized by a thickness of less than or about 10 μm.

13. The method of claim 9, wherein the second layer is formed on the first layer by atomic layer deposition.

14. The method of claim 9, wherein the second layer comprises a metal oxide, a metal fluoride, or a metal oxyfluoride.

15. A semiconductor manufacturing component comprising: a surface of the semiconductor manufacturing component; a first layer formed in the surface of the semiconductor fabrication component, wherein the first layer is characterized by a porosity of greater than or about 0.01 vol. %; and A second layer is positioned on the first layer, wherein the second layer is characterized by a porosity of less than or about 20 vol. %.

16. The semiconductor manufacturing component of claim 15, wherein the surface of the semiconductor manufacturing component comprises aluminum.

17. The semiconductor manufacturing component of claim 15, wherein the first layer is characterized by a thickness greater than or about 0.01 μm, and further wherein the first layer is characterized by an amorphous grain structure.

18. The semiconductor manufacturing component of claim 15, wherein the second layer is characterized by a thickness of less than or about 10 μm, and further wherein the second layer is characterized by a crystalline grain structure.

19. The semiconductor manufacturing component of claim 15, wherein the second layer comprises a metal oxide, a metal fluoride, a metal oxyfluoride, a metal nitride, a metal oxynitride, a metal carbide, a metal oxycarbide, a metal boride, or a stoichiometric mixture of the foregoing.

20. The semiconductor manufacturing component of claim 15, wherein the component is a panel or heater assembly operable to be incorporated into a semiconductor manufacturing chamber.

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