Techniques for semiconductor die coupling in stacked memory architecture

Abstract

Methods, systems, and devices are described for techniques for semiconductor die coupling in stacked memory architectures. A semiconductor system may include a semiconductor unit formed by a plurality of semiconductor dies, wherein each semiconductor die may be fabricated to be individually separable. Each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. The plurality of semiconductor dies may be coupled with a carrier, and each semiconductor die may be (e.g., electrically, communicatively) coupled with at least one other semiconductor die. At least some of the semiconductor dies may be coupled with a respective group of one or more memory arrays, where each memory array may operate based on the coupling between the plurality of semiconductor dies.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 776,197 filed by Bhushan et al. on July 17, 2024, entitled “TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES,” and U.S. patent application No. 63 / 588,642 filed by Bhushan et al. on October 6, 2023, entitled “TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The following relates to one or more systems for memory, including techniques for coupling semiconductor dies in a stacked memory architecture. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and the like. Memory cells can be described according to either a volatile configuration or a non-volatile configuration. A memory cell in a non-volatile configuration can maintain a stored logic state for an extended period even in the absence of an external power source. A memory cell in a volatile configuration may lose its stored state when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1

[0014] An example of a system supporting techniques for semiconductor die coupling in a stacked memory architecture is shown according to examples as disclosed herein.

[0007] Figure 2

[0014] An example of a system supporting techniques for semiconductor die coupling in a stacked memory architecture is shown according to examples as disclosed herein.

[0008] Figure 3

[0014] Shown are examples of interface architectures supporting techniques for semiconductor die coupling in a stacked memory architecture according to examples as disclosed herein.

[0009] Figure 4A and 4B Examples of semiconductor components and die assemblies are shown that support techniques for semiconductor die coupling in a stacked memory architecture according to examples as disclosed herein.

[0010] Figures 5 to 12 An example of operations for forming a semiconductor system utilizing techniques for semiconductor die coupling in a stacked memory architecture according to examples as disclosed herein is described.

[0011] Figure 13 and 14 Flowcharts are shown illustrating one or several methods supporting techniques for semiconductor die coupling in a stacked memory architecture according to examples as disclosed herein. DETAILED DESCRIPTION

[0012] Some memory systems may include a stack of semiconductor dies, including one or more memory dies (e.g., array dies) or one or more stacks of stacked memory dies stacked with a logic die that is operable to access a set of memory arrays distributed across the one or more memory dies. This stacked architecture may be implemented as part of a high-bandwidth memory (HBM) system or a tightly coupled dynamic random access memory (TCDRAM) system and may support solutions with memory-centric logic, such as a graphics processing unit (GPU), among other implementations. In some examples, an HBM system may include a stack of memory dies located (e.g., positioned on, placed on) atop a logic die. In some examples, a TCDRAM system may be tightly coupled (e.g., physically, electrically, directly coupled) to a processor, such as a GPU or other host, as part of a physical memory map accessible to the processor. This coupling can include one or more processors implemented in the same semiconductor die as at least a portion of the HBM system or TCDRAM system (e.g., as part of a logic die), or one or more processors implemented in a die that is directly coupled (e.g., fused) to another die that includes at least a portion of the HBM system or TCDRAM system, or coupled in other ways (e.g., via a silicon interposer or other intervening component) to another die that includes at least a portion of the HBM system or TCDRAM system. Unlike cache-based memory, the TCDRAM system may not be supported by an external memory hierarchy with the same physical address. For example, the TCDRAM system may be associated with and located within a dedicated base address, wherein each portion of the TCDRAM system may be non-overlapping within the address.

[0013] Some semiconductor dies (e.g., logic dies) may include multiple components, such as interface blocks (e.g., memory interface blocks, interface circuitry), logic blocks, controllers, processors, and other components. In some instances, such dies may be associated with relatively low manufacturing yields, which may be related to the relative size or complexity of integrating multiple components on the same die. For example, if at least one of the components of a die fails an evaluation procedure, the die may be rejected (e.g., discarded) during the manufacturing process. That is, even though most of the components of the die may meet the evaluation, a single faulty component may cause the die to be rejected. Consequently, the likelihood that each component of a relatively complex or relatively large die will meet the evaluation may be relatively low, thereby resulting in a relatively low yield for such dies.

[0014] According to examples disclosed herein, a semiconductor component (e.g., a semiconductor unit, a semiconductor subsystem, a logic unit, a logic portion of an HBM system, a logic portion of a TCDRAM system, a heterogeneous semiconductor device) can be formed with multiple semiconductor die portions (e.g., relatively small dies, dies each including a respective subset of components of the logic unit) bonded to a carrier and interconnected with each other. At least some, if not all, of the die portions can be individually qualified for evaluation (e.g., they can be known good dies (KGDs) before interconnection). In some examples, the die portions can be referred to as "chiplets" (e.g., logic chiplets), and each chiplet can include a respective portion of circuitry that can otherwise be associated with the functionality of the relatively larger die. For example, such a semiconductor component can be formed with a first chiplet including memory interface circuitry, a second chiplet including processor circuitry, a third chiplet including logic circuitry, and other examples of subdivision of circuitry. The plurality of chiplets can be interconnected with conductive paths (e.g., in redistribution layers (RDLs) via the backside of at least some of the chiplets) and with one or more through-silicon vias (TSVs) in each of the chiplets, which can involve various semiconductor fabrication technologies that join the chiplets. At least some of the chiplets can further be coupled with one or more memory dies (e.g., stacked memory dies). In some implementations, the one or more stacked memory dies can have dedicated conductive paths (e.g., for a power distribution network (PDN), using through-reconstruction vias (TRVs)) for power delivery or other signals that bypass the chiplets (e.g., bypass one or more dies of the logic layer).

[0015] By supporting the subdivision and coupling of multiple chiplets (e.g., making up a multi-die semiconductor unit), a relatively small portion of the wafer can be rejected (e.g., based on rejecting faulty chiplets), which can support increased yield of the wafer. As a result, the manufacturing yield of multi-die semiconductor units (e.g., logic units) can be improved compared to the yield of single-die semiconductor units (e.g., based on the increased yield of interconnecting relatively small KGD chiplets). In addition, dedicated conductive paths (e.g., for delivering power to one or more memory dies) can be associated with lower resistance and may not occupy area in the substrate of other dies (e.g., of a single-die logic system), which can support increased semiconductor circuitry area, increased wafer circuitry yield, and improved memory system performance.

[0016] In addition to its applicability in the systems described herein, the techniques for coupling semiconductor dies in stacked memory architectures can generally be implemented to support artificial intelligence or machine learning applications, as well as other types of computationally intensive applications. As the use of artificial intelligence increases to support machine learning, analytics, decision-making, or other related applications, electronic devices that support artificial intelligence applications and programs may be desirable. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from memory systems that can effectively and efficiently store relatively large amounts of data or access the stored data relatively quickly. Implementing the techniques described herein can support artificial intelligence and machine learning technologies by supporting higher device yields and interconnectivity, including by forming semiconductor units (e.g., logic dies in HBM systems, logic dies in TCDRAM systems) from relatively small semiconductor die portions (e.g., rather than as a single monolithic unit). Such techniques can allow relatively small components to be rejected and remaining smaller components to be accepted, which can improve the manufacturing yield of devices that support artificial intelligence and machine learning technologies. Furthermore, the yield of such devices can be improved based on dedicated vias for delivering power to the memory array (e.g., rather than routing power through the circuitry of other dies), which can support increased circuit density on the wafer. Furthermore, the techniques herein can improve the power efficiency of memory arrays (e.g., tightly coupled stacks of array dies), thereby supporting increased performance and reduced latency for stacked memory architectures.

[0017] Features of the present disclosure are illustrated and described in the context of systems and dies. Features of the present disclosure are further illustrated and described in the context of interface architectures, semiconductor components, die assemblies, illustrative fabrication techniques, and flow charts.

[0018] Figure 1 An example of a system 100 supporting techniques for coupling semiconductor dies in a stacked memory architecture according to examples as disclosed herein is shown. The system 100 may comprise part of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 coupling the host system 105 with the memory system 110 (e.g., to provide a communicative coupling). The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system 110.

[0019] The host system 105 may be an example of a processing system (e.g., circuitry, one or more processors, an application processing system, processing circuitry, one or more processing components) that uses memory to execute processes (e.g., applications, functions, calculations) (e.g., a processing system of a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic device, among other examples). The host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers (not shown)). The components of the host system 105 may be coupled to each other using a bus 135.

[0020] The external memory controller 120 can be configured to facilitate communication of information (e.g., data, commands, control information, configuration information) between components of the system 100 (e.g., between components of the host system 105 (e.g., the processor 125) and the memory system 110). For example, the external memory controller 120 can generate commands (e.g., in response to or to otherwise support an application of the host system 105) to write data to the memory system 110, read data from the memory system 110, or otherwise communicate with the memory system 110. The external memory controller 120 can process (e.g., convert, translate) communications exchanged between the host system 105 and the memory system 110. In some examples, the external memory controller 120, or other components of the system 100, or associated functionality described herein, can be implemented by or be part of the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is illustrated as being external to the memory system 110, in some examples, the external memory controller 120, or its functionality described herein, can be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165), or vice versa. In various examples, the host system 105 or the external memory controller 120 can be referred to as a host.

[0021] Processor 125 is operable to provide functionality (e.g., control functionality, processing functionality) for system 100 or host system 105. Processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof (e.g., as one or more processing components that are individually or collectively configured to support an application of host system 105). In some examples, processor 125 can be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a SoC, among other examples.

[0022] In some examples, system 100 or host system 105 may include input components, output components, or a combination thereof. Input components may include sensors, microphones, keyboards, another processor (e.g., on a printed circuit board), interfaces (e.g., user interfaces, interfaces between other devices), or peripherals that interface with system 100 via one or more peripheral components, among other examples. Output components may include displays, audio speakers, printing devices, another processor on a printed circuit board, or peripherals that interface with system 100 via one or more peripheral components, among other examples.

[0023] The memory system 110 may be a component of the system 100 operable to provide physical memory locations (e.g., addresses) that can be used or referenced by the system 100 (e.g., by the host system 105). The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity for data storage. The memory system 110 may be configured to operate with one or more different types of host systems 105 and may respond to and execute commands provided by the host system 105 (e.g., via the external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive a write command indicating that the memory system 110 will store data received from the host system 105, or a read command indicating that the memory system 110 will provide data stored in the memory die 160 to the host system 105, or a refresh command indicating that the memory system 110 will refresh data stored in the memory die 160, among other types of commands and operations.

[0024] The memory system controller 155 may include components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory system controller 155 may cooperate with the local memory controller 165 of the memory die 160 to control the operation of the memory system 110.

[0025] Each memory die 160 may include one or more local memory controllers 165 and one or more memory arrays 170. A memory array 170 may be a collection of memory cells, each of which is operable to store one or more bits of data. A memory array 170 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some examples, a two-dimensional (2D) memory die 160 may include a single memory array 170. In some examples, a three-dimensional (3D) memory die 160 may include two or more memory arrays 170 that may be stacked or positioned side by side (e.g., relative to a substrate) with respect to one another.

[0026] The local memory controller 165 may include components (e.g., circuitry, logic, instructions) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the memory system controller 155 (e.g., to receive or transmit data or commands, or both). In some examples, the memory system 110 may not include a memory system controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, a sensing component for sensing the state of memory cells of the memory array 170, a writing component for writing the state to the memory cells of the memory array 170, or various other components operable to support the described operations of the memory system 110.

[0027] The host system 105 (e.g., external memory controller 120) and the memory system 110 (e.g., memory system controller 155) can use one or more channels 115 to communicate information (e.g., data, commands, control information, configuration information). Each channel 115 can be an example of a transmission medium that carries information, and each channel 115 can include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals associated with components of the system 100. For example, a channel 115 can be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. A terminal can be an example of an electrically conductive input or output point of a device of the system 100, and the terminal can be operable to serve as part of a channel 115. In some implementations, at least the channel 115 between the host system 105 and the memory system 110 can include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) at the host system 105 (e.g., at the external memory controller 120), or at the memory system 110 (e.g., at the memory system controller 155), or at both.

[0028] In some examples, channels 115 (e.g., associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, signaling may be conveyed via channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either the rising or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be registered for each clock cycle (e.g., on both the rising and falling edges of a clock signal).

[0029] In some examples, at least a portion of system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some such implementations, circuitry for accessing one or more memory arrays 170 (e.g., circuitry of memory system 110) may be distributed across multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., memory interface blocks, instances of first interface circuitry), and one or more second dies may include corresponding second interface blocks, each configured to access one or more memory arrays of the second die, each coupled to the first interface block of the first die. In some examples, the system may include a controller (e.g., a memory controller, an interface controller, a host interface controller, at least a portion of external memory controller 120) for each set of one or more first interface blocks to support access operations (e.g., accessing one or more memory arrays 170) via the set of first interface blocks. In some examples, such controllers may be located on the same first die as the first interface blocks.

[0030] In some examples, multiple semiconductor dies of memory system 110 or system 100 (e.g., an HBM system including aspects of memory system 110, a TCDRAM system including aspects of memory system 110 and host system 105) may include one or more array dies (e.g., memory die 160) stacked with a logic die (e.g., including aspects of host system 105, coupled to another die or other component including host system 105), the logic die including an interface block operable to access a set of memory arrays 170 distributed across one or more second dies. System 100 or portions thereof having a stacked memory architecture may support techniques for semiconductor die coupling in a stacked memory architecture. For example, a semiconductor unit (e.g., a semiconductor component, a logic unit) may be formed with multiple semiconductor die portions (e.g., chiplets, logic chiplets) interconnected after an evaluation process (e.g., as interconnects of logic chiplets (e.g., KGDs) that meet the evaluation). At least some of the chiplets may be further coupled to one or more stacked memory arrays 170, which may also have dedicated vias (e.g., PDN through vias (TVs), TRVs) for power delivery. Thus, the manufacturing yield of the memory system 110 or system 100 (e.g., an HBM system, a TCDRAM system) may be improved based on forming a semiconductor unit having multiple semiconductor chiplets and dedicated vias, and the memory system 110 may have improved power efficiency based on delivering power to the one or more stacked memory arrays 170 via the one or more dedicated vias.

[0031] Figure 2An example of a system 200 (e.g., a semiconductor system, a system for coupling semiconductor dies, an HBM system, a TCDRAM system) supporting techniques for semiconductor die coupling in a stacked memory architecture according to examples disclosed herein is shown. System 200 illustrates an example of a die 205 (e.g., die 205-a, a semiconductor die, a logic die, a processor die, a host die, a logic unit) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, a semiconductor die, a memory die, an array die, a memory cell). Die 205 or 240 can be formed using a respective semiconductor substrate (e.g., a substrate of a crystalline semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or gallium nitride), a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG), silicon-on-sapphire (SOS)), or an epitaxial semiconductor material formed on another substrate, among other examples. Although the illustrated example of system 200 includes two dies 240, a system 200 according to the described techniques may include any number of one or more dies 240 coupled to die 205, as well as other dies in stacked or other coupled arrangements. Furthermore, although the non-limiting examples of system 200 are generally described herein in terms of applicability to memory systems, memory subsystems, memory devices, or combinations thereof, examples of system 200 are not limited thereto. For example, aspects of the present disclosure may also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communications, power, artificial intelligence, system-on-chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0032] System 200 illustrates an example of interface circuitry between a host and memory (e.g., via a host interface, via a physical host interface) implemented in (e.g., partitioned among) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205-a may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 including interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, die 240-a-2 including interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0033] Although the example of system 200 is illustrated as having one interface block 245 included in each die 240, a die 240 according to the described techniques may include any number of one or more interface blocks 245, each coupled to a corresponding set of one or more memory arrays 250 and to the interface block 220 of die 205. Thus, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, with each interface block 220 coupled (e.g., in communication) with one or more interface blocks 245 of die 240 (e.g., external to die 205). In some examples, the coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels (e.g., one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or a combination thereof)) may include or be referred to as a data path associated with the corresponding set of one or more memory arrays 250.

[0034] In some embodiments (e.g., TCDRAM embodiments), die 205 may include a host processor 210. Host processor 210 may be an example of host system 105, or a portion thereof (e.g., an aspect of processor 125, external memory controller 120, or both). Host processor 210 may be configured to perform operations that implement storage of memory array 250 (e.g., to support applications or other functions of host system 105 that may request access to memory array 250). For example, host processor 210 may receive data to be read from memory array 250, or may transmit data to be written to memory array 250, or both (e.g., depending on the application or other operation of host processor 210). Additionally or alternatively, host processor 210 may be external to die 205 (e.g., in HBM embodiments), such as in another semiconductor die or other component that is coupled (e.g., communicatively coupled, directly coupled, bonded, coupled via another intervening component) to die 205 via one or more contacts 212 (e.g., externally accessible terminals of die 205).

[0035] The host processor 210 may be configured to communicate (eg, transmit, receive) signals with the interface block 220 via the host interface 216 (eg, a physical host interface), which may implement reference Figure 1 In some examples, the host interface 216 can provide a communication coupling between the physical or functional boundaries of the host system 105 and the memory system 110. For example, the host processor 210 can be configured to communicate access signaling (e.g., control signaling, access command signaling, data signaling, configuration signaling) via the host interface 216 to support access operations (e.g., read operations, write operations) and other operations to the memory array 250. Although the example of the system 200 includes a single host interface 216, a system according to the described techniques can include any number of one or more host interfaces 216 for accessing the memory array 250 of the system.

[0036] In some examples, a respective host interface 216 can be coupled between a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2) and a respective controller 215. The controller 215 can be an example of control circuitry (e.g., memory controller circuitry, host interface control circuitry) associated with the host system 105 and can be associated with a respective instance that implements one or more aspects of the external memory controller 120 or the memory system controller 155, or a combination thereof. For example, the controller 215 can be operable to respond to instructions (e.g., requests, commands) from the host processor 210 to access one or more memory arrays 250 to support functions or applications of the host processor 210, transmit associated commands (e.g., for one or more interface blocks 220) to access the one or more memory arrays 250, and communicate data (e.g., write data, read data) with the host processor 210, among other functions.

[0037] In some examples, one or more controllers 215 may be implemented in die 205 (e.g., the same die that includes one or more interface blocks 220), regardless of whether host processor 210 is included in die 205 or external to die 205. In some other examples, controller 215 or associated circuitry or functionality may be implemented external to die 205 (e.g., in another die (not shown), coupled to a respective interface block 220 via a respective terminal of each of respective host interfaces 216), which may be in the same or a different die than the die that includes host processor 210. Interface block 220 may operate via a single controller 215 or through one or more of a group of multiple controllers 215 (e.g., according to a controller multiplexing scheme). In some other examples, aspects of one or more controllers 215 may be included in host processor 210 (e.g., as a memory interface for host processor 210, as a memory interface for host system 105).

[0038] While in some examples, the controller 215 may be directly coupled to one or more interface blocks 220 (not shown), in some other examples, the controller 215 (e.g., the host interface 216) may be coupled to a set of multiple interface blocks 220 via a logic block 225 (e.g., logic circuitry for a channel group, logic circuitry for the host interface 216, multiplexing circuitry). For example, the logic block 225 may be coupled to the interface block 220-a-1 via a bus 223-a-1 and to the interface block 220-a-2 via a bus 223-a-1. The controller 215 and the one or more corresponding interface blocks 220 may communicate (e.g., collaborate) using the host interface 216 via the logic block 225 to perform one or more operations associated with accessing a set of corresponding one or more memory arrays 250 (e.g., scheduling operations, access operations, operations initiated by the host processor 210).

[0039] In some examples, the logic block 225, the controller 215, or the host interface 216, or a combination thereof, can be associated with a “channel group” corresponding to multiple memory arrays 250 (e.g., for parallel or otherwise coordinated access of the multiple memory arrays 250). For example, such a channel group can be associated with multiple memory arrays 250 accessed via a single interface block 245, or multiple memory arrays 250 accessed via respective ones of the interface blocks 245, or multiple memory arrays 250 accessed via respective ones of the interface blocks 220, any of which can be associated with signaling via a single logic block 225, via a single host interface 216, or via a single controller 215. These and other configurations for implementing one or more channel groups in a system can support various techniques for parallel and high-bandwidth data transfer, memory management operations, repair and replacement techniques, or power and thermal distribution, as well as other techniques that utilize the described coupling of components and interfaces in multiple semiconductor dies (e.g., according to a high-bandwidth memory configuration of the system 200, according to a tightly coupled configuration of the system 200). In some examples, such techniques may be implemented (eg, at or using logic block 225 ) in a manner transparent to host interface 216 or other aspects of host system 105 .

[0040] In some examples, the host interface 216 may include a respective set of one or more signal paths for each logic block 225 or interface block 220, such that the host processor 210 can communicate with each logic block 225 or interface block 220 via its corresponding set of signal paths (e.g., based on selection of the corresponding set to perform access operations via the logic block 225 or interface block 220 selected by the host processor 210). Additionally or alternatively, the host interface 216 may include one or more signal paths shared among multiple logic blocks 225 (not shown) or interface blocks 220, and the logic blocks 225, interface blocks 220, or host processor 210, or any of these, may interpret, ignore, respond to, or refrain from responding to signaling via the shared signal paths of the host interface 216 based on a logic indication (e.g., an addressing indication associated with the logic block 225 or interface block 220, an interface enable signal, or an interface select signal, which may be provided by the host processor 210, the corresponding logic block 225, or the corresponding interface block 220, depending on the signaling direction).

[0041] In some examples, the host processor 210 may determine an access address (e.g., a logical address of the memory array 250, a physical address of the memory array 250, an address of the logic block 225, an address of the interface block 220, an address of the host interface 216, in response to an application of the host processor 210 or an application supported by the host processor 210) and determine to which controller 215 to transmit access signaling for the access address (e.g., the controller 215, logic block 225, or interface block 220 corresponding to the address). In some examples, the address may be associated with a row of memory cells of the memory array 250, a column of memory cells of the memory array 250, or both. The host processor 210 may transmit access signaling (e.g., one or more access signals, one or more access commands) to the determined controller 215, and the determined controller 215 may, in turn, transmit the access signaling to the corresponding logic block 225 or interface block 220. The corresponding interface block 220 may then transmit access signaling to the coupling interface block 245 to access the determined address (eg, of the corresponding memory array 250).

[0042] Die 205 may also include a logic block 230 (e.g., a shared logic block, a central logic block, common logic circuitry, evaluation circuitry, memory system configuration circuitry, memory system management circuitry) that may be configured to communicate (e.g., transmit, receive) signaling with logic block 225, interface block 220, or both of die 205. In some cases, logic block 230 may be configured to communicate information (e.g., commands, instructions, directives, data) with one or more logic blocks 225 or interface blocks 220 to facilitate operation of system 200. For example, logic block 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling) that may be received by logic block 225 or interface block 220 to support configuration of logic block 225 or interface block 220, or to operate other aspects of die 240 (e.g., via corresponding interface block 245). Logic block 230 may be coupled to each logic block 225 and each interface block 220 via respective buses. In some examples, such buses may each include a respective set of one or more signal paths, such that logic block 230 may communicate with each logic block 225 or each interface block 220 via the respective set of signal paths. Additionally or alternatively, such buses may include one or more signal paths (not shown) that are shared among multiple logic blocks 225 or interface blocks 220.

[0043] In some embodiments, logic block 230 can be configured to communicate (e.g., transmit, receive) signals with host processor 210 (e.g., via a bus, via contacts 212 for host processor 210 external to die 205) so that logic block 230 can support an interface between host processor 210 and logic block 225 or interface block 220. For example, host processor 210 can be configured to transmit initialization signaling (e.g., a power-on command) or other configuration or operational signaling, which can be received by logic block 230 to support initialization, configuration, evaluation, or other operation of logic block 225 or interface block 220. Additionally or alternatively, in some embodiments, logic block 230 can be configured to communicate (e.g., transmit, receive) signals with a component external to system 200 (e.g., via contacts 234, which can be externally accessible terminals of die 205) so that logic block 230 can support an interface that bypasses host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210 and may communicate with one or more memory arrays 250 of one or more dies 240 (e.g., to perform self-test operations for accessing memory arrays 250). In some examples, such implementations may support evaluation, configuration, or other operations of system 200 during manufacturing, assembly, verification, or other operations associated with system 200 (e.g., prior to coupling with host processor 210, for operation independent of host processor 210, without implementing host processor 210), via one or more contacts 234 accessible at the system's physical interface. Additionally or alternatively, logic block 230 may implement one or more aspects of controller 215. For example, logic block 230 may include or operate as one or more controllers 215 and may perform operations attributed to controller 215.

[0044] Each interface block 220 can be coupled to at least a corresponding bus 221 of die 205 and a corresponding bus 246 of die 240, which are configured to communicate (e.g., via one or more associated signal paths) signals with the corresponding interface block 245. For example, interface block 220-a-1 can be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 can be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some examples, die 240 can include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 can be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which can bypass interface block 245 of die 240-a-1. Such techniques can be extended for interconnection in more than two dies 240 (e.g., for interconnection via respective buses 255 of multiple dies 240).

[0045] The respective signal paths of buses 221, 246, and 255 can be coupled to each other from one die to another via various contact arrangements at the surfaces of the interfacing dies (e.g., exposed contacts, metal surfaces of the respective dies). For example, bus 221-a-1 can be coupled to bus 246-a-1 via contact 222-a-1 of die 205-a (e.g., at its surface) and contact 247-a-1 of die 240-a-1, bus 221-a-2 can be coupled to bus 255-a-1 via contact 222-a-2 of die 205 and contact 256-a-1 of die 240-a-1, bus 255-a-1 can be coupled to bus 246-a-2 via contact 257-a-1 of die 240-a-1 and contact 247-a-2 of die 240-a-2, and so on. While each respective bus is illustrated as having a single line coupled via a single contact, it should be understood that each signal path of a given bus may be associated with a respective contact to support separate communication coupling of each signal path via the given bus. In some examples, bus 255 may traverse a portion of die 240 (e.g., in an in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement, in a staircase arrangement), which may support an arrangement of contacts 222 along the surface of die 205, in which case die 205 is coupled to interface blocks 245 of different dies 240 along a stacking direction (e.g., via respective contacts 256 and 257 that are non-overlapping when viewed along the thickness direction).

[0046] Interconnection of the interface contacts can be supported by various techniques. For example, in a hybrid bonding embodiment, the interface contacts can be coupled by fusing the conductive material (e.g., conductive material) of the interface contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembled condition, the coupling of die 205-a and die 240-a-1 can include fusing the conductive material of contact 222-a-2 with the conductive material of contact 256-a-1, and the coupling of die 240-a-1 and die 240-a-2 can include fusing the conductive material of contact 257-a-1 with the conductive material of contact 247-a-2, and so on. In some examples, such coupling can include an ineffective fusing of contacts (e.g., non-communicative coupling, physical coupling), such as fusing contact 260-a-1 with contact 256-a-2, neither of which is coupled to the operating circuitry of die 240-a-1 or 240-a-2. In some instances, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contact 260 that may not be operably coupled to interface block 245 or interface block 220), or such coupling may be a byproduct of duplication of components that may be operable or inoperative in various configurations (e.g., where for a die 240 having a common arrangement of contacts 256 and 257, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0047] In some examples, the fusion of conductive material between the dies (e.g., between contacts) can be accompanied by fusion of other materials at one or more surfaces of the interfacing dies. For example, in an assembled condition, the coupling of die 205 and die 240-a-1 can include fusion of dielectric material 207 (e.g., a non-conductive material) of die 205-a with dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 and die 240-a-2 can include fusion of dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some examples, such dielectric materials can include oxides, nitrides, carbides, oxynitrides, oxycarbides, or other transformations or doping of the substrate material (e.g., semiconductor substrate material) of die 205 or die 240, as well as other materials that can support such fusion. However, the coupling between die 205 and die 240 may be implemented according to other techniques, which may implement solder, adhesives, thermal interface materials, and other intervening materials.

[0048] In some examples, the dies 240 may be coupled in a stack (e.g., forming a "cube" or other arrangement of dies 240), and one or more of such stacks may subsequently be coupled to the die 205 (e.g., in a stack-to-chip bonding arrangement). In some examples, a respective group of one or more dies 240 may be coupled to each die 205 of the plurality of dies 205 as formed in a wafer (e.g., before dicing the wafer of dies 205, in a chip-to-wafer bonding arrangement, in a stack-to-wafer bonding arrangement), and the dies 205 of the wafer to which the respective groups of dies 240 are coupled may be separated from each other (e.g., by at least dicing the wafer of dies 205). In some other examples, a respective group of one or more dies 240 may be coupled to the respective die 205 (e.g., in a chip-to-chip bonding arrangement) after the dies 205 are separated from the wafer of dies 205. In some other examples, one or more wafers, each comprising a respective group of a plurality of dies 240, may be coupled into a stack (e.g., in a wafer-to-wafer bonding arrangement). In various examples, such techniques may then be used to separate the stack of dies 240 from the coupled wafers, or the wafer stack with dies 240 may be coupled to another wafer comprising a plurality of dies 205 (e.g., in a second wafer-to-wafer bonding arrangement), after which the system 200 may be separated from the coupled wafers. In some other examples, in addition to other examples for forming the system 200, the wafer-to-wafer coupling technique may be implemented by stacking one or more wafers of dies 240 (e.g., sequentially) on top of a wafer of dies 205 before separation into the system 200.

[0049] Buses 221, 246, and 255 can be implemented to provide configured signaling (e.g., coordinated signaling, logical signaling, modulated signaling, digital signaling) between interface block 220 and corresponding interface block 245, which can involve various modulation or coding techniques through a transmission interface block (e.g., through a driver component of the transmission interface block). In some examples, this signaling can be supported (e.g., accompanied) by clock signaling communicated via the respective buses (e.g., in conjunction with the signal transmission). For example, the buses can be configured to pass one or more clock signals transmitted by interface block 220 for reception by interface block 245 (e.g., to trigger signal reception by a latch or other receiving component of interface block 245 to support clocked operations of interface block 245). Additionally or alternatively, the buses can be configured to pass one or more clock signals transmitted by interface block 245 for reception by interface block 220 (e.g., to trigger signal reception by a latch or other receiving component of interface block 220 to support clocked operations of interface block 220). Such clock signals may be associated with the communication (e.g., unidirectional communication, bidirectional communication, deterministic communication) of various signaling such as control signaling, command signaling, data signaling, or any combination thereof. For example, a bus may include one or more signal paths for communicating a data bus (e.g., one or more data lanes, a DQ bus, via a data interface of an interface block) according to one or more corresponding clock signals (e.g., a data clock signal), or one or more signal paths for communicating a control bus (e.g., a command / address (C / A) bus, via a command interface of an interface block) according to one or more clock signals (e.g., a control clock signal), or any combination thereof.

[0050] Interface block 220, interface block 245, logic block 225, and logic block 230, respectively, may include circuitry (signaling circuitry, multiplexing circuitry, processing circuitry, controller circuitry, logic circuitry, physical components, hardware) in various configurations (e.g., hardware configurations, logic configurations, software or instruction configurations) that support functionality assigned to the respective blocks for accessing or otherwise operating a set of corresponding memory arrays 250. For example, interface block 220 may include circuitry configured to perform a first subset of operations to support access of memory array 250, and interface block 245 may include circuitry configured to perform a second subset of operations to support access of memory array 250. In some examples, interface block 220, interface block 245, and logic block 225 may support functional partitioning or distribution of functionality associated with memory system controller 155, local memory controller 165, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, logic block 225, or a combination thereof, and may support implementation of one or more aspects of memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or controller 215, or operations performed without commands from host processor 210 or controller 215 (e.g., operations determined or initiated by interface block 225, operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0051] In some implementations, system 200 may include one or more instances of non-volatile storage (e.g., non-volatile storage 235 of die 205, non-volatile storage 270 of one or more dies 240, or a combination thereof). In some examples, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof, may be configured to communicate signaling with the one or more instances of non-volatile storage. For example, logic block 230, logic block 225, interface block 220, or interface block 245, where applicable, may be coupled to the one or more instances of non-volatile storage via one or more buses (not shown) or corresponding contacts (not shown), each of which may include one or more signal paths operable to communicate signaling (e.g., command signaling, data signaling). In some examples, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of non-volatile storage. Additionally or alternatively, in some examples, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (e.g., configuration information, evaluation information) to be stored in one or more instances of non-volatile storage. In some examples, such non-volatile storage may include fuses, antifuses, or other types of one-time programmable storage elements, or any combination thereof.

[0052] In some embodiments, system 200 may include one or more sensors (e.g., one or more sensors 237 of die 205, one or more sensors 275 of one or more dies 240, or a combination thereof). In some embodiments, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements of one or more sensors of system 200. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, or other types of sensors. In some examples, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of one or more sensors. For example, logic block 230 may configure one or more operations of logic block 225 or interface block 220 based on signaling (e.g., indication, data) received from one or more sensors. Additionally or alternatively, logic block 225 or interface block 220 may generate access signaling based on one or more sensors for transmission to corresponding interface block 245.

[0053] In some examples, the circuitry of logic block 225, interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from a doped portion of a substrate of the corresponding die. In some examples, the substrate of die 205 may have characteristics (e.g., material, material properties, physical shape, or size) that differ from characteristics of a substrate of die 240. Additionally or alternatively, in some examples, transistors formed from the substrate of die 205 may have characteristics (e.g., manufacturing characteristics, performance characteristics, physical shape, or size) that differ from transistors formed from the substrate of die 240 (e.g., according to a different transistor architecture, according to a different transistor design).

[0054] In some examples, the interface block 220 can support a layout of one or more components within the interface block 220. For example, the layout can include paired components for sharing access ports (e.g., command ports, data ports). Furthermore, in some examples, the layout can support an interface for the controller 215 (e.g., host interface 216) that is different from the interface for the interface block 245 (e.g., via bus 221). For example, the host interface 216 can be synchronous and have separate channels for read and write operations, while the interface between the interface block 220 and one or more interface blocks 245 can be asynchronous and support read and write operations using the same channel. In some examples, signaling for the host interface 216 can be implemented using deterministic timing (e.g., deterministic timing between the controller 215 and the logic block 225 or one or more interface blocks 220), which can be associated with configured timing between a first signal and a responsive second signal. In some examples, signaling between interface block 220 and one or more interface blocks 245 may be implemented using timing that is different from the timing of host interface 216 (e.g., according to a different clock frequency, according to a timing offset, such as a phase offset), which may be deterministic or non-deterministic.

[0055] The die 240 may include one or more cells 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of cells 265. Although each die 240 of the system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described techniques may include any number of cells 265, which may be arranged in various patterns (e.g., groups of one or more cells 265 along a row direction, groups of one or more cells 265 along a column direction, and other patterns). Each cell 265 may include at least the circuitry of a corresponding interface block 245, as well as the memory array 250, bus 251, bus 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some examples, each unit 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260, where applicable (e.g., associated with respective interface blocks 245 of units 265 of different dies 240), which may support varying degrees of stackability or modularity in or through units 265 of other dies 240. Although examples of nonvolatile storage 270 and sensor 275 are illustrated as being external to unit 265, in some other examples, nonvolatile storage 270, sensor 275, or both may additionally or alternatively be included in unit 265.

[0056] In some examples, the interface block 220 may include circuitry configured to receive first access command signaling (e.g., from the host processor 210, from the controller 215, from the logic block 225, via the host interface 216, from the host processor 210 or the controller 215 external to the die 205 via the one or more contacts 212, based on a request from a host application) and transmit second access command signaling to a corresponding (e.g., coupled) interface block 245 based on (e.g., in response to) the received first access command signaling. The interface block 245 may accordingly include circuitry configured to receive second access command signaling from the corresponding interface block 220 and, in some examples, access a corresponding bank of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various examples, the first access command signaling may include an access command associated with an operation type (e.g., a read operation, a write operation, a refresh operation, a memory management operation), which may be associated with an indication of an address (e.g., a logical address, a physical address) of one or more memory arrays 250. In some examples, the first access command signaling may include an indication of a logical address associated with the memory array 250, and the circuitry of the interface block 220 may be configured to generate the second access command signaling to indicate a physical address associated with the memory array 250 (e.g., a row address, a column address, using a logical-to-physical (L2P) table or other mapping or calculation functionality of the interface block 220).

[0057] In some examples, to support write operations of the system 200, the circuitry of the interface block 220 may be configured to receive first data signaling associated with a first access command signaling (e.g., from the host processor 210, from the controller 215, from the logic block 225), and transmit second data signaling (e.g., associated with a second access command signaling) based on the received first access command signaling and the first data signaling. The interface block 245 may accordingly be configured to receive second data signaling and, based on the received second access command signaling and the second data signaling, write data to the one or more memory arrays 250 (e.g., according to the indicated address associated with the first access command signaling). In some examples, the interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, an ECC engine) that enables the interface block 220 to generate second data signaling based on performing error control operations using the received first data signaling (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits to be conveyed in the second data signaling and written with the data).

[0058] In some examples, to support read operations of system 200, the circuitry of interface block 245 can be configured to read data from memory array 250 based on received second access command signaling and transmit first data signaling based on the read data. Interface block 220 can accordingly be configured to receive the first data signaling and transmit second data signaling based on the received first data signaling (e.g., to host processor 210, to controller 215, to logic block 225). In some examples, interface block 220 can include error control functionality that enables interface block 220 to generate second data signaling based on performing error control operations using the received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0059] In some examples, access command signaling and other signaling transmitted to the interface block 245 may be generated according to various determination or generation techniques configured at the interface block 220 or logic block 225 (e.g., based on access command signaling received from the host processor 210, based on start signaling received from the host processor 210, without receiving or otherwise independently of signaling from the host processor 210) (e.g., based on access command signaling received from the host processor 210, based on start signaling received from the host processor 210, without receiving or otherwise independently of signaling from the host processor 210). In some examples, such techniques may involve signaling or other coordination with the logic block 230, the logic block 225, the host processor 210, one or more controllers 215, one or more instances of non-volatile storage devices, one or more sensors, or any combination thereof. Such techniques may enable the interface block 220 or logic block 225 to configure aspects of access operations and other operations performed on the memory array 250 through the corresponding interface block 245. For example, interface block 220 or logic block 225 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, adverse access (e.g., row hammer) mitigation circuitry, and other circuitry operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0060] According to examples disclosed herein, the functionality of die 205 can be implemented as a semiconductor unit (e.g., a semiconductor system) formed with multiple semiconductor die portions (e.g., semiconductor chiplets, relatively small semiconductor dies, KGDs), wherein each die portion can include a respective portion of the circuitry associated with die 205. For example, cell 280 can represent a portion of a circuitry component included in a die portion (e.g., included in a chiplet), and a die portion can include an integer multiple of cells 280. In some examples, each semiconductor die portion of a semiconductor unit can include a different respective portion of the circuitry. As a non-limiting example, a semiconductor unit (e.g., having the functionality of die 205) can be formed from one or more first die portions including one or more cells 280-a-1 and one or more second die portions including one or more cells 280-a-2. One or more units 280-a-1 may include one or more interface blocks 220, logic blocks 225, or any combination thereof, and one or more units 280-a-2 may include host processor 210, one or more controllers 215, logic blocks 230, or any combination thereof. Although non-limiting examples of units 280 are shown, each unit 280 may include any combination of components of die 205 or other components. For example, unit 280-a-1 may additionally include logic blocks 230, or logic blocks 225 may be included in a different unit 280 (e.g., in a different unit 280 of another chiplet, in a partitioned HBM or TCDRAM implementation). In some instances, one or more dies 240 of a corresponding group may be stacked on a corresponding die portion (e.g., a die portion having one or more units 280-a-1), and the corresponding die portion may include a circuit system for operating (e.g., controlling) the one or more dies 240 of the corresponding group (e.g., unit 280-a-1 may correspond to one or more units 265 for each die 240 in the corresponding group).

[0061] According to the techniques herein, the first die portion and the second die portion can be formed separately (e.g., can have separate substrates, can be cut from different wafers) and can be coupled (e.g., electrically, functionally) to each other during processing (e.g., after the die portions are built as KGDs according to semiconductor manufacturing techniques) as part of forming a semiconductor unit (e.g., rather than forming die 205 as a single monolithic unit from a wafer). In some examples, the first die portion can be coupled to the second die portion via one or more conductive signal paths, which can be included in one or more conductive layers of an RDL (e.g., above the first die portion and the second die portion). The one or more conductive paths can be examples of or include host interface 216, bus 231, bus 232, bus 233, or other conductive signal paths described herein. In some examples, one or more conductive paths may be formed along multiple (e.g., two, three, or more) different depths in parallel with one or more other conductors (e.g., TSVs, PDN TRVs) as part of the fabrication of a semiconductor unit, such as in a dual damascene operation, a triple damascene operation, or a combination thereof.

[0062] Figure 3 An example of an interface architecture 300 supporting techniques for coupling semiconductor dies in a stacked memory architecture according to examples as disclosed herein is shown. Interface architecture 300 illustrates an example of an interface block 245-b (e.g., of die 240) coupled to an interface block 220-b (e.g., of die 205). Interface block 245-b can be communicatively coupled to interface block 220-b via one or more of bus 301, bus 302, bus 303, and bus 304, each of which can be an example of one or more signal paths of bus 221 and bus 246, as well as bus 255 (if applicable). Interface block 245-b can further be coupled to one or more buses 306 (e.g., power delivery bus, PDN TRV, communication bus), which can deliver power directly to interface block 245-b or components of memory array 250-b (e.g., or some other component of die 240).

[0063] Interface block 245-b includes a control interface 310 (e.g., a command interface) that can be configured to communicate signaling with interface block 220-b. For example, control interface 310 can include circuitry (e.g., a receiver, one or more latches) configured to receive control signaling (e.g., modulated control signaling, access command signaling, configuration signaling, address signaling, such as row address signaling or column address signaling) via bus 301-a. Control interface 310 can also include circuitry configured to receive clock signaling (e.g., clock signaling associated with control interface 310, clock signaling having one or more phases, such as true and complement phases, or dk_t / c signaling from interface block 220-b) via bus 302-a. Control interface 310 can use bus 302-a to receive control signaling from bus 301-a (e.g., for triggering one or more latches). The control interface 310 may transmit (eg, forward) control signaling and clock signaling (eg, for timing of other operations of the interface block 245 - b ) to the interface controller 320 .

[0064] Interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured to communicate signaling with interface block 220-b. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, or based on) control signaling via control interface 310. Although the example of interface block 245-b includes two data interfaces 330 associated with control interface 310 (e.g., in a "channel pair" arrangement, in a "pseudo-channel pair" arrangement), the described techniques for interface block 245 may include any number of one or more data interfaces 330 and associated buses and circuitry for a given control interface 310 of interface block 245.

[0065] Each data interface 330 may be associated with a corresponding data path circuitry, which may include corresponding first-in, first-out (FIFO) and serialization / deserialization (SERDES) circuitry (e.g., FIFO / SERDES 340), corresponding write / sense circuitry 350, corresponding synchronization and sequencing circuitry (e.g., synchronization / sequencing logic 360), and corresponding timing circuitry 370, as well as interconnect signal paths (e.g., one or more buses). However, in some other examples, the data path circuitry may be arranged differently or may include different circuitry components, which may include circuitry dedicated to the corresponding data path, shared among the data paths, or various combinations thereof. Each data interface 330 may also be associated with a corresponding group of one or more memory arrays 250. In some examples, each memory array 250 may be understood to include corresponding addressing circuitry, such as memory bank logic or decoders (e.g., row decoders, column decoders) or memory cell sense amplifier circuitry, as well as other array circuitry. However, in some other examples, at least a portion of this circuitry may be included in the interface block 245.

[0066] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via the corresponding bus 303. Each data interface 330 may also include circuitry for communicating clock signaling via the corresponding bus 304, which may support reception of a clock signal by the data interface 330 (e.g., first clock signaling associated with the data interface 330, clock signaling having one or more phases, such as true and complement phases, DQS_t / c signaling from the interface block 220-b, clock signaling associated with data reception or write operations), transmission of a clock signal by the data interface 330 (e.g., second clock signaling associated with the data interface 330, RDQS_t / c signaling to the interface block 220-b, clock signaling associated with data transmission or read operations), or both. In some examples, data interface 330, bus 303, or a combination of bus 303 and bus 304 can be associated with a "pseudo-channel," and multiple pseudo-channels can be associated with the same control interface 310 or the same control bus (e.g., bus 301, a combination of bus 301 and bus 302). In some implementations, pseudo-channels of multiple interface blocks 245 can be grouped together (e.g., functionally, logically, electrically, such as by hard-wired signal paths or multiplexing circuitry) to support a channel group (e.g., associated with a corresponding host interface 216). Each data interface 330 can transmit clock signaling (e.g., received clock signaling, DQS_t / c signaling) to synchronization / sequencing logic 360 (e.g., for timing of other operations of interface block 245-b) via a respective bus.

[0067] The interface controller 320 can support various functionalities (e.g., control functionality, configuration functionality) of the interface block 245-b for accessing or otherwise managing the operation of the coupled memory array 250. For example, the interface controller 320 can support access command coordination or configuration, latency or timing compensation, access command buffering (e.g., according to a FIFO or other organizational scheme), mode registers or logic for configuration settings, or test functionality (e.g., evaluation functionality, BIST functionality), among other functions or combinations thereof. For each data path of the interface block 245 (e.g., associated with a corresponding data interface 330), the interface controller 320 can be configured to transmit signaling (e.g., address signaling, such as column address or column start signaling) to the corresponding memory array 250 via a bus. For each data path of the interface block 245 , the interface controller 320 may communicate signaling (eg, timing signaling, configuration signaling, which may be based on clock signaling received from the control interface 310 ) with the corresponding timing circuitry 370 and synchronization / sequencing logic 360 via the corresponding bus.

[0068] For each data path, the corresponding timing circuitry 370 can support the timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) relative to the timing signaling received from the interface controller 320. For example, the timing circuitry 370 can include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other initiation signals for controlling the operation of the corresponding data path, and this signaling can include transitions that deviate from, operate at a different rate from, or otherwise differ from the signaling from the interface controller 320 (e.g., rising edge transitions, falling edge transitions, on / off transitions) to support a given operation or combination of operations. For example, the timing circuitry 370 can be configured to transmit signaling (e.g., address signaling, such as column address or column activation signaling) to the corresponding memory array 250, transmit signaling (e.g., latch or driver timing signaling) to the corresponding write / sense circuitry 350, and transmit signaling (e.g., timing signaling) to the corresponding synchronization / sequencing logic.

[0069] For each data path, a corresponding FIFO / SERDES 340 can be configured to convert data signaling between a first bus width (e.g., a relatively wide bus width, a data read / write (DRW) bus, for communicating with a write / sense circuitry 350 having a relatively large number of signal paths) and a second bus width (e.g., a relatively narrow bus width, for communicating with a data interface 330 having a relatively small number of signal paths). In some examples, this conversion can be accompanied by changing the signaling rate between signaling from the data interface 330 and the write / sense circuitry 350 (e.g., to maintain a given throughput). In various examples, the FIFO / SERDES 340 can receive data signaling from the data interface 330 and transmit the data signaling to the write / sense circuitry 350 (e.g., to support a write operation), or can receive data signaling from the sense circuitry 350 and transmit the data signaling to the data interface 330 (e.g., to support a read operation). In some examples (eg, to support read operations), FIFO / SERDES 340 may be configured to transmit clock signaling (eg, RDQS_t / c signaling) to data interface 330 , which may be forwarded to interface block 220 - b .

[0070] Timing or other synchronization of operations performed by the FIFO / SERDES 340 may be supported by one or more clock signals and other signaling received from corresponding synchronization / sequencing logic 360. For example, the synchronization / sequencing logic 360 may generate or otherwise coordinate clock signaling to support different signaling rates for different buses (e.g., based on received clock signaling). Additionally or alternatively, the FIFO / SERDES 340 may operate in a direction (e.g., for transmitting data to the data interface 330, for receiving data from the data interface 330), or in other modes based on configuration signaling received from the synchronization / sequencing logic 360.

[0071] For each data path, a corresponding write / sense circuitry 350 can be configured to support access (e.g., data signaling, write signaling, read signaling) to a corresponding group of one or more memory arrays 250. For example, the write / sense circuitry 350 can be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which can include a corresponding signal path associated with each memory array 250, or can include a signal path shared by all memory arrays 250 of the group, in which case the memory array circuitry can include multiplexing circuitry operable to couple the bus to selected ones of the memory arrays 250. In some examples, the bus between the write / sense circuitry 350 and the group of one or more memory arrays 250 can include the same number of signal paths as the bus between the write / sense circuitry 350 and the FIFO / SERDES 340 (e.g., for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other examples, the memory array 250 may include a number of columns that is an integer multiple of the number of signal paths of the bus, in which case the memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the columns of memory cells, or associated circuitry, to the bus.

[0072] To support write operations, the write / sense circuitry 350 can be configured to drive signaling operable to write one or more logic states to memory cells of the memory array 250 (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some examples, this signaling can be transmitted (e.g., as an output of a signal corresponding to the logic state to be written) to support circuitry of or otherwise associated with the memory array 250, such as sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable to apply a bias across a storage element of a memory cell (e.g., across a capacitor, across a ferroelectric capacitor), or to apply charge, current, or other signaling to a storage element of a memory cell (e.g., applying current to a chalcogenide or other configurable memory material, applying charge to the gate of a NAND memory cell), as well as other examples.

[0073] To support read operations, the write / sense circuitry 350 can be configured to receive signaling, which can be further amplified by the write / sense circuitry 350 for communication via the interface block 245-b. For example, the write / sense circuitry 350 can be configured to receive signaling corresponding to logic states read from the memory array 250, but with a relatively low drive strength (e.g., relatively "analog" signaling, which can be associated with relatively low drive strengths of the sense amplifiers of the memory array 250). Accordingly, the write / sense circuitry 350 can include further sense amplifiers (e.g., data sense amplifiers (DSAs) between the signal paths between the write / sense circuitry and the set of one or more memory arrays and the corresponding signal paths between the write / sense amplifiers and the FIFO / SERDES), each of which can have a relatively high drive strength (e.g., for driving relatively "digital" signaling).

[0074] The features of interface architecture 300 can be replicated in various numbers and arrangements to support semiconductor systems with multiple dies, such as various instances of system 200. In an example embodiment, each die 240 can be configured with 64 instances of interface block 245-b, which can support a data signaling width of 9,216 signal paths for each die 240 (e.g., where each bus 303 of a channel pair is associated with 72 signal paths). For a system 200 having a stack of eight dies 240 coupled to die 205, die 205 can thus be configured with 512 instances of interface block 220-b, thereby supporting a total data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 can be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 can be configured with a different number of dies 240 per die 205.

[0075] According to the techniques herein, a semiconductor unit (e.g., a logic unit, a semiconductor assembly) can be formed with multiple relatively small semiconductor dies (e.g., chiplets, logic chiplets). The relatively small semiconductor die can include one or more interface blocks 220-b. Thus, a set of memory dies (e.g., an array die) stacked on a die portion can include one or more interface blocks 245-b with multiple memory arrays 250-b. In some examples, each of bus 301-a, bus 302-a, bus 303, and bus 304 can include or be an example of a TSV, a bond pad, a conductive path, or other mechanism that supports coupling between a die portion and the set of memory dies (e.g., between a logic chiplet and a stack of memory dies). In addition, one or more buses 306 (e.g., PDN TRVs) may bypass interface block 220-b (e.g., may bypass the die portion), which may be able to deliver power to a group of memory dies with increased efficiency (e.g., compared to delivering power through interface block 220-b or other components of the logic die).

[0076] Figure 4A and 4B An example of a semiconductor component 400 and a die assembly 450 is shown that supports techniques for semiconductor die coupling in a stacked memory architecture according to examples as disclosed herein. Figure 4A , semiconductor component 400-a (e.g., a wafer, a group of dies) may include multiple dies 405 (e.g., logic dies), each of which may include multiple components (e.g., subcomponents). For example, die 405 may include multiple portions of circuitry (e.g., interface circuitry, memory controller circuitry, host controller circuitry, and host processor circuitry, among other examples). In some cases, die 405 may be an example of or include die 205. Although semiconductor component 400-a is shown as including four dies 405, semiconductor component 400-a may include any number of dies 405.

[0077] As part of the manufacturing process, each of the dies 405 may be evaluated to verify proper operation. Manufacturing yield may refer to the number or proportion of dies 405 that meet the evaluation (e.g., the number of "good" dies). For example, the evaluation process may determine whether the die 405 includes a fault 415 (e.g., a defect, an error) that causes the die 405 to operate improperly. If the die 405 is found to include a fault 415, the die 405 may be rejected (e.g., discarded). Relatively large dies (e.g., die 405) may be more likely to be rejected than relatively small dies. For example, if a fault 415 is found in at least one portion of the circuitry of the die 405, the entire die 405 may be rejected. Therefore, the semiconductor component 400-a may be associated with a relatively low yield (e.g., because each of the dies 405 includes a fault 415).

[0078] To improve the manufacturing yield (e.g., wafer yield) of semiconductor component 400, it may be desirable to manufacture (e.g., fabricate) relatively small portions of die 405 (e.g., smaller dies that can be separated as individual portions of die 405, with each portion of the circuitry of die 405 manufactured separately). For example, semiconductor component 400-b may include multiple dies 410 (e.g., chiplets, die portions), where die 410 may be smaller than die 405. Each die 410 may include a respective portion (e.g., a subset, less than all) of the circuitry of die 405 and may be relatively less complex than die 405. Because die 410 can be separated individually, relatively small dies 410 may be rejected rather than the entire die 405 (e.g., failure 415 may be isolated to a relatively small portion of the die), thereby improving the overall manufacturing yield (e.g., of known good dies 410). As an illustrative example, semiconductor components 400-a and 400-b may include faults 415 in multiple identical portions of circuitry. Faults 415 in semiconductor component 400-a may cause each of dies 405 (e.g., the entire semiconductor component 400-a) to be rejected (e.g., even though semiconductor component 400-a may include some good die portions). In contrast, the same fault 415 in semiconductor component 400-b may cause only a portion of die 410 (e.g., die 410-a) to be rejected, while other dies (e.g., die 410-b) may be accepted. For example, die 410-b may be accepted (e.g., as an example of KGD) based on satisfying an evaluation procedure (e.g., evaluating the circuitry or functionality of die 410-b).

[0079] According to examples described herein, and to improve the manufacturing yield of semiconductor circuit systems, a die assembly 450 having one or more semiconductor units 420 can be formed by interconnecting relatively small dies 410 (e.g., chiplets, logic chiplets, relatively small semiconductor dies) to otherwise support the functionality of a relatively large die 405. For example, multiple dies 410 can be coupled (e.g., via RDL) with conductive lines 425 to form semiconductor units 420 (e.g., units having the functionality of die 205, die 405, or another die). In some examples, each of the dies 410 can be fabricated from a different wafer or the same wafer. In some examples, the semiconductor units 420 can be functionally equivalent to the die 405. The gaps between the dies 410 can be filled with one or more dielectric materials 435 (e.g., silicon oxide gap fillers) that separate each of the dies 410 (e.g., the substrates separating the dies 410). In some examples, different dies 410 may use various manufacturing technologies (e.g., different technologies for transistor formation). For example, a first fabrication technology (e.g., a memory fabrication flow) may be used to fabricate transistors (e.g., FinFETs, planar transistors) for die 410-c (e.g., for interface block 220) and a second fabrication technology (e.g., a logic fabrication flow, a foundry process) may be used to fabricate transistors (e.g., FinFETs, gate-all-around transistors) for die 410-d (e.g., for host processor 210, for controller 215). Furthermore, the different fabrication technologies may be associated with each die 410 being supplied from a different wafer, from a different manufacturer, or both. In some examples, multiple dies 410, along with conductive lines 425, dielectric material 435, and any other circuitry (e.g., TRVs), may be formed as part of a reconstructed KGD wafer (e.g., a KGD wafer assembly), which may have various sizes (e.g., 200 mm, 300 mm, or some other size).

[0080] Figures 5 to 12 An example of operation of forming a semiconductor system 500 (e.g., a heterogeneous device, a heterogeneous die semiconductor system, a heterogeneous HBM system, a heterogeneous TCDRAM system) utilizing techniques for semiconductor die coupling in a stacked memory architecture according to examples as disclosed herein is described. For example, Figures 5 to 12Aspects of a series of operations that may support manufacturing system 100 or a portion thereof, system 200 (e.g., a unit supporting the functionality of die 205, die 405), die assembly 450, or some other device herein may be described that may increase device yield and improve power delivery to stacked memory dies during manufacturing. Each of the figures may be described with reference to the x-direction, y-direction, and z-direction of coordinate system 501. The operations that may be performed by a manufacturing system (e.g., a semiconductor fabrication system configured to perform additive operations (e.g., deposition, epitaxy, bonding), subtractive operations (e.g., etching, grooving, planarization, polishing), modifying operations (e.g., oxidation, doping, reacting, conversion), and supporting operations (e.g., masking, patterning, lithography, alignment), as well as other operations supporting the described techniques) may be described. Figures 5 to 12 Instructions and references Figures 5 to 12 Describes the operation.

[0081] Figure 5 A portion of semiconductor system 500 is illustrated after a first set of one or more fabrication operations. For example, semiconductor system 500 may include die 410 - e - 1 and die 410 - e - 2 (eg, KGDs, which may be heterogeneous KGDs), which may be bonded to carrier 505 .

[0082] The carrier 505 (e.g., a sacrificial silicon carrier) may include one or more material levels, such as a substrate 510 (e.g., a carrier substrate, a wafer substrate) and a bonding layer 515. The carrier 505 may provide a surface for bonding (e.g., mounting) multiple dies 410-e and provide structural support for the semiconductor unit. Each die 410-e may include material levels, such as a substrate 535 (e.g., a semiconductor substrate, a crystalline substrate) and a bonding layer 520. Although two dies 410-e are shown, any number of dies 410-e may be formed on the carrier 505 (e.g., arranged along the x-direction, arranged along the y-direction). The dies 410-e may each be an instance of a die 410 (e.g., a semiconductor die, a chiplet, a portion of a semiconductor unit).

[0083] The bonding layer 515 may include one or more alignment features 545 (e.g., alignment marks, fiducial marks), such as alignment features 545-a-1, 545-a-3, 545-a-5, and 545-a-6. The alignment features 545 may include a material different from the other materials of the bonding layer 515, which may provide visibility for proper alignment of the carrier 505 and the one or more dies 410-e or between them. In some examples, the alignment features 545 may include a conductive material, which may or may not support electrical coupling (e.g., alignment features 545-a-1 and 545-a-6 may support electrical coupling, while alignment features 545-a-2, 545-a-3, 545-a-4, and 545-a-5 may not support electrical coupling).

[0084] The first set of manufacturing operations may include bonding semiconductor die 410-e to carrier 505 (e.g., as a chip-to-wafer bond, as a face-to-face bond). Each of die 410-e may include respective circuitry 525, which includes a portion of the circuitry associated with a semiconductor unit (e.g., a respective portion of the functionality associated with die 205 or die 405), which may have been evaluated for acceptable performance prior to bonding for the first set of operations. In some examples, at least some instances of circuitry 525 may include memory interface circuitry (e.g., interface block 220, interface block 245, logic block 225), memory controller circuitry (e.g., logic block 230, controller 215), host controller circuitry, host processor circuitry (e.g., host processor 210), sensor circuitry (e.g., sensor 237, sensor 275), storage circuitry (e.g., memory array 250, non-volatile storage device 235, non-volatile storage device 270), other circuitry (e.g., graphics circuitry, peripheral circuitry), or any combination thereof. In some examples, circuitry 525 of one die 410 may be different from circuitry 525 of another die 410 (e.g., in a heterogeneous chiplet configuration) or may be the same circuitry. For example, circuitry 525-a-1 may include memory interface circuitry and circuitry 525-a-2 may include host processor circuitry, among other examples of differences among the dies 410. In some examples, circuitry 525-a may include circuitry associated with one or more units 280-a-1 and may not include at least some circuitry associated with one or more units 280-a-2 (e.g., host system 105 or host processor 210 may be coupled separately, such as in an HBM implementation). In some other examples, circuitry 525-a may not include circuitry associated with one or more units 280-a-1 (e.g., one or more units 280-a-1 may be coupled separately) and may include circuitry associated with one or more units 280-a-2 (e.g., such as host processor 210 and controller 215). In some examples, at least a portion of circuitry 525 (e.g., one or more transistors of circuitry 525, complementary metal oxide semiconductor (CMOS) circuitry) may be formed from a portion of substrate 535 of die 410-e (e.g., a doped portion of substrate 535, a doped semiconductor material, a doped crystalline semiconductor). In some examples, one or more instances of circuitry 525 may include front-end-of-the-line (FEOL) circuitry (e.g., transistor circuitry), back-end-of-the-line (BEOL) circuitry (e.g., interconnect circuitry, one or more conductive paths formed above the transistor circuitry), or both.

[0085] Each die 410-e may include a bonding layer 520 that may be opposite the substrate 535 of the die 410-e (e.g., along the z-direction). The plurality of dies 410-e may at least partially overlap along a direction from the carrier (e.g., along the z-direction, along the thickness dimension). Bonding the dies 410-e may include bonding a face of the die 410-e opposite the substrate 535 of the die 410-e (e.g., the front side of the die 410-e) to a face of the carrier 505 opposite the substrate 510 of the carrier 505 (e.g., the front side of the carrier 505). The die 410-e and the carrier 505 may be bonded according to a face-to-face bonding (e.g., chip-to-wafer face-to-face fusion bonding), and the bonding may be a fusion bonding of one or more materials of the bonding layer 520-a with one or more materials of the bonding layer 515 of the carrier 505. In some examples, bonding the plurality of semiconductor dies 410-e to the carrier 505 can be based on alignment features 545 of the carrier 505, alignment features 545 of the dies 410-e (e.g., alignment features 545-a-2, alignment features 545-a-4 included in the bonding layer 520-a), or both. In some examples, bonding the dies 410-e to the carrier 505 can provide mechanical coupling between the dies 410 and the carrier 505 without requiring an accompanying electrical coupling.

[0086] Figure 6 A portion of the semiconductor system 500 is illustrated after a second set of one or more manufacturing operations. For example, the second set of operations may include removing a portion of material from at least one die 410-e (e.g., die 410-e-1, die 410-e-2) after bonding the plurality of dies 410-e to the carrier 505. For example, at least a portion of the substrate 535 of the die 410-e may be removed by a chemical mechanical planarization (CMP) technique or other technique such as thinning, grinding, cutting, polishing, planarization, or etching. The removal of the portion of material (e.g., excess silicon, excess substrate 535) may reduce the size of the die 410-e from a first thickness to a second thickness (e.g., in a silicon thinning operation, along the z-direction). In some examples, the second set of manufacturing operations may be optional and may not be performed as part of the process (e.g., there may be no excess material to be removed from the die 410-e).

[0087] Figure 7A portion of the semiconductor system 500 is illustrated after a third set of one or more fabrication operations. For example, the third set of operations may include forming one or more dielectric materials 705 (e.g., silicon oxide, a gap fill material, an oxide, a nitride, a carbide, an oxide-nitride, an oxide-carbide, other conversion or doping of a substrate material, or some other dielectric material). In some examples, the one or more dielectric materials 705 may be formed at least along the carrier 505 between the plurality of dies 410-e. The one or more dielectric materials 705 may separate the respective substrates 535 of the dies 410-e (e.g., may separate each chiplet). For example, the one or more dielectric materials 705 may separate the substrate 535-a-1 of the die 410-e-1 from the substrate 535-a-2 of the die 410-e-2. Thus, at least prior to subsequent interconnect operations, each of the dies 410-e can be electrically insulated from the other dies 410-e by the one or more dielectric materials 705 (e.g., each die 410-e can be insulated by the one or more dielectric materials 705 on each side except the side bonded to the carrier 505). The one or more dielectric materials 705 can also provide structural support for various components of the semiconductor system 500.

[0088] Figure 8 A portion of semiconductor system 500 is illustrated after a fourth set of one or more fabrication operations. For example, the fourth set of operations may include removing a portion of one or more dielectric materials 705 (e.g., removing excess material; in some examples, at least some dielectric material remains over die 410-e). For example, at least some of the one or more dielectric materials 705 over die 410-e (e.g., along the z-direction) may be removed after forming the one or more dielectric materials at least along carrier 505. In some examples, removing a portion of the one or more dielectric materials 705 may involve CMP (e.g., as silicon oxide CMP).

[0089] Figure 9 A portion of the semiconductor system 500 is illustrated after a fifth set of one or more fabrication operations. For example, the fifth set of operations may include forming conductive paths 906 (e.g., forming at least a portion of an RDL, forming a conductive signal path, forming conductive paths 906 at least partially on the backside of the die 410-e, forming conductive paths along each direction in the xy plane), which may include forming one or more first cavities at a first depth (e.g., along the z-direction from a surface of the one or more dielectric materials 705) through the one or more dielectric materials 705. In some examples, each of the conductive paths 906 may contact (e.g., may provide electrical coupling between) at least two of the dies 410-e (e.g., through vias 910-a-3 and 910-a-4).

[0090] The fifth set of operations may also include forming one or more through-vias 910 (e.g., TSVs, forming through-vias 910 on the backside of die 410-e, forming through-vias 910 through substrate 535), which may include forming one or more second cavities at a second depth through at least one or more dielectric materials 705, wherein each second cavity may also pass through at least a portion of die 410-e (e.g., contacting or exposing a portion of circuitry 525-a). In some examples, the one or more through-vias 910 may support an interface between die 410-e and at least one of a group of one or more other semiconductor dies (e.g., a memory die, a stack of dies 240) and may be based on TSVs formed through at least one substrate 535. Additionally or alternatively, the one or more through-vias 910 may provide an interface between die 410-e and at least one other die 410-e. For example, the circuit system 525-a-1 of the die 410-e-1 and the circuit system 525-a-2 of the die 410-e-2 may be coupled (e.g., communicatively coupled, electrically coupled) based on a through-hole 910-a-3 through the substrate 535-a-1 and a through-hole 910-a-4 through the substrate 535-a-2, which may be coupled via one or more conductors (e.g., conductive path 906) of the RDL.

[0091] The fifth set of operations may also include forming one or more vias 915 (e.g., TVs, PDN TRVs, bypass vias), which may include forming one or more third cavities at a third depth through at least one or more dielectric materials 705. Each third cavity may be formed (e.g., along the x-direction, along the y-direction, or both) between, beside, or otherwise around the plurality of dies 410-e and may be in contact with the carrier 505 (e.g., may be filled with a conductive material that contacts the alignment features 545-a or otherwise contacts or reaches the carrier 505). The vias 915 may be formed through a layer 905 (e.g., a logic layer, a layer including logic chiplets). The via 915 may bypass the die 410-e and may provide an interface between a group of one or more other semiconductor dies (e.g., die 240) positioned above the layer 905 and a surface of one or more dielectric materials 705 opposite the group of one or more other semiconductor dies (e.g., which may later be coupled to the group of one or more other semiconductor dies).

[0092] Forming the conductive paths 906, vias 910, and vias 915 can include filling the one or more first cavities, the one or more second cavities, and the one or more third cavities in parallel or otherwise sequentially with one or more conductive materials (e.g., according to a parallel damascene process, a triple damascene process, or a backside triple damascene process). Thus, in some examples, the conductive paths 906, vias 910, and vias 915 can be referred to as or included in a backside triple damascene RDL. Forming the semiconductor unit 920 can be based on filling the plurality of conductive paths 906, the one or more vias 910, and, in some examples, the one or more vias 915 with one or more conductive materials (e.g., a single conductive material, a conductive liner material, and a conductive fill material). For example, based on forming conductive paths 906, each of the plurality of dies 410-e may be electrically coupled (e.g., connected) to at least one other die 410-e via an RDL (e.g., an RDL that may include the plurality of conductive paths 906) (e.g., die 410-e-1 may be electrically connected to die 410-e-2). That is, electrically connecting the dies 410-e may be based on forming an RDL that includes the plurality of conductive paths 906 over the dies 410-e. Forming the semiconductor unit 920 may be based on coupling each of the plurality of dies 410-e to at least one other die 410-e. The semiconductor unit 920 may be an example of an implementation of the functionality of the die 205, the die 405, a logic die, or some other die.

[0093] Figure 10A portion of semiconductor system 500 is illustrated after a sixth set of one or more fabrication operations. For example, the sixth set of operations may include forming a layer 1005 (e.g., at least a portion of an RDL) over die 410-e, which may include one or more dielectric materials 1010 and one or more conductive pads 1015 (e.g., bond pads). In some examples, layer 1005 may also include conductive paths between conductive pads 1015 (e.g., signal paths of the RDL along each direction in the xy plane, not shown), or provide electrical coupling between vias 910, vias 915, or a combination thereof. In some examples, each conductive pad 1015 can couple (e.g., or enable coupling) one or more other semiconductor dies (e.g., die 240) stacked above layer 1005 to a PDN (e.g., via carrier 505, via 915, PDN TRV), to via 910 of die 410-e, to an RDL (e.g., conductive path 906) above die 410-e, or any combination thereof. The sixth set of manufacturing operations can also include forming one or more pads 1020 (e.g., redundant pads, dummy pads, conductive pads) that can be used for purposes other than electrical coupling of components (e.g., as alignment features). In some examples, at least some of the conductive pads 1015 can implement the functionality of contacts 222. In some examples, the formation of the conductive pads 1015 and the liner 1020, as well as corresponding vias (e.g., through the layer 1005 for coupling with the layer 905), and the signal paths of the layer 1005 can be based on filling the cavity with one or more conductive materials in parallel (e.g., according to a parallel damascene process, a dual damascene process, or a backside dual damascene process). Thus, in some examples, the conductive pads 1015, the liner 1020, the corresponding signal paths, and the vias of the layer 1005 can be referred to as or included in a backside dual damascene RDL, which can correspond to a backside dual damascene RDL formed above a triple damascene RDL associated with the fifth set of operations (e.g., the device of the heterogeneous die 410-e).

[0094] Figure 11 A portion of semiconductor system 500 is illustrated after a seventh set of one or more fabrication operations. For example, the seventh set of operations may include forming (e.g., stacking, assembling, bonding) layer 1105 (e.g., including die 240, a memory die, an array die) over carrier 505, layer 905, and layer 1005. Components of semiconductor system 500 may include various layers and materials, such as bonding layer 1115, bonding layer 1120, one or more dielectric materials 1130 (e.g., silicon oxide), substrate 1135 (e.g., a silicon substrate), and one or more conductive materials 1140 (e.g., copper, aluminum, or some other material).

[0095] In some examples, forming layer 1105 can include coupling (e.g., bonding) a respective group (e.g., a stack) of one or more dies 1145-a over at least one of dies 410-e (e.g., coupling a respective group (e.g., a stack) of one or more dies 1145-a to at least one of dies 410-e) (e.g., via one or more RDLs, via layer 1005), wherein each die of the respective group of dies 1145-a can include circuitry 1125-a, such as memory circuitry (e.g., a plurality of memory arrays, memory array 250), interface circuitry (e.g., interface block 245 or components thereof), or other circuitry (e.g., associated with non-volatile storage device 270, sensor 275, or other circuitry). In some examples, dies 1145 or stacks thereof can be coupled individually as a respective group to at least one of dies 410-e. In some other examples, multiple dies 1145 (e.g., layers of dies 1145) or stacks thereof may be continuous (e.g., as part of a wafer or other semiconductor component, as part of a stack of wafers or other semiconductor components) or otherwise mechanically connected (e.g., along the x-direction, along the y-direction, not shown), which may include lateral separation (e.g., singulation) into semiconductor units. In some such other examples, dies 1145 may be part of a rebuilt wafer or other rebuilt semiconductor component of dies 1145 (e.g., known good dies 1145), such reconstruction may involve coupling of singulated or otherwise separated dies 1145 to a carrier (e.g., similar to the coupling of die 410 to carrier 505, not shown). Thus, in some instances, the wafer of die 1145 or the reconstructed wafer of die 1145 may be coupled to (e.g., bonded to) the semiconductor unit 920 formed at least in part by the coupling die 410 (e.g., coupled to an RDL that provides at least a portion of such coupling (e.g., an RDL between the reconstructed wafer of die 1145 and the reconstructed wafer of die 410)).

[0096] Circuitry 1125-a may include FEOL circuitry (e.g., transistor circuitry, circuitry formed at least in part from doped portions of substrate 1135) and BEOL circuitry (e.g., interconnect circuitry). Each instance of circuitry 1125-a may be based on an instance of circuitry 525-a of a corresponding set of bonded die 410-e and operate via one or more interconnect regions 1150-a. In some examples, interconnect region 1150-a may include components or circuitry (e.g., TSVs, bond pads, BEOL circuitry) that couple circuitry 1125 with other circuitry 1125 of a corresponding die 1145-a (e.g., coupling between circuitry 1125-a-1 and circuitry 1125-a-2), with conductive pads 1110, or with conductive pads 1112, or various combinations thereof.

[0097] In some examples, bonding one die 1145-a to another die 1145-a can involve bonding one or more conductive pads 1110-a to one or more conductive pads 1112-a. For example, conductive pad 1110-a can be an implementation of contact 247 or contact 256, and conductive pad 1112-a can be an implementation of contact 257 or contact 260, among other examples. In some examples, conductive pad 1112-a of a first die 1145-a (e.g., conductive pad 1112-a-1) can be coupled (e.g., fused) with conductive pad 1110-a of a second die 1145-a (e.g., conductive pad 1110-a-3), including through hybrid bonding implementations (e.g., wafer-to-wafer or die-to-die front-to-back hybrid bonding). In some examples, this coupling may be accompanied by coupling of corresponding dielectric portions (e.g., surfaces) of die 1145-a, such as fusion of dielectric material 242. In some examples, material 1160 (e.g., additional silicon, additional substrate material) may be formed or placed on top of semiconductor system 500 and may be bonded to die 1145-a located on top of the stack of die 1145-a, including through fusion bonding implementations (e.g., wafer-to-wafer front-to-back fusion bonding).

[0098] In some examples, bonding the corresponding group of one or more dies 1145-a to die 410-e can be based on one or more conductive pads 1110-a in each group of dies 1145-a and one or more conductive pads 1015-a in die 410-e. For example, a group of dies 1145-a can be bonded to die 410-e using a hybrid bonding implementation (e.g., front-to-back hybrid bonding stacked onto a wafer). Interconnect region 1150-a can be coupled to conductive pads 1110-a to provide a communication interface between die 410-e and die 1145-a. In some examples, interconnect region 1150-a can implement the functionality of buses 255, 246, 251, 301, 302, 303, 304, or a combination thereof. For example, one or more conductive pads 1110-a (e.g., conductive pad 1110-a-2) may be coupled to a via 910 (e.g., TSV), one or more conductive paths 906 (e.g., RDL), or both, which may pass through the substrate 535-a of the die 410-e to which the corresponding set of dies 1145-a is coupled. The vias 910 and conductive paths 906 may provide an interface between the corresponding set of one or more dies 1145-a and the die 410-e. In some examples, one or more conductive pads 1110-a (e.g., conductive pad 1110-a-1) may be coupled to a via 915 (e.g., PDN TRV), which may provide an interface through the layer 905 that bypasses the die 410-e. In some examples, bonding the corresponding set of one or more dies 1145-a to the die 410-e may be based on fusion between the corresponding conductor portions and fusion between the corresponding dielectric portions (e.g., surface-to-wafer bonding, front-to-back bonding, hybrid bonding of dielectric and conductive materials). In some examples, before bonding the corresponding set of one or more dies 1145-a to the die 410-e, at least some (if not all) of the dies 410-e, 1145-a may meet (e.g., may be verified to meet) an assessment (e.g., an operational assessment).

[0099] Figure 12A portion of semiconductor system 500 is illustrated after an eighth set of one or more manufacturing operations. For example, the eighth set of operations may include forming one or more contacts 1205 (e.g., electrical contacts, solder balls, μ-bumps, controller folded chip connection (C4) bumps) at one or more depths relative to carrier 505 (e.g., along the z-direction). Forming contacts 1205 may include forming a cavity through at least a portion of carrier 505. In some examples, forming one or more contacts 1205-a (e.g., for each of dies 410-e) may be based on forming a cavity through at least a portion of the carrier, through at least a portion of die 410-e, and forming one or more conductor materials in each of the cavities. Forming contacts 1205 may include forming at least some contacts 1205 (e.g., contacts 1205-a-2 and contacts 1205-a-3) at a surface of semiconductor system 500 (e.g., at a surface of carrier 505 opposite plurality of dies 410-e) and coupling with circuitry 525 of die 410-e. In some examples, one or more contacts 1205 (e.g., contacts 1205-a-1 and contacts 1205-a-4) may be formed at a surface of semiconductor system 500 and coupled with at least one group of one or more dies 1145-a, which may bypass die 410-e. For example, vias 915 may provide an interface between a group of dies 1145-a and a surface of the semiconductor unit opposite the respective group of dies 1145-a (e.g., a surface of layer 905) via contacts 1205. In some examples, the semiconductor system 500 can include a combination of one or more first contacts 1205 (e.g., contact 1205-a-1) that can be coupled to one or more through-vias 915 (e.g., PDN TRVs) and one or more second contacts 1205 (e.g., contact 1205-a-2) that can be coupled to one or more dies 410-e (e.g., to pads of a logic chiplet), which can be associated with different depths along the z-direction. Forming the one or more contacts 1205 can enable the semiconductor system 500 to be communicatively coupled with other components (e.g., a GPU or other peripheral components).

[0100] After the eighth set of manufacturing operations, the semiconductor system 500 may be ready for packaging, which may include separating (eg, dicing) the plurality of semiconductor units 920 on the same carrier 505 from one another. Figures 5 to 12Using the described techniques, a semiconductor system 500 may include a plurality of dies 410-e (e.g., chiplets, logic chiplets, logic dies, semiconductor dies, die portions) electrically coupled via conductive paths 906 (e.g., included in RDLs) to form one or more semiconductor units 920 (e.g., associated with the functionality of a logic die, die 205, or die 405). The semiconductor system 500 may further include one or more groups of dies 1145-a (e.g., die 240, semiconductor dies, array dies, DRAM dies, stacks of memory dies) bonded to respective dies 410-e (e.g., of respective semiconductor units 920) via one or more bond pads 1015-a (e.g., in layer 1005) and one or more through-vias 910 (e.g., TSVs). For example, layer 905 (e.g., the lower die in the stack) may be associated with one or more units 280, and layer 1105 may be associated with one or more dies 240. One or more groups of dies 1145-a may also be bonded to one or more through-vias 915 (e.g., PDN TRVs), which may provide an interface (e.g., a power delivery interface) to the group of dies 1145-a at a surface of the semiconductor system 500 (e.g., via contacts 1205-a).

[0101] Utilizing one or more techniques as described herein can support increased manufacturing yields for wafers associated with components of semiconductor system 500 (e.g., HBM devices, TCDRAM devices). For example, the techniques herein enable the manufacture and evaluation of relatively small semiconductor dies (e.g., die 410) that can be individually separated and can be used to rebuild a relatively large semiconductor unit (e.g., implementing the functionality of die 205 or die 405) using multiple relatively small dies (e.g., using die 410 that meets the evaluation requirements). Furthermore, the described techniques can enable power to be delivered directly to one or more stacked memory dies (e.g., die 1145-a, die 240) with reduced resistance based on one or more vias 915, which can bypass die 410-e and support more efficient use of die area. Consequently, the manufacture of semiconductor system 500 can be associated with increased yields, and semiconductor system 500 can operate with increased efficiency. Although some of the described techniques are described in the context of memory systems, the techniques described herein may be implemented in other semiconductor systems that implement heterogeneous semiconductor components (e.g., dies associated with different functions including different logic functions, different storage or processing functions, or any combination thereof) including heterogeneous semiconductor components interconnected within layers, between layers, or any combination thereof.

[0102] Figure 13A flowchart illustrating method 1300 for supporting techniques for semiconductor die coupling in a stacked memory architecture according to examples disclosed herein is shown. The operations of method 1300 can be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some examples, the one or more controllers can execute an instruction set to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers can use dedicated hardware to perform aspects of the described functions.

[0103] At 1305 , the method may include bonding a plurality of first semiconductor dies to a carrier, each of the first semiconductor dies including a respective portion of circuitry of a semiconductor unit.

[0104] At 1310 , the method may include, after bonding the plurality of first semiconductor dies to a carrier, forming a semiconductor unit based at least in part on electrically connecting each of the plurality of first semiconductor dies to at least one other of the first semiconductor dies.

[0105] At 1315, the method may include bonding a respective group of one or more second semiconductor dies to at least one of a plurality of first semiconductor dies, each second semiconductor die of the respective group including a memory array that is operable based at least in part on a respective portion of a circuit system of a semiconductor unit of the first semiconductor die to which the respective group is bonded.

[0106] In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform one or several methods, such as method 1300. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of a manufacturing system) for performing the following aspects of the present disclosure, or any combination thereof:

[0107] Aspect 1: A method or apparatus comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: bonding a plurality of first semiconductor dies (e.g., die 410) to a carrier (e.g., carrier 505), each of the first semiconductor dies including a respective portion of circuitry (e.g., circuitry 525) of a semiconductor unit (e.g., semiconductor unit 920); forming the semiconductor units after bonding the plurality of first semiconductor dies to the carrier based at least in part on electrically connecting each of the plurality of first semiconductor dies to at least one other of the first semiconductor dies; and bonding a respective group of one or more second semiconductor dies (e.g., die 240, die 1145) to at least one of the plurality of first semiconductor dies, each second semiconductor die of the respective group including a memory array (e.g., at least one memory array 250 of circuitry 1125) operable based at least in part on the respective portion of the circuitry of the semiconductor units of the respective group bonded to the first semiconductor die.

[0108] Aspect 2: The method or apparatus of aspect 1, wherein for each of the first semiconductor dies, the respective portion of circuitry includes memory interface circuitry, memory controller circuitry, host controller circuitry, host processor circuitry, or any combination thereof.

[0109] Aspect 3: A method or apparatus according to any one of Aspects 1 to 2, wherein a first corresponding portion of the circuit system of a first semiconductor die of the semiconductor unit is associated with a first logical function, and a second corresponding portion of the circuit system of a different first semiconductor die of the semiconductor unit is associated with a second logical function different from the first logical function.

[0110] Aspect 4: The method or apparatus of any of aspects 1-3, wherein a first respective set of one or more second semiconductor dies and a second respective set of one or more second semiconductor dies are included in a reconstructed wafer of second semiconductor dies bonded to the semiconductor unit.

[0111] Aspect 5: The method or apparatus of any one of Aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for forming one or more dielectric materials (e.g., dielectric material 705) between the plurality of first semiconductor dies at least along the carrier, wherein the one or more dielectric materials separate respective substrates (e.g., substrate 535) of the first semiconductor dies.

[0112] Aspect 6: The method or apparatus of aspect 5, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: forming a plurality of first cavities at a first depth through the one or more dielectric materials, each of the first cavities in contact with at least two of the first semiconductor dies; forming a plurality of second cavities at a second depth through the one or more dielectric materials, each of the second cavities passing through at least a portion of a respective one of the first semiconductor dies; forming a plurality of third cavities at a third depth through the one or more dielectric materials, each of the third cavities being between the plurality of first semiconductor dies and in contact with the carrier; and forming one or more conductor materials in parallel (e.g., continuously) in the plurality of first cavities, in the plurality of second cavities, and in the plurality of third cavities.

[0113] Aspect 7: The method or apparatus of Aspect 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for forming one or more conductive pads (e.g., bonding pad 1015, pad 1020), one or more conductive paths, and one or more through-holes in one or more second dielectric materials (e.g., layer 1005) adjacent to the one or more conductor materials (e.g., conductive path 906), wherein the one or more conductive pads, the one or more conductive paths, and the one or more through-holes are formed at least in part based on forming the one or more second conductor materials in parallel in a cavity associated with the one or more conductive pads, the one or more conductive paths, and the one or more through-holes.

[0114] Aspect 8: The method or apparatus of any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for removing a portion of the one or more dielectric materials above the plurality of first semiconductor dies after forming the one or more dielectric materials at least along the carrier.

[0115] Aspect 9: The method or apparatus of any of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for forming one or more through-holes (e.g., through-hole 915) through one or more dielectric materials between the plurality of first semiconductor dies, each of the one or more through-holes being coupled to one of the group of one or more second semiconductor dies.

[0116] Aspect 10: A method or apparatus according to Aspect 9, wherein at least one of the one or more through-holes provides an interface (e.g., supports the interface, is part of the interface) between the one or more second semiconductor dies of the corresponding group and a surface of the semiconductor unit opposite to the one or more second semiconductor dies of the corresponding group.

[0117] Aspect 11: The method or apparatus of any of Aspects 9 to 10, further comprising operations, features, circuit systems, logic, components, or instructions for forming one or more electrical contacts for each of the one or more through-holes based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductor materials in the cavity.

[0118] Aspect 12: The method or apparatus of any of Aspects 1 to 11, wherein electrically connecting each of the plurality of first semiconductor dies is based at least in part on forming a plurality of conductive signal paths (e.g., conductive paths 906) over the first semiconductor die of the semiconductor unit.

[0119] Aspect 13: The method or apparatus according to Aspect 12, further comprising an operation, feature, circuit system, logic, component or instruction or any combination thereof for verifying that each first semiconductor die of the plurality of first semiconductor die and the one or more second semiconductor die of the corresponding group meet an operational evaluation before joining the one or more second semiconductor die of the corresponding group to the at least one of the plurality of first semiconductor die.

[0120] Aspect 14: A method or apparatus according to any one of Aspects 1 to 13, wherein joining the one or more second semiconductor dies of the respective group to the at least one of the plurality of first semiconductor dies is at least partially based on forming one or more through-holes (e.g., through-hole 910) through the substrate of the first semiconductor die to which the respective group is joined.

[0121] Aspect 15: The method or apparatus of aspect 14, wherein each via provides an interface between the respective set of one or more second semiconductor dies and the at least one first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both.

[0122] Aspect 16: The method or apparatus according to any one of Aspects 1 to 15, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for forming a plurality of conductive pads (e.g., conductive pad 1015) above the plurality of first semiconductor dies, wherein each of the plurality of conductive pads couples the corresponding group of one or more second semiconductor dies to a PDN, couples the corresponding group of one or more second semiconductor dies to TSVs of the plurality of first semiconductor dies, couples RDLs above the plurality of first semiconductor dies, or any combination thereof, via the carrier.

[0123] Aspect 17: The method or apparatus of any one of aspects 1 to 16, wherein bonding the respective set of one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies is based at least in part on fusion between respective conductor portions and fusion between respective dielectric portions.

[0124] Aspect 18: The method or apparatus of any of Aspects 1 to 17, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for forming one or more electrical contacts for each of the first semiconductor dies based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductor materials in the cavity.

[0125] Aspect 19: The method or apparatus of any one of aspects 1 to 18, wherein bonding the plurality of first semiconductor die to the carrier comprises, for at least one first semiconductor die, bonding a face of the at least one semiconductor die opposite the substrate of the at least one semiconductor die to the carrier.

[0126] Aspect 20: The method or apparatus of any one of Aspects 1 to 19, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for removing a portion of material from at least one of the plurality of first semiconductor dies after bonding the first semiconductor dies to the carrier.

[0127] Aspect 21: The method or apparatus of any one of aspects 1 to 20, wherein the plurality of first semiconductor dies at least partially overlap along a direction from the carrier.

[0128] Aspect 22: The method or apparatus of any of aspects 1 to 21, wherein the bonding the plurality of first semiconductor dies to the carrier is based at least in part on one or more alignment features (eg, alignment features 545 ) of the carrier.

[0129] Aspect 23: The method or apparatus of any of aspects 1 to 22, wherein the bonding the plurality of first semiconductor dies to the carrier provides mechanical coupling between the plurality of first semiconductor dies and the carrier without an accompanying electrical coupling.

[0130] Figure 14A flowchart illustrating method 1400 for supporting techniques for semiconductor die coupling in a stacked memory architecture according to examples disclosed herein is shown. The operations of method 1400 can be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some examples, the one or more controllers can execute an instruction set to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers can use dedicated hardware to perform aspects of the described functions.

[0131] At 1405 , the method may include bonding a plurality of first semiconductor dies to a carrier, each first semiconductor die including a respective portion of circuitry of a semiconductor unit of a semiconductor system.

[0132] At 1410 , the method may include coupling each of a plurality of first semiconductor die with at least one other first semiconductor die via an RDL including a plurality of conductive signal paths, wherein a semiconductor unit is formed by the coupled first semiconductor die.

[0133] At 1415 , the method may include forming a dielectric portion of a semiconductor unit including one or more dielectric materials between the plurality of first semiconductor dies.

[0134] At 1420 , the method may include forming a plurality of vias through the dielectric portion and between the plurality of first semiconductor dies.

[0135] At 1425, the method may include bonding at least one group of one or more second semiconductor dies to a semiconductor unit, each second semiconductor die including a memory array operable by at least one of the coupled first semiconductor dies, wherein the bonding is based at least in part on fusing a plurality of first bond pads of the first semiconductor die with a plurality of second bond pads of at least one group of the second semiconductor dies and on bonding a plurality of third bond pads coupled with a plurality of through-vias with a plurality of fourth bond pads of the at least one group of the second semiconductor dies.

[0136] In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform one or several methods, such as method 1400. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of a manufacturing system) for performing the following aspects of the present disclosure, or any combination thereof:

[0137] Aspect 24: A method or apparatus comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: bonding a plurality of first semiconductor dies to a carrier, each first semiconductor die comprising a respective portion of circuitry of a semiconductor unit of the semiconductor system; coupling each of the plurality of first semiconductor dies with at least one other first semiconductor die via an RDL comprising a plurality of conductive signal paths, wherein the semiconductor unit is formed by the coupled first semiconductor dies; forming a dielectric portion of the semiconductor unit comprising one or more dielectric materials between the plurality of first semiconductor dies; forming a plurality of vias through the dielectric portion and between the plurality of first semiconductor dies; and bonding at least one set of one or more second semiconductor dies to the semiconductor unit, each second semiconductor die comprising a memory array operable by at least one of the coupled first semiconductor dies, wherein the bonding is based at least in part on fusing a plurality of first bond pads of the first semiconductor die with a plurality of second bond pads of the at least one set of second semiconductor dies and bonding a plurality of third bond pads coupled to the plurality of vias with a plurality of fourth bond pads of the at least one set of second semiconductor dies.

[0138] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0139] A system is described. The following provides an overview of aspects of the system as described herein:

[0140] Aspect 25: A system comprising: a carrier comprising one or more material levels; a plurality of first semiconductor dies bonded to the carrier, each first semiconductor die comprising a respective substrate separated from the respective substrate of each other first semiconductor die, and each first semiconductor die comprising a respective portion of a circuit system of a semiconductor unit electrically coupled to the respective portion of the circuit system of the semiconductor unit of at least one other first semiconductor die; and at least one group of one or more second semiconductor dies, each group of one or more second semiconductor dies electrically coupled to a respective first semiconductor die of the plurality of first semiconductor dies, and each second semiconductor die comprising one or more memory arrays operable at least in part based on the respective first semiconductor die to which the second semiconductor die is connected.

[0141] Aspect 26: The system of aspect 25, wherein for each of the first semiconductor dies, the respective portion of circuitry includes memory interface circuitry, memory controller circuitry, host controller circuitry, host processor circuitry, or any combination thereof.

[0142] Aspect 27: The system of any of aspects 25-26, further comprising: a dielectric portion of one or more dielectric materials interposed between the respective substrates of the plurality of first semiconductor dies.

[0143] Aspect 28: The system according to Aspect 27, further comprising: one or more through-vias passing through the dielectric portion between the plurality of first semiconductor dies, each of the one or more through-vias being coupled to one of the group of one or more second semiconductor dies and bypassing the plurality of first semiconductor dies.

[0144] Aspect 29: The system of aspect 28, wherein at least one of the one or more through-vias provides an interface between one of the set of one or more second semiconductor dies and a surface of the semiconductor unit opposite the respective set of one or more second semiconductor dies.

[0145] Aspect 30: The system of any one of aspects 25 to 29, further comprising: an RDL comprising a plurality of conductive signal paths, wherein each first semiconductor die is electrically coupled with the at least one other first semiconductor die via the RDL.

[0146] Aspect 31: The system of any one of Aspects 25 to 30, further comprising: one or more through-holes formed through the corresponding substrate of at least one of the plurality of first semiconductor dies, wherein each through-hole provides an interface between at least one of the group of one or more second semiconductor dies and the corresponding first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both.

[0147] Aspect 32: The system according to any one of Aspects 25 to 31, further comprising: a plurality of conductive pads located above the plurality of first semiconductor dies, wherein each of the plurality of conductive pads couples the corresponding group of one or more second semiconductor dies to the PDN, couples the corresponding group of one or more second semiconductor dies to the TSVs of the plurality of first semiconductor dies, couples the RDL above the plurality of first semiconductor dies, or any combination thereof, via the carrier.

[0148] Aspect 33: The system of any one of Aspects 25 to 32, further comprising: one or more first electrical contacts located at a surface of the system and coupled to at least one first semiconductor die among the plurality of first semiconductor dies; and one or more second electrical contacts located at the surface of the system and coupled to the at least one group of one or more second semiconductor dies and bypassing the plurality of first semiconductor dies.

[0149] A system is described. The following provides an overview of aspects of the system as described herein:

[0150] Aspect 34: A system formed by the following process: bonding a plurality of first semiconductor dies to a carrier, each of the first semiconductor dies including a corresponding portion of the circuit system of a semiconductor unit; after bonding the plurality of first semiconductor dies to the carrier, forming the semiconductor unit at least in part based on electrically connecting each of the plurality of first semiconductor dies to at least one other of the first semiconductor dies; and bonding a corresponding group of one or more second semiconductor dies to at least one of the plurality of first semiconductor dies, each second semiconductor die of the corresponding group including a memory array, the memory array being operable at least in part based on the corresponding portion of the circuit system of the semiconductor unit of the first semiconductor die to which the corresponding group is bonded.

[0151] A system is described. The following provides an overview of aspects of the system as described herein:

[0152] Aspect 35: A system comprising: a plurality of first semiconductor dies electrically coupled to form a semiconductor unit of the system; a dielectric material separating a respective substrate associated with each of the plurality of first semiconductor dies; an RDL comprising a plurality of conductive paths electrically connecting each of the plurality of first semiconductor dies with at least one other first semiconductor die; one or more groups of second semiconductor dies, each second semiconductor die comprising a plurality of memory arrays; one or more bonding pads coupling each group of second semiconductor dies with a respective one of the plurality of first semiconductor dies; and a plurality of through-vias passing through the dielectric material and between the plurality of first semiconductor dies, each of the plurality of through-vias being coupled with at least one group of second semiconductor dies.

[0153] Aspect 36: The system according to Aspect 35 further includes: a first portion comprising one or more first conductor materials formed continuously along three depths relative to the thickness of the system; and a second portion above the first portion, the second portion comprising one or more second conductor materials formed continuously along two depths relative to the thickness of the system.

[0154] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0155] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication (e.g., in conductive contact, connected, coupled) with one another if any electrical path (e.g., a conductive path) exists between the components that can readily support the flow of signals (e.g., charge, current, voltage) between the components. At any given time, the conductive path between components in electronic communication (e.g., in conductive contact, connected, coupled) with one another may be open or closed, depending on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or an indirect conductive path between the connected components that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0156] The descriptions set forth herein and the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The embodiments include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0157] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label to distinguish the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the additional reference labels.

[0158] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including portions distributed so that the functions are implemented at different physical locations.

[0159] The illustrative blocks and modules described herein may be implemented or executed using one or more processors designed to perform the functions described herein (e.g., DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof). A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0160] As used herein, including in the claims, "or" as used in a list of items (for example, a list of items beginning with a phrase such as "at least one of ..." or "one or more of ...") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an example step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0161] As used herein, including in the claims, the article "a" or "an" preceding a noun is open-ended and is understood to refer to "at least one" of the noun or "one or more" of the noun. Thus, the terms "a," "at least one," "one or more," and "at least one of one or more" are interchangeable. For example, if a claim lists "a component" that performs one or more functions, each of the individual functions may be performed by a single component or by any combination of multiple components. Thus, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. Subsequent reference to a component introduced with the article "a" using the term "the" or "said" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components," and subsequent mention of "said component" in the claim may be understood to be equivalent to referring to "at least one of the one or more components." Similarly, reference to a component introduced as "one or more components" using the terms "the" or "said" later may refer to any or all of the one or more components. For example, reference to "the one or more components" later in a claim may be understood as equivalent to referring to "at least one of the one or more components."

[0162] Computer-readable media include non-transitory computer storage media and communication media including any media that facilitates a computer program to be transferred from one location to another. Non-transitory storage media can be any available media that can be accessed by a computer. By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage device, or can be used to carry or store desired program code components and any other non-transitory media that can be accessed by a computer or processor in the form of an instruction or data structure. In addition, any connection is suitably referred to as computer-readable media. For example, if coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, then coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0163] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: bonding a plurality of first semiconductor dies to a carrier, each of the first semiconductor dies including a respective portion of circuitry of a semiconductor unit; forming the semiconductor unit based at least in part on electrically connecting each of the plurality of first semiconductor dies to at least one other of the first semiconductor dies after bonding the plurality of first semiconductor dies to the carrier; and One or more second semiconductor dies of a respective group are joined to at least one of the plurality of first semiconductor dies, each second semiconductor die of the respective group comprising a memory array operable at least in part based on the respective portion of the circuit system of the semiconductor unit of the first semiconductor die to which the respective group is joined.

2. The method of claim 1 , wherein for each of the first semiconductor dies, the respective portion of circuitry comprises memory interface circuitry, memory controller circuitry, host controller circuitry, host processor circuitry, or any combination thereof.

3. The method of claim 1 , wherein a first corresponding portion of the circuitry of a first semiconductor die of the semiconductor unit is associated with a first logic function, and a second corresponding portion of the circuitry of a different first semiconductor die of the semiconductor unit is associated with a second logic function different from the first logic function. 4 . The method of claim 1 , wherein a first respective set of one or more second semiconductor dies and a second respective set of one or more second semiconductor dies are included in a reconstructed wafer bonded to the second semiconductor dies of the semiconductor unit.

5. The method according to claim 1, further comprising: One or more dielectric materials are formed between the plurality of first semiconductor dies at least along the carrier, wherein the one or more dielectric materials separate respective substrates of the first semiconductor dies.

6. The method according to claim 5, further comprising: forming a plurality of first cavities at a first depth through the one or more dielectric materials, each of the first cavities being in contact with at least two of the first semiconductor dies; forming a plurality of second cavities at a second depth through the one or more dielectric materials, each of the second cavities passing through at least a portion of a respective one of the first semiconductor dies; forming a plurality of third cavities at a third depth through the one or more dielectric materials, each of the third cavities being between the plurality of first semiconductor dies and in contact with the carrier; and One or more conductor materials are formed in parallel in the plurality of first cavities, in the plurality of second cavities, and in the plurality of third cavities.

7. The method according to claim 6, further comprising: One or more conductive pads, one or more conductive paths, and one or more through-holes are formed in one or more second dielectric materials adjacent to the one or more conductor materials, wherein the one or more conductive pads, the one or more conductive paths, and the one or more through-holes are formed at least in part based on concurrently forming the one or more second conductor materials in cavities associated with the one or more conductive pads, the one or more conductive paths, and the one or more through-holes.

8. The method according to claim 1, further comprising: One or more vias are formed through the one or more dielectric materials between the plurality of first semiconductor dies, each of the one or more vias being coupled with one of the set of one or more second semiconductor dies.

9. The method of claim 8, wherein at least one of the one or more through-vias provides an interface between the respective set of one or more second semiconductor dies and a surface of the semiconductor unit opposite the respective set of one or more second semiconductor dies.

10. The method according to claim 8, further comprising: One or more electrical contacts for each of the one or more through-vias are formed based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductor materials in the cavity. 11 . The method of claim 1 , wherein electrically connecting each of the plurality of first semiconductor dies is based at least in part on forming a plurality of conductive signal paths over the first semiconductor die of the semiconductor unit.

12. The method according to claim 11, further comprising: Each first semiconductor die of the plurality of first semiconductor die and the respective set of one or more second semiconductor die are verified to satisfy an operational evaluation prior to bonding the respective set of one or more second semiconductor die to the at least one of the plurality of first semiconductor die.

13. The method of claim 1, wherein bonding the respective set of one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies is based at least in part on forming one or more vias through a substrate of the first semiconductor die to which the respective set is bonded.

14. The method of claim 1, further comprising: One or more electrical contacts for each of the first semiconductor dies are formed based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductor materials in the cavity. 15 . The method of claim 1 , wherein bonding the plurality of first semiconductor die to the carrier comprises, for at least one first semiconductor die, bonding a face of the at least one semiconductor die opposite a substrate of the at least one semiconductor die to the carrier.

16. A system comprising: a carrier comprising one or more material layers; a plurality of first semiconductor dies bonded to the carrier, each first semiconductor die including a respective substrate separate from the respective substrate of each other first semiconductor die, and each first semiconductor die including a respective portion of circuitry of a semiconductor unit electrically coupled with the respective portion of circuitry of the semiconductor unit of at least one other first semiconductor die; and At least one set of one or more second semiconductor dies, each set of one or more second semiconductor dies being electrically coupled to a corresponding first semiconductor die of the plurality of first semiconductor dies, and each second semiconductor die comprising one or more memory arrays operable at least in part based on the corresponding first semiconductor die to which the second semiconductor die is connected.

17. The system of claim 16, wherein for each of the first semiconductor dies, the respective portion of circuitry comprises memory interface circuitry, memory controller circuitry, host controller circuitry, host processor circuitry, or any combination thereof.

18. The system of claim 16, further comprising: A dielectric portion of one or more dielectric materials is interposed between the respective substrates of the plurality of first semiconductor dies.

19. The system of claim 18, further comprising: One or more through-vias pass through the dielectric portion between the plurality of first semiconductor dies, each of the one or more through-vias being coupled with one of the set of one or more second semiconductor dies and bypassing the plurality of first semiconductor dies.

20. The system of claim 19, wherein at least one of the one or more through-vias provides an interface between the one of the set of one or more second semiconductor dies and a surface of the semiconductor unit opposite the respective set of one or more second semiconductor dies.

21. The system of claim 16, further comprising: A redistribution layer includes a plurality of conductive signal paths, wherein each first semiconductor die is electrically coupled to the at least one other first semiconductor die via the redistribution layer.

22. The system of claim 16, further comprising: One or more through-vias formed through the respective substrate of at least one of the plurality of first semiconductor dies, wherein each through-via provides an interface between at least one of the set of one or more second semiconductor dies and the respective first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both.

23. The system of claim 16, further comprising: A plurality of conductive pads located above the plurality of first semiconductor dies, wherein each of the plurality of conductive pads couples the corresponding group of one or more second semiconductor dies to a power distribution network, couples the corresponding group of one or more second semiconductor dies to a through silicon via of the plurality of first semiconductor dies, couples a redistribution layer above the plurality of first semiconductor dies, or any combination thereof, via the carrier.

24. The system of claim 16, further comprising: one or more first electrical contacts located at a surface of the system and coupled to at least one first semiconductor die of the plurality of first semiconductor die; and One or more second electrical contacts are located at the surface of the system and are coupled with the at least one set of one or more second semiconductor dies and bypass the plurality of first semiconductor dies.

25. A system comprising: a plurality of first semiconductor dies electrically coupled to form a semiconductor unit of the system; a dielectric material separating a respective substrate associated with each of the plurality of first semiconductor dies; a redistribution layer comprising a plurality of conductive paths electrically connecting each of the plurality of first semiconductor dies with at least one other first semiconductor die; one or more sets of second semiconductor dies, each second semiconductor die comprising a plurality of memory arrays; one or more bond pads coupling each set of second semiconductor dies with a respective one of the plurality of first semiconductor dies; and A plurality of vias pass through the dielectric material and between the plurality of first semiconductor dies, each of the plurality of vias being coupled with at least one set of second semiconductor dies.

26. The system of claim 25, wherein the redistribution layer comprises: a first portion comprising one or more first conductor materials formed continuously along three depths relative to the thickness of the system; and A second portion is located above the first portion, the second portion including one or more second conductor materials formed continuously along two depths relative to the thickness of the system.

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