Test circuit and working method thereof

Abstract

The invention discloses a test circuit and a working method thereof, and the test circuit is used for carrying out the performance test of a standard cell library, and the test circuit comprises a calculation module which is used for carrying out the calculation processing of input matrix information, and then outputting result matrix information; and the comparison module is used for comparing the input matrix information with the result matrix information to obtain a comparison result signal, and the frequency of the comparison result signal is in positive correlation with the calculation rate of the calculation module. The calculation module calculates and processes the input matrix information and then outputs result matrix information, the above steps are repeated to realize self-circulation calculation of the calculation module, and the comparison module compares the input matrix information and the result matrix information in each step to output a comparison result signal. The test process of the standard cell library is simplified, the performance of the standard cell library can be evaluated only by measuring the frequency of the comparison result signal, and the optimization speed and the working performance of the standard cell library are improved.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a testing circuit and a working method thereof. Background Art

[0002] The rapid development of AI technology in the digital age has led to a huge demand for AI chips, necessitating specialized chips focused on AI computing. Optimizing standard cell libraries for AI computing and making them suitable for AI chips is a key area of optimization. Therefore, methods are needed to quickly and flexibly evaluate the performance of standard cell libraries in AI computing to accelerate iterative design optimization and rapidly adapt to the AI market.

[0003] Currently, the performance evaluation method of standard cell libraries consumes too much time and resources, cannot meet the requirements of rapid iteration, and reduces the optimization speed and working performance of standard cell libraries. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a test circuit and a working method thereof, so as to improve the optimization speed and working performance of a standard cell library.

[0005] To solve the above technical problems, an embodiment of the present invention provides a test circuit for performing performance testing on a standard cell library, comprising: a calculation module for performing calculation processing on input matrix information and outputting result matrix information; a comparison module for comparing the input matrix information and the result matrix information to obtain a comparison result signal, wherein the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module.

[0006] In one possible design, in another implementation of another aspect of the embodiment of the present application, the test circuit further includes: a register unit, used to store input matrix information, and also used to update the input matrix information using the result matrix information according to the comparison result signal to store new input matrix information; the calculation module obtains the input matrix information from the register.

[0007] In one possible design, in another implementation of another aspect of the embodiment of the present application, the test circuit further includes: a frequency divider for obtaining the frequency of the comparison result signal, and evaluating the performance of the calculation module according to the frequency of the comparison result signal.

[0008] In one possible design, in another implementation of another aspect of the embodiment of the present application, the calculation module includes an input end and an output end, the input end is used to obtain input matrix information, and the output end is used to output result matrix information.

[0009] In one possible design, in another implementation of another aspect of the embodiment of the present application, the comparison module includes a first input terminal, a second input terminal and an output terminal, the first input terminal of the comparison module is used to obtain input matrix information, the second input terminal of the comparison module is used to obtain result matrix information, and the output terminal of the comparison module is used to output a comparison result signal.

[0010] In one possible design, in another implementation of another aspect of the embodiment of the present application, the register unit includes a register, including a first input terminal, a second input terminal and an output terminal, the first input terminal of the register is used to obtain a clock signal or a comparison result signal, the second input terminal of the register is used to obtain result matrix information, and the output terminal of the register is used to output the result matrix information; a selector, including a first input terminal and a second input terminal, the first input terminal of the selector is used to obtain input matrix information, the second input terminal of the selector is used to obtain result matrix information, and the output terminal of the selector is used to input matrix information.

[0011] In one possible design, in another implementation of another aspect of the embodiment of the present application, the register unit further includes a clock selector for outputting a clock signal to initialize the register.

[0012] In one possible design, in another implementation of another aspect of the embodiment of the present application, the frequency divider includes an input end and an output end, the input end of the frequency divider is used to obtain the comparison result signal, and the output end of the frequency divider is used to compare the frequency of the result signal.

[0013] In one possible design, in another implementation of another aspect of the embodiment of the present application, the computing module includes an odd number of computing units connected in series, each of the computing units includes a first input end and an output end, the output end of each of the computing units is connected to the input end of the next stage computing unit, and the output end of the last stage computing unit is connected to the input end of the first stage computing unit to form a ring oscillation circuit.

[0014] In one possible design, in another implementation of another aspect of the embodiment of the present application, each of the computing units also includes a second input end, and the second input end of the computing unit is used to obtain weight matrix information, perform calculations on the weight matrix information and the input matrix information, and output the output result matrix information.

[0015] In one possible design, in another implementation of another aspect of the embodiment of the present application, the calculation and processing method includes: performing matrix multiplication calculation on the weight matrix information and the input matrix information.

[0016] In one possible design, in another implementation of another aspect of the embodiment of the present application, a method for comparing input matrix information and result matrix information to obtain a comparison result signal includes: comparing the input matrix information and the result matrix information bit by bit, when all the bits on the input matrix information and the result matrix information are inverses of each other, the comparison result signal is a first level; when at least one of all the bits on the input matrix information and the result matrix information is the same, the comparison result signal is a second level, and the first level and the second level are different.

[0017] In one possible design, in another implementation of another aspect of the embodiment of the present application, the input matrix information, the result matrix information, and the weight matrix information are all 2*2 matrices.

[0018] In one possible design, in another implementation of another aspect of the embodiments of the present application, the computing unit includes a combination of several different types of standard units.

[0019] In one possible design, in another implementation of another aspect of the embodiment of the present application, the computing unit includes 8 multipliers and 4 adders.

[0020] In one possible design, in another implementation of another aspect of the embodiment of the present application, the frequency of the comparison result signal is the same as the signal frequency of the result matrix information.

[0021] Correspondingly, the technical solution of the present invention also provides a working method of the above-mentioned test circuit, including: after calculating and processing the input matrix information, outputting the result matrix information; comparing the input matrix information and the result matrix information to obtain a comparison result signal, and the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module.

[0022] In one possible design, in another implementation of another aspect of the embodiment of the present application, the test circuit further includes: storing input matrix information; and updating the input matrix information using the result matrix information according to the comparison result signal to store new input matrix information.

[0023] In one possible design, in another implementation of another aspect of the embodiment of the present application, the test circuit further includes: obtaining the frequency of the comparison result signal, and evaluating the performance of the calculation module according to the frequency of the comparison result signal.

[0024] In one possible design, in another implementation of another aspect of an embodiment of the present application, after calculating and processing the input matrix information, the method of outputting the result matrix information also includes: obtaining weight matrix information, calculating and processing the weight matrix information and the input matrix information, and outputting the output result matrix information.

[0025] In one possible design, in another implementation of another aspect of the embodiment of the present application, the calculation and processing method includes: performing matrix multiplication calculation on the weight matrix information and the input matrix information.

[0026] In one possible design, in another implementation of another aspect of the embodiment of the present application, a method for comparing input matrix information and result matrix information to obtain a comparison result signal includes: comparing the input matrix information and the result matrix information bit by bit, when all the bits on the input matrix information and the result matrix information are inverses of each other, the comparison result signal is a first level; when at least one of all the bits on the input matrix information and the result matrix information is the same, the comparison result signal is a second level, and the first level and the second level are different.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the test circuit provided by the technical solution of the present invention, the calculation module calculates and processes the input matrix information, outputs the result matrix information, and repeats the above steps to realize the self-loop calculation of the calculation module. The input matrix information and the result matrix information in each step are compared by the comparison module to output a comparison result signal. The frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module, thereby simplifying the test process of the standard cell library. It only needs to measure the frequency of the comparison result signal to evaluate the performance of the standard cell library, thereby improving the optimization speed and working performance of the standard cell library.

[0029] Furthermore, in the technical solution of the present invention, in the initial stage, the input matrix information is stored through the register unit, wherein the input matrix information in the initial stage is the initial value, so that the calculation module performs calculation processing according to the initial value and outputs the result matrix information; after the calculation module outputs the result matrix information, the register unit uses the calculation module to output the result matrix information, updates the initial value in the register unit in the initial stage to store the new input matrix information, and forms a feedback loop between the calculation module and the register unit, realizing the self-circulating calculation of the calculation module, thereby making the calculation module output a stable signal, ensuring the accuracy of the test data, and improving the working performance of the standard cell library.

[0030] Furthermore, the computing module in the technical solution of the present invention includes an odd number of computing units connected in series to form a ring oscillation circuit. The self-oscillation of the ring oscillation circuit is achieved through the self-circulating calculation of the computing module. That is, the oscillation frequency in the ring oscillation circuit is only related to the algorithm structure of the computing unit itself and the speed of the physical unit, and is therefore suitable for comparative evaluation of different processes of the computing unit.

[0031] Furthermore, in the technical solution of the present invention, the comparison module compares the input matrix information and the result matrix information bit by bit, and compares the input matrix information and the result matrix information bit by bit. When all the bits on the input matrix information and the result matrix information are mutually inverse, a first level is output, indicating that the calculation module has completed the calculation processing of the input matrix information, so that the register outputs the result matrix information as the input matrix information to the calculation module according to the first level; when at least one of all the bits on the input matrix information and the result matrix information is the same, a second level is output, indicating that the calculation module has not completed the calculation processing of the input matrix information. At this time, the register stops outputting the result matrix information as the input matrix information to the calculation module according to the second level, thereby realizing monitoring of the calculation process, and determining whether to output the result matrix information as the input matrix information by different level signals, thereby ensuring that the current result matrix information is always opposite to the input matrix information, thereby making the calculation module always in a self-loop calculation state, thereby achieving stability in the test process of the standard cell library.

[0032] In the working method of the test circuit provided by the technical solution of the present invention, after the input matrix information is calculated and processed, the result matrix information is output, and the above steps are repeated to realize self-loop calculation. By comparing the input matrix information and the result matrix information in each step to output a comparison result signal, the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module, thereby simplifying the test process of the standard cell library. It is only necessary to measure the frequency of the comparison result signal to evaluate the performance of the standard cell library, thereby improving the optimization speed and working performance of the standard cell library. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the structure of the test circuit in one embodiment of the present invention. Figure 1 ;

[0034] Figure 2 This is a schematic diagram of the structure of the test circuit in one embodiment of the present invention. Figure 2 ;

[0035] Figure 3 is a schematic structural diagram of a calculation unit in one embodiment of the present invention;

[0036] Figure 4This is a schematic diagram of the calculation process of weight matrix information and input matrix information in one embodiment of the present invention. Figure 1 ;

[0037] Figure 5 This is a schematic diagram of the calculation process of weight matrix information and input matrix information in one embodiment of the present invention. Figure 2 . DETAILED DESCRIPTION

[0038] As mentioned in the background art, the current performance evaluation method of standard cell libraries still needs to be improved.

[0039] Currently, AI computing chips have millions of transistors. If the performance of the standard cell library is evaluated through the CPU or GPU after completing all the back-end processes, the optimization of the standard cell library will take up too much time and resources, cannot meet the requirements of rapid iteration, and reduce the optimization speed and working performance of the standard cell library.

[0040] To solve the above technical problems, the technical solution of the present invention provides a test circuit and a working method thereof. After the calculation module calculates and processes the input matrix information, it outputs the result matrix information and repeats the above steps to realize the self-loop calculation of the calculation module. The comparison module compares the input matrix information and the result matrix information in each step to output a comparison result signal. The frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module, thereby simplifying the test process of the standard cell library. It only needs to measure the frequency of the comparison result signal to evaluate the performance of the standard cell library, thereby improving the optimization speed and working performance of the standard cell library.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram of the structure of the test circuit in one embodiment of the present invention. Figure 1 .

[0043] Please refer to Figure 1 The test circuit is used to perform performance testing on a standard cell library, and includes: a calculation module 1, which is used to calculate and process input matrix information INPUT and output result matrix information OUTPUT; a comparison module 2, which is used to compare the input matrix information INPUT and the result matrix information OUTPUT to obtain a comparison result signal, and the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module 1.

[0044] The calculation module 1 includes an input end and an output end, the input end is used to obtain input matrix information INPUT, and the output end is used to output result matrix information OUTPUT.

[0045] The comparison module 2 includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the comparison module 2 is used to obtain input matrix information INPUT, the second input terminal of the comparison module 2 is used to obtain result matrix information OUTPUT, and the output terminal of the comparison module 2 is used to output a comparison result signal.

[0046] The comparison module 2 includes a comparator.

[0047] In this embodiment, a method for comparing input matrix information INPUT and result matrix information OUTPUT to obtain a comparison result signal includes: performing a bit-by-bit comparison on the input matrix information INPUT and the result matrix information OUTPUT; when all bits on the input matrix information INPUT and the result matrix information OUTPUT are inverses of each other, the comparison result signal is at a first level; when at least one bit among all bits on the input matrix information INPUT and the result matrix information OUTPUT is the same, the comparison result signal is at a second level, and the first level and the second level are different.

[0048] The calculation processing of the calculation module 1 includes multiplication and addition operations.

[0049] The signal frequency of the result matrix information OUTPUT is the same as the signal frequency of the comparison result signal, but from the perspective of the signal waveform, since the comparison result signal is a pulse signal and there are peaks in the waveform, the signal frequency waveform of the result matrix information OUTPUT is smoother than the signal frequency waveform of the comparison result signal, that is, the signal frequency waveform of the result matrix information OUTPUT is easier to obtain. The subsequent divider evaluates the performance of the standard cell library by obtaining the signal frequency waveform of the result matrix information OUTPUT.

[0050] In the above scheme, after the calculation module 1 calculates and processes the input matrix information INPUT, it outputs the result matrix information OUTPUT and repeats the above steps to realize the self-loop calculation of the calculation module 1. The input matrix information INPUT and the result matrix information OUTPUT in each step are compared by the comparison module 2 to output a comparison result signal. The frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module 1, thereby simplifying the test process of the standard cell library. It is only necessary to measure the frequency of the comparison result signal to evaluate the performance of the standard cell library, thereby improving the optimization speed and working performance of the standard cell library.

[0051] In addition, the comparison module 2 compares the input matrix information INPUT and the result matrix information OUTPUT bit by bit, and compares the input matrix information INPUT and the result matrix information OUTPUT bit by bit. When all the bits on the input matrix information INPUT and the result matrix information OUTPUT are mutually inverse, a first level is output, which indicates that the calculation module 1 completes the calculation processing of the input matrix information INPUT, so that the register 301 outputs the result matrix information OUTPUT as the input matrix information INPUT to the calculation module 1 according to the first level; when all the bits on the input matrix information INPUT and the result matrix information OUTPUT are mutually inverse, a first level is output, which indicates that the calculation module 1 completes the calculation processing of the input matrix information INPUT, so that the register 301 outputs the result matrix information OUTPUT as the input matrix information INPUT to the calculation module 1 according to the first level; When at least one of the digits is the same, a second level is output, indicating that the calculation processing of the input matrix information INPUT by the calculation module 1 is not completed. At this time, the register 301 stops outputting the result matrix information OUTPUT as the input matrix information INPUT to the calculation module 1 according to the second level, thereby realizing monitoring of the calculation process and determining whether to output the result matrix information OUTPUT as the input matrix information INPUT through different level signals, thereby ensuring that the current result matrix information OUTPUT is always opposite to the input matrix information INPUT, thereby making the calculation module 1 always in a self-loop calculation state, thereby realizing the stability of the test process of the standard cell library.

[0052] Figure 2 This is a schematic diagram of the structure of the test circuit in one embodiment of the present invention. Figure 2 .

[0053] Please refer to Figure 2 The test circuit further includes: a register unit 3, used to store input matrix information INPUT, and further used to update the input matrix information INPUT using the result matrix information OUTPUT according to the comparison result signal to store new input matrix information INPUT; the calculation module 1 obtains the input matrix information INPUT from the register 301.

[0054] The register unit 3 includes a register 301, including a first input end, a second input end and an output end, the first input end of the register 301 is used to obtain a clock signal or a comparison result signal, the second input end of the register 301 is used to obtain result matrix information OUTPUT, and the output end of the register 301 is used to output the result matrix information OUTPUT; the selector 302 includes a first input end and a second input end, the first input end of the selector 302 is used to obtain input matrix information INPUT, the second input end of the selector 302 is used to obtain result matrix information OUTPUT, and the output end of the selector 302 is used to input matrix information INPUT.

[0055] The selector 302 also includes a data selection terminal DATASEL. Specifically, the data selection terminal DATASEL is used to switch the selector 302 to a state of obtaining the input matrix information INPUT when the input matrix information INPUT is an initial value in the initial stage of the calculation. After the calculation module 1 enters the calculation processing, the selector 302 is switched to a state of obtaining the result matrix information OUTPUT in the register 301.

[0056] The register unit 3 further includes a clock selector 303 for outputting a clock signal to initialize the register 301 .

[0057] In this embodiment, the clock selector 303 further includes a clock signal terminal CLK, an input terminal and a clock signal selection terminal CLK SEL. The clock signal terminal CLK is used to receive a clock signal, the input terminal obtains a comparison result signal, and the clock signal selection terminal CLK SEL is used to select an output clock signal.

[0058] Specifically, in the initial stage of calculation, there is no signal input in the register 301, and a clock signal needs to be added externally so that the input matrix information INPUT is input into the calculation module 1. At this time, the clock selector 303 outputs a clock signal. After the calculation module 1 enters the calculation process, the comparison module 2 outputs a comparison result signal to the clock selector 303 based on the input matrix information INPUT and the result matrix information OUTPUT. At this time, the clock signal selection terminal CLK SEL switches the clock selector 303 to a state of outputting a comparison result signal, so that the comparison result signal is stored in the register 301.

[0059] In the above scheme, in the initial stage, the input matrix information INPUT is stored through the register unit 3, wherein the input matrix information INPUT in the initial stage is an initial value, so that the calculation module 1 performs calculation processing according to the initial value and outputs the result matrix information OUTPUT; after the calculation module 1 outputs the result matrix information OUTPUT, the register unit 3 uses the result matrix information OUTPUT output by the calculation module 1 to update the initial value in the register unit 3 in the initial stage to store the new input matrix information INPUT, forming a feedback loop between the calculation module 1 and the register unit 3, realizing the self-circulating calculation of the calculation module 1, and then making the calculation module 1 output a stable signal, thereby ensuring the accuracy of the test data and improving the working performance of the standard cell library.

[0060] The test circuit further includes: a frequency divider for obtaining the frequency of the comparison result signal and evaluating the performance of the calculation module 1 according to the frequency of the comparison result signal.

[0061] The frequency divider includes an input end and an output end. The input end of the frequency divider is used to obtain the comparison result signal, and the output end of the frequency divider is used to output the frequency of the comparison result signal.

[0062] The computing module 1 includes an odd number of computing units 101 connected in series, each of the computing units 101 including a first input and an output, the output of each computing unit 101 being connected to the input of the next computing unit 101, and the output of the last computing unit 101 being connected to the input of the first computing unit 101 to form a ring oscillation circuit.

[0063] The computing unit 101 includes a combination of several different types of standard units.

[0064] Each of the calculation units 101 further includes a second input terminal, and the second input terminal of the calculation unit 101 is used to obtain weight matrix information WT, perform calculation processing on the weight matrix information WT and the input matrix information INPUT, and output the output result matrix information OUTPUT.

[0065] In the above scheme, the computing module 1 includes an odd number of computing units 101 connected in series to form a ring oscillation circuit. The self-circulating calculation of the computing module 1 realizes the self-oscillation of the ring oscillation circuit. That is, the oscillation frequency in the ring oscillation circuit is only related to the algorithm structure of the computing unit 101 itself and the speed of the physical unit, and is therefore suitable for comparative evaluation of different processes of the computing unit 101.

[0066] Figure 3 It is a structural diagram of a calculation unit in one embodiment of the present invention.

[0067] Please refer to Figure 3 The computing unit 101 includes 8 multipliers 1011 and 4 adders 1012, but the present invention is not limited thereto. Other numbers of multipliers and adders in the computing unit are within the protection scope of the present invention.

[0068] Figure 4 This is a schematic diagram of the calculation process of weight matrix information and input matrix information in one embodiment of the present invention. Figure 1 .

[0069] Please refer to Figure 4 The calculation and processing method includes: performing matrix multiplication calculation on the weight matrix information B and the input matrix information A to obtain the result matrix information C.

[0070] The matrix multiplication calculation process is: c1 = a1*b1 + a2*b3, c2 = a1*b2 + a2*b4, a3*b1 + a4*b3, a3*b2 + a4*b4.

[0071] Figure 5 This is a schematic diagram of the calculation process of weight matrix information and input matrix information in one embodiment of the present invention. Figure 2 .

[0072] Please refer to Figure 5 , perform matrix multiplication calculation on the weight matrix information B and the input matrix information A to obtain the result matrix information C. As can be seen from the above figure, the result matrix information C and the input matrix information A are both inverse codes of each other.

[0073] In the above scheme, the left and right matrix elements in the input matrix information A are exchanged through the matrix multiplication operation between the left and right inverse codes of the weight matrix information B and the specific input matrix information A, thereby obtaining the result matrix information C.

[0074] Correspondingly, the technical solution of the present invention also provides a working method of the above-mentioned test circuit, including: after calculating and processing the input matrix information, outputting the result matrix information; comparing the input matrix information and the result matrix information to obtain a comparison result signal, and the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module.

[0075] In this embodiment, the test circuit further includes: storing input matrix information; and updating the input matrix information using the result matrix information according to the comparison result signal to store new input matrix information.

[0076] In this embodiment, the test circuit further includes: acquiring the frequency of the comparison result signal, and evaluating the performance of the calculation module according to the frequency of the comparison result signal.

[0077] In this embodiment, after calculating and processing the input matrix information, the method of outputting the result matrix information further includes: obtaining weight matrix information, calculating and processing the weight matrix information and the input matrix information, and outputting the output result matrix information.

[0078] In this embodiment, the calculation and processing method includes: performing matrix multiplication calculation on the weight matrix information and the input matrix information.

[0079] In this embodiment, a method for comparing input matrix information and result matrix information to obtain a comparison result signal includes: comparing the input matrix information and the result matrix information bit by bit, and when all bits in the input matrix information and the result matrix information are inverses of each other, the comparison result signal is at a first level; when at least one bit among all bits in the input matrix information and the result matrix information is the same, the comparison result signal is at a second level, and the first level and the second level are different.

[0080] In the above scheme, after the input matrix information is calculated and processed, the result matrix information is output, and the above steps are repeated to realize self-loop calculation. By comparing the input matrix information and the result matrix information in each step to output a comparison result signal, the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module, thereby simplifying the test process of the standard cell library. It is only necessary to measure the frequency of the comparison result signal to evaluate the performance of the standard cell library, thereby improving the optimization speed and working performance of the standard cell library.

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test circuit for performing performance testing on a standard cell library, characterized in that: include: The calculation module is used to calculate and process the input matrix information and output the result matrix information; The comparison module is used to compare the input matrix information and the result matrix information to obtain a comparison result signal, wherein the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module.

2. The test circuit according to claim 1, wherein: Also includes: The register unit is used to store input matrix information and is also used to update the input matrix information using the result matrix information according to the comparison result signal to store new input matrix information; the calculation module obtains the input matrix information from the register.

3. The test circuit according to claim 1, wherein: Also includes: The frequency divider is used to obtain the frequency of the comparison result signal and evaluate the performance of the calculation module according to the frequency of the comparison result signal.

4. The test circuit according to claim 1, wherein: The calculation module includes an input end and an output end, the input end is used to obtain input matrix information, and the output end is used to output result matrix information.

5. The test circuit according to claim 1, wherein: The comparison module includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the comparison module is used to obtain input matrix information, the second input terminal of the comparison module is used to obtain result matrix information, and the output terminal of the comparison module is used to output a comparison result signal.

6. The test circuit according to claim 2, wherein: The register unit includes a register, including a first input end, a second input end and an output end, the first input end of the register is used to obtain a clock signal or a comparison result signal, the second input end of the register is used to obtain result matrix information, and the output end of the register is used to output the result matrix information; a selector, including a first input end and a second input end, the first input end of the selector is used to obtain input matrix information, the second input end of the selector is used to obtain result matrix information, and the output end of the selector is used to input matrix information.

7. The test circuit according to claim 6, wherein: The register unit further includes a clock selector for outputting a clock signal to initialize the register.

8. The test circuit according to claim 3, wherein: The frequency divider includes an input end and an output end. The input end of the frequency divider is used to obtain the comparison result signal, and the output end of the frequency divider is used to output the frequency of the comparison result signal.

9. The test circuit according to claim 4, wherein: The calculation module includes an odd number of calculation units connected in series, each of the calculation units includes a first input end and an output end, the output end of each calculation unit is connected to the input end of the next stage calculation unit, and the output end of the last stage calculation unit is connected to the input end of the first stage calculation unit to form a ring oscillation circuit.

10. The test circuit according to claim 9, wherein: Each of the calculation units further includes a second input terminal, and the second input terminal of the calculation unit is used to obtain weight matrix information, perform calculation processing on the weight matrix information and the input matrix information, and output the output result matrix information.

11. The test circuit according to claim 10, wherein: The calculation and processing method includes: performing matrix multiplication calculation on weight matrix information and input matrix information.

12. The test circuit according to claim 1, wherein: The method for comparing input matrix information and result matrix information to obtain a comparison result signal includes: comparing the input matrix information and the result matrix information bit by bit, when all bits in the input matrix information and the result matrix information are inverse codes of each other, the comparison result signal is at a first level; when at least one bit among all bits in the input matrix information and the result matrix information is the same, the comparison result signal is at a second level, and the first level and the second level are different.

13. The test circuit according to claim 11, wherein: The input matrix information, the result matrix information, and the weight matrix information are all 2*2 matrices.

14. The test circuit according to claim 10, wherein: The computing unit comprises a combination of several different types of standard units.

15. The test circuit according to claim 14, wherein: The computing unit includes 8 multipliers and 4 adders.

16. The test circuit according to claim 1, wherein: The frequency of the comparison result signal is the same as the signal frequency of the result matrix information.

17. An operating method of a test circuit according to any one of claims 1 to 16, characterized in that: include: After calculating and processing the input matrix information, the result matrix information is output; The input matrix information and the result matrix information are compared to obtain a comparison result signal, wherein the frequency of the comparison result signal is positively correlated with the calculation rate of the calculation module.

18. The operating method of the test circuit according to claim 17, wherein: Also includes: Storing input matrix information; and updating the input matrix information using the result matrix information according to the comparison result signal to store new input matrix information.

19. The operating method of the test circuit according to claim 17, wherein: Also includes: The frequency of the comparison result signal is obtained, and the performance of the calculation module is evaluated according to the frequency of the comparison result signal.

20. The operating method of the test circuit according to claim 17, wherein: After calculating and processing the input matrix information, the method for outputting result matrix information further includes: obtaining weight matrix information, calculating and processing the weight matrix information and the input matrix information, and outputting the output result matrix information.

21. The operating method of the test circuit according to claim 20, wherein: The calculation and processing method includes: performing matrix multiplication calculation on weight matrix information and input matrix information.

22. The operating method of the test circuit according to claim 17, wherein: The method for comparing input matrix information and result matrix information to obtain a comparison result signal includes: comparing the input matrix information and the result matrix information bit by bit, when all bits in the input matrix information and the result matrix information are inverse codes of each other, the comparison result signal is at a first level; when at least one bit among all bits in the input matrix information and the result matrix information is the same, the comparison result signal is at a second level, and the first level and the second level are different.

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