Mask pattern, mask structure and preparation method of semiconductor structure

Abstract

The embodiment of the invention provides a mask pattern, a mask structure and a preparation method of a semiconductor structure, the mask pattern comprises a main pattern array and a preset pattern array, the main pattern array comprises a plurality of main patterns arranged along a first direction and a second direction, the main pattern array at least comprises a first pattern array located on the edge of the main pattern array, and the first pattern array comprises a reference main pattern and a secondary reference main pattern which are located on the outermost side and the secondary outer side of the main pattern array respectively. The preset pattern array is located on at least one side of the first pattern array and comprises a plurality of preset patterns, in the preset direction, the size of the preset patterns is smaller than that of the reference main pattern, and the first pitch is smaller than the second pitch; wherein the preset direction comprises at least one of the first direction and the second direction, and in the preset direction, the distance between the preset pattern array and the first pattern array is smaller than the second pitch in the same direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a mask pattern, a mask structure, and a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, it is used to transfer the designed circuit pattern onto the wafer. As chip integration increases, the chip design layout environment becomes increasingly complex. As device size continues to shrink, the difference between the chip surface pattern and the original mask pattern increases after the photolithography process, which can easily lead to optical proximity effect (OPE) and other problems such as pattern distortion.

[0003] Therefore, in the process of transferring the pattern on the mask to the wafer, there are still many problems that need to be improved. Summary of the Invention

[0004] An embodiment of the present disclosure provides a mask pattern, wherein the mask pattern includes:

[0005] a main pattern array, the main pattern array comprising a plurality of main patterns arranged along a first direction and a second direction, the main pattern array comprising at least a first pattern array located at an edge of the main pattern array, the first pattern array comprising reference main patterns and secondary reference main patterns, the reference main patterns being located at the outermost sides of the edge of the main pattern array, and the secondary reference main patterns being located at the second outer sides of the edge of the main pattern array, wherein the first direction and the second direction are parallel to surfaces of the main patterns and intersect with each other, and the edge of the main pattern array is the edge of the main pattern array in the first direction and / or the second direction;

[0006] a preset pattern array, the preset pattern array being located on at least one side of the first pattern array and comprising a plurality of preset patterns, wherein, in a preset direction, the size of the preset patterns is smaller than the size of the reference main pattern, the sum of the spacing between two adjacent preset patterns and the size of the preset patterns is a first pitch, the sum of the spacing between the reference main pattern and the sub-reference main pattern and the size of the reference main pattern is a second pitch, and the first pitch is smaller than the second pitch;

[0007] The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing between the preset pattern array and the first pattern array is smaller than the second pitch in the same direction.

[0008] In some embodiments, the ratio of the size of the preset graphic to the size of the reference main graphic has a first range, the ratio of the first pitch to the second pitch has a second range, the first range is the same as the second range, and the first range and the second range are both between 1 / 5 and 1 / 3.

[0009] In some embodiments, a ratio of the spacing between the preset pattern array and the first pattern array to the second pitch ranges from 1 / 5 to 1 / 3.

[0010] In some embodiments, a boundary of the reference main pattern adjacent to a side of the preset pattern array is defined as a first boundary; and a range of the number of columns of the preset patterns arranged in the preset pattern array in a direction extending parallel to the first boundary satisfies one of the following conditions:

[0011] When the size of the reference main pattern is smaller than 0.5 times the exposure wavelength in the exposure process, the number of columns ranges from 5 to 6;

[0012] When the size of the reference main pattern is 0.5 to 1 times the exposure wavelength in the exposure process, the number of columns ranges from 3 to 4;

[0013] When the size of the reference main pattern is greater than 1 times the exposure wavelength in the exposure process, the number of columns ranges from 1 to 2.

[0014] In some embodiments, the main patterns are evenly arranged in the main pattern array; or,

[0015] In a direction from the center of the main pattern array to the edge of the main pattern array, the arrangement density of the main patterns gradually increases or decreases.

[0016] In some embodiments, the sizes of the preset graphics are equal; and / or

[0017] In a direction extending parallel to the first boundary, there are multiple columns of the preset patterns, and in a direction extending perpendicular to the first boundary, the spacing between two adjacent preset patterns is equal; and / or

[0018] In a direction extending parallel to the first boundary, the distances between two adjacent preset patterns are equal.

[0019] In some embodiments, the main graphic and the preset graphic have the same shape.

[0020] In some embodiments, the size of the preset pattern is larger than the size of a sub-resolution pattern in a photolithography process.

[0021] An embodiment of the present disclosure further provides a mask structure, which includes the mask pattern described in any one of the above embodiments.

[0022] The present disclosure also provides a method for preparing a semiconductor structure, the method comprising:

[0023] Providing a substrate, forming a material layer to be etched on the substrate, and sequentially forming a first mask layer and a second mask layer on the material layer to be etched;

[0024] An exposure process is performed on the second mask layer using the mask structure described in any of the above embodiments to form an initial first pattern and an initial second pattern on the second mask layer that exposes the top of the first mask layer, wherein the initial first pattern is a pattern obtained by transferring the main pattern to the second mask layer, and the initial second pattern is a pattern obtained by transferring the preset pattern to the second mask layer;

[0025] Etching the first mask layer along the thickness direction of the material layer to be etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer;

[0026] The material layer to be etched is etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred into the material layer to be etched, or the second pattern is transferred into the material layer to be etched to form a second structure, and the second structure does not penetrate the material layer to be etched.

[0027] In some embodiments, the preparation method further comprises: forming a filling material layer in the first structure, wherein:

[0028] When the material of the filling material layer is a conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; comprising:

[0029] Etching the first mask layer using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates a portion of the first mask layer and does not expose the top of the material layer to be etched;

[0030] Etching the material layer to be etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, comprising:

[0031] The material layer to be etched is etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred into the material layer to be etched.

[0032] In some embodiments, the preparation method further comprises: forming a filling material layer in the first structure, wherein:

[0033] When the material of the filling material layer is a non-conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; comprising:

[0034] Etching the first mask layer using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates the first mask layer and exposes the top of the material layer to be etched;

[0035] Etching the material layer to be etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, comprising:

[0036] The material layer to be etched is etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, and the second pattern is transferred into the material to be etched to form a second structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second structure does not penetrate the material layer to be etched.

[0037] In some embodiments, after forming the first structure, the preparation method further includes:

[0038] A conductive material layer is formed in the first structure to form a conductive structure.

[0039] In some embodiments, after forming the first structure, the preparation method further includes:

[0040] A non-conductive material layer is formed in the first structure to form a non-conductive structure.

[0041] In some embodiments, in the step of etching the material layer to be etched using the etched first mask layer as a mask, an etching selectivity ratio between the etched first mask layer and the material layer to be etched is in the range of 1:(5-10).

[0042] The mask pattern provided by the embodiment of the present disclosure includes: a main pattern array, the main pattern array including a plurality of main patterns arranged along a first direction and a second direction, the main pattern array including at least a first pattern array located at an edge of the main pattern array, the first pattern array including a reference main pattern and a secondary reference main pattern, the reference main pattern being located at the outermost side of the edge of the main pattern array, and the secondary reference main pattern being located at the second outer side of the edge of the main pattern array, wherein the first direction and the second direction are parallel to the surface of the main pattern and intersect with each other, and the edge of the main pattern array is the edge of the main pattern array in the first direction and / or the second direction; a preset pattern array The preset pattern array is located on at least one side of the first pattern array and includes a plurality of preset patterns, wherein, in a preset direction, the size of the preset pattern is smaller than the size of the reference main pattern, the sum of the spacing between two adjacent preset patterns and the size of the preset pattern is a first pitch, the sum of the spacing between the reference main pattern and the sub-reference main pattern and the size of the reference main pattern is a second pitch, and the first pitch is smaller than the second pitch; wherein the preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing between the preset pattern array and the first pattern array is smaller than the second pitch in the same direction. Thus, in the embodiment of the present disclosure, by adding a preset pattern array to the mask pattern, and based on the size and pitch information of the main pattern, multiple designs are performed on the size and pitch information of the preset pattern located in the preset pattern array, as well as the spacing between the preset pattern array and the first pattern array being smaller than the second pitch in the same direction. This can effectively increase the light intensity distribution of the exposure light source at the edge position of the main pattern array, thereby improving the optical correction effect of the mask pattern after the optical correction operation, reducing the occurrence of pattern distortion at the edge position, and improving the quality of photolithography imaging. This can help and enable the semiconductor structure to have a significantly higher degree of match with the main pattern in both the middle area and the edge area after the exposure, development, etching and other processes are completed.

[0043] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 A schematic structural diagram of a mask structure provided by an embodiment of the present disclosure;

[0046] Figure 2 A schematic structural diagram of another mask structure provided by an embodiment of the present disclosure;

[0047] Figure 3 A schematic diagram of a partial structure of a mask structure provided in an embodiment of the present disclosure;

[0048] Figure 4 A flowchart of a method for preparing a semiconductor structure provided by the present disclosure;

[0049] Figures 5 to 10 A process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure; wherein, Figure 5 This is a three-dimensional structural diagram of the semiconductor structure during the preparation process. Figure 6 Figure (1) and Figure 9 Figure (1) is a schematic diagram of the local structure of the mask structure. Figure 6 Figure (2) and Figure 9 Figure (2) is a schematic diagram of the structure of the semiconductor structure during the preparation process;

[0050] Figures 11 to 15 A process flow chart of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure; wherein, Figure 11 This is a three-dimensional structural diagram of the semiconductor structure during the preparation process. Figure 12 Figure (1) and Figure 14 Figure (1) is a schematic diagram of the local structure of the mask structure. Figure 12 Figure (2) and Figure 14 Figure (2) is a schematic diagram of the structure of the semiconductor structure during the preparation process. DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0053] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0054] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] As process nodes continue to shrink, the requirements for lithography resolution and pattern edge accuracy in semiconductor structures are becoming increasingly higher. During the preparation of semiconductor structures, the pattern density at the edge of the pattern array changes compared to the middle area of the pattern array, which easily causes optical proximity effect (OPE) at the edge of the pattern, resulting in pattern distortion. In many cases, even after performing the operation of adding sub-resolution patterns, the problem of edge distortion is still not completely solved.

[0058] Based on this, the technical solution of the embodiment of the present disclosure is proposed:

[0059] The embodiment of the present disclosure provides a mask pattern, the mask pattern including:

[0060] a main pattern array, the main pattern array comprising a plurality of main patterns arranged along a first direction and a second direction, the main pattern array comprising at least a first pattern array located at an edge of the main pattern array, the first pattern array comprising reference main patterns and secondary reference main patterns, the reference main patterns being located at the outermost sides of the edge of the main pattern array, and the secondary reference main patterns being located at the second outer sides of the edge of the main pattern array, wherein the first direction and the second direction are parallel to surfaces of the main patterns and intersect with each other, and the edges of the main pattern array are edges of the main pattern array in the first direction and / or the second direction;

[0061] a preset pattern array, the preset pattern array being located on at least one side of the first pattern array and comprising a plurality of preset patterns, wherein, in a preset direction, the size of the preset patterns is smaller than the size of the reference main pattern, the sum of the spacing between two adjacent preset patterns and the size of the preset patterns is a first pitch, the sum of the spacing between the reference main pattern and the sub-reference main pattern and the size of the reference main pattern is a second pitch, and the first pitch is smaller than the second pitch;

[0062] The preset direction includes at least one of a first direction and a second direction, and in the preset direction, a spacing between the preset pattern array and the first pattern array is smaller than a second pitch in the same direction.

[0063] Thus, in the embodiment of the present disclosure, by adding a preset pattern array to the mask pattern, and based on the size and pitch information of the main pattern, multiple designs are performed on the size and pitch information of the preset pattern located in the preset pattern array, as well as the spacing between the preset pattern array and the first pattern array being smaller than the second pitch in the same direction. This can effectively increase the light intensity distribution of the exposure light source at the edge position of the main pattern array, thereby improving the optical correction effect of the mask pattern after the optical correction operation, reducing the occurrence of pattern distortion at the edge position, and improving the quality of photolithography imaging. This can help and enable the semiconductor structure to have a significantly higher degree of match with the main pattern in both the middle area and the edge area after the exposure, development, etching and other processes are completed.

[0064] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0065] Figure 1 A schematic structural diagram of a mask structure provided by an embodiment of the present disclosure; Figure 2 A schematic structural diagram of another mask structure provided by an embodiment of the present disclosure; Figure 3 A schematic diagram of the partial structure of the mask structure provided in an embodiment of the present disclosure.

[0066] The mask pattern provided by the embodiment of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0067] like Figure 1 and Figure 2 As shown, the mask pattern Y includes:

[0068] A main pattern array 10, the main pattern array 10 includes a plurality of main patterns 11 arranged along a first direction and a second direction. The main pattern array 10 includes at least a first pattern array 12 located at an edge of the main pattern array 10. The first pattern array 12 includes a reference main pattern A1 and a sub-reference main pattern A2. The reference main pattern A1 is located at the outermost edge of the main pattern array 10, and the sub-reference main pattern A2 is located at the second outermost edge of the main pattern array 10. The first direction and the second direction are parallel to the surface of the main pattern 11 and intersect with each other. The edge of the main pattern array 10 is the edge of the main pattern array 10 in the first direction and / or the second direction.

[0069] A preset pattern array 20 is located on at least one side of the first pattern array 12 and includes a plurality of preset patterns 21. In a preset direction, the size of the preset patterns 21 is smaller than the size of the reference main pattern A1. The sum of the spacing between two adjacent preset patterns 21 and the size of the preset patterns 21 is a first pitch D1. The sum of the spacing between the reference main pattern A1 and the sub-reference main pattern A2 and the size of the reference main pattern A1 is a second pitch D2. The first pitch D1 is smaller than the second pitch D2.

[0070] The predetermined direction includes at least one of a first direction and a second direction, and in the predetermined direction, a spacing G between the predetermined pattern array 20 and the first pattern array 12 is smaller than a second pitch D2 in the same direction.

[0071] Here, the first direction and the second direction intersect with each other, which may include being perpendicular to each other, or not being perpendicular to each other but having other angles. Specifically, it can be flexibly selected according to actual conditions and is not specifically limited here.

[0072] In some embodiments, the main patterns 11 are evenly arranged in the main pattern array 10; or,

[0073] In a direction from the center of the main pattern array 10 to the edge of the main pattern array 10 , the arrangement density of the main patterns 11 gradually increases or decreases.

[0074] In the embodiment of the present disclosure, the arrangement of the main graphics 11 set next to the preset graphic array 20 can be divided into the following situations:

[0075] One is that the main pattern 11 can be a repeated arrangement of unit patterns, and within the range where the main pattern array 10 is located, there is only one arrangement density. At the same time, in the surrounding area of the main pattern array 10 (which can be understood as the area starting from the edge point of the main pattern array 10 and with a distance from the edge point that is 5 to 10 times the size of the main pattern 11 along the same direction), no other patterns corresponding to the functional structures in the semiconductor structure are set.

[0076] The other is that the arrangement density of the main patterns 11 gradually increases or decreases in the direction from the center of the main pattern array 10 to the edge of the main pattern array 10, and there is still an area around which a preset pattern array can be set.

[0077] In some specific embodiments, with respect to the center of the main graphic array 10 pointing to the edge of the main graphic array 10, the range of increase or decrease of the arrangement density of the main graphics 11 can be greater than 0% and less than or equal to 90%, for example, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc.

[0078] That is to say, in the embodiment of the present disclosure, the provided mask pattern Y does not impose any specific restrictions on the pattern density in the area where the main pattern array 10 is located, and main patterns 11 arranged in various densities can be applied to the mask pattern Y provided in the embodiment of the present disclosure.

[0079] In some embodiments, as Figure 1 As shown, the preset pattern array 20 may be located on one side of the edge of the main pattern array 10. The preset pattern array 20 includes a plurality of columns R arranged along a first direction, and any column R includes a plurality of preset patterns 21 arranged along a second direction.

[0080] At this point, the understanding of the dimensions, pitch, and spacing between the preset pattern 21, reference main pattern A1, and sub-reference main pattern A2 in the preset direction, as well as the spacing between the two pattern arrays, can be further explained as follows: in the first and second directions, the dimensions of the preset pattern 21 are smaller than the dimensions of the reference main pattern A1 in the same directions; in the first direction, the sum of the spacing between two adjacent preset patterns 21 and the dimensions of the preset patterns 21 is a first pitch D1; the sum of the spacing between the reference main pattern A1 and the sub-reference main pattern A2 and the dimensions of the reference main pattern A1 is a second pitch D2; in the first direction, the first pitch D1 is smaller than the second pitch D2; and in the first direction, the spacing G between the preset pattern array 20 and the first pattern array 12 is smaller than the second pitch D2 in the same direction.

[0081] Continue to refer Figure 1 In some cases, the sum of the distance between two adjacent preset graphics 21 in the second direction and the size of the preset graphics 21 can also be referred to as the first pitch D1. At the same time, the sum of the distance between two adjacent reference main graphics A1 in the second direction and the size of the reference main graphics A1 can also be referred to as the second pitch D2. In the second direction, the first pitch D1 is smaller than the second pitch D2.

[0082] But not limited to this, in other embodiments, such as Figure 2 As shown, the preset pattern array 20 may also be located on both sides of the main pattern array 10. In this embodiment, the first pattern array 12 may further include a first sub-pattern array 121 located at an edge of the main pattern array 10 along a first direction, and a second sub-pattern array 122 located at an edge of the main pattern array 10 along a second direction. The preset pattern array 20 includes a first preset pattern array 201 located at an edge of the first sub-pattern array 121 along the first direction, and a second preset pattern array 202 located at an edge of the second sub-pattern array 122 along the second direction.

[0083] exist Figure 2In the illustrated embodiment, the preset pattern array 20 may be located on both sides of the edge of the main pattern array 10. The preset pattern array 20 may include multiple columns R. The columns R may further include multiple first columns R1 arranged along a first direction and multiple second columns R2 arranged along a second direction. Any column R may include multiple preset patterns 21 arranged along the first direction or the second direction.

[0084] At this time, the understanding of the size, pitch, and spacing between the preset pattern 21, the reference main pattern A1, and the sub-reference main pattern A2 in the preset direction can be further explained as the size, spacing, and pitch information between the first sub-pattern array 121 and the first preset pattern array 201. This information can be referred to in conjunction with Figure 1 The relevant content will not be elaborated here.

[0085] At the same time, regarding the dimensions, pitch, and spacing between the two pattern arrays related to the preset pattern 21, the reference main pattern A1, and the sub-reference main pattern A2 in the preset direction, it can be further explained that, in the first or second direction, the dimensions of the preset pattern 21 are smaller than those of the reference main pattern A1, and in the second direction, the sum of the spacing between two adjacent preset patterns 21 and the dimensions of the preset patterns 21 is a first pitch D1, and the sum of the spacing between the reference main pattern A1 and the sub-reference main pattern A2 and the dimensions of the reference main pattern A1 is a second pitch D2. In the second direction, the first pitch D1 is smaller than the second pitch D2, and in the second direction, the spacing G between the second preset pattern array 202 and the second sub-pattern array 122 is smaller than the second pitch D2 in the same direction.

[0086] Continue to refer Figure 2 In some cases, in the second preset pattern array 202, the sum of the spacing between two adjacent preset patterns 21 in the first direction and the size of the preset pattern 21 can also be referred to as a first pitch D1. At the same time, in the second sub-pattern array 122, the sum of the spacing between two adjacent reference main patterns A1 in the first direction and the size of the reference main pattern A1 can also be referred to as a second pitch D2, and in the first direction, the first pitch D1 is smaller than the second pitch D2.

[0087] In some embodiments, the shape of the main graphic 11 may include but is not limited to at least one of a circle, an ellipse, a polygon or an irregular shape, or a combination thereof. When the shape of the main graphic 11 includes a polygon, the shape of the main graphic 11 may further include a triangle, a quadrilateral, a rectangle (e.g. Figure 3The main graphic 11 may be a strip-shaped graphic as shown), a pentagon or even a polygon with more sides. Furthermore, the shape of the main graphic 11 may be a combination of any two or more of the above-mentioned shapes. No specific limitation is made here and the shape can be flexibly selected according to actual conditions.

[0088] It should be noted that although Figure 1 FIG shows that the preset graphic array 20 can be located on one side of the main graphic array 10, and Figure 2 The figure shows that the preset graphic arrays 20 can be located on both sides of the main graphic array 10 . This is only an exemplary description and is not intended to be the only limitation on the application scenarios of the embodiments of the present disclosure.

[0089] In some other embodiments, in the embodiment where the preset pattern array 20 is located on one side, the preset pattern array 20 can also be located on Figure 2 The second sub-pattern array 122 is located on the side shown in FIG, or is set to the opposite side thereof, or is set to Figure 1 The opposite sides of the preset pattern array 20 are not specifically limited here and can be flexibly set according to actual conditions.

[0090] Furthermore, in some embodiments, when the preset pattern arrays 20 are located on both sides, the preset pattern arrays 20 may also be arranged adjacent to each other or opposite to each other, which is not specifically limited here and can be flexibly selected according to actual conditions.

[0091] Furthermore, when the preset graphic array 20 can also be set on more sides of the main graphic array 10, such as three sides or four sides, depending on the boundary shape of the main graphic array 10, the preset graphic array 20 can be set accordingly following the boundary of the main graphic array 10, or can be flexibly set on the side of the boundary where graphic distortion is likely to occur or on any other arbitrary area according to actual process conditions.

[0092] Continue to refer Figure 1 and Figure 2 In some embodiments, the shapes of the main graphic 11 and the preset graphic 21 may be the same.

[0093] In some specific embodiments, the specific shape of the preset pattern 21 can be set according to the shape of the main pattern 11, and in particular, can be set according to the setting of the main pattern 11 located at the edge of the main pattern array 10, that is, the reference main pattern A1. For example, the specific shape, size, etc. of the pattern can be set with reference to the setting of the reference main pattern A1 located at the edge of the main pattern array 10, and the setting of the spacing and other related aspects can be set with reference to the setting between the reference main pattern A1 and the secondary reference main pattern A2 for specific settings.

[0094] Continue to refer Figure 1 and Figure 2 As shown, in any of the above embodiments, the ratio of the size of the preset graphic 21 to the size of the reference main graphic A1 has a first range, the ratio of the first pitch D1 to the second pitch D2 has a second range, the first range is the same as the second range, and the first range and the second range are both between 1 / 5 and 1 / 3 (including endpoint values), for example, 0.2, 0.21, 0.22, 0.23, 0.25, 0.27, 0.29, 0.3, 0.31, 0.32, 0.33, etc.

[0095] In some embodiments, a ratio of the spacing G between the preset pattern array 20 and the first pattern array 12 to the second pitch D2 ranges from 1 / 5 to 1 / 3 (inclusive of the endpoints), for example, 0.2, 0.21, 0.22, 0.23, 0.25, 0.27, 0.29, 0.3, 0.31, 0.32, 0.33, etc.

[0096] It can be seen that in the embodiment of the present disclosure, the setting of the relevant information in the preset graphic array 20 is highly correlated with the setting of the relevant information in the main graphic array 10. Specifically, this can be manifested in the following aspects:

[0097] (1) The shape of the preset graphic 21 can be set in the same manner as the shape of the main graphic 11.

[0098] (2) The size of the preset pattern 21 is smaller than the size of the main pattern 11 in the same direction, the first pitch D1 is smaller than the second pitch D2, and the spacing is smaller than the second pitch.

[0099] (3) The size ratio range between the preset pattern 21 in the preset pattern array 20 and the reference main pattern A1 in the first pattern array 12 is the same as the ratio range between the first pitch D1 and the second pitch D2.

[0100] (4) The ratio range of the spacing G between the preset pattern array 20 and the first pattern array 12 to the second pitch D2 may also be the same as the aforementioned ratio range.

[0101] Thus, it can be seen that in the embodiment of the present disclosure, the setting of the relevant information in the preset graphic array 20 and the setting of the relevant information in the main graphic array 10 have a strong dependence and correlation. The two complement each other and work together to improve the graphic distortion at the edge of the main graphic array 10. In addition, because the information setting in the preset graphic array 20 in the embodiment of the present disclosure is set based on the setting information of the main graphic 11, the preset graphic 21 information added in the embodiment of the present disclosure has a high degree of compatibility with the information of the main graphic array 10, especially the first graphic array 12. Therefore, the graphic distortion at the edge of the main graphic array 10 can be effectively and targetedly improved to a large extent.

[0102] Continue to refer Figure 1 and Figure 2 In some embodiments, a boundary of the reference main pattern A1 adjacent to the preset pattern array 20 is defined as a first boundary W1; and the number range of the columns R of the preset patterns 21 arranged in the preset pattern array 20 in a direction extending parallel to the first boundary W1 satisfies one of the following conditions:

[0103] When the size of the reference main pattern A1 is smaller than 0.5 times the exposure wavelength in the exposure process (e.g., the exposure wavelength of the exposure light source, the same below), the value of column R ranges from 5 to 6 (including the endpoints), for example, 5 or 6;

[0104] When the size of the reference main pattern A1 is 0.5 to 1 times the exposure wavelength in the exposure process, the value of column R ranges from 3 to 4 (including the endpoint values), for example, 3 or 4;

[0105] When the size of the reference main pattern A1 is greater than 1 times the exposure wavelength in the exposure process, the value range of the column R is between 1 and 2 (including the endpoint values), for example, 1 or 2.

[0106] In some embodiments, as Figure 2 As shown, the first boundary W1 may further include a first sub-boundary W11 and a second sub-boundary W12. When the number of columns R is set based on the size of the reference main pattern A1 and the multiple of the exposure wavelength in the exposure process, the specific number of columns R can be set based on the position of the preset pattern array 20 on the side of the main pattern array 10, the extension direction of the corresponding sub-boundary is selected, and the specific value of the corresponding column R is set accordingly.

[0107] In some embodiments, in the same direction, the sizes of the preset graphics 21 are equal; and / or

[0108] In a direction extending parallel to the first boundary W1, there are a plurality of rows R of preset patterns 21 extending in the same direction, and in a direction extending perpendicular to the first boundary W1, the spacing between two adjacent preset patterns 21 is equal; and / or

[0109] In a direction extending parallel to the first boundary W1 , the intervals between two adjacent preset patterns 21 are equal.

[0110] In some embodiments, the size of the predetermined pattern 21 is larger than the size of a sub-resolution pattern in a photolithography process.

[0111] It is understandable that when the size of a graphic is within the size range of a sub-resolution graphic, the graphic will not be transferred to the semiconductor structure in the actual lithography process. In the embodiment of the present disclosure, the size of the preset graphic 21 is set to be larger than the size of the sub-resolution graphic in the lithography process. This helps in actual operation to obtain a transferred or non-transferred graphic structure according to structural requirements by matching the parameter settings in the process, which has higher flexibility.

[0112] It can be seen that in the embodiment of the present disclosure, by limiting the size, shape, density, and arrangement of the preset pattern 21, and the information setting method that is related to the size, pitch, and array spacing of the main pattern 11, the mask pattern Y can be transferred to the mask layer (for example, the subsequent Figure 5 and transferred to the hard mask layer (e.g., the subsequent Figure 5 On the first mask layer 31 in the etching process or the material layer L to be etched, the fidelity of the main pattern 11 after pattern transfer is improved.

[0113] like Figure 1 and Figure 2 As shown, an embodiment of the present disclosure further provides a mask structure M, and the mask structure M includes the mask pattern Y of any of the above embodiments.

[0114] In some embodiments, when obtaining the mask structure M, an optical correction operation (OPC), i.e., optical proximity effect simulation optimization, can be performed based on the mask pattern Y provided in any of the above embodiments. During the execution of this operation, optimization can be performed with the main pattern 11 as the target reference.

[0115] The present disclosure also provides a method for preparing a semiconductor structure. Figure 4 As shown, the preparation method includes the following steps:

[0116] Step S101: providing a substrate, forming a material layer to be etched on the substrate, and sequentially forming a first mask layer and a second mask layer on the material layer to be etched;

[0117] Step S102: performing an exposure process on the second mask layer using the mask structure of any of the above embodiments to form an initial first pattern and an initial second pattern on the second mask layer that expose the top of the first mask layer, wherein the initial first pattern is a pattern obtained by transferring the main pattern to the second mask layer, and the initial second pattern is a pattern obtained by transferring the preset pattern to the second mask layer;

[0118] Step S103: etching the first mask layer along the thickness direction of the material layer to be etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer;

[0119] Step S104: Etching the material layer to be etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred into the material layer to be etched, or the second pattern is transferred into the material layer to be etched to form a second structure, and the second structure does not penetrate the material layer to be etched.

[0120] It should be understood that although Figure 4 The steps in the diagram are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0121] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0122] First, execute step S101, as Figure 5 and Figure 11 As shown, a substrate 30 is provided, a material layer L to be etched is formed on the substrate 30, and a first mask layer 31 and a second mask layer 32 are sequentially formed on the material layer L to be etched.

[0123] Here, substrate 30 may be a semiconductor substrate; the material of the semiconductor substrate specifically includes a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 30 is a silicon substrate.

[0124] like Figure 5 and Figure 6 ,and Figure 11 and Figure 12 As shown, in some embodiments, before forming the material layer L to be etched, the preparation method further includes:

[0125] Sequentially forming a preset material layer 35 and a functional layer 33;

[0126] forming a preset structure 34, wherein the preset structure 34 is located on the functional layer 33;

[0127] After forming the preset structure 34, forming the material layer L to be etched includes:

[0128] A material layer L to be etched is formed, and the material layer L to be etched covers the surface of the preset structure 34 .

[0129] In some embodiments, the material of the material layer L to be etched may include but is not limited to an oxide material layer, such as silicon oxide.

[0130] In some embodiments, the first mask layer 31 may be divided into two sub-layers from bottom to top. The material of the sub-layer adjacent to the substrate 30 may include, but is not limited to, a carbon layer (SOC), and the material layer of the sub-layer located above the carbon layer may include, but is not limited to, an anti-reflective coating (ARC) material, such as an oxynitride layer, specifically a silicon oxynitride layer (SiON). The material of the second mask layer 32 may include, but is not limited to, a photoresist layer.

[0131] In some embodiments, the thickness of the first mask layer 31 can be determined based on various parameters of the structure of the main pattern 11 to be obtained in the subsequent etching process and the etching conditions. The preset pattern 21 is generally not used as a reference factor in determining the thickness of the first mask layer 31. This ensures that the first mask layer 31 has sufficient etching resistance during the process of obtaining the structure corresponding to the main pattern 11.

[0132] In some embodiments, the preset structure 34 may include but is not limited to a capacitor structure, and a functional structure may be formed in the functional layer 33 , and the functional structure may include but is not limited to a transistor structure.

[0133] In some embodiments, the material of the preset material layer 35 includes but is not limited to metal tungsten or titanium nitride.

[0134] Then, execute step S102, as Figure 6 and Figure 12 As shown, an exposure process is performed on the second mask layer 32 using the mask structure M of any of the above embodiments to form an initial first pattern P1a and an initial second pattern P2a on the second mask layer 32 that expose the top of the first mask layer 31. The initial first pattern P1a is a pattern obtained by transferring the main pattern 11 to the second mask layer 32, and the initial second pattern P2a is a pattern obtained by transferring the preset pattern 21 to the second mask layer 32.

[0135] In the embodiment of the present disclosure, the mask pattern Y included in the mask structure M includes: a main pattern array 10 and a preset pattern array 20, wherein the main pattern array 10 includes a plurality of main patterns 11 arranged along a first direction and a second direction, the main pattern array 10 includes at least a first pattern array 12 located at an edge of the main pattern array 10, the first pattern array 12 further includes a reference main pattern A1 located at the outermost side and a secondary reference main pattern A2 located at the second outermost side, the preset pattern array 20 is located on at least one side of the first pattern array 12 and includes a plurality of preset patterns 21, wherein in the preset direction, the size of the preset pattern 21 is smaller than the size of the reference main pattern A1, the sum of the spacing between two adjacent preset patterns 21 and the size of the preset pattern 21 is a first pitch D1, the sum of the spacing between the reference main pattern A1 and the secondary reference main pattern A2 and the size of the reference main pattern A1 is a second pitch D2, the first pitch D1 is smaller than the second pitch D2, and the spacing G between the preset pattern array 20 and the first pattern array 12 is smaller than the second pitch D2 in the same direction.

[0136] In this way, since the mask pattern Y included in the mask structure M includes both the main pattern 11 for forming the desired target structure and the preset pattern array 20 having multiple preset patterns 21, and supplemented by the size relationship between the first pitch and the second pitch, and the size relationship between the second pitch and the spacing, the light intensity distribution of the main pattern 11 located at the edge during the exposure process can be effectively enhanced, the optical correction effect of the mask pattern Y after the optical correction operation can be improved, the occurrence of pattern distortion and the like can be reduced, and the quality of photolithography imaging can be improved. In this way, it can be helpful and make it possible for the semiconductor structure to be processed after the exposure, development, etching and other processes are completed, which can also be understood as the completion of step S104, in the subsequent Figure 9 or Figure 14 In the embodiment, the obtained first structure S1 can have a significantly higher matching degree with the main pattern 11 whether in the middle area or the edge area.

[0137] Then, step S103 is executed. Figure 7 and Figure 13 As shown, along the thickness direction of the material layer L to be etched, the first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates at least a portion of the first mask layer 31.

[0138] In some embodiments, the second mask layer 32 may have a high etching selectivity to the first mask layer 31, for example, between 1:(5-10) (including endpoints), such as 1:5, 1:6, 1:7, 1:8, 1:9 or 1:10.

[0139] Here, the etching selectivity refers to the ratio of the etching amount of the material to be etched (the first mask layer 31) to the etching amount of the etching mask material (the second mask layer 32). It can be used as an important reference for evaluating the etching conditions (such as etching gas, flow rate) and the selection of matching materials (photoresist / hard mask) and thickness setting in the graphic conversion program. Simply put, as shown in the figure below, the material to be etched is a carbon layer (Carbon), and the etching mask material (i.e., the etching pattern film layer) is a photoresist layer. In the process of etching the pattern on the photoresist layer onto the carbon layer (Carbon), the thickness of the photoresist layer (the second mask layer 32) will also be consumed at the same time. After the carbon layer (Carbon) etching is finally completed, the thickness of the photoresist layer will be sacrificed.

[0140] In the embodiment of the present disclosure, when the second mask layer 32 and the first mask layer 31 can have a higher etching selectivity, the second mask layer 32 and the first mask layer 31 are formed in this step. Figure 6 and Figure 12 During the process of the initial first pattern P1a and the initial second pattern P2a shown, the pattern is transferred from the second mask layer 32 to the first mask layer 31. Before the transfer process is completed, the second mask layer 32 will not disappear due to natural consumption to ensure the smooth progress of the pattern transfer process.

[0141] In some cases, the etch selectivity can be determined using a simplified method. For example, the ratio of the thickness of the etch mask material to the thickness of the material to be etched can be used as the etch selectivity. However, this is not limited to this. In some cases, a relatively accurate value can be obtained by comprehensively considering the thickness of the etch mask material and the thickness of the material to be etched, as well as the etching conditions and other factors that may affect the etching rate. The specific method used can be selected based on actual circumstances and is not specifically limited here.

[0142] In some embodiments, the size of the predetermined pattern 21 is larger than the size of a sub-resolution pattern in a photolithography process.

[0143] It is understandable that when the size of a graphic is within the size range of a sub-resolution graphic, the graphic will not be transferred to the semiconductor structure in the actual lithography process. In the embodiment of the present disclosure, the size of the preset graphic 21 is set to be larger than the size of the sub-resolution graphic in the lithography process. This helps in actual operation to obtain a transferred or non-transferred graphic structure according to structural requirements by matching the parameter settings in the process, which has higher flexibility.

[0144] In some embodiments, when the material layer L to be etched on the substrate 30 is a dielectric layer, which only serves as an insulating layer to isolate the circuit, and has a thickness in the range of 100 to 200 nm, the preset pattern 21 generally stops at the hard mask layer (first mask layer 31) thereon and does not etch to the dielectric layer. Figure 5 or Figure 11 When the preset structure 34 is wrapped, that is, as a wrapping layer, the radial depth of the wrapped structure is more than 500nm, and the top of the wrapped preset structure 34 is still more than about 300nm away from the top of the dielectric layer, the preset pattern 21 can be selected to be etched to the dielectric layer, and an incomplete etching phenomenon is formed, that is, the material layer L to be etched is not completely penetrated, and it stays on this layer.

[0145] In some cases, whether the second pattern P2 is etched into the material layer L to be etched may be determined based on the type of material filled after the step of etching the material layer L to be etched is completed. For example:

[0146] In some embodiments, as Figures 7 to 10 As shown, after executing the subsequent step S104, the preparation method further includes: forming a filling material layer 36 in the first structure S1, wherein,

[0147] When the filling material layer 36 is made of a conductive material, the first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates at least a portion of the first mask layer 31.

[0148] The first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched. The second pattern P2 penetrates a portion of the first mask layer 31 and does not expose the top of the material layer L to be etched.

[0149] The material layer to be etched L is etched using the etched first mask layer 31 as a mask to transfer the first pattern P1 into the material layer to be etched L to form a first structure S1, including:

[0150] The material layer to be etched L is etched using the etched first mask layer 31 as a mask to transfer the first pattern P1 into the material layer to be etched L to form a first structure S1. The first structure S1 penetrates the material layer to be etched L and exposes the top of the functional layer 33 on the substrate 30, and the second pattern P2 is not transferred into the material layer to be etched L.

[0151] In this embodiment, when the material filled in the first structure S1 is a conductive material, the practice of not transferring the second pattern P2 to the material layer L to be etched helps to improve the anti-puncture performance of the structure obtained based on the conductive material, and improve the electrical performance and reliability of the semiconductor structure finally obtained.

[0152] In other embodiments, Figures 13 to 15 As shown, the preparation method further includes: forming a filling material layer 36 in the first structure S1, wherein,

[0153] When the filling material layer 36 is made of a non-conductive material, the first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates at least a portion of the first mask layer 31.

[0154] The first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched. The second pattern P2 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched.

[0155] The material layer to be etched L is etched using the etched first mask layer 31 as a mask to transfer the first pattern P1 into the material layer to be etched L to form a first structure S1, including:

[0156] The material layer to be etched L is etched using the etched first mask layer 31 as a mask to transfer the first pattern P1 into the material layer to be etched L to form a first structure S1, and the second pattern P2 is transferred into the material to be etched to form a second structure S2; wherein the first structure S1 penetrates the material layer to be etched L and exposes the top of the substrate 30, and the second structure S2 does not penetrate the material layer to be etched L, that is, the second structure S2 does not expose the top of the functional layer 33 located on the substrate 30.

[0157] In this embodiment, when the material filled in the first structure S1 is a non-conductive material, the second pattern P2 is transferred to the material layer L to be etched, so that the pattern distribution density at the edge position of the first structure S1 is closer to the pattern distribution density at the middle position of the first structure S1, which helps to improve the filling performance when the filling material layer 36 is formed and improve the integrity of the semiconductor structure.

[0158] Finally, step S104 is executed. Figure 8 and Figure 9 ,as well as Figure 14 As shown, the material layer to be etched L is etched using the etched first mask layer 31 as a mask to transfer the first pattern P1 into the material layer to be etched L to form a first structure S1; wherein the first structure S1 penetrates the material layer to be etched L and exposes the top of the substrate 30, and the second pattern P2 is not transferred into the material layer to be etched L, or the second pattern P2 is transferred into the material layer to be etched L to form a second structure S2, and the second structure S2 does not penetrate the material layer to be etched L.

[0159] In some embodiments, as Figure 8 As shown, the thickness of the first mask layer 31 is reduced due to natural consumption during the etching process, and in this embodiment, the second pattern P2 in the first mask layer 31 is not transferred to the material layer L to be etched.

[0160] In other embodiments, Figure 14 As shown, the thickness of the first mask layer 31 is reduced due to natural consumption during the etching process, and in this embodiment, the second pattern P2 in the first mask layer 31 is transferred to the material layer L to be etched.

[0161] In some embodiments, Figure 7 and Figure 8 In the embodiment shown, in order to prevent the second pattern P2 from being transferred thereto during the subsequent etching process of the material layer to be etched L, in the step of etching the material layer to be etched using the etched first mask layer 31 as a mask, the etching selectivity ratio between the first mask layer 31 retained at the bottom of the second pattern P2 after etching and the material layer to be etched L is in the range of 1:(5-10) (including the endpoint values), for example, 1:5, 1:6, 1:7, 1:8, 1:9 or 1:10, etc.

[0162] In this way, the second pattern P2 can be obtained without being transferred to the material layer L to be etched by controlling the etching selectivity, thereby preventing the structure obtained by subsequently filling the conductive material in the first structure S1 from being broken down, thereby improving the reliability of the semiconductor structure.

[0163] In some embodiments, as Figure 10As shown, after forming the first structure S1, the preparation method further includes:

[0164] A filling material layer 36 is formed in the first structure S1 , and the filling material layer is a conductive material layer, so as to form a conductive structure C.

[0165] Here, the conductive material layer may include any suitable conductive material, and the conductive structure C may be used as a conductive plug.

[0166] In some embodiments, as Figure 15 As shown, after forming the first structure S1, the preparation method further includes:

[0167] A filling material layer 36 is formed in the first structure S1 . The filling material layer 36 is a non-conductive material layer, so as to form a non-conductive structure D.

[0168] Here, the non-conductive material layer may include any suitable material, such as oxide, nitride or oxynitride material, etc., which is not specifically limited here. The non-conductive structure D may be used as an insulating or isolating structure.

[0169] In any of the above embodiments, the selection of etching process and etching parameters in the etching step can be determined according to the structure to be formed corresponding to the main pattern 11, thereby ensuring that the main pattern 11 is smoothly transferred from the second mask layer 32 to the first mask layer 31 and the material layer L to be etched.

[0170] In some embodiments, the etching process may adopt at least one of reactive ion etching (RIE) or deep reactive ion etching (DRE) to ensure high-precision pattern transfer.

[0171] In some embodiments, after the etching process is completed, etching parameters may be further adjusted according to the etching results to obtain an ideal target structure.

[0172] In some embodiments, the conductive structure C in the semiconductor structure obtained by the preparation method of the present disclosure can be a contact structure (contact, CT), for example, it can be a channel that connects the local interconnect (Metal0) metal layer and the upper plate of the capacitor (for example, TCP capacitor) to the upper metal layer (for example, Metal1, i.e., M1 layer).

[0173] The various technical features in the technical solutions described in the various embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0174] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A mask pattern, characterized in that: The mask pattern includes: a main pattern array, the main pattern array comprising a plurality of main patterns arranged along a first direction and a second direction, the main pattern array comprising at least a first pattern array located at an edge of the main pattern array, the first pattern array comprising reference main patterns and secondary reference main patterns, the reference main patterns being located at the outermost sides of the edge of the main pattern array, and the secondary reference main patterns being located at the second outer sides of the edge of the main pattern array, wherein the first direction and the second direction are parallel to surfaces of the main patterns and intersect with each other, and the edge of the main pattern array is the edge of the main pattern array in the first direction and / or the second direction; a preset pattern array, the preset pattern array being located on at least one side of the first pattern array and comprising a plurality of preset patterns, wherein, in a preset direction, the size of the preset patterns is smaller than the size of the reference main pattern, the sum of the spacing between two adjacent preset patterns and the size of the preset patterns is a first pitch, the sum of the spacing between the reference main pattern and the sub-reference main pattern and the size of the reference main pattern is a second pitch, and the first pitch is smaller than the second pitch; The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing between the preset pattern array and the first pattern array is smaller than the second pitch in the same direction.

2. The mask pattern according to claim 1, wherein: The ratio of the size of the preset pattern to the size of the reference main pattern has a first range, the ratio of the first pitch to the second pitch has a second range, the first range is the same as the second range, and the first range and the second range are both between 1 / 5 and 1 / 3.

3. The mask pattern according to claim 2, wherein: The ratio of the spacing between the preset pattern array and the first pattern array to the second pitch is in a range of 1 / 5 to 1 / 3.

4. The mask pattern according to claim 1, wherein: A boundary of the reference main pattern adjacent to the preset pattern array is defined as a first boundary; and a range of the number of columns of the preset patterns arranged in the preset pattern array in a direction extending parallel to the first boundary satisfies one of the following conditions: When the size of the reference main pattern is smaller than 0.5 times the exposure wavelength in the exposure process, the number of columns ranges from 5 to 6; When the size of the reference main pattern is 0.5 to 1 times the exposure wavelength in the exposure process, the number of columns ranges from 3 to 4; When the size of the reference main pattern is greater than 1 times the exposure wavelength in the exposure process, the number of columns ranges from 1 to 2.

5. The mask pattern according to any one of claims 1 to 4, characterized in that: The main patterns are evenly arranged in the main pattern array; or, In a direction from the center of the main pattern array to the edge of the main pattern array, the arrangement density of the main patterns gradually increases or decreases.

6. The mask pattern according to claim 4, wherein: The sizes of the preset graphics are equal; and / or In a direction extending parallel to the first boundary, the number of columns of the preset patterns is multiple, and in a direction extending perpendicular to the first boundary, the spacing between two adjacent preset patterns is equal; and / or In a direction extending parallel to the first boundary, the distances between two adjacent preset patterns are equal.

7. The mask pattern according to any one of claims 1 to 4, characterized in that: The main graphic and the preset graphic have the same shape.

8. The mask pattern according to any one of claims 1 to 4, characterized in that: The size of the preset pattern is larger than the size of a sub-resolution pattern in a photolithography process.

9. A mask structure, characterized in that: The mask structure includes the mask pattern according to any one of claims 1 to 8.

10. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate, forming a material layer to be etched on the substrate, and sequentially forming a first mask layer and a second mask layer on the material layer to be etched; performing an exposure process on the second mask layer using the mask structure according to claim 9 to form an initial first pattern and an initial second pattern on the second mask layer that exposes the top of the first mask layer, wherein the initial first pattern is a pattern obtained by transferring the main pattern to the second mask layer, and the initial second pattern is a pattern obtained by transferring the preset pattern to the second mask layer; Etching the first mask layer along the thickness direction of the material layer to be etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; The material layer to be etched is etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred into the material layer to be etched, or the second pattern is transferred into the material layer to be etched to form a second structure, and the second structure does not penetrate the material layer to be etched.

11. The preparation method according to claim 10, characterized in that: The preparation method further comprises: forming a filling material layer in the first structure, wherein: When the material of the filling material layer is a conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; comprising: Etching the first mask layer using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates a portion of the first mask layer and does not expose the top of the material layer to be etched; Etching the material layer to be etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, comprising: The material layer to be etched is etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred into the material layer to be etched.

12. The preparation method according to claim 10, characterized in that The preparation method further comprises: forming a filling material layer in the first structure, wherein: When the material of the filling material layer is a non-conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; comprising: Etching the first mask layer using the exposed second mask layer as a mask to form a first pattern and a second pattern, wherein the first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates the first mask layer and exposes the top of the material layer to be etched; Etching the material layer to be etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, comprising: The material layer to be etched is etched using the etched first mask layer as a mask to transfer the first pattern into the material layer to be etched to form a first structure, and the second pattern is transferred into the material to be etched to form a second structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second structure does not penetrate the material layer to be etched.

13. The preparation method according to claim 11, characterized in that After forming the first structure, the preparation method further includes: A conductive material layer is formed in the first structure to form a conductive structure.

14. The preparation method according to claim 12, characterized in that After forming the first structure, the preparation method further includes: A non-conductive material layer is formed in the first structure to form a non-conductive structure.

15. The preparation method according to any one of claims 10 to 14, characterized in that: In the step of etching the material layer to be etched using the etched first mask layer as a mask, an etching selectivity ratio between the etched first mask layer and the material layer to be etched is in the range of 1:(5-10).

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