Calibration method, device, electronic device and storage medium for photolithography model

Abstract

The embodiments of the present application disclose a method, device, electronic device, and storage medium for calibrating a photolithography model. This solution can select different types of standard patterns and test patterns on a mask as initial sampling points, adjust the parameters in the optical model, and perform optical simulation on the initial sampling points based on the adjusted optical model to obtain simulated dimensions. The simulated dimensions are compared with the designed dimensions, and the initial sampling points are screened based on the comparison results to obtain target sampling points. The target sampling points are subjected to wafer measurement to obtain a first measurement result, and the optical model and photoresist model are calibrated based on the first measurement result. The embodiments of the present application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip manufacturing technology, and in particular to a method, device, electronic device and storage medium for calibrating a photolithography model. Background Art

[0002] As chip design density and complexity continue to increase, the industry is placing higher demands on the prediction accuracy of lithography models and the range of pattern types and sizes they cover. In this context, collecting a large number of sampling points to train and calibrate complex lithography models has become critical. Especially as logic chip manufacturing processes advance to the 28nm node and below, building lithography models for many complex lithography layers often requires tens of thousands or even hundreds of thousands of sampling points. For example, lithography models using negative development technology often require over 100,000 sampling points.

[0003] Currently, traditional sampling point selection methods rely on design rules to mechanically cover various patterns on the test mask. To ensure model coverage, these methods often require the inclusion of a large number of sub-design rule-sized patterns, for example, less than 50% of the design rule size. However, during actual exposure, these patterns exceed the limits of the lithography process window, resulting in some sampling points being unable to be imaged or having substandard imaging quality, seriously affecting the accuracy and efficiency of the lithography model. Summary of the Invention

[0004] The present application provides a method, device, electronic device and storage medium for calibrating a lithography model, which can simulate and screen sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency.

[0005] The present application provides a method for calibrating a lithography model, comprising:

[0006] Select different types of standard patterns and test patterns on the mask as initial sampling points;

[0007] Adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size;

[0008] Comparing the simulated size with the designed size, and screening the initial sampling points according to the comparison result to obtain target sampling points;

[0009] Wafer measurement is performed on the target sampling point to obtain a first measurement result, and the optical model and the photoresist model are calibrated according to the first measurement result.

[0010] Optionally, adjusting the parameters in the optical model includes:

[0011] Adjusting the focus parameters to make the optical model symmetrical with respect to the preset graphic focus;

[0012] The threshold parameters are calibrated according to the anchor point so that the simulated value of the optical model is consistent with the target value.

[0013] Optionally, calibrating the threshold parameter according to the anchor point includes:

[0014] Selecting an anchor point graphic that matches the design size among the initial sampling points;

[0015] The threshold parameter of the optical model is iteratively adjusted until the error between the simulated size of the anchor point pattern of the optical model and the actual measured size of the wafer is less than a preset tolerance.

[0016] Optionally, screening the initial sampling points according to the comparison results to obtain target sampling points includes:

[0017] Eliminating sampling points whose simulation size is smaller than a preset percentage of the design rule size;

[0018] A target size interval not covered by the initial sampling point set in the design rule is determined to supplement the sampling points corresponding to the target size interval to obtain target sampling points.

[0019] Optionally, after calibrating the optical model and the photoresist model according to the first measurement result, the method further includes:

[0020] adding supplementary sampling points, and performing optical simulation on the supplementary sampling points according to the calibrated optical model to screen the supplementary sampling points;

[0021] performing wafer measurement on the screened supplementary sampling points to obtain a second measurement result;

[0022] The first measurement result and the second measurement result are fused, and the optical model and the photoresist model are calibrated according to the fusion result.

[0023] Optionally, the process of acquiring the supplementary sampling points includes:

[0024] When screening the initial sampling points, obtaining a graph in which the similarity between the simulated size and the designed size reaches a preset value among the eliminated sampling points; or

[0025] A pattern is selected on the mask according to a calibration residual of the optical model and the photoresist model.

[0026] Optionally, the fusing the first measurement result and the second measurement result includes:

[0027] Determining repeated sampling points in the first measurement result and the second measurement result, and calculating measurement means of the repeated sampling points;

[0028] The first measurement result and the second measurement result are weighted according to the position information of the initial sampling point and the supplementary sampling point on the wafer, and the weighted data are fused.

[0029] The present application also provides a calibration device for a lithography model, comprising:

[0030] A selection module is used to select different types of standard patterns and test patterns on the mask as initial sampling points;

[0031] A simulation module, configured to adjust parameters in the optical model and perform optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size;

[0032] A screening module, configured to compare the simulated size with the designed size, and screen the initial sampling points according to the comparison result to obtain target sampling points;

[0033] The calibration module is configured to perform wafer measurement on the target sampling point to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result.

[0034] The present application also provides an electronic device, characterized in that the electronic device includes a memory and a processor, the memory stores a computer program, and the processor executes the steps of any one of the lithography model calibration methods provided in the present application by calling the computer program stored in the memory.

[0035] The present application also provides a storage medium, characterized in that the storage medium stores a computer program, and the computer program is suitable for being loaded by a processor to execute the steps in any one of the lithography model calibration methods provided in the present application.

[0036] The lithography model calibration method provided in this application can select different types of standard patterns and test patterns on a mask as initial sampling points, adjust the parameters in the optical model, and perform optical simulation on the initial sampling points based on the adjusted optical model to obtain simulated dimensions. The simulated dimensions are compared with the designed dimensions, and the initial sampling points are screened based on the comparison results to obtain target sampling points. Wafer measurement is performed on the target sampling points to obtain a first measurement result, and the optical model and photoresist model are calibrated based on the first measurement result. The embodiments of the present application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in this application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 This is a flow chart of a method for calibrating a lithography model provided in an embodiment of the present application;

[0039] Figure 2 1 is another flow chart of a method for calibrating a lithography model provided in an embodiment of the present application;

[0040] Figure 3 This is a schematic structural diagram of a calibration device for a lithography model provided in an embodiment of the present application;

[0041] Figure 4 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0043] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0044] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and they can be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0045] It should be noted that in this article, step codes such as 101 and 102 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. Those skilled in the art may execute 102 first and then 101, etc. during specific implementation, but these should all be within the scope of protection of this application.

[0046] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0047] An embodiment of the present application provides a method for calibrating a lithography model. The executor of the method for calibrating a lithography model may be a calibration device for the lithography model provided in the embodiment of the present application, or a server integrating the calibration device for the lithography model, wherein the calibration device for the lithography model may be implemented in hardware or software.

[0048] like Figure 1 As shown, Figure 1 1 is a schematic diagram of a first process flow of a method for calibrating a lithography model provided in an embodiment of the present application. The specific process flow of the method for calibrating a lithography model may be as follows:

[0049] 101. Select different types of standard patterns and test patterns on the mask as initial sampling points.

[0050] In one embodiment, standard patterns and test patterns can be selected on a test mask based on the design rules of the lithography layer, wherein the above-mentioned design rules may include the minimum feature size, the allowed size range, the pattern type, etc. The standard patterns may include industry-common test structures, such as isolated lines (ISO lines), dense line arrays (dense lines), contact holes (contact holes) or corner structures (corner structures). These patterns cover basic lithography behaviors and are used to evaluate the versatility of the model. The test patterns may include patterns that simulate actual chip designs, such as complex patterns similar to those in logic cells (such as L-shaped, T-shaped or curved structures), or variant size patterns generated based on design rules, such as changing from the minimum design size to the maximum allowed size in 10% steps to obtain initial sampling points.

[0051] In one embodiment, a specific sampling method can be used to construct an initial sampling matrix. For example, with the design rule size (such as 28nm) as the center, the small size (10nm~20nm) and large size (30nm~50nm) are distributed logarithmically, and stratified sampling is performed according to the pattern density and duty cycle in each size range to ensure uniform coverage of the sampling points in the feature space.

[0052] The patterns selected in this embodiment cover all key pattern types to capture the various optical effects of the lithography process. They also include the minimum, typical, and larger sizes allowed by the design rules, as well as some sizes exceeding the design rules to test the model's boundary behavior. The initial sampling points can include information such as the coordinates, type, design size, and reticle position of all selected patterns.

[0053] 102. Adjust the parameters in the optical model, and perform optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size.

[0054] In one embodiment, an optical model can be established based on lithography conditions, which may include parameters such as light source wavelength, numerical aperture, and illumination mode. The parameters in the optical model are then adjusted to improve model accuracy. Adjusting the parameters in the optical model can include adjusting focus parameters to make the optical model focally symmetrical with respect to a preset pattern, and calibrating a threshold parameter based on an anchor point to ensure that the simulated value of the optical model is consistent with the target value. Specifically, the focus parameter represents the focal position of the lithography machine. ISO patterns (such as isolated lines or holes) can be selected because they are sensitive to focus variations. The focus parameter is then iteratively adjusted to ensure that the model's simulated behavior for the ISO pattern remains symmetrical during focus defocus, i.e., that the dimensional changes are consistent under positive and negative focus offsets. For example, if the simulated dimensional differences between focus offsets of +100nm and -100nm are too large, the focus parameter in the model is adjusted until the difference is less than a threshold (e.g., 5%).

[0055] In one embodiment, the step of calibrating the threshold parameters based on the anchor points may include selecting an anchor point pattern matching the design dimensions from the initial sampling points, and iteratively adjusting the threshold parameters of the optical model until the error between the simulated dimensions of the anchor point pattern and the actual measured dimensions of the wafer is less than a preset tolerance. Specifically, the threshold parameter of the optical model, or threshold, represents the threshold energy during the lithography process and affects the image size of the pattern. Calibration is performed using the anchor point pattern matching the design dimensions as a key reference point. For example, a standard-sized pattern in the design rules with a known target value is used for calibration. By comparing the simulated dimensions of the model at the key reference point with the actual target value (or historical measured value), the threshold value is adjusted to ensure that the simulated dimensions are consistent with the target value (e.g., within a 1% error). For example, if the design dimension of the key reference point is 50 nm, but the model simulates 52 nm, the threshold value is reduced until the simulated value converges to 50 nm. After this adjustment, an accurate purely optical lithography model is obtained.

[0056] Next, the adjusted optical model can be used to simulate each initial sampling point. The simulation process calculates the predicted size of each point on the wafer, also known as the simulated size, based on the lithography conditions (such as light source wavelength and numerical aperture) and the mask pattern. The simulation tool then outputs the simulated size data for each sampling point.

[0057] 103. Compare the simulated size with the designed size, and screen the initial sampling points according to the comparison results to obtain the target sampling points.

[0058] In one embodiment, for each initial sampling point, the simulated size is compared to the designed size. The designed size is the expected size of the pattern on the mask, for example, a line width of 40 nm. The percentage deviation of the simulated size relative to the designed size is then calculated, for example, simulated size = design size × (1 + deviation percentage). Initial sampling points are then selected based on the comparison results.

[0059] In one embodiment, the step of screening the initial sampling points may include eliminating invalid points and supplementing missing points. Specifically, based on the comparison results, features with simulated sizes less than 30% of the design rule size can be identified and removed. For example, if the design rule minimum size is 40 nm, features with simulated sizes less than 28 nm are eliminated. These features may not be imaged (e.g., the features disappear) or have poor image quality (e.g., blurred edges) in actual lithography, resulting in invalid wafer metrology. The elimination criteria ensure that the sampling points are focused on the valid measurable area. Next, during the screening process, the initial sampling points can be further checked to ensure that they cover all critical dimension ranges and types. If certain design dimension ranges (e.g., near the design rule minimum size) or feature types (e.g., complex corner structures) are not adequately covered, additional sampling points can be added. The supplementation principle is based on the design rules to ensure a uniform distribution of sampling points. Specifically, the step of screening the initial sampling points based on the comparison results to obtain target sampling points may include: eliminating sampling points with simulated sizes less than a preset percentage of the design rule size; determining the target dimension range within the design rule that is not covered by the initial sampling point set; and supplementing the sampling points corresponding to the target dimension range to obtain the target sampling points. It should be noted that the simulation size being 30% smaller than the design rule size is not a prescribed standard. Implementers can adjust this standard according to different situations. For example, if the lithography conditions meet a resolution smaller than the design rule size, or for certain 2D graphics, graphics whose simulation size is 40% to 50% smaller than the design rule size can be eliminated.

[0060] Furthermore, after screening the initial sampling points, the comprehensiveness of the target sampling points can be verified. For example, the size distribution (from the smallest design size to the largest size), type coverage (the proportion of standard patterns and test patterns), and number (after screening, the scale is reduced, and invalid points are reduced by 10-20%, but the total number of points is still sufficient for modeling) can be checked.

[0061] 104. Perform wafer measurement on the target sampling point to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result.

[0062] In one embodiment, a test mask can be used to expose the wafer to generate the actual lithographic pattern. Then, physical measurements are performed on the target sampling points. The measurement tool can be a scanning electron microscope (SEM) or optical measurement equipment, which measures the actual dimensions on the wafer based on the location of each target sampling point. The measurement process involves establishing an automated measurement script, defining the coordinates of the measurement points, the number of measurements (e.g., measuring each point three times and taking the average), and conditions (e.g., acceleration voltage). During the measurement process, invalid data points are removed, such as points where imaging failed, points with abnormally small or large measurement dimensions, or points with a low signal-to-noise ratio. After collecting all measurement values, data cleaning can be performed, such as deleting invalid points, calculating the mean and standard deviation, and organizing them into a structured data set. This serves as the first measurement result.

[0063] Next, the first measurement results can be used to calibrate the photolithography model. The photolithography model consists of two components: an optical model and a photoresist model. The photoresist model simulates the chemical processes of the photoresist, such as development and baking. For the optical model, parameters (such as focus or threshold) can be fine-tuned based on the measurement data. This is done by using an optimization algorithm, such as the least-squares method, to minimize the error between the simulated and measured dimensions. For example, if the measurement shows that certain features are too large, the threshold value can be adjusted to reduce the deviation. For the photoresist model, parameters such as the diffusion coefficient or sensitivity are primarily adjusted. Specifically, measurement data can be used, especially for photoresist-sensitive features, to align the model predictions with the measured values ​​through iterative fitting. For example, the diffusion parameter can be adjusted to match the edge roughness measured. In one embodiment, after the calibration, partial data can be used to verify the model's accuracy. If the error is large, such as exceeding 5%, the parameters can be readjusted until the model converges, for example, to an error of less than 2%.

[0064] This embodiment reduces wafer measurement time and data collation overhead by pre-screening invalid sampling points, thereby improving lithography modeling efficiency. It also avoids the measurement of a large number of invalid points in traditional methods by establishing an accurate optical model for simulation screening, thereby providing high-quality data for subsequent modeling.

[0065] As described above, the lithography model calibration method proposed in the embodiment of the present application can select different types of standard patterns and test patterns on the mask as initial sampling points, adjust the parameters in the optical model, and perform optical simulation on the initial sampling points based on the adjusted optical model to obtain simulated dimensions. The simulated dimensions are compared with the design dimensions, and the initial sampling points are screened based on the comparison results to obtain target sampling points. The target sampling points are then subjected to wafer measurement to obtain a first measurement result, and the optical model and photoresist model are calibrated based on the first measurement result. The embodiment of the present application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency.

[0066] The method described in the above embodiment will be further described below.

[0067] See also Figure 2 , Figure 2 This is a second flow chart of the method for calibrating a photolithography model provided in an embodiment of the present application. The method includes:

[0068] 201. Select different types of standard patterns and test patterns on the mask as initial sampling points.

[0069] Specifically, based on the design rules for the photolithography layer, a variety of standard patterns of different types and sizes, as well as test patterns similar to the design patterns, can be selected on the test mask. These patterns cover the various characteristics that may be present in the photolithography layer, such as different shapes, line widths, and spacing. By selecting a rich and diverse set of patterns, we ensure that the initial sampling points cover the various conditions required by the photolithography model, providing comprehensive foundational data for subsequent model training and calibration.

[0070] 202. Adjust the parameters in the optical model, and perform optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size.

[0071] After establishing an initial optical model, the focus parameters within the model are adjusted to ensure focus symmetry with respect to the ISO pattern. Next, key pattern points with known precise target values ​​or actual measured values ​​are used as anchor points. Threshold parameters are adjusted to ensure that the simulated values ​​of the optical model at these anchor points align with the target values ​​(e.g., actual wafer measurements). This series of parameter adjustments results in a relatively accurate pure optical lithography model.

[0072] The adjusted optical model can be used to perform optical simulation on the selected initial sampling points, simulating the imaging conditions of these patterns during the photolithography process, thereby obtaining the simulated size of each initial sampling point.

[0073] 203. Compare the simulated size with the designed size, and screen the initial sampling points according to the comparison results to obtain the target sampling points.

[0074] The simulated dimensions of each initial sampling point obtained in step 202 are compared with the design dimensions of the photoresist layer. Patterns whose simulated dimensions are less than 30% of the design rule dimensions are eliminated. A check is also performed to determine whether any sampling points of the target size are uncovered. If so, these uncovered sampling points of the target size are added. After this screening and addition process, the target sampling points are ultimately obtained.

[0075] 204. Perform wafer measurement on the target sampling point to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result.

[0076] On the wafer after the test mask is exposed, the target sampling points are measured, the measurement values ​​are collected, and the first measurement results are obtained. The measured data are sorted and invalid measurement data is removed, such as sampling points without imaging, poor imaging quality, and measurement dimensions far smaller than the latest design rules. The sorted valid data is then used to calibrate the optical model and photoresist model so that the model can more accurately reflect the actual lithography process.

[0077] 205. Add additional sampling points and perform optical simulation on the additional sampling points according to the calibrated optical model to screen the additional sampling points.

[0078] In one embodiment, the process of acquiring supplemental sampling points may include: acquiring patterns from the eliminated sampling points whose simulated dimensions meet a preset value for similarity to the designed dimensions when screening the initial sampling points; or selecting patterns on the mask based on calibration residuals of the optical model and the photoresist model. Specifically, when screening the initial sampling points, patterns from the eliminated sampling points whose simulated dimensions meet a preset value for similarity to the designed dimensions may be acquired. Although these patterns were eliminated during the initial screening, they may be helpful for model calibration and verification. Additionally, patterns may be selected on the mask based on calibration residuals of the optical model and the photoresist model, i.e., the difference between the model's predicted value and the actual measured value. By analyzing the residuals, areas where the model performs poorly can be identified, and supplemental sampling points can be selected in a targeted manner.

[0079] The calibrated optical model can then be used to perform optical simulation on the obtained supplementary sampling points to obtain simulated dimensions. The simulated dimensions are then compared with the design dimensions, and sampling points with simulated dimensions less than 30% of the design rule dimensions are eliminated to select supplementary sampling points that meet the requirements.

[0080] 206. Perform wafer measurement on the screened supplementary sampling points to obtain a second measurement result.

[0081] For the selected additional sampling points, the same measurement method as above can be used to measure the wafer, establish a measurement recipe, and collect the measurement values ​​to obtain the second measurement result. Similarly, the measurement data is sorted to remove invalid data.

[0082] 207. Fuse the first measurement result and the second measurement result, and calibrate the optical model and the photoresist model according to the fusion result.

[0083] In one embodiment, the step of fusing the first and second measurement results may include: determining repeated sampling points in the first and second measurement results, calculating a measurement mean of the repeated sampling points, weighting the first and second measurement results based on the on-wafer location information of the initial and supplementary sampling points, and fusing the weighted data. Because the supplementary sampling points may include the initial sampling points eliminated in step 203, such as patterns whose simulated dimensions have a predetermined similarity to the designed dimensions, the sampling point identifiers of the two sets of data must be compared to filter out sampling points that exist in both sets of results. The sampling point identifiers may include information such as pattern type, size, and coordinates on the reticle. Specifically, a data comparison table may be established, using the unique sampling point identifier as a key field. The first and second measurement results are then traversed to identify repeated sampling points. The arithmetic mean of the multiple measurement values ​​(the values ​​in the first and second measurement results) for each repeated sampling point is then calculated.

[0084] The on-wafer location information for the initial and supplementary sampling points is the physical coordinates of the sampling points on the reticle or the corresponding exposure position on the wafer. Specifically, the wafer can be divided into several regions, with each sampling point's location corresponding to a unique region coordinate. For adjacent sampling points, the spatial distance between them is calculated; closer distances indicate higher positional correlation. Sampling points with closer locations have more similar lithography process conditions and stronger correlation in measurement data, thus being assigned higher weights. For non-duplicate sampling points in the first and second measurement results, the weight relationship relative to the surrounding sampling points is then calculated based on their on-wafer location. Finally, the measurement data from all sampling points (averaging for duplicate points and weighted fusion for non-duplicate points) is merged to form a unified fused dataset. This fused dataset, containing measurement information for both the initial and supplementary sampling points, covers common design dimensions while supplementing details in the model's residual error regions. This allows for more accurate calibration of the optical and photoresist models, shortening the modeling cycle.

[0085] As described above, the lithography model calibration method proposed in the embodiment of the present application can select different types of standard patterns and test patterns on the mask as initial sampling points, adjust the parameters in the optical model, and perform optical simulation on the initial sampling points based on the adjusted optical model to obtain simulated dimensions. The simulated dimensions are compared with the designed dimensions. The initial sampling points are screened based on the comparison results to obtain target sampling points. Wafer measurement is performed on the target sampling points to obtain a first measurement result. The optical model and the photoresist model are calibrated based on the first measurement result. Supplementary sampling points are added and optical simulation is performed on the supplementary sampling points based on the calibrated optical model to screen the supplementary sampling points. Wafer measurement is performed on the screened supplementary sampling points to obtain a second measurement result. The first measurement result and the second measurement result are fused, and the optical model and the photoresist model are calibrated based on the fused result. The embodiment of the present application can simulate and filter the sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency.

[0086] In order to implement the above method, an embodiment of the present application further provides a calibration device for a lithography model, which can be integrated into a terminal device such as a mobile phone, a tablet computer, or the like.

[0087] For example, Figure 3 FIG. 1 is a schematic diagram of a structure of a calibration device for a photolithography model provided in an embodiment of the present application. The calibration device for a photolithography model may include:

[0088] The selection module 301 is used to select different types of standard patterns and test patterns on the mask as initial sampling points;

[0089] A simulation module 302 is configured to adjust parameters in the optical model and perform optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size;

[0090] A screening module 303 is configured to compare the simulated size with the designed size, and screen the initial sampling points according to the comparison result to obtain target sampling points;

[0091] The calibration module 304 is configured to perform wafer measurement on the target sampling point to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result.

[0092] As can be seen from the above, the lithography model calibration device proposed in the embodiment of the present application can select different types of standard patterns and test patterns on the mask as initial sampling points, adjust the parameters in the optical model, and perform optical simulation on the initial sampling points based on the adjusted optical model to obtain simulated dimensions. The simulated dimensions are compared with the design dimensions, and the initial sampling points are screened based on the comparison results to obtain target sampling points. The target sampling points are then subjected to wafer measurement to obtain a first measurement result, and the optical model and photoresist model are calibrated based on the first measurement result. The embodiment of the present application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency.

[0093] All of the above technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0094] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be accomplished by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0095] To this end, an embodiment of the present application provides a computer-readable storage medium storing a plurality of computer programs, which can be loaded by a processor to execute the steps of any of the lithography model calibration methods provided in the embodiments of the present application. For example, the computer program can execute the following steps:

[0096] Select different types of standard patterns and test patterns on the mask as initial sampling points;

[0097] Adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size;

[0098] Comparing the simulated size with the designed size, and screening the initial sampling points according to the comparison result to obtain target sampling points;

[0099] Wafer measurement is performed on the target sampling point to obtain a first measurement result, and the optical model and the photoresist model are calibrated according to the first measurement result.

[0100] The specific implementation of the above operations can be found in the previous embodiments and will not be repeated here.

[0101] The storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0102] Since the computer program stored in the storage medium can execute the steps in any one of the photolithography model calibration methods provided in the embodiments of the present application, the beneficial effects that can be achieved by any one of the photolithography model calibration methods provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0103] An embodiment of the present application also provides an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the device equipped with the chip executes the methods in various possible implementation modes as described above.

[0104] For example, the computer device mentioned above can be a terminal device with corresponding functions such as a mobile phone, tablet computer, personal computer, cloud computer, etc. Figure 4 , Figure 4 A schematic diagram of the structure of a computer provided in an embodiment of the present application.

[0105] The computer device 400 may include components such as a memory 401 and a processor 402. Those skilled in the art will appreciate that Figure 4 The computer device structure shown in the figure does not constitute a limitation to the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0106] Memory 401 can be used to store applications and data. The applications stored in memory 401 include executable code. Applications can be composed of various functional modules. Processor 402 executes various functional applications and data processing by running the applications stored in memory 401.

[0107] The processor 402 is the control center of the computer device. It uses various interfaces and lines to connect the various parts of the entire computer device. By running or executing applications stored in the memory 401 and calling data stored in the memory 401, it performs various functions of the computer device and processes data, thereby monitoring the computer device as a whole.

[0108] In this embodiment, the processor 402 in the computer device loads the executable code corresponding to one or more application processes into the memory 401 according to the following instructions, and the processor 402 runs the application stored in the memory 401 to execute:

[0109] Select different types of standard patterns and test patterns on the mask as initial sampling points;

[0110] Adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size;

[0111] Comparing the simulated size with the designed size, and screening the initial sampling points according to the comparison result to obtain target sampling points;

[0112] Wafer measurement is performed on the target sampling point to obtain a first measurement result, and the optical model and the photoresist model are calibrated according to the first measurement result.

[0113] It is understood that the above scenarios are merely examples and do not limit the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, those skilled in the art will appreciate that with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application will also be applicable to similar technical problems.

[0114] The steps in the method of the embodiment of the present application can be adjusted in order, combined, or deleted according to actual needs. The modules in the device of the embodiment of the present application can be combined, divided, or deleted according to actual needs.

[0115] In this application, the same or similar terminology, technical solutions and / or application scenario descriptions are only described in detail the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, for the same or similar terminology, technical solutions and / or application scenario descriptions that are not described in detail later, you can refer to the previous relevant detailed descriptions.

[0116] In this application, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0117] The various technical features of the technical solution of this application can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0118] The above embodiments can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. A computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. Available media can include magnetic media (e.g., floppy disks, storage disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks).

[0119] The above is a detailed introduction to the calibration method, device, electronic device and storage medium of a lithography model provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for calibrating a lithography model, characterized in that: include: Select different types of standard patterns and test patterns on the mask as initial sampling points; Adjusting parameters in the optical model, the adjusting the parameters in the optical model comprising: adjusting focus parameters to make the optical model symmetrical about a preset pattern focus; selecting an anchor point pattern matching the design size at the initial sampling point; iteratively adjusting a threshold parameter of the optical model until an error between a simulated size of the optical model at the anchor point pattern and an actual measured size of the wafer is less than a preset tolerance, so that a simulated value of the optical model is consistent with a target value; Performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulated size; Comparing the simulated size with the design size, and eliminating sampling points whose simulated size is smaller than a preset percentage of the design rule size; determining a target size interval in the design rule that is not covered by the initial sampling point set, and supplementing the sampling points corresponding to the target size interval to obtain target sampling points; Wafer measurement is performed on the target sampling point to obtain a first measurement result, and the optical model and the photoresist model are calibrated according to the first measurement result.

2. The method for calibrating a lithography model according to claim 1, wherein: After calibrating the optical model and the photoresist model according to the first measurement result, the method further includes: adding supplementary sampling points, and performing optical simulation on the supplementary sampling points according to the calibrated optical model to screen the supplementary sampling points; performing wafer measurement on the screened supplementary sampling points to obtain a second measurement result; The first measurement result and the second measurement result are fused, and the optical model and the photoresist model are calibrated according to the fusion result.

3. The method for calibrating a lithography model according to claim 2, wherein: The process of obtaining the supplementary sampling points includes: When screening the initial sampling points, obtaining a graph in which the similarity between the simulated size and the designed size reaches a preset value among the eliminated sampling points; or A pattern is selected on the mask according to a calibration residual of the optical model and the photoresist model.

4. The method for calibrating a lithography model according to claim 2, wherein: The fusing of the first measurement result and the second measurement result includes: Determining repeated sampling points in the first measurement result and the second measurement result, and calculating measurement means of the repeated sampling points; The first measurement result and the second measurement result are weighted according to the position information of the initial sampling point and the supplementary sampling point on the wafer, and the weighted data are fused.

5. A calibration device for a photolithography model, characterized in that: include: A selection module is used to select different types of standard patterns and test patterns on the mask as initial sampling points; a simulation module configured to adjust parameters in an optical model, wherein the adjustment of the parameters in the optical model includes: adjusting a focus parameter to make the optical model symmetrical about a preset pattern focus; selecting an anchor point pattern matching the designed size at the initial sampling point; iteratively adjusting a threshold parameter of the optical model until an error between a simulated size of the optical model at the anchor point pattern and an actual measured size of the wafer is less than a preset tolerance, so that a simulated value of the optical model is consistent with a target value; and performing an optical simulation on the initial sampling point based on the adjusted optical model to obtain a simulated size. a screening module, configured to compare the simulated size with the design size, and eliminate sampling points whose simulated size is smaller than a preset percentage of the design rule size; determine a target size interval in the design rule that is not covered by the initial sampling point set, and supplement the sampling points corresponding to the target size interval to obtain target sampling points; The calibration module is configured to perform wafer measurement on the target sampling point to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result.

6. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and the processor executes the steps of the lithography model calibration method according to any one of claims 1 to 4 by calling the computer program stored in the memory.

7. A storage medium, characterized in that: The storage medium stores a computer program, and the computer program is suitable for being loaded by a processor to execute the steps of the method for calibrating a lithography model according to any one of claims 1 to 4.

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