Branch prediction method

Abstract

According to the branch prediction method provided by the invention, the branch prediction result is obtained by indexing the historical branch prediction instructions in the branch prediction condition table, and the relevance between the historical branch prediction instructions can be well utilized, so that the success rate of branch prediction is greatly improved; meanwhile, the last four bits of the branch prediction instruction and values in the global historical register are subjected to logical operation, an operation value is obtained and then indexed, and the influence of the alias of the branch prediction instruction on branch prediction can be reduced; meanwhile, when the branch prediction result is skipping and the operation code of the branch prediction result is matched with the operation code of the indexed historical branch prediction instruction, the branch prediction result is trusted, so that the branch prediction accuracy is further improved; and moreover, the jump address is obtained by adopting a direct operation method, so that the area overhead and the delay caused by storing a large number of branch addresses by the BTB (Branch Target Buffer) can be saved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a branch prediction method. Background Art

[0002] RISC-V is an open standard instruction set architecture (ISA) based on the principles of Reduced Instruction Set Computing (RISC). Unlike other commercial and proprietary ISAs (such as ARM and x86), RISC-V is an open and free-to-use ISA, allowing anyone to design, manufacture, and sell RISC-V chips and software without paying licensing fees. Current RISC-V processors in the embedded field are mostly short pipeline designs, offering 2-5 stages. To simplify the design and reduce area, their branch prediction schemes are mostly simple static branch prediction. There are two types of static branch prediction schemes. One is based on the jump address. After the jump address is calculated, it is compared with the current program counter (PC) value. If the jump address is less than the current PC value, the branch instruction is predicted to jump; otherwise, it is predicted not to jump. The other is a two-bit branch predictor. A two-bit branch predictor uses two bits of history information to predict whether a branch will occur (taken) or not (not taken). This predictor usually uses a two-bit saturating counter to represent the historical behavior of each branch. The value of the counter is updated based on the most recent branch result.

[0003] Static branch prediction does not adjust its prediction strategy based on the actual execution of the program. It typically determines branch paths based on simple heuristics or compiler analysis. The main advantage of this approach is its simplicity of implementation and the lack of additional hardware support to track and predict branch behavior. However, due to the lack of runtime information, static branch prediction accuracy is generally low. A two-bit branch predictor relies solely on the historical behavior of a single branch. This means it may not accurately predict branches that depend on the behavior of other branches in the program. The state transition of a saturating counter takes time. For example, if the behavior of a branch suddenly changes from frequently taken to not taken, it takes several iterations for the counter to transition from a "strongly taken" state to a "strongly not taken" state. During this process, multiple mispredictions may occur. For certain types of branches, such as those with highly erratic behavior, a two-bit branch predictor may not provide satisfactory prediction accuracy, especially when the branch behavior changes frequently.

[0004] Furthermore, for design simplicity and area reduction, current embedded processors often feature tightly coupled data paths and processor components, resulting in a high degree of binding and few expandable interfaces. Similarly, their memory design typically consists of a large, adjacent SRAM with limited access speeds, or no memory design is implemented, with direct bus access to various memory modules and peripherals. The lack of expansion interfaces and the tightly coupled design hinder the future upgradeability of these embedded processors, as well as their adaptability and optimization for specific domains and target groups. Furthermore, the overly simplistic memory structure significantly impacts processor performance during the value retrieval phase and memory accesses. External memory accesses often consume multiple cycles, and the lack of a memory structure increases the cycle time required for each memory access, reducing overall efficiency. Accessing main memory consumes more energy than accessing cache, as it typically involves longer physical distances and more complex communication protocols. Therefore, systems without caches may have higher energy consumption. Summary of the Invention

[0005] The object of the present invention is to provide a branch prediction method to solve the problem of low accuracy of existing branch prediction methods.

[0006] In order to achieve the above object, the present invention provides a branch prediction method, comprising:

[0007] Fetching an instruction from an instruction cache module and pre-decoding it to determine whether the instruction is a branch prediction instruction;

[0008] When the instruction is a branch prediction instruction, performing a logical operation on the last N bits of the PC address of the branch prediction instruction and a value in a global history register to obtain an operation value, wherein the global history register stores the most recent N branch jumps, where N ≥ 2;

[0009] Using the operation value to index a historical branch prediction instruction in a branch prediction table to obtain a branch prediction result, wherein the branch prediction table is used to store a jump result and an operation code of the historical branch prediction instruction;

[0010] When the branch prediction result is a jump and the operation code of the branch prediction result matches the operation code of the indexed historical branch prediction instruction, calculating a jump address and jumping; and,

[0011] The branch prediction instruction is decoded and executed to verify whether the branch prediction result is accurate.

[0012] Optionally, the instruction cache module adopts a fully associative design and uses a dedicated handshake signal to communicate directly with the main memory.

[0013] Optionally, each cache line of the instruction cache module has a valid bit and a count bit, and the valid bit is used to indicate whether the corresponding cache line is valid. When the instruction cache module hits, the count bit of the hit cache line is cleared, and the count bit of other valid cache lines is increased by 1.

[0014] Optionally, when the instruction cache module is full, if a miss occurs in the instruction cache module, all the count bits are checked, the valid bit of the cache line with the largest count bit value is cleared, and the cache line is replaced with the instruction retrieved from the main memory by the instruction cache module, and then the valid position of the cache line is set to 1.

[0015] Optionally, the global history register has N storage bits, and the N storage bits record the most recent N branch jump situations in sequence, wherein when the branch jump situation is a jump, the corresponding storage bit is 1, and when the branch jump situation is no jump, the corresponding storage bit is 0.

[0016] Optionally, the jump result has two storage bits. When the jump result of the historical branch prediction instruction is a jump, the corresponding jump result is increased by one; when the jump result of the historical branch prediction instruction is not a jump, the corresponding jump result is decreased by one.

[0017] Optionally, when the historical branch prediction instruction is indexed in the branch prediction status table using the operation value, the branch prediction instruction is decoded and executed, and then the indexed jump result and operation code are updated.

[0018] Optionally, the logical operation is an exclusive-OR operation, and the opcode is the last 7 bits of the branch prediction instruction.

[0019] Optionally, after the branch prediction instruction is decoded, it is sent to a corresponding execution unit for execution, and each of the execution units is isolated from each other in communication.

[0020] Optionally, after the branch prediction instruction is decoded, it is sent to the single execution unit that successfully shakes hands for execution, and only the execution unit that successfully shakes hands is valid among all the execution units.

[0021] The branch prediction method provided by the present invention obtains a branch prediction result by indexing the historical branch prediction instruction in the branch prediction situation table, which can make good use of the correlation between the historical branch prediction instructions, thereby greatly improving the success rate of branch prediction. At the same time, the last four bits of the branch prediction instruction are logically operated with the value in the global history register to obtain an operation value and then indexed, which can reduce the impact of the alias of the branch prediction instruction on the branch prediction; at the same time, the branch prediction result is trusted only when the branch prediction result is a jump and the operation code of the branch prediction result matches the operation code of the indexed historical branch prediction instruction, thereby further improving the accuracy of branch prediction; and, the jump address is obtained by a direct operation method, thereby saving the area overhead and delay caused by storing a large number of branch addresses in the BTB (branch target buffer). BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flow chart of the branch prediction method provided in this embodiment;

[0023] Figure 2 A processing pipeline diagram provided for this embodiment;

[0024] Figure 3 A structural block diagram of the instruction cache module provided in this embodiment;

[0025] Figure 4 A schematic diagram of the communication between the instruction cache module and the main memory provided in this embodiment;

[0026] Figure 5 A schematic diagram of the global history register provided in this embodiment;

[0027] Figure 6 The structural block diagram of the ex stage provided for this embodiment;

[0028] Figure 7 This is a diagram of the jump address generation structure provided in this embodiment. DETAILED DESCRIPTION

[0029] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0030] Figure 1 This is a flow chart of the branch prediction method provided in this embodiment. Figure 1 As shown, the branch prediction method includes:

[0031] Step S100: fetching an instruction from an instruction cache module and pre-decoding the instruction to determine whether the instruction is a branch prediction instruction;

[0032] Step S200: When the instruction is a branch prediction instruction, a logical operation is performed on the last four bits of the branch prediction instruction and a value in a global history register to obtain an operation value, wherein the global history register stores the most recent N branch jumps, where N≥2;

[0033] Step S300: using the operation value to index a historical branch prediction instruction in a branch prediction table to obtain a branch prediction result, wherein the branch prediction table is used to store the jump result and operation code of the historical branch prediction instruction;

[0034] Step S400: When the branch prediction result is a jump and the opcode of the branch prediction result matches the opcode of the indexed historical branch prediction instruction, a jump address is calculated, and the branch prediction instruction is decoded and executed.

[0035] Figure 2 The processing pipeline diagram provided for this embodiment. Figure 2 As shown, the branch prediction method has a four-stage pipeline, which is implemented using a 32-bit RISC-V processor, supports IM instructions, namely integer and multiplication instruction sets, and supports machine mode and interrupt handling functions. The four stages of the pipeline are if (instruction fetch), id (instruction decode), ex (execution), and wb (write back). Instructions are executed sequentially and have a variable-length execution pipeline.

[0036] In the if phase, step S100 is executed, and the value module directly fetches instructions from the instruction cache module (icache or cache). Considering the embedded design, the program running on the processor will not be particularly large, so a smaller instruction cache module can be used. Using a small-capacity instruction cache module can significantly improve memory access efficiency without consuming too much area. It also helps to split the timing path between the value module and main memory, which can effectively increase the processor frequency.

[0037] Figure 3 This is a block diagram of the instruction cache module provided in this embodiment. Figure 4 This is a schematic diagram of the communication between the instruction cache module and the main memory provided in this embodiment. Figure 3 and Figure 4 As shown, the instruction cache module adopts a fully connected design, is physically close to the CPU, and uses dedicated handshake signals to communicate directly with the main memory without going through the bus, thereby improving memory access efficiency.

[0038] Each cache line of the instruction cache module has 1 valid bit and 6 count bits (6-bit saturated counter). The valid bit is used to indicate whether the corresponding cache line is valid. When a hit occurs in the instruction cache module, the count bit of the hit cache line is cleared, and the count bits of other valid cache lines are increased by 1. The instruction cache module adopts the LRU (Least Recently Used) strategy for replacement. The LRU strategy will eliminate the data items that have not been accessed for the longest time. Specifically, when the instruction cache module is full (which can be determined by checking the valid bits), if the instruction cache module has a cache miss, all the count bits are checked, the valid bit of the cache line with the largest count bit value is cleared, and the cache line is replaced with the instruction fetched from the main memory by the instruction cache module, and then the valid position of the cache line is set to 1.

[0039] Figure 7 The jump address generation structure diagram provided for this embodiment illustrates how the jump address of this method is obtained when a jump is required.

[0040] Furthermore, the retrieved instruction will be pre-decoded to determine whether the instruction is a branch prediction instruction. Specifically, the purpose of pre-decoding is to distinguish branch prediction instructions (branch instructions) and jal instructions and jalr instructions in advance. Among them, the jalr instruction can be used as a function call and return, and a specific register will be used to indicate this situation. A specific return address stack (RAS) can be designed. If a jalr instruction in this situation is detected, then in the write-back phase (wb phase), in addition to writing the result back to the register, it will also be written to the return address stack. When this situation is detected again, the data in the return address stack can be popped out and used as the address of the next instruction.

[0041] For the identified jal instruction, the jump address can be directly calculated and jumped.

[0042] Furthermore, for any ecall instruction (privileged context call instruction) detected during pre-decoding, its jump target address is also stored in the CAT (CSR jump address table, where CSR stands for Control and Status Register). Given the relatively small number of ecall instructions, the CAT contains only four entries, indexed by the last two digits of the ecall instruction's PC address. When an ecall instruction is detected again, the jump address read from the CAT is used directly for the jump.

[0043] Executing step S200, when the instruction is a branch prediction instruction, performing a logical operation on the last N bits of the PC address of the branch prediction instruction and the value in a global history register to obtain an operation value, wherein the global history register stores the most recent N branch jump conditions, where N ≥ 2. The global history register has N storage bits, and the N storage bits sequentially record the most recent N branch jump conditions. When the branch jump condition is a jump, the corresponding storage bit is 1, and when the branch jump condition is a no-jump, the corresponding storage bit is 0.

[0044] In this embodiment, the last four bits of the PC address of the branch prediction instruction and the value in the global history register are subjected to an XOR operation to obtain the operation value.

[0045] Figure 5 Schematic diagram of the global history register provided in this embodiment. Figure 5 As shown, the global history register can record the latest four branch jumps. If a jump occurs, it will save 1, otherwise it will save 0. Figure 5 The branch jump conditions in are no jump, jump, jump, and jump.

[0046] Execute step S300, and use the operation value to index the historical branch prediction instruction in the branch prediction situation table to obtain a branch prediction result. The branch prediction situation table is used to store the jump result and operation code of the historical branch prediction instruction. The operation code is usually 13-15 bits of the branch prediction instruction. The jump result has two storage bits. When the jump result of the historical branch prediction instruction is a jump, the corresponding jump result is increased by one. When the jump result of the historical branch prediction instruction is not a jump, the corresponding jump result is decreased by one. The operation code has 3 storage bits to store the 3-bit operation code. The branch prediction result is the jump result of the indexed historical branch prediction instruction.

[0047] Specifically, each entry in the branch prediction status table consists of a two-bit saturated counter and a three-bit saturated counter. When a jump occurs in the historical branch prediction instruction (the previous branch prediction instruction predicted to this point), the value stored in the corresponding two-bit saturated counter is incremented by one; if no jump occurs, the value is decremented by one. The three-bit saturated counter stores bits 13-15 of the PC address of the historical branch prediction instruction (the previous branch prediction instruction predicted to this point), i.e., the opcode (func3).

[0048] Next, step S400 is executed. When the branch prediction result is a jump and the opcode of the branch prediction result matches the opcode of the indexed historical branch prediction instruction, a jump address is directly calculated and the jump is performed. If the branch prediction result is not a jump, the PC address of the branch prediction instruction is increased by 4 to re-fetch the instruction to obtain the PC address of the next instruction. Obtaining the branch prediction result by indexing the historical branch prediction instruction in the branch prediction status table can effectively utilize the correlation between the historical branch prediction instructions, thereby significantly improving the success rate of branch prediction. At the same time, the last four bits of the branch prediction instruction are logically operated with the value in the global history register to obtain an operation value before indexing, thereby reducing the impact of branch prediction instruction aliases on branch prediction. Furthermore, the branch prediction result is only trusted when the branch prediction result is a jump and the opcode of the branch prediction result matches the opcode of the indexed historical branch prediction instruction, further improving the accuracy of branch prediction. Furthermore, obtaining the jump address by direct calculation can save the area overhead and delay caused by storing a large number of branch addresses in the BTB (branch target buffer).

[0049] In the id stage, step S500 is executed to decode the branch prediction instruction.

[0050] In the ex stage, the decoded branch prediction instruction is executed to verify whether the branch prediction result is accurate.

[0051] Specifically, Figure 6 The structural diagram of the ex stage provided in this embodiment is as follows: Figure 6 As shown, after the branch prediction instruction is decoded, it is sent to the corresponding execution unit for execution, and each execution unit is isolated from each other in communication. The execution unit adopts a separate design, and each execution unit is separated from each other. No data path is designed. The result from the ID stage (the decoding result of the ID stage) selects a specific execution unit to send data for execution. A handshake connection method is adopted. The handshake between the ID and each execution unit ensures that only one execution unit is valid. After the branch prediction instruction is decoded, it is sent to the single execution unit with a successful handshake for execution. Among all the execution units, only the execution unit with a successful handshake is valid. Figure 6 ALU stands for arithmetic logic execution unit, LSU stands for load and store execution unit, BJU stands for branch and jump instruction execution unit, and MULDIVU stands for multiplication and division execution unit. Multiplication and division adopt a configurable pipeline length design.

[0052] At the same time, for the results to be submitted by the selection unit (mux), possible raw data conflicts are checked through simple register index comparison, and the results are directly bypassed and forwarded to the ID stage to resolve the conflict problem.

[0053] In this way, for new execution units, if they want to expand, they only need to add two-way handshake signals on the basis of the original execution units, and then they can be directly connected to the processor for merging and upgrading. The execution cycle required by each execution unit is also not fixed, and the pipeline length is variable. The execution unit in the execution stage will send a global pause signal during operation, which will be released when the calculation result is obtained, and at the same time, the valid bit of the handshake signal to the next level will be pulled high. The subsequent abnormal interrupt processing and instruction submission and writeback are all processed in the wb stage. In other words, the present invention adopts a loosely coupled ex execution stage design, and there is no coupling and data path between the execution units, which facilitates the upgrade of each unit. It is also convenient to add new functional units on this basis to expand the application scenarios and computing power of the processor.

[0054] The result of the execution is passed to the wb stage. If successful, the instruction is retired smoothly. A handshake is also used between each execution unit and the wb to ensure that only one result is written back at a time.

[0055] In summary, in the branch prediction method provided in the embodiment of the present invention, the branch prediction result is obtained by indexing the historical branch prediction instruction in the branch prediction situation table, which can make good use of the correlation between the historical branch prediction instructions, thereby greatly improving the success rate of branch prediction. At the same time, the last four bits of the branch prediction instruction are logically operated with the value in the global history register to obtain an operation value and then indexed, which can reduce the impact of the alias of the branch prediction instruction on the branch prediction; at the same time, the branch prediction result is trusted only when the branch prediction result is a jump and the operation code of the branch prediction result matches the operation code of the indexed historical branch prediction instruction, thereby further improving the accuracy of branch prediction; and the jump address is obtained by direct operation, thereby saving the area overhead and delay caused by the BTB (branch target buffer) storing a large number of branch addresses.

[0056] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0057] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0058] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0059] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A branch prediction method, characterized in that: include: Fetching an instruction from an instruction cache module and pre-decoding it to determine whether the instruction is a branch prediction instruction; When the instruction is a branch prediction instruction, performing a logical operation on the last N bits of the PC address of the branch prediction instruction and a value in a global history register to obtain an operation value, wherein the global history register stores the most recent N branch jumps, where N ≥ 2; Using the operation value to index a historical branch prediction instruction in a branch prediction table to obtain a branch prediction result, wherein the branch prediction table is used to store a jump result and an operation code of the historical branch prediction instruction; When the branch prediction result is a jump and the operation code of the branch prediction result matches the operation code of the indexed historical branch prediction instruction, calculating a jump address and jumping; and, The branch prediction instruction is decoded and executed to verify whether the branch prediction result is accurate.

2. The branch prediction method according to claim 1, wherein: The instruction cache module adopts a fully associative design and uses a dedicated handshake signal to communicate directly with the main memory.

3. The branch prediction method according to claim 2, wherein: Each cache line of the instruction cache module has a valid bit and a count bit. The valid bit is used to indicate whether the corresponding cache line is valid. When a hit occurs in the instruction cache module, the count bit of the hit cache line is cleared, and the count bit of other valid cache lines is increased by 1.

4. The branch prediction method according to claim 3, wherein: When the instruction cache module is full, if a miss occurs in the instruction cache module, all the count bits are checked, the valid bit of the cache line with the largest count bit value is cleared to zero, and the cache line is replaced with the instruction retrieved from the main memory by the instruction cache module, and then the valid position of the cache line is set to 1.

5. The branch prediction method according to claim 1, wherein: The global history register has N storage bits, and the N storage bits record the most recent N branch jump situations in sequence. When the branch jump situation is a jump, the corresponding storage bit is 1, and when the branch jump situation is no jump, the corresponding storage bit is 0.

6. The branch prediction method according to claim 1, wherein: The jump result has two storage bits. When the jump result of the historical branch prediction instruction is a jump, the corresponding jump result is increased by one. When the jump result of the historical branch prediction instruction is not a jump, the corresponding jump result is decreased by one.

7. The branch prediction method according to claim 6, wherein: When the historical branch prediction instruction is indexed in the branch prediction status table using the operation value, the branch prediction instruction is decoded and executed, and then the indexed jump result and operation code are updated.

8. The branch prediction method according to claim 1, wherein: The logical operation is an exclusive OR operation, and the operation code is bits 13-15 of the branch prediction instruction.

9. The branch prediction method according to claim 1, wherein: After the branch prediction instruction is decoded, it is sent to the corresponding execution unit for execution, and each of the execution units is isolated from each other in communication.

10. The branch prediction method according to claim 9, wherein: After the branch prediction instruction is decoded, it is sent to the single execution unit with successful handshake for execution. Among all the execution units, only the execution unit with successful handshake is valid.

11. The branch prediction method according to claim 1, wherein: The jump address can be directly calculated from CAT, RAS, and branch instructions according to different instruction types.

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