Resource unified management method and system based on heterogeneous computing power

Abstract

The invention provides a resource unified management method and system based on heterogeneous computing power, and relates to the technical field of resource allocation of heterogeneous computing power. According to the method, operation instructions of different computing units are converted into bidirectional irreversible instruction sequences by constructing a heterogeneous presentation layer, and physical resources are abstracted to generate a virtual computing power unit. A multi-dimensional efficiency baseline is constructed based on parameters such as real-time load and network jitter tolerance, and a time-varying efficiency curve is dynamically generated in combination with a hardware aging rate. A user task is decomposed into sub-task chains, intelligent resource binding is realized by matching hardware sensitivity characteristics with an efficiency curve, and conflicts are solved by adopting reinforcement learning. And monitoring efficiency offset in real time during execution, performing reverse backtracking during abnormality, and generating a recombination strategy based on the alternative resource set. According to the system, efficient management and dynamic optimization of heterogeneous computing power resources are realized, and the computing efficiency and reliability are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of resource allocation for heterogeneous computing power, and specifically to a unified resource management method and system based on heterogeneous computing power. Background Art

[0002] In recent years, with the rapid development of heterogeneous computing architectures, diverse computing units such as CPUs, GPUs, and FPGAs have been widely integrated in cloud computing and edge computing scenarios. These heterogeneous computing resources exhibit significant differences in instruction sets, network topologies, and storage access, significantly increasing the complexity of unified resource management.

[0003] However, existing technologies still have core bottlenecks. When scheduling heterogeneous resource tasks, it is impossible to accurately quantify the impact of dynamic resource changes on task execution. When faced with resource conflicts or local anomalies, traditional methods rely on manually predefined rules or local optimization, and their real-time perception and adaptive adjustment capabilities of the global state are not strong. The resource allocation strategy is seriously out of touch with the dynamic needs of the actual environment. Summary of the Invention

[0004] To achieve the above objectives, the present invention is implemented through the following technical solutions: a unified resource management system based on heterogeneous computing power, comprising:

[0005] Heterogeneous representation layer module: This module analyzes the differences in the underlying instruction sets of heterogeneous computing resources and generates a heterogeneous representation layer. This layer converts the operation instructions of different computing units into a bidirectional, irreversible instruction sequence. It also performs logical abstraction on the network topology and storage access paths of physical resources and generates virtual computing units that carry interface protocol compatibility tags.

[0006] Multi-dimensional performance baseline construction module: Based on the real-time load of the virtual computing unit, network jitter tolerance, and storage media access latency, a multi-dimensional performance baseline is constructed, including compute-intensive weights and communication coupling coefficients. By correlating hardware aging rates with load mutations, the performance baseline is nonlinearly calibrated to generate dynamically updated time-varying performance curves and performance offsets.

[0007] Task decomposition and resource binding module: This module decomposes user-required tasks into chains of subtasks with data dependencies, extracts the hardware sensitivity characteristics of each subtask, matches these characteristics with the time-varying performance curve using an incremental evaluation algorithm, and generates a subtask-resource binding priority list. When binding conflicts are detected, it dynamically rearranges conflicting instructions or inserts isolation instructions based on reinforcement learning to generate an instruction-level resolution solution.

[0008] Resource allocation and exception handling module: performs initial resource allocation according to the subtask-resource binding priority list, and continuously monitors the performance offset of the virtual computing power unit during task execution; when the performance offset exceeds the preset fault tolerance threshold of its corresponding time-varying performance curve, it is determined to be a resource abnormal state, and the resource abnormal state is traced back along the subtask chain to the associated subtask, and a local resource reorganization strategy is generated based on the resource replacement candidate set and instruction isolation cost on the backtracking path.

[0009] In the process of building the heterogeneous representation layer, the underlying instruction sets of heterogeneous computing resources such as CPU, GPU, and FPGA are statically analyzed and dynamically tracked to extract feature differences such as opcodes, register addressing modes, and parallelism, and a differential feature set including instruction type, bit width, and throughput is constructed. Based on this set, a multimodal mapping matrix is used to map x86, ARM, CUDA, and other instructions to a unified instruction representation space to form the initial heterogeneous representation layer. The multimodal mapping matrix has an N×M dimension, where N is the number of heterogeneous computing unit types and M is the multimodal mapping matrix of instruction feature dimensions, and is obtained through training with historical instruction set simulation data. The mapped instructions are asymmetrically encrypted using the SM3 algorithm with a 256-bit hash length and a collision probability less than 2^-128. When generating a unique hash digest for each instruction, the computing unit hardware fingerprint, such as the last 4 bytes of the PCIe device ID, is used as a salt value to differentiate the hash outputs of the same instruction on different platforms. A collision detection mechanism is also designed. When a hash collision occurs, the instruction sequence is reconstructed by extending the hash chain and appending a timestamp and random number. The functional consistency of the simulated execution results with the original instructions is then verified. The resulting instruction sequence is both one-way generative and collision-resistant. For example, for the AVX512 instruction VPDPBUSD zmm1,zmm2,zmm3, the irreversible sequence 3A7F...E2C4#PCIe0A3D is generated after this processing, and the reverse deduction success rate is lower than the theoretical decryption threshold of 2^-256.

[0010] When analyzing the network topology of physical resources, the communication connection relationship and link transmission characteristics between network nodes are extracted to construct a network topology sequence, in which links with inter-node delays exceeding 5ms will be marked as inefficient paths; at the same time, the storage access path is parsed to obtain storage parameters including access delay and throughput, forming a storage access path feature sequence, and triggering a performance alarm when the access delay exceeds 50μs; through logical conversion, the nodes and links in the physical topology are mapped to the logical connection relationship between virtual computing units, and coordinated with the storage access characteristics to ensure that the performance fluctuation of the logical path is controlled within the allowable range of ±10%; by comparing the extracted interface protocol features with the protocol standard, the compatibility type is identified, and when the matching degree exceeds the preset threshold, the corresponding compatibility label is generated and added to the virtual computing unit to achieve unified scheduling and management of cross-platform resources.

[0011] In the process of building a multi-dimensional performance baseline, the real-time load data of the virtual computing unit is collected. When the CPU utilization reaches 75%, the system is marked as a high-load state; at the same time, the network jitter tolerance is monitored, and delay fluctuations exceeding 3 milliseconds are recorded as network anomalies. The storage medium access delay is detected, and 100 microseconds is set as the performance threshold; these data together constitute the basic performance data set; the correlation between the hardware aging rate and the load mutation is calculated using θ(t) = αL(t) + βdL / dt + γ∫L(τ)dτ, where the three weight coefficients α, β, and γ are taken as 0.55, 0.3, and 0.15 respectively, and floating adjustments within the range of ±0.05 are allowed; these coefficients are determined by analyzing historical load data using the least squares fitting method; the real-time load level L(t) is processed by a sliding average filter with a 60-second window to ensure Data stability; the nonlinear regression analysis process uses a quadratic polynomial, and its coefficients are dynamically adjusted by continuously learning the latest 100 sets of performance baseline data. It is considered valid only when the goodness of fit is greater than 0.85; time series analysis generates a time-varying performance curve based on the weighted moving average method, assigning a weight of 0.6 to recent data, a weight of 0.3 to mid-term data, and a weight of 0.1 to long-term data; the performance offset is determined by calculating the relative deviation between the predicted value and the actual value. When the deviation exceeds the fault tolerance threshold of 10% for three sampling cycles, the system triggers the recalculation process of the communication coupling coefficient; the value range of the communication coupling coefficient is limited to between 0.1 and 0.9; all parameter thresholds are set based on the numerical values of historical data, and are continuously dynamically optimized using the latest 300 sets of sample data to keep its performance evaluation indicators always in the optimal state.

[0012] When the heterogeneous representation layer parses the subtask chain, it quantifies the instruction set dependency index of each subtask on the computing unit by comparing the difference in the operation instructions and the instruction characteristics of the virtual computing unit. The value range of this index is 0 to 1. When the dependency exceeds 0.7, it is determined to be a strong binding relationship. At the same time, combined with the computationally intensive weights in the performance baseline, the communication path characteristics of the subtask in the logical network topology are analyzed. If the communication delay sensitivity of the subtask exceeds 50 microseconds or the bandwidth requirement exceeds 10Gbps, it is marked as a highly sensitive communication subtask. The instruction set dependency and communication sensitivity characteristics are fused into a hardware sensitivity feature vector, which contains normalized parameters of two dimensions and synchronizes the dynamic evaluation parameters in the time-varying performance curve in real time. Based on This constructs the state space of reinforcement learning, where state parameters include the hardware sensitivity differences of conflicting instructions and the performance offsets of associated subtasks; the action space is designed to be divided into two basic operations: dynamic reordering operations and protocol-compatible isolation instruction insertion, where the isolation instruction types strictly match the constraints defined by the interface protocol compatibility label; the immediate reward function of reinforcement learning is calculated using the relative error between the predicted value and the actual value of the time-varying performance curve, and a positive reward is given when the error is less than 5%; when it is detected that the performance offset continues to exceed the fault tolerance threshold of 15%, for example, if the matrix operation performance of a GPU computing unit drops by 18% due to hardware aging, an alternative FPGA unit with a communication coupling coefficient less than 0.3 is preferentially selected for resource reorganization.

[0013] When the performance offset exceeds the preset fault tolerance threshold, for example, the fault tolerance threshold is set to a 20% extension of the average response time or a 15% increase in the error rate, based on the data dependency description information pre-stored in the subtask chain, starting from the subtask node where the exception occurs, backtrack step by step along the data upstream direction, and at the same time refer to the mapping records between the virtual computing power unit and each subtask, and reversely transfer the resource abnormal state to the subtask associated with the abnormal resource until the affected initial subtask is located; in the backtracking process, screen the resources in the virtual computing power unit that match the compatibility label of the abnormal resource interface protocol and whose current load is lower than the preset threshold to form a list of candidate replacement resources, and perform a preliminary performance evaluation on each candidate resource, and select the resource with the highest performance score as the replacement object; for each subtask and candidate replacement object on the backtracking path, according to the hardware of the subtask The sensitivity characteristics and efficiency parameters of alternative resources are combined with the data dependencies in the subtask chain to calculate the performance loss and resource overhead under different alternative schemes, obtain the instruction isolation cost, and generate a local resource reorganization strategy. The quantification of the instruction isolation cost comprehensively considers indicators such as clock cycle delay, cache hit rate, and power consumption increment, and is obtained through weighted summation. The weight coefficient is determined based on historical data and experimental results. For example, for high-frequency trading systems, the weight of clock cycle delay is set to 0.6, the weight of cache hit rate is 0.3, and the weight of power consumption increment is 0.1. When screening the candidate set of alternative resources, the interface protocol compatibility label is dynamically adjusted through the protocol priority table, and resources with higher protocol versions and faster transmission rates are given priority. For example, when there are multiple resources with matching compatibility labels, resources that support the PCIe 5.0 protocol are given priority. The specific numerical range of the load threshold is dynamically adjusted according to the real-time load of the system and is set to 80% to 90% of the current system average load to ensure that the candidate resources have sufficient processing power.

[0014] The present invention provides a resource unified management method and system based on heterogeneous computing power, which has the following features:

[0015] Beneficial effects:

[0016] 1. The present invention converts the underlying instruction set differences of different computing units into bidirectional irreversible instruction sequences by constructing a heterogeneous representation layer, and generates virtual computing power units with interface protocol compatibility tags; it significantly improves the unified management efficiency of heterogeneous computing power resources, solves the compatibility problems caused by instruction set differences in traditional methods, and realizes the seamless integration of hardware resources.

[0017] 2. The present invention constructs a multi-dimensional performance baseline and generates a dynamically updated time-varying performance curve through nonlinear calibration. It uses principal component analysis to dynamically adjust weights and combines reinforcement learning to dynamically rearrange or isolate conflicting instructions, significantly improving the accuracy and robustness of computing resource allocation and optimizing the execution efficiency of computationally intensive tasks.

[0018] 3. The present invention proposes a mechanism for reverse tracing along the subtask chain, combining interface protocol compatibility labels and performance pre-assessment to generate a local resource reorganization strategy; by quantifying the instruction isolation cost and the performance score of alternative resources, it ensures that the reorganization process minimizes performance loss and improves the system's resource allocation. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0020] When building a unified resource management system based on heterogeneous computing power, it is necessary to extract instruction set features from various heterogeneous computing units in the target computing environment. For example, the vectorization features of the AVX-512 instruction set are extracted for the Intel Xeon Platinum 8380 processor, the parallel thread execution features of the CUDA Core are extracted for the NVIDIA A100 GPU, and the parallel thread execution features of the Xilinx Alveo U280 are extracted. The FPGA extracts opcode features from the hardware description language. The feature extraction process requires a combination of static analysis and dynamic tracing, using instrumentation to capture the actual behavioral characteristics of the runtime instruction pipeline. After storing the extracted features in a differential feature set, a multimodal mapping matrix is constructed for instruction space conversion. The matrix dimension is set to N×M, where N is the number of computing unit types and M is the number of instruction feature dimensions. For example, in implementation, when the environment contains three computing units and five feature dimensions are extracted, a 3×5 real number matrix is constructed. The matrix parameters are obtained through training with historical instruction set simulation data. The mean square error loss function and Adam optimizer are used during training, and the learning rate is set to 0.001. The SM3 algorithm is used for processing during instruction conversion, with a fixed hash length of 256 bits and a salt value taken from the last 4 bytes of the PCIe device ID. During implementation, special attention must be paid to the design of the hash conflict handling mechanism. When a collision is detected, the hash chain should be automatically extended, and a nanosecond timestamp and a 32-bit random number should be appended to reconstruct the instruction sequence. Functional consistency verification should be used to ensure that the converted instruction sequence is semantically equivalent to the original instruction.

[0021] The physical resource abstraction stage requires synchronous processing of network topology and storage access paths. During implementation, distributed probes must be deployed to collect real-time communication data between network nodes. When the inter-node delay exceeds 5 milliseconds, the link is marked as an inefficient path in the topology sequence. Storage access path analysis must be combined with the performance characteristics of NVMe SSDs, setting the access delay threshold to 50 microseconds and the throughput threshold to 3GB / s. The logical abstraction process requires establishing a mapping relationship between physical resources and virtual computing units. For example, a physical server node with a 32-core CPU, 16GB of HBM2 video memory, and 200Gbps of network bandwidth can be abstracted into a virtual computing unit with a computing power index of 85 and a storage bandwidth index of 90. The generation of interface protocol compatibility labels requires an automated matching algorithm. When it is detected that the resource supports the PCIe 4.0x16 interface and the bandwidth reaches 64GB / s, the PCIe_4.0_High_Bandwidth label is automatically attached.

[0022] The implementation of the multi-dimensional performance baseline building module requires the deployment of a multi-dimensional data collection system; real-time load data collection requires setting the sampling interval to 500 milliseconds, and triggering the high load status flag when the CPU utilization exceeds 75% for three consecutive sampling cycles; network jitter tolerance monitoring requires calculating the average delay fluctuation of the last 100 network packets, and recording a network abnormality event when the standard deviation exceeds 3 milliseconds; storage media access delay monitoring requires distinguishing between sequential read and write and random read and write modes, setting thresholds of 70 microseconds and 120 microseconds respectively; the correlation between hardware aging rate and load mutation adopts θ(t) = 0.55L(t) + 0.3 The load level L(t) is calculated using the sliding average filter of a 60-second window, dL / dt, and dL / dt+0.15∫L(τ)dτ. The differential term dL / dt is calculated using the central difference method, and the integral term ∫L(τ)dτ is numerically integrated using the trapezoidal rule. The nonlinear calibration process uses a quadratic polynomial regression model with a goodness of fit of no less than 0.85 and is updated every 30 minutes. The time-varying performance curve is generated using a weighted moving average algorithm, with a weight of 0.6 for recent data, 0.3 for mid-term data, and 0.1 for long-term data. The performance offset is determined by calculating the relative deviation between the predicted value and the actual value.

[0023] The implementation of the task decomposition and resource binding module requires the design of a task parser. When receiving a deep learning training task submitted by a user, the task parser decomposes it into six subtasks: data loading, data augmentation, forward propagation, loss calculation, backpropagation, and parameter update. Hardware sensitivity feature extraction requires quantifying the computational characteristics of each subtask. For example, the instruction set dependency score of the forward propagation subtask is 0.85, and the communication coupling coefficient is 0.45. The incremental evaluation algorithm uses a sliding window mechanism, with the window size set to the data of the most recent 20 evaluation cycles. When two subtasks are detected to request the same GPU resource simultaneously and the hardware sensitivity difference is less than 0.2, the binding conflict handling process is triggered. The reinforcement learning model adopts the DQN architecture. The state space contains three dimensions: the hardware sensitivity difference of the conflicting instructions, the performance offset of the associated subtasks, and the real-time load data of the virtual computing power unit. The action space includes two types of operations: instruction reordering and isolation insertion. The reward function is designed to be R = 1-|Δ| / Δ_max, where Δ is the actual performance offset and Δ_max is the maximum allowable offset.

[0024] The resource allocation and exception handling module needs to implement a real-time monitoring system for performance offset; the monitoring period is set to 1 second, and when it is detected that the matrix multiplication performance offset of the FPGA computing unit exceeds 15% three times in a row, the exception handling process is triggered; reverse backtracking needs to perform a depth-first search along the subtask dependency graph, and the backtracking depth is limited to 5 layers; the screening conditions for the alternative resource candidate set include interface protocol compatibility label matching exceeding 90%, current load rate less than 70%, and communication coupling coefficient less than 0.4; performance pre-assessment input features include the computing power index, storage bandwidth index and network delay index of the alternative resource, and the output is a performance score from 0 to 100; instruction isolation cost calculation requires the integration of three indicators: clock cycle delay increment, cache hit rate reduction and power consumption increase, with weights set to 0.6, 0.3 and 0.1 respectively; after the local resource reorganization strategy is generated, the effectiveness of the strategy is verified in a simulation environment, requiring that the execution time deviation of the reorganized task does not exceed 5% of the original plan and the power consumption increase does not exceed 10%.

[0025] For example, in an application scenario, when the system processes the real-time inference task of the autonomous driving perception system, the heterogeneous representation layer successfully converts the CPU's SIMD instructions, the GPU's Tensor Core instructions, and the FPGA's customized IP core instructions into a standard intermediate representation; the multi-dimensional performance baseline accurately predicts the increase in computing delay caused by long-term operation of the FPGA unit, and promptly migrates the convolution calculation subtask to the spare GPU unit for execution; the task decomposition module rationally divides the perception task into three subtasks: image decoding, feature extraction, and target detection, and dynamically adjusts the execution order of the feature extraction subtask through the reinforcement learning model to avoid storage bandwidth competition; after detecting the data transmission delay caused by network jitter, the exception handling module completes the reconstruction of the computing path in only 200 milliseconds, ensuring that the overall system response time is stable within 50 milliseconds; it realizes efficient management and dynamic optimization of heterogeneous computing resources, significantly improving computing efficiency and reliability.

[0026] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A unified resource management method based on heterogeneous computing power, characterized by: The following steps are involved: S1. Analyze the differences in the underlying instruction sets of heterogeneous computing resources and generate a heterogeneous representation layer. This heterogeneous representation layer converts the operation instructions of different computing units into a bidirectional, irreversible instruction sequence. It also logically abstracts the network topology and storage access paths of physical resources to generate virtual computing units with interface protocol compatibility tags. S2. Based on the real-time load of the virtual computing units, network jitter tolerance, and storage media access latency, a multi-dimensional performance baseline is constructed, including compute-intensive weights and communication coupling coefficients. By correlating hardware aging rates with load mutations, the performance baseline is nonlinearly calibrated to generate dynamically updated time-varying performance curves and performance offsets. S3. Decompose the user-required task into a chain of subtasks with data dependencies, extract the hardware sensitivity characteristics of each subtask, match the hardware sensitivity characteristics with the time-varying performance curve using an incremental evaluation algorithm, and generate a subtask-resource binding priority list. When a binding conflict is detected, dynamically reorder the conflicting instructions or insert isolation instructions based on reinforcement learning to generate an instruction-level resolution solution. S4. Perform initial resource allocation according to the subtask-resource binding priority list, and continuously monitor the performance offset of the virtual computing power unit during task execution; when the performance offset exceeds the preset fault tolerance threshold of its corresponding time-varying performance curve, it is determined to be a resource abnormality state, and the resource abnormality state is traced back along the subtask chain to the associated subtask, and a local resource reorganization strategy is generated based on the resource replacement candidate set and instruction isolation cost on the backtracking path.

2. The method for unified resource management based on heterogeneous computing power according to claim 1, characterized in that: In the step S1, the underlying instruction sets of various heterogeneous computing resources are analyzed and identified, and the feature differences of the operation instructions of different computing units are extracted to construct a difference feature set; based on The differential feature set maps the operation instructions of different computing units to an instruction representation space through a multimodal mapping matrix to form an initial heterogeneous representation layer; the mapped instructions are processed using an asymmetric encryption hash algorithm, so that the instruction sequence can only be generated in one direction during the conversion process, and the original instructions cannot be reversely deduced through the output, resulting in a bidirectional and irreversible instruction sequence corresponding to the heterogeneous representation layer.

3. The method for unified resource management based on heterogeneous computing power according to claim 1, characterized in that: In the step S1, the network topology of the physical resources is analyzed, network node and link information is extracted, and a network topology sequence is constructed; the storage access path is parsed, storage parameters are extracted, and a storage access path feature sequence is formed; Based on the network topology sequence and the storage access path feature sequence, the node and link information in the network topology sequence is logically converted to form logical nodes and logical links, and a logical network topology structure is constructed; Logically mapping the parameters in the storage access path feature sequence to form a logical storage access path; Align the logical network topology and the logical storage access path to generate an abstracted resource model; extract interface protocol information from the resource model and construct an interface protocol feature set; The extracted interface protocol feature set is compared with the protocol standard to identify the interface protocol type supported by the resource model; the corresponding interface protocol compatibility label is selected based on the identification result; the selected interface protocol compatibility label is added to the virtual computing power unit to obtain a virtual computing power unit carrying the interface protocol compatibility label.

4. The method for unified resource management based on heterogeneous computing power according to claim 1, characterized in that: In the step S2, the real-time load data, network jitter tolerance and storage medium access delay of the virtual computing power unit are collected to construct a basic performance data set; the basic performance data set is nonlinearly transformed through the correlation between the hardware aging rate and the load mutation to generate dynamic performance evaluation parameters; the initial allocation strategy of the computing-intensive weight is matrix-fused with the calculated value of the communication coupling coefficient, where the communication coupling coefficient is obtained by analyzing the data transmission mode between the virtual computing power units; the formed multi-dimensional performance baseline is dynamically weighted to the parameters of each dimension through the principal component analysis method.

5. The method for unified resource management based on heterogeneous computing power according to claim 4, characterized in that: The correlation between hardware aging rate and load mutation is θ(t) = αL(t) + βdL / dt + γ∫L(τ)dτ, where α, β, and γ are weight coefficients, L(t) is the real-time load level, dL / dt refers to the rate of change of the load level L with time t, and ∫L(τ)dτ is the long-term load level. Nonlinear regression analysis is used to calibrate the multidimensional performance baseline. Through training with historical data, the parameters of the performance baseline are dynamically adjusted according to the real-time hardware aging rate and load mutation. Based on the calibrated performance baseline, time series analysis is used to generate a time-varying performance curve, where the time-varying performance curve is used to quantify the performance of the virtual computing power unit at different time points. The performance offset is calculated as the difference between the current performance value and the predicted performance value.

6. The method for unified resource management based on heterogeneous computing power according to claim 1, characterized in that: In step S3, the instruction sequence conversion relationship in the subtask chain is analyzed, and the instruction set dependencies of the subtasks on different computing units are identified by combining the differences in the operation instruction characteristics of the virtual computing units. Based on the computationally intensive weights in the performance baseline, the communication path characteristics of the subtasks in the logical network topology are analyzed to quantify their sensitivity to network jitter tolerance. A hardware sensitivity feature including instruction set dependency and communication sensitivity is generated, and the hardware sensitivity feature is updated synchronously with the dynamic performance evaluation parameters in the time-varying performance curve.

7. The method for unified resource management based on heterogeneous computing power according to claim 6, characterized in that: The process of resolving the subtask-resource binding conflict includes: constructing a state space of reinforcement learning based on the performance offset and hardware sensitivity characteristics, wherein the state parameters include the hardware sensitivity difference of the current conflicting instruction, the performance offset of the associated subtask, and the real-time load data of the virtual computing unit; inserting dynamic reordering operations and isolation instructions as the action space, wherein the type of isolation instruction is determined according to the interface protocol compatibility label; using the deviation between the predicted value of the time-varying performance curve and the actual execution performance as an immediate reward, driving reinforcement learning to optimize the instruction-level resolution solution; when the performance offset exceeds a preset fault tolerance threshold, preferentially selecting an alternative virtual computing unit with the smallest communication coupling coefficient for resource reorganization, and updating the state space of reinforcement learning at the same time.

8. The method for unified resource management based on heterogeneous computing power according to claim 1, characterized in that: In step S4, when the performance offset exceeds a preset fault tolerance threshold, based on the data dependency description information pre-stored in the subtask chain, starting from the subtask node where the exception occurred, the data is traced back step by step along the upstream direction of the data flow, and at the same time, referring to the mapping record between the virtual computing power unit and each subtask, the resource abnormality status is reversely transmitted to the upstream subtasks associated with the abnormal resource until the affected initial subtask is located; During the backtracking process, resources in the virtual computing power unit that match the compatibility label of the abnormal resource interface protocol and whose current load is lower than the preset threshold are screened to form a list of candidate replacement resources. The performance of each candidate resource is pre-evaluated, and the resource with the highest performance score is selected as the replacement object; for each subtask and candidate replacement object on the backtracking path, according to the hardware sensitivity characteristics of the subtask and the performance parameters of the replacement resource, combined with the data dependency in the subtask chain, the performance loss and resource overhead under different replacement schemes are calculated to obtain the instruction isolation cost and generate a local resource reorganization strategy.

9. A system for unified resource management based on heterogeneous computing power according to any one of claims 1 to 7, characterized in that: include: Heterogeneous representation layer module: Analyzes the differences in the underlying instruction sets of heterogeneous computing resources and generates a heterogeneous representation layer; The heterogeneous representation layer converts the operation instructions of different computing units into bidirectional irreversible instruction sequences; performs logical abstraction on the network topology and storage access path of physical resources, and generates virtual computing units carrying interface protocol compatibility tags; Multi-dimensional performance baseline construction module: Based on the real-time load of the virtual computing unit, network jitter tolerance, and storage media access latency, a multi-dimensional performance baseline is constructed, including compute-intensive weights and communication coupling coefficients. By correlating hardware aging rates with load mutations, the performance baseline is nonlinearly calibrated to generate dynamically updated time-varying performance curves and performance offsets. Task decomposition and resource binding module: This module decomposes user-required tasks into subtask chains with data dependencies, extracts the hardware sensitivity characteristics of each subtask, matches the hardware sensitivity characteristics with the time-varying performance curve using an incremental evaluation algorithm, and generates a subtask-resource binding priority list. When binding conflicts are detected, it dynamically rearranges conflicting instructions or inserts isolation instructions based on reinforcement learning to generate an instruction-level resolution solution. Resource allocation and exception handling module: performs initial resource allocation according to the subtask-resource binding priority list, and continuously monitors the performance offset of the virtual computing power unit during task execution; when the performance offset exceeds the preset fault tolerance threshold of its corresponding time-varying performance curve, it is determined to be a resource abnormal state, and the resource abnormal state is traced back along the subtask chain to the associated subtask, and a local resource reorganization strategy is generated based on the resource replacement candidate set and instruction isolation cost on the backtracking path.