Memory controller performance monitoring system and monitoring method based on DFI interface
Through the memory controller performance monitoring system based on the DFI interface, the problem of difficulty in evaluating the performance of the memory controller by the AXI interface is solved, and the accurate evaluation and optimization design of the performance of the memory controller is achieved.
Patent Information
- Application Number
- CN202510633623.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-16
- Publication Date
- 2025-08-19
AI Technical Summary
There are difficulties in the prior art to evaluate the performance of memory controllers through the AXI interface, and it is impossible to accurately analyze the imitation characteristics and imitation strategies.
The memory controller performance monitoring system based on the DFI interface is adopted, including the memory controller monitoring unit MCMU, the memory controller monitoring controller unit MCMCR and the monitoring software. By monitoring the write signals and read signals and related transaction information of the DFI interface, it is stored in the register group and analyzed and processed by the monitoring software.
Real-time monitoring of memory controller performance and optimization of memory access strategies is realized, improving the accuracy of performance evaluation and design optimization effect.
Smart Images
Figure CN120508472A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory, and more particularly to a memory controller performance monitoring system and monitoring method based on a DFI interface. Background Art
[0002] DDR (Double Data Rate) is a high-performance memory standard based on SDRAM (Synchronous Dynamic Random Access Memory) technology. Its core feature is that it transmits data twice per clock cycle (once on the rising edge and once on the falling edge), significantly increasing bandwidth. It has become a core memory technology for modern computers, servers, consumer electronics, and other fields.
[0003] DFI (DDRPHY Interface) is an interface protocol developed by several semiconductor giants, such as Intel, ARM, and Synopsys. It is a standardized interface connecting the memory controller and the physical layer (PHY). It can transmit the signals, timing parameters, and programmable parameters required for control information and data transmission. The programmable parameters are programmed into the MC and PHY based on options defined by the MC, PHY, or the system. The DFI interface protocol is applicable to DDR4, DDR3, DDR2, DDR1, LPDDR3, LPDDR2, and LPDDR1 DRAMs.
[0004] The DFI interface can be divided into five interface groups: Control Interface Group, Write Data Interface Group, Read Data Interface Group, Update Interface Group, and Status Interface Group.
[0005] As more and more host devices require memory for large data caches, bandwidth requirements vary across different application scenarios. Currently, most memory controllers use the AXI protocol interface for data exchange. Memory controller performance can be analyzed by monitoring the AXI interface. However, the AXI bus's out-of-order (OOO) transmission mechanism, outstanding transaction (OT) transmission mechanism, and interleaving make it difficult to evaluate memory controller performance and analyze emulation characteristics and strategies. Summary of the Invention
[0006] Aiming at the problem that it is difficult to evaluate the performance of a memory controller through an AXI interface in the prior art, the present invention provides a memory controller performance monitoring system and a monitoring method based on a DFI interface.
[0007] According to a first aspect of the present invention, a memory controller performance monitoring system based on a DFI interface is provided, wherein the memory controller exchanges data with a memory through the DFI interface, and is characterized in that the memory controller performance monitoring system includes a memory controller monitoring unit MCMU, a memory controller monitoring controller unit MCMCR, and monitoring software, wherein the memory controller monitoring unit MCMU includes a write transaction monitoring module WTM and a read transaction monitoring module RTM;
[0008] The write transaction monitoring module WTM is used to monitor the write signal and write-related transaction information of the DFI interface of the memory controller;
[0009] The read transaction monitoring module RTM is used to monitor the read signal and read-related transaction information of the DFI interface of the memory controller;
[0010] The memory controller monitoring unit MCMU is used to encapsulate the write transaction monitoring module and the read transaction monitoring module, and send the acquired write signal, read signal and various transaction information of the DFI interface to the memory controller monitoring controller unit MCMCR;
[0011] The memory controller monitoring controller unit MCMCR is used to control the working state of the memory controller monitoring unit MCMU and store various types of monitored transaction information in a register group, wherein the register group includes multiple registers, and each type of transaction information is stored in one register;
[0012] The monitoring software is used to read various types of transaction information in the register group in a round-robin manner, analyze and process the various types of transaction information, and obtain the performance of the memory controller.
[0013] According to a second aspect of the present invention, a method for monitoring memory controller performance based on a DFI interface is provided, comprising:
[0014] After the memory controller is initialized, it automatically enables the work when the first transaction of the memory controller comes, captures the transaction information of the DFI interface of the memory controller, and counts all transaction information of the DFI interface of the memory controller at preset time intervals;
[0015] Updating all captured transaction information of the memory controller to a related transaction register group of the memory controller;
[0016] The monitoring software reads the relevant transaction register group of the memory controller, reads all transaction information in the register group, analyzes and processes all transaction information, and obtains the performance of the memory controller.
[0017] The present invention provides a memory controller performance monitoring system and monitoring method based on the DFI interface. The system monitors the memory controller in real time through the DFI interface to evaluate the performance of the memory controller. The system can also monitor the memory controller's memory access strategy and optimize the memory controller design based on the memory access strategy. This solves the problem of inaccurate performance evaluation of the memory controller by monitoring the AXI interface in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 A structural block diagram of a memory controller performance monitoring system based on a DFI interface provided by an embodiment of the present invention;
[0019] Figure 2 This is a schematic diagram of the structure of the bank in the memory;
[0020] Figure 3 A flowchart of a method for monitoring memory controller performance based on a DFI interface provided by an embodiment of the present invention;
[0021] Figure 4 This is a flow chart of monitoring transaction information of a memory controller DFI port according to an embodiment of the present invention;
[0022] Figure 5 A schematic diagram of the state transition diagram of the memory controller monitoring unit MCMU;
[0023] Figure 6-1 This is the timing diagram of the write signal on the DFI port;
[0024] Figure 6-2 This is the timing diagram of the read signal on the DFI port. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0026] The memory controller exchanges data with the outside world via the AXI interface protocol and with the internal memory via the DFI interface. The present invention analyzes the performance of the memory controller by monitoring its DFI interface, including analyzing its memory access characteristics and data flow.
[0027] Figure 1 The embodiment of the present invention provides a memory controller performance monitoring system based on the DFI interface, wherein the memory controller exchanges data with the memory through the DFI interface. Figure 1 The memory controller performance monitoring system includes a write transaction monitoring module WTM, a read transaction monitoring module RTM, a memory controller monitoring unit MCMU, a memory controller monitoring controller unit MCMCR, and monitoring software. The write transaction monitoring module WTM and the read transaction monitoring module RTM are located in the memory controller monitoring unit MCMU.
[0028] It is understandable that existing solutions typically monitor memory controller performance by monitoring the AXI protocol interface. Since the AXI protocol interface is the communication interface between the memory controller and the outside world, monitoring the AXI interface cannot monitor the internal performance of the memory controller, such as monitoring the memory controller's memory access characteristics and data flow. Since the DFI interface is the communication interface between the memory controller and internal memory, embodiments of the present invention monitor the internal performance of the memory controller by monitoring the DFI interface.
[0029] Specifically, the embodiment of the present invention designs a memory controller performance monitoring system based on the DFI interface, wherein the working principles of each module are as follows:
[0030] The write transaction monitoring module WTM is used to monitor the write signal and write-related transaction information of the DFI interface of the memory controller;
[0031] The read transaction monitoring module RTM is used to monitor the read signal and read-related transaction information of the DFI interface of the memory controller;
[0032] The memory controller monitoring unit MCMU is used to encapsulate the write transaction monitoring module and the read transaction monitoring module, and send the acquired write signal, read signal and various transaction information of the DFI interface to the memory controller monitoring controller unit MCMCR;
[0033] The memory controller monitoring controller unit MCMCR is used to control the working state of the memory controller monitoring unit MCMU and store various types of monitored transaction information in a register group, wherein the register group includes multiple registers, and each type of transaction information is stored in one register;
[0034] The monitoring software is used to read various types of transaction information in the register group in a round-robin manner, analyze and process the various types of transaction information, and obtain the performance of the memory controller.
[0035] It is understandable that the write transaction monitoring module in the memory controller performance monitoring system mainly monitors the write signal and related transaction information of the DFI interface of the memory controller, while the read transaction monitoring module mainly monitors the read signal and related transaction information of the DFI interface of the memory controller.
[0036] The memory controller monitoring unit (MCMU) is primarily responsible for monitoring the signals and related transaction information of the memory controller's DFI interface. It sends the memory controller's DFI interface write and read signals, as well as related transaction information, to the memory controller monitoring unit (MCMCCR). The memory controller monitoring unit (MCMCCR) stores the DFI interface related transaction information in a register group.
[0037] The monitoring software periodically obtains various transaction information related to the DFI interface from the register group, analyzes and processes the various transaction information related to the monitored DFI interface, and monitors the performance of the memory controller.
[0038] In one embodiment of the present invention, the memory controller monitoring unit MCMU includes a Bypass transaction counter, a HIF transaction counter, a CAM transaction counter, a Power Saving transaction counter, and a DFI transaction counter.
[0039] When a read command or an activate command sent to a memory from the memory controller needs to pass through the Bypass path, the Bypass transaction counter starts counting.
[0040] When a read command, write command, activate command, etc. sent to the memory from the memory controller passes through the CAM, the CAM transaction counter starts counting.
[0041] When the memory controller sends a read command, a write command, a read-modify-write command, or a high-priority read command to the DDRC, the HIF transaction counter starts counting.
[0042] When the memory controller enters self-refresh mode, powerdown mode, deeppowerdown mode, or maximumpowersaving mode, the Power Saving transaction counter starts counting.
[0043] See also Figure 2 , is a schematic diagram of the structure of a bank in a memory, wherein the memory includes multiple groups of banks (bankgroups), each bank group includes multiple banks, and each bank stores byte data (bit data) in a row and column array.
[0044] When the memory controller performs read and write transactions to the memory through the DFI port, the DFI transaction counter monitors the address information of the memory controller accessing the memory bank. This includes the address information of the memory controller accessing the bank in each bank group, the address information of the same bank in different bank groups, the address information of the bit data in different rows of the same bank, and the address information of the bit data in the same row of the same bank.
[0045] It is understandable that the memory controller monitoring unit MCMU includes multiple transaction counters that can be used to collect statistics on different transaction information of the DFI interface, mainly including statistics on Bypass transaction information, HIF transaction information, CAM transaction information, PowerSaving transaction information and DFI transaction information.
[0046] The memory controller monitoring unit MCMU sends monitored Bypass transaction information, HIF transaction information, CAM transaction information, Power Saving transaction information, and DFI transaction information to the memory controller monitoring controller unit MCMCR. The memory controller monitoring controller unit MCMCR stores the Bypass transaction information, HIF transaction information, CAM transaction information, Power Saving transaction information, and DFI transaction information in respective registers in the register, with one type of transaction being stored in one register.
[0047] If multiple memory controllers need to be monitored, multiple monitoring systems are required, and the transaction information of each memory controller is stored in a corresponding register group.
[0048] See also Figure 3 The present invention provides a memory controller performance monitoring method based on a DFI interface, comprising the following steps:
[0049] Step 1: After the memory controller is initialized, it is automatically enabled when the first transaction of the memory controller arrives, the transaction information of the DFI interface of the memory controller is captured, and all transaction information of the DFI interface of the memory controller is counted every preset time.
[0050] Step 2: updating all captured transaction information of the memory controller to a related transaction register group of the memory controller;
[0051] Step 3: The monitoring software reads the relevant transaction register group of the memory controller, reads all transaction information in the register group, analyzes and processes all transaction information, and obtains the performance of the memory controller.
[0052] Among them, see Figure 4 , is a flowchart of the specific monitoring process of the memory controller monitoring system, that is, a specific flowchart of the above step 1 for counting all transaction information of the DFI interface of the memory controller. Step 1 mainly includes the following steps:
[0053] Step 11, after the memory controller is initialized, the memory controller monitoring controller unit MCMCR controls the working state of the memory controller monitoring unit MCMU. If the memory controller monitoring unit MCMU does not need to be turned on (i.e., the performance of the memory controller does not need to be monitored), the memory controller monitoring controller unit MCMCR turns off its clock signal by changing the clock enable register value;
[0054] Step 12: Enable the clock to change the statistical time register value as needed. If no change is required, use the default statistical time register value. The statistical time register value indicates the time period for statistical monitoring of various transaction information of the DFI interface.
[0055] Step 13: When the first transaction of the memory controller arrives, the memory controller monitoring unit MCMU automatically starts to count all transaction information of the DFI interface of the memory controller;
[0056] Step 14: When the statistical time reaches the statistical time register value, all statistical transaction information is output to the register group; wherein, during the monitoring period, the memory controller monitoring unit MCMU can be selected to stop statistics as needed.
[0057] See also Figure 5 , describes the state transition diagram of the memory controller monitoring unit MCMU, and the specific process of generating transaction information in step S13 is as follows:
[0058] Step 131: After the memory controller monitoring unit MCMU is enabled, its state machine jumps from the idle state to the counting state, and each transaction information counter starts counting;
[0059] Step 132: When each transaction signal of the memory controller DFI interface is valid, the corresponding transaction counter is incremented by one; if not, the counter remains unchanged.
[0060] Step 133: When a read command or an activate command sent to the memory by the memory controller needs to pass through the Bypass path, the Bypass transaction counter counts the number of transactions respectively.
[0061] Step 134 , when a read command, a write command, an activate command, etc. sent to the memory from the memory controller passes through the CAM, the CAM transaction counter starts counting respectively;
[0062] Step 135 , when a read command, a write command, a read-modify-write command, and a high-priority read command are sent from the memory controller to the DDRC, the HIF transaction counters start counting respectively;
[0063] Step 136: When the memory controller enters the self-refresh mode, powerdown mode, deep powerdown mode, or maximum power saving mode, its active signal is monitored by the power saving transaction counter, and a counting operation is performed to obtain the number of times the memory controller enters other modes during the counting cycle;
[0064] Step 137, when the memory controller performs read and write transactions, the DFI transaction counter can monitor the number of different bank group numbers, the number of different bank numbers, the number of different rows with the same bank number, and the number of the same row with the same bank number during the emulation process, and use the DFI write valid signal using a three-stage pipeline adder design to achieve the number of write transfer bytes within the statistical time, and use the DFI read valid signal to achieve the number of read transfer bytes within the statistical time, thereby obtaining the memory controller bandwidth utilization.
[0065] Step 138 , after the memory controller monitoring unit MCMU statistical time ends, its state machine jumps from the counting state to the recording state, the software reads and updates the register group, and then enters the initial state.
[0066] in, Figure 6-1 and Figure 6-2Describes the specific statistical timing diagram of bandwidth utilization in step 137, Figure 6-1 This is the write signal timing diagram of the DFI interface. Figure 6-2 This is the DFI interface read signal timing diagram. The DFI CLK to MEMCLK (memory clock frequency) frequency ratio is 1:2. The DRAM transmits data on both rising and falling clock edges, resulting in a 4:1 data bit width ratio between the DFI interface and the DRAM. In fact, the data bit width of a single phase of the DFI interface is twice that of a single phase of the DRAM. At a 1:2 frequency ratio, the DFI interface data and data valid signals are transmitted to the PHY over two phases (P0 / P1) to complete data transmission.
[0067] In this embodiment of the present invention, the P0 phase valid signal, the P1 phase valid signal, and the mask signal of the DFI interface write data are captured to analyze the number of cycles and bytes of the memory controller write data, thereby analyzing the write utilization and bandwidth utilization of the memory controller. Similarly, the w0 phase valid signal, the w1 phase valid signal, and the mask signal of the DFI interface read data are captured to analyze the number of cycles and bytes of the memory controller read data, thereby analyzing the read utilization and bandwidth utilization of the memory controller.
[0068] The embodiments of the present invention provide a memory controller performance monitoring system and method based on a DFI interface, which have the following beneficial effects:
[0069] (1) Introducing various transaction activity signals of the memory controller DFI interface into a monitoring system: When the first read / write transaction of the memory controller DFI interface comes, the read / write channel of the memory controller starts to work, and captures various related transaction information of the memory controller, including bypass transaction information, CAM transaction information, HIF transaction information, Power Saving transaction information, DFI transaction information, etc. By analyzing these transaction information, the emulation characteristics and strategies of the memory controller can be monitored in real time.
[0070] (2) Based on the active read and write transaction signals of the DFI interface, the total number of read and write transaction bytes of the memory controller is counted, and then its bandwidth utilization is evaluated, and the data traffic of the memory controller is monitored in real time; based on the above-obtained simulated memory characteristics and bandwidth utilization, the design of the memory controller can be optimized and the performance of the memory controller can be improved.
[0071] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.
[0072] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0073] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0074] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0075] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0076] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0077] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.
Claims
1. A memory controller performance monitoring system based on a DFI interface, wherein the memory controller exchanges data with a memory via the DFI interface, characterized in that: The memory controller performance monitoring system includes a memory controller monitoring unit MCMU, a memory controller monitoring controller unit MCMCR and monitoring software, wherein the memory controller monitoring unit MCMU includes a write transaction monitoring module WTM and a read transaction monitoring module RTM; The write transaction monitoring module WTM is used to monitor the write signal and write-related transaction information of the DFI interface of the memory controller; The read transaction monitoring module RTM is used to monitor the read signal and read-related transaction information of the DFI interface of the memory controller; The memory controller monitoring unit MCMU is used to encapsulate the write transaction monitoring module and the read transaction monitoring module, and send the acquired write signal, read signal and various transaction information of the DFI interface to the memory controller monitoring controller unit MCMCR; The memory controller monitoring controller unit MCMCR is used to control the working state of the memory controller monitoring unit MCMU and store various types of monitored transaction information in a register group, wherein the register group includes multiple registers, and each type of transaction information is stored in one register; The monitoring software is used to read various types of transaction information in the register group in a round-robin manner, analyze and process the various types of transaction information, and obtain the performance of the memory controller.
2. The memory controller performance monitoring system based on the DFI interface according to claim 1, characterized in that: The memory controller monitoring unit MCMU includes a Bypass transaction counter, a HIF transaction counter, a CAM transaction counter, a Power Saving transaction counter and a DFI transaction counter; When a read command or an activate command sent to the memory from the memory controller needs to pass through the bypass path, the bypass transaction counter counts; When a read command, write command, or activate command sent from the memory controller passes through the CAM, the CAM transaction counter starts counting; When a read command, write command, read-modify-write command, or high-priority read command is sent to the DDRC from the memory controller, the HIF transaction counter starts counting. When the memory controller enters self-refresh mode, powerdown mode, deeppowerdown mode or maximum powersaving mode, the Power Saving transaction counter starts counting; When the memory controller performs read and write transactions to the memory through the DFI port, the DFI transaction counter monitors the address information of the memory controller accessing the bank in the memory, including the address information of the memory controller accessing the bank in each bank group in the memory, accessing the address information of the same bank in different bank groups, accessing the address information of bit data in different rows of the same bank, and accessing the address information of bit data in the same row of the same bank. The DFI write valid signal is used to count the number of write transfer bytes within a preset time, and the DFI read valid signal is used to count the number of read transfer bytes within a preset time.
3. A memory controller performance monitoring method based on a DFI interface, applied to the memory controller performance monitoring system based on a DFI interface according to claim 1, characterized in that: include: After the memory controller is initialized, it automatically enables the work when the first transaction of the memory controller comes, captures the transaction information of the DFI interface of the memory controller, and counts all transaction information of the DFI interface of the memory controller at preset time intervals; Updating all captured transaction information of the memory controller to a related transaction register group of the memory controller; The monitoring software reads the relevant transaction register group of the memory controller, reads all transaction information in the register group, analyzes and processes all transaction information, and obtains the performance of the memory controller.
4. The memory controller performance monitoring method based on the DFI interface according to claim 3, characterized in that: After the memory controller is initialized, it is automatically enabled when the first transaction of the memory controller arrives, captures the transaction information of the DFI interface of the memory controller, and counts all transaction information of the DFI interface of the memory controller at preset time intervals, including: After the memory controller is initialized, the memory controller monitoring controller unit MCMCR controls the working state of the memory controller monitoring unit MCMU. If the memory controller monitoring unit MCMU does not need to be turned on, the memory controller monitoring controller unit MCMCR turns off its clock signal by changing the clock enable register value. Configure the statistical time register value; When the first transaction of the memory controller comes, the memory controller monitoring unit MCMU automatically starts to count all transaction information of the DFI interface of the memory controller; When the statistical time reaches the statistical time register value, all statistical transaction information is output to the register group; wherein, during the monitoring period, the memory controller monitoring unit MCMU can be selected to stop statistics as needed.
5. The memory controller performance monitoring method based on the DFI interface according to claim 3, characterized in that: The monitoring software reads a relevant transaction register group of the memory controller, reads all transaction information in the register group, analyzes and processes all transaction information, and obtains the performance of the memory controller, including: By capturing the P0 phase valid signal, the P1 phase valid signal and the mask signal of the DFI interface writing data, the number of cycles and the number of bytes of the memory controller writing data are analyzed, and then the write utilization and bandwidth utilization of the memory controller are analyzed; By capturing the w0 phase valid signal, w1 phase valid signal and mask signal of the DFI interface read data, the number of cycles and the number of bytes of the memory controller read data are analyzed, and then the read utilization and bandwidth utilization of the memory controller are analyzed.