Performance adjusting method and device, electronic equipment and medium

Abstract

The invention relates to a performance adjusting method and device, electronic equipment and a medium. The performance adjusting method comprises the following steps: determining a key task in a system; in the current operation cycle of the key task, determining target load information of the multiple pieces of hardware; and in the next operation cycle of the key task, adjusting performance parameters of the multiple pieces of hardware according to the target load information. Performance scheduling is carried out in a unified manner by adjusting performance parameters of multiple pieces of hardware at the same time in the next operation cycle, and the scheduling cycles of the multiple pieces of hardware are unified to improve the overall performance of the multiple pieces of hardware, so that the possibility that a system is stuck is reduced, and the power consumption of the electronic equipment is reduced. Meanwhile, the target load information is determined in the current operation cycle, and the performance of multiple pieces of hardware can be scheduled in time in the next operation cycle, so that the possibility of system jamming is further reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic equipment, and in particular to a performance adjustment method, device, electronic equipment, and medium. Background Art

[0002] Currently, electronic devices rely on multiple hardware components to coordinate and execute various tasks. However, due to differences in hardware manufacturers, scheduling multiple hardware components to execute critical tasks can lead to system lags. Summary of the Invention

[0003] To overcome the problems existing in the related art, the present disclosure provides a performance adjustment method, device, electronic device and medium.

[0004] According to a first aspect of an embodiment of the present disclosure, a performance adjustment method is provided, the performance adjustment method comprising:

[0005] Identify key tasks in the system;

[0006] determining target load information of a plurality of hardware devices during a current operation cycle of the critical task;

[0007] In the next operation cycle of the critical task, performance parameters of the plurality of hardware are adjusted according to the target load information.

[0008] In some embodiments of the present disclosure, determining target load information of multiple hardware devices includes:

[0009] Acquire first load information of the plurality of hardware in the current operation cycle;

[0010] Correcting the first load information to obtain second load information;

[0011] The target load information is determined according to the second load information.

[0012] In some embodiments of the present disclosure, the plurality of hardware includes a central processing unit (CPU), a graphics processing unit (GPU), and a memory; the first load information includes first sub-load information of the CPU, second sub-load information of the graphics processing unit (GPU), and third sub-load information of the memory; the second load information includes fourth sub-load information of the CPU, fifth sub-load information of the graphics processing unit (GPU), and sixth sub-load information of the memory; and correcting the first load information to obtain the second load information includes:

[0013] Obtaining seventh sub-load information cached in the current operation cycle;

[0014] determining the fourth sub-load information according to the first sub-load information and the seventh sub-load information; and / or,

[0015] determining the fifth sub-load information according to the second sub-load information and the seventh sub-load information; and / or,

[0016] The sixth sub-load information is determined according to the third sub-load information and the seventh sub-load information.

[0017] In some embodiments of the present disclosure, the seventh sub-load information includes CPU stall information and cache miss information; and determining the fourth sub-load information based on the first sub-load information and the seventh sub-load information includes:

[0018] multiplying the difference between the first preset value and the CPU stall information by the first sub-load information as the fourth sub-load information; and / or,

[0019] The determining the fifth sub-load information according to the second sub-load information and the seventh sub-load information includes:

[0020] multiplying the difference between the first preset value and the CPU stall information by the second sub-load information as the fifth sub-load information; and / or,

[0021] The determining the sixth sub-load information according to the third sub-load information and the seventh sub-load information includes:

[0022] The product of the ratio of the CPU stall information to the cache miss information and the second preset value and the third sub-load information is used as the sixth sub-load information.

[0023] In some embodiments of the present disclosure, the target load information includes first sub-target load information in the memory; and determining the target load information based on the second load information includes:

[0024] determining first bandwidth information of the memory according to the fourth sub-load information and the first preset relationship;

[0025] determining second bandwidth information of the memory according to the fifth sub-load information and the second preset relationship;

[0026] The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0027] In some embodiments of the present disclosure, determining the sum of the first bandwidth information and the second bandwidth information as the first sub-target load information includes:

[0028] In a case where the sum of the first bandwidth information and the second bandwidth information is greater than the sixth sub-load information, the sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0029] In some embodiments of the present disclosure, determining the target load information according to the second load information includes:

[0030] Determine the target operating cycle duration of the critical tasks;

[0031] Determining the duration of the current operation cycle;

[0032] The target load information is determined according to the duration of the target operation cycle, the duration of the current operation cycle, and the second load information.

[0033] In some embodiments of the present disclosure, the target load information includes second sub-target load information of the central processing unit and third sub-target load information of the graphics processing unit; and determining the target load information based on the duration of the target operation cycle, the duration of the current operation cycle, and the second load information includes:

[0034] determining first load adjustment information of the central processing unit and second load adjustment information of the graphics processing unit according to a ratio of a duration of the current operation cycle to a duration of the target operation cycle;

[0035] adjusting the fourth sub-load information using the first load adjustment information to obtain the second sub-target load information;

[0036] The fifth sub-load information is adjusted using the second load adjustment information to obtain the third sub-target load information.

[0037] In some embodiments of the present disclosure, determining the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processing unit according to the ratio of the current operating cycle to the target operating cycle includes:

[0038] When the duration of the current operating cycle is less than the duration of the target operating cycle, the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processing unit are determined based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle.

[0039] In some embodiments of the present disclosure, the target load information further includes first sub-target load information in the memory; after adjusting the fifth sub-load information using the second load adjustment information to obtain the third sub-target load information, determining the target load information based on the target operating cycle, the current operating cycle, and the second load information further includes:

[0040] determining first bandwidth information of the memory according to the second sub-target load information and a first preset relationship;

[0041] Determining second bandwidth information of the memory according to the third sub-target load information and a second preset relationship;

[0042] The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0043] In some embodiments of the present disclosure, the plurality of hardware components include a central processing unit (CPU), a graphics processing unit (GPU), and a memory; the target load information includes first sub-target load information of the memory, second sub-target load information of the CPU, and third sub-target load information of the graphics processing unit; and adjusting performance parameters of the plurality of hardware components based on the target load information includes:

[0044] adjusting the operating frequency of the memory according to the first sub-target load information; and / or,

[0045] adjusting the operating frequency of the central processing unit according to the second sub-target load information; and / or,

[0046] The operating frequency of the graphics processor is adjusted according to the third sub-target load information.

[0047] In some embodiments of the present disclosure, determining key tasks in the system includes:

[0048] Get the foreground application of the system;

[0049] A thread for rendering in the foreground application is determined to be the critical task.

[0050] In some embodiments of the present disclosure, adjusting the performance parameters of the plurality of hardware according to the target load information in the next operation cycle of the critical task includes:

[0051] At the start of the next operation cycle of the critical task, the performance parameters of the plurality of hardware are adjusted according to the target load information.

[0052] According to a second aspect of an embodiment of the present disclosure, a performance adjustment device is provided, the performance adjustment device comprising:

[0053] a first determining module, configured to determine a key task in a system;

[0054] a second determining module, the second determining module being configured to determine target load information of a plurality of hardware devices in a current operation cycle of the critical task;

[0055] An adjustment module is configured to adjust the performance parameters of the plurality of hardware according to the target load information in a next operation cycle of the critical task.

[0056] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising:

[0057] CPU;

[0058] Graphics processor;

[0059] Memory;

[0060] a memory for storing instructions executable by the central processing unit;

[0061] Wherein, the central processing unit is configured to execute the performance adjustment method as described above.

[0062] According to a fourth aspect of an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided. When instructions in the storage medium are executed by a processor of a terminal, the terminal is enabled to perform the performance adjustment method as described above.

[0063] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0064] Determine the critical tasks in the system to identify tasks that require a large amount of resources and may cause system jams. In the current operating cycle of the critical task, determine the target load information of multiple hardware to determine the performance that needs to be scheduled when multiple hardware cooperate to perform the critical task. In the next operating cycle of the critical task, adjust the performance parameters of multiple hardware according to the target load information to uniformly schedule the performance of multiple hardware. By adjusting the performance parameters of multiple hardware at the same time in the next operating cycle to uniformly schedule performance, the scheduling cycles of multiple hardware are unified to improve the overall performance of multiple hardware, thereby reducing the possibility of system jams and reducing the power consumption of electronic devices. At the same time, since the target load information is determined in the current operating cycle, the performance of multiple hardware can be scheduled in time in the next operating cycle, further reducing the possibility of system jams.

[0065] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0067] Figure 1 It is a schematic diagram of hardware performance scheduling;

[0068] Figure 2 is a flowchart of a performance adjustment method according to an exemplary embodiment;

[0069] Figure 3 is a flowchart of a performance adjustment method according to another exemplary embodiment;

[0070] Figure 4 is a flowchart of a performance adjustment method according to another exemplary embodiment;

[0071] Figure 5 is a flowchart of a performance adjustment method according to another exemplary embodiment;

[0072] Figure 6 is a flowchart of a performance adjustment method according to another exemplary embodiment;

[0073] Figure 7 is a flowchart of a performance adjustment method according to another exemplary embodiment;

[0074] Figure 8 is a schematic diagram showing hardware performance scheduling according to an exemplary embodiment;

[0075] Figure 9 is a block diagram of a performance adjustment device according to an exemplary embodiment;

[0076] Figure 10 is a block diagram of an electronic device according to an exemplary embodiment.

[0077] In the picture:

[0078] 100 - first determination module; 200 - second determination module; 300 - adjustment module; 400 - electronic device; 402 - processing component; 404 - memory; 406 - power supply component; 408 - multimedia component; 410 - audio component; 412 - input / output interface; 414 - sensor component; 416 - communication component; 420 - processor. DETAILED DESCRIPTION

[0079] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with certain aspects of the present disclosure as detailed in the appended claims. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0080] At present, during the operation of the system of an electronic device, multiple hardware need to cooperate with each other to perform various tasks in the system. For example, multiple hardware may include a central processing unit (CPU), a cache (Cache), a graphics processing unit (GPU) and a double data rate synchronous dynamic random access memory (DDR), etc. Among them, the double data rate synchronous dynamic random access memory can also be called memory. In the process of executing a task, if there is a bottleneck in the performance of one or more hardware, it will cause the system to freeze. If the performance of multiple hardware is increased, the power consumption of multiple hardware increases, causing the electronic device to heat up. Therefore, in order to balance the performance and power consumption of electronic equipment, different hardware manufacturers have corresponding scheduling methods for the performance of their respective hardware. Such as Figure 1 As shown in the figure, the operating cycles of critical tasks include t0, t1, t2, t3, t4, t5, and t6. The performance scheduling of the CPU, memory, and GPU is not uniform in each operating cycle. For example, in the second half of the t4 operating cycle, the operating frequency of the CPU and GPU is too high, while the operating frequency of the memory is low. Because critical tasks may require a large amount of resources, if the performance scheduling of multiple hardware is not uniform, system lag will occur. In addition, because the overall performance of multiple hardware cannot reach the optimal level, some hardware may have excessive performance, resulting in high power consumption of electronic equipment.

[0081] To address the above technical issues, the present disclosure provides a performance adjustment method. By adjusting the performance of multiple hardware components based on target load information during the next operating cycle of a critical task, the performance of multiple hardware components can be uniformly scheduled to maximize the overall performance of the multiple hardware components, thereby reducing the possibility of system lag. Furthermore, since the overall performance of multiple hardware components can be optimized, over-performance of some hardware components is avoided, thereby reducing the power consumption of electronic devices.

[0082] The present disclosure provides a performance adjustment method, such as Figure 2 As shown, the method includes:

[0083] S100. Determine the key tasks in the system.

[0084] S200: Determine target load information of multiple hardware in the current operation cycle of the critical task.

[0085] S300: In the next operation cycle of the critical task, adjust the performance parameters of multiple hardware according to the target load information.

[0086] In this embodiment, the critical tasks in the system are determined to determine the tasks that require a large amount of resources and may cause the system to freeze. In the current operation cycle of the critical task, the target load information of multiple hardware is determined to determine the performance that needs to be scheduled when multiple hardware cooperate to perform the critical task. In the next operation cycle of the critical task, the performance parameters of multiple hardware are adjusted according to the target load information to uniformly schedule the performance of multiple hardware. By adjusting the performance parameters of multiple hardware at the same time in the next operation cycle to uniformly schedule the performance, the scheduling cycles of multiple hardware are unified to improve the overall performance of multiple hardware, thereby reducing the possibility of system freezes and reducing the power consumption of electronic devices. At the same time, since the target load information is determined in the current operation cycle, the performance of multiple hardware can be scheduled in time in the next operation cycle, thereby further reducing the possibility of system freezes.

[0087] In one embodiment, if Figure 3 As shown, the key tasks in the system are determined in step S100 by:

[0088] S110: Acquire the foreground application of the system.

[0089] S120: Determine that a thread used for rendering in the foreground application is a critical task.

[0090] In this embodiment, because the system's foreground application is active and consumes a large amount of resources, the system's foreground application is retrieved. Because the rendering thread in the foreground application consumes a large number of resources, the rendering thread in the foreground application is determined to be a critical task. By scheduling the performance of multiple hardware devices based on the rendering thread in the foreground application, the performance of multiple hardware devices can meet the resource requirements of the critical task, thereby reducing the possibility of system lag.

[0091] In one embodiment, if Figure 4 As shown, the target load information of the multiple hardware in step S200 is determined by:

[0092] S210: Obtain first load information of multiple hardware in a current operation cycle.

[0093] S220: Correct the first load information to obtain second load information.

[0094] S230: Determine target load information according to the second load information.

[0095] In this embodiment, first load information of multiple hardware in the current operating cycle is obtained to determine whether the performance of the hardware has reached a bottleneck or is in excess. Since the first load information is limited by some hardware and cannot reflect the actual load information, the first load information is corrected to obtain second load information to reflect the actual load information. Since the second load information can reflect the actual load information, the target load information required for the critical task for the multiple hardware in the next operating cycle can be accurately determined based on the second load information. By determining the target load information based on the corrected second load information, the performance parameters of the multiple hardware adjusted based on the target load information can meet the needs of the critical task, thereby reducing the possibility of system freezes and reducing the power consumption of the electronic device.

[0096] Exemplarily, the multiple hardware components include a central processing unit (CPU), a graphics processing unit (GPU), and memory. The first load information includes first sub-load information of the CPU, second sub-load information of the GPU, and third sub-load information of the memory. The first sub-load information may be information that comprehensively reflects part or all of the CPU's operating frequency, busy time, number of instructions, machine cycles, etc. The second sub-load information may be information that comprehensively reflects part or all of the GPU's operating frequency, busy time, etc. The third sub-load information may be memory bandwidth information.

[0097] In one embodiment, the second load information includes the fourth sub-load information of the central processing unit. The correction of the first load information in step S220 to obtain the second load information can be determined as follows:

[0098] Get the seventh subload information cached in the current run cycle.

[0099] Fourth sub-load information is determined according to the first sub-load information and the seventh sub-load information.

[0100] In this embodiment, since the first sub-load information of the central processing unit is limited by the cached seventh sub-load information and cannot reflect the actual load information, the fourth sub-load information is determined based on the first sub-load information and the seventh sub-load information. This enables the fourth sub-load information to reflect the actual load information, thereby reducing the possibility of system lag caused by the performance limitation of the central processing unit.

[0101] For example, the seventh sub-load information may be information that comprehensively reflects part or all of cache miss information, CPU stall information, etc. The CPU stall information refers to information indicating that the CPU stalled due to an inability to obtain data from the memory in a timely manner.

[0102] In one embodiment, in the above step, the fourth sub-load information is determined based on the first sub-load information and the seventh sub-load information in the following manner:

[0103] The product of the difference between the first preset value and the CPU stall information and the first sub-load information is used as the fourth sub-load information.

[0104] In this embodiment, because the first sub-load information cannot reflect actual load information due to the limitations of cached CPU stall information, a first preset value is subtracted from the CPU stall information, and the difference is used to reflect the correction coefficient of the first sub-load information. The product of the difference between the first preset value and the CPU stall information and the first sub-load information is used as the fourth sub-load information. The fourth sub-load information can reflect actual load information, thereby increasing the accuracy of the target load information, reducing the possibility of system lag and lowering the power consumption of the electronic device.

[0105] For example, the value of the first preset value may be 1. In the above step, the product of the difference between the first preset value and the CPU stall information and the first sub-load information as the fourth sub-load information can be expressed by the following formula:

[0106] util new1 =util old1 ×(1-sstall d );

[0107] Among them, util new1 Indicates the fourth sub-load information, util old1 Indicates the first sub-load information, stall d Indicates CPU stall information.

[0108] In one embodiment, the second load information includes fifth sub-load information of the graphics processor. The correction of the first load information in step S220 to obtain the second load information can also be determined as follows:

[0109] Get the seventh subload information cached in the current run cycle.

[0110] Fifth sub-load information is determined according to the second sub-load information and the seventh sub-load information.

[0111] In this embodiment, because the second sub-load information of the graphics processor is limited by the cached seventh sub-load information and cannot reflect the actual load information, the fifth sub-load information is determined based on the second sub-load information and the seventh sub-load information. This allows the fifth sub-load information to reflect the actual load information, thereby reducing the possibility of system lag caused by the performance limitations of the graphics processor.

[0112] In one embodiment, the fifth sub-load information is determined according to the second sub-load information and the seventh sub-load information in the above step by:

[0113] The product of the difference between the first preset value and the CPU stall information and the second sub-load information is used as the fifth sub-load information.

[0114] In this embodiment, because the second sub-load information cannot reflect actual load information due to the limitations of cached CPU stall information, the CPU stall information is subtracted from the first preset value, and the difference is used to reflect the correction coefficient of the second sub-load information. The product of the difference between the first preset value and the CPU stall information and the second sub-load information is used as the fifth sub-load information. The fifth sub-load information can reflect actual load information, thereby increasing the accuracy of the target load information, reducing the possibility of system lag and lowering the power consumption of the electronic device.

[0115] For example, in the above step, the product of the difference between the first preset value and the CPU stall information and the second sub-load information as the fifth sub-load information can be expressed by the following formula:

[0116] util new2 =util old2 ×(1-stall d );

[0117] Among them, util new2 Indicates the fifth sub-load information, util old2 Indicates the second sub-load information, stall d Indicates CPU stall information.

[0118] In one embodiment, the second load information includes the sixth sub-load information in the memory. The correction of the first load information in step S220 to obtain the second load information can also be determined in the following manner:

[0119] Get the seventh subload information cached in the current run cycle.

[0120] Sixth sub-load information is determined according to the third sub-load information and the seventh sub-load information.

[0121] In this embodiment, since the third sub-load information of the memory is limited by the cached seventh sub-load information and cannot reflect the actual load information, the sixth sub-load information is determined based on the third sub-load information and the seventh sub-load information. This allows the sixth sub-load information to reflect the actual load information, thereby reducing the possibility of system lag caused by memory performance limitations.

[0122] In one embodiment, the sixth sub-load information is determined according to the third sub-load information and the seventh sub-load information in the above step by:

[0123] The product of the ratio of the CPU stall information to the cache miss information and the second preset value and the third sub-load information is used as the sixth sub-load information.

[0124] In this embodiment, because the third sub-load information cannot reflect actual load information due to the limitations of cached CPU stall information and cache miss information, the CPU stall information is compared with the cache miss information and a second preset value, and the ratio is used to reflect the correction coefficient of the third sub-load information. The product of the ratio of the CPU stall information to the cache miss information and the second preset value and the third sub-load information is used as the sixth sub-load information. The sixth sub-load information can reflect actual load information, thereby increasing the accuracy of the target load information, reducing the possibility of system lag and lowering the power consumption of the electronic device.

[0125] Illustratively, the second preset value may be a preset scratch pad memory (SPM) threshold.

[0126] For example, in the above step, the sixth sub-load information is obtained by multiplying the ratio of the CPU stall information to the cache miss information and the second preset value by the third sub-load information. This can be expressed by the following formula:

[0127]

[0128] Among them, BW new Indicates the sixth sub-load information, BW old Indicates the third sub-load information, stall d Indicates CPU stall information, miss d Indicates cache miss information, and SPM indicates scratch pad memory threshold.

[0129] In one embodiment, Figure 5 As shown, the target load information is determined according to the second load information in step S230 by:

[0130] S231: Determine first bandwidth information of the memory according to the fourth sub-load information and the first preset relationship.

[0131] S232: Determine second bandwidth information of the memory according to the fifth sub-load information and the second preset relationship.

[0132] S233: Determine the sum of the first bandwidth information and the second bandwidth information as first sub-target load information.

[0133] In this embodiment, since the memory bandwidth information required by the system is the bandwidth information required by the CPU and the GPU, the first memory bandwidth information is determined based on the fourth sub-load information of the CPU and the first preset relationship, and the second memory bandwidth information is determined based on the fifth sub-load information of the GPU and the second preset relationship. The sum of the first and second bandwidth information is determined as the first sub-target load information to determine the total bandwidth information required by the CPU and the GPU. By determining the first sub-target load information based on the corrected fourth and fifth sub-load information, the bandwidth information provided by the memory during the next operation cycle of the critical task can meet the requirements of the CPU and the GPU without excess, thereby reducing the possibility of system lag and lowering the power consumption of the electronic device.

[0134] For example, the first preset relationship may be a correspondence between CPU load information and memory bandwidth information. The correspondence between the CPU load information and the memory bandwidth information may be represented by a configuration table of the CPU load information and the memory bandwidth information. The second preset relationship may be a correspondence between the GPU load information and the memory bandwidth information. The correspondence between the GPU load information and the memory bandwidth information may be represented by a configuration table of the GPU load information and the memory bandwidth information.

[0135] In one embodiment, the sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information in step S233 by:

[0136] In a case where the sum of the first bandwidth information and the second bandwidth information is greater than the sixth sub-load information, the sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0137] In this embodiment, if the sum of the first and second bandwidth information is greater than the sixth sub-load information, the execution of critical tasks is affected by a memory performance bottleneck, causing system lag. The sum of the first and second bandwidth information is determined as the first sub-target load information to eliminate the memory performance bottleneck in the next operation cycle. By adjusting the memory performance parameters for the next operation cycle when a memory performance bottleneck is encountered, the memory performance bottleneck is prevented from affecting the execution of critical tasks, thereby reducing the possibility of system lag.

[0138] It can be understood that when the sum of the first bandwidth information and the second bandwidth information is less than or equal to the sixth sub-load information, the sum of the first bandwidth information and the second bandwidth information can be determined as the first sub-target load information to reduce the power consumption of the electronic device, or the sum of the first bandwidth information and the second bandwidth information can not be determined as the first sub-target load information to reduce the complexity of performance adjustment, which is not limited here.

[0139] In one embodiment, the target load information may be determined according to the second load information in step S230 by:

[0140] Determine the target run cycle lengths for key tasks.

[0141] Determine the duration of the current run cycle.

[0142] Target load information is determined according to the duration of the target operation cycle, the duration of the current operation cycle, and the second load information.

[0143] In this embodiment, since critical tasks occupy a large amount of resources, it is necessary to match the scheduling cycles of multiple hardware with the operating cycles of critical tasks, and determine the duration of the target operating cycle of the critical tasks. Since the current operating cycle may deviate from the target operating cycle and cause system jams, the duration of the current operating cycle is determined. Based on the duration of the target operating cycle, the duration of the current operating cycle, and the second load information, the target load information is determined to adjust the performance parameters of multiple hardware. By combining the duration of the target operating cycle, the duration of the current operating cycle, and the corrected second load information to determine the target load information, the scheduling cycles of multiple hardware can match the target operating cycle in the next operating cycle, thereby reducing the possibility of system jams and reducing the power consumption of electronic devices.

[0144] For example, determining the target run cycle duration of the critical task in the above step may include obtaining the name of the foreground application, obtaining a frame rate setting corresponding to the foreground application name, and determining the target run cycle duration based on the frame rate setting.

[0145] Illustratively, determining the duration of the current running cycle in the above step may be determining the difference between the timestamp of the end rendering and the timestamp of the start rendering of the critical task in the current running cycle as the duration of the current running cycle.

[0146] In one embodiment, Figure 6 As shown, in the above steps, the target load information is determined according to the duration of the target operation cycle, the duration of the current operation cycle and the second load information in the following manner:

[0147] S234: Determine first load adjustment information for the central processing unit and second load adjustment information for the graphics processing unit according to a ratio of the duration of the current operation cycle to the duration of the target operation cycle.

[0148] S235 . Adjust the fourth sub-load information using the first load adjustment information to obtain second sub-target load information.

[0149] S236: Adjust the fifth sub-load information using the second load adjustment information to obtain third sub-target load information.

[0150] In this embodiment, since the mismatch between the duration of the current operating cycle and the duration of the target operating cycle is caused by the performance bottleneck of the central processing unit and the graphics processing unit, the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processing unit are determined based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle. The fourth sub-load information is adjusted using the first load adjustment information, and the fifth sub-load information is adjusted using the second load adjustment information to obtain the adjusted second sub-target load information and third sub-target load information. By adjusting the load information of the central processing unit and the graphics processing unit based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle, the performance of the central processing unit and the graphics processing unit in the next operating cycle of the critical task can meet the requirements of the critical task without being excessive, thereby reducing the possibility of system lag and reducing the power consumption of the electronic device.

[0151] In one embodiment, determining the first load adjustment information of the CPU and the second load adjustment information of the GPU based on the ratio of the duration of the current operation cycle to the duration of the target operation cycle in step S234 may be performed as follows:

[0152] When the duration of the current operation cycle is less than the duration of the target operation cycle, the first load adjustment information of the CPU and the second load adjustment information of the GPU are determined according to the ratio of the duration of the current operation cycle to the duration of the target operation cycle.

[0153] In this embodiment, when the duration of the current operating cycle is less than the duration of the target operating cycle, the execution of critical tasks is affected by the performance bottlenecks of the CPU and GPU, causing system lag. Based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle, first load adjustment information for the CPU and second load adjustment information for the GPU are determined to eliminate the CPU and GPU performance bottlenecks in the next operating cycle. By adjusting the performance parameters of the CPU and GPU for the next operating cycle when the CPU and GPU performance bottlenecks are encountered, the CPU and GPU performance bottlenecks are prevented from affecting the execution of critical tasks, thereby reducing the possibility of system lag.

[0154] In one embodiment, determining the first load adjustment information of the CPU and the second load adjustment information of the GPU based on the ratio of the duration of the current operation cycle to the duration of the target operation cycle in step S234 may also be determined as follows:

[0155] When the duration of the current operating cycle is less than the duration of the target operating cycle and the sum of the first bandwidth information and the second bandwidth information is less than or equal to the sixth sub-load information, the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processing unit are determined based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle.

[0156] In this embodiment, when the duration of the current operating cycle is less than the duration of the target operating cycle and the sum of the first bandwidth information and the second bandwidth information is less than or equal to the sixth sub-load information, the operation of the critical task is affected by the performance bottleneck of the central processing unit and the graphics processing unit rather than the memory performance bottleneck. The first load adjustment information for the central processing unit and the second load adjustment information for the graphics processing unit are determined based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle to eliminate the performance bottleneck of the central processing unit and the graphics processing unit in the next operating cycle. By adjusting the performance parameters of the central processing unit and the graphics processing unit for the next operating cycle when the performance bottleneck of the central processing unit and the graphics processing unit is encountered, the performance bottleneck of the central processing unit and the graphics processing unit is prevented from affecting the operation of the critical task, thereby reducing the possibility of system lag.

[0157] Exemplarily, in step S235, the fourth sub-load information is adjusted with the first load adjustment information to obtain the second sub-target load information. When the duration of the current operating cycle is less than the duration of the target operating cycle, the sum of the first load adjustment information and the fourth sub-load information is used as the second sub-target load information.

[0158] Exemplarily, in step S236, the fifth sub-load information is adjusted with the second load adjustment information to obtain the third sub-target load information. When the duration of the current operating cycle is less than the duration of the target operating cycle, the sum of the second load adjustment information and the fifth sub-load information is used as the third sub-target load information.

[0159] It can be understood that when the duration of the current operating cycle is greater than or equal to the duration of the target operating cycle, the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processor can be determined based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle to reduce the power consumption of the electronic device. It is also possible not to determine the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processor based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle to reduce the complexity of performance adjustment.

[0160] In one embodiment, after the fifth sub-load information is adjusted using the second load adjustment information to obtain the third sub-target load information in step S236, the above step of determining the target load information based on the target operating cycle, the current operating cycle, and the second load information further includes:

[0161] Determine first bandwidth information of the memory according to the second sub-target load information and the first preset relationship.

[0162] Second bandwidth information of the memory is determined according to the third sub-target load information and the second preset relationship.

[0163] The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0164] In this embodiment, since the memory bandwidth information required by the system is the bandwidth information required by the central processing unit and the graphics processing unit, the first bandwidth information of the memory is determined based on the adjusted second sub-target load information of the central processing unit and the first preset relationship, and the second bandwidth information of the memory is determined based on the adjusted third sub-target load information of the graphics processing unit and the second preset relationship. The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information to determine the total bandwidth information required by the central processing unit and the graphics processing unit in the next operating cycle. By determining the first sub-target load information based on the adjusted second sub-target load information and the third sub-target load information, the bandwidth information provided by the memory in the next operating cycle of the critical task can meet the needs of the performance-adjusted central processing unit and the graphics processing unit without excess, thereby reducing the possibility of system lag and reducing the power consumption of the electronic device.

[0165] In one embodiment, in step S300, in the next operation cycle of the critical task, adjusting the performance parameters of the plurality of hardware according to the target load information is determined as follows:

[0166] At the beginning of the next operation cycle of the critical task, the performance parameters of multiple hardware are adjusted according to the target load information.

[0167] In this embodiment, by adjusting the performance parameters of multiple hardware at the beginning of the next operation cycle of the critical task, the performance of multiple hardware can meet the needs of the critical task in a timely manner, thereby reducing the possibility of system freezes.

[0168] In one embodiment, in step S300, in the next operation cycle of the critical task, adjusting the performance parameters of the plurality of hardware according to the target load information may be determined by:

[0169] Adjust the operating frequency of the memory according to the first sub-target load information.

[0170] In this embodiment, by adjusting the operating frequency of the memory according to the first sub-target load information, the critical tasks in the next operating cycle will not be affected by the memory performance bottleneck and the memory performance will not be excessive, thereby reducing the possibility of system freezes and reducing the power consumption of electronic devices.

[0171] In one embodiment, in step S300, in the next operation cycle of the critical task, adjusting the performance parameters of the plurality of hardware according to the target load information may also be determined by:

[0172] According to the second sub-target load information, the operating frequency of the central processing unit is adjusted.

[0173] In this embodiment, by adjusting the operating frequency of the central processing unit according to the second sub-target load information, the critical tasks in the next operating cycle will not be affected by the performance bottleneck of the central processing unit and the performance of the central processing unit will not be excessive, thereby reducing the possibility of system freezes and reducing the power consumption of electronic equipment.

[0174] In one embodiment, in step S300, in the next operation cycle of the critical task, adjusting the performance parameters of the plurality of hardware according to the target load information may also be determined in the following manner:

[0175] The operating frequency of the graphics processor is adjusted according to the third sub-target load information.

[0176] In this embodiment, by adjusting the operating frequency of the graphics processor based on the third sub-target load information, critical tasks in the next operating cycle will not be affected by the performance bottleneck of the graphics processor and the performance of the graphics processor will not be excessive, thereby reducing the possibility of system lag and reducing the power consumption of the electronic device.

[0177] Exemplarily, the above steps of adjusting the operating frequency of the memory according to the first sub-target load information, adjusting the operating frequency of the central processing unit according to the second sub-target load information, and adjusting the operating frequency of the graphics processing unit according to the third sub-target load information can be implemented by the system governor.

[0178] The present disclosure provides a performance adjustment method, such as Figure 7 As shown, the method includes:

[0179] S400: Acquire the foreground application of the system.

[0180] S410: Determine that a thread used for rendering in a foreground application is a critical task.

[0181] S420 , in the current running cycle of the critical task, obtaining first sub-load information of the CPU, second sub-load information of the GPU, third sub-load information of the memory, and CPU stall information and cache miss information of the cache.

[0182] S430: Calculate the product of the difference between the first preset value and the CPU stall information and the first sub-load information as the fourth sub-load information.

[0183] S440: Calculate the product of the difference between the first preset value and the CPU stall information and the second sub-load information as fifth sub-load information.

[0184] S450: multiplying the ratio of the CPU stall information to the cache miss information and the second preset value by the third sub-load information as sixth sub-load information.

[0185] S460. Determine the target operating cycle duration of the key task.

[0186] S470: Determine the duration of the current operation cycle.

[0187] S480: Determine first load adjustment information for the central processing unit and second load adjustment information for the graphics processing unit according to a ratio of a duration of the current operation cycle to a duration of the target operation cycle.

[0188] S490: Adjust the fourth sub-load information using the first load adjustment information to obtain second sub-target load information.

[0189] S500: Adjust the fifth sub-load information using the second load adjustment information to obtain third sub-target load information.

[0190] S510: Determine first bandwidth information of the memory according to the second sub-target load information and the first preset relationship.

[0191] S520: Determine second bandwidth information of the memory according to the third sub-target load information and the second preset relationship.

[0192] S530: Determine the sum of the first bandwidth information and the second bandwidth information as first sub-target load information.

[0193] S540: At the start of the next operation cycle of the critical task, adjust the operating frequency of the memory according to the first sub-target load information.

[0194] S550: Adjust the operating frequency of the central processing unit according to the second sub-target load information.

[0195] S560: Adjust the operating frequency of the graphics processor according to the third sub-target load information.

[0196] In this embodiment, the system's foreground applications are obtained to identify applications that consume more resources. Because the rendering thread consumes more resources, the rendering thread in the foreground application is determined to be a critical task, and the performance of multiple hardware components is scheduled based on the critical task. During the current execution cycle of the critical task, first sub-load information of the CPU, second sub-load information of the GPU, third sub-load information of the memory, and CPU stall information and cache miss information of the cache are obtained as first load information for the multiple hardware components and seventh load information for correction. Because the first load information is limited by the cache and cannot reflect the actual load information, the product of the difference between the first preset value and the CPU stall information and the first sub-load information is used as fourth sub-load information, the product of the difference between the first preset value and the CPU stall information and the second sub-load information is used as fifth sub-load information, and the product of the ratio of the CPU stall information to the cache miss information and the second preset value and the third sub-load information is used as sixth sub-load information. The first load information is corrected to obtain second load information that reflects the actual load information. The target operating cycle duration of the critical task and the current operating cycle duration are determined, and based on the ratio of the current operating cycle duration to the target operating cycle duration, first load adjustment information for the central processing unit (CPU) and second load adjustment information for the graphics processing unit (GPU) are determined to determine load adjustment information for the next operating cycle. The fourth sub-load information is adjusted using the first load adjustment information to obtain the second sub-target load information, and the fifth sub-load information is adjusted using the second load adjustment information to obtain the third sub-target load information, thereby determining the load information for the CPU and the graphics processing unit (GPU) in the next operating cycle. Because the first sub-target load information for the memory depends on the second sub-target load information for the CPU and the third sub-target load information for the graphics processing unit (GPU), the first sub-target load information is determined based on the second sub-target load information and the first preset relationship, as well as the third sub-target load information and the second preset relationship. At the start of the next operating cycle of the critical task, the operating frequencies of the memory, CPU, and graphics processing unit (GPU) are adjusted based on the first sub-target load information, the second sub-target load information, and the third sub-target load information. By simultaneously adjusting the performance parameters of multiple hardware components during the next operating cycle, performance scheduling is unified. This unifies the scheduling cycles of multiple hardware components to improve overall performance, reducing the likelihood of system lag and lowering the power consumption of electronic devices. Furthermore, because target load information is determined during the current operating cycle, the performance of multiple hardware components can be promptly scheduled during the next operating cycle, further reducing the likelihood of system lag.

[0197] For example, Figure 8As shown, after adjusting the performance of multiple hardware components using the above performance adjustment method, the performance of multiple hardware components can be uniformly scheduled during each operation cycle of the critical task to improve the overall performance of the multiple hardware components. In addition, the scheduling cycles of multiple hardware components can match each operation cycle of the critical task, thereby reducing the possibility of system freezes and reducing the power consumption of electronic devices. The operation cycles of the critical task include t0, t1, t2, t3, t4, t5, and t6.

[0198] In an exemplary embodiment, a performance adjustment device is provided, which is used to implement the above method. Figure 9 As shown, the performance adjustment device may include a first determination module 100, a second determination module 200 and an adjustment module 300, wherein, in the process of implementing the above method,

[0199] The first determining module 100 is configured to determine a key task in the system.

[0200] The second determining module 200 is configured to determine target load information of multiple hardware in the current running cycle of the critical task.

[0201] The adjustment module 300 is configured to adjust the performance parameters of multiple hardware according to the target load information during the next operation cycle of the critical task.

[0202] In an exemplary embodiment, a performance adjustment device is provided, in which a first determining module 100 is configured to:

[0203] Get the system's foreground application.

[0204] Identify the rendering thread in the foreground application as mission-critical.

[0205] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0206] Obtain first load information of multiple hardware in a current operation cycle.

[0207] The first load information is corrected to obtain second load information.

[0208] Target load information is determined according to the second load information.

[0209] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0210] Fourth sub-load information is determined according to the first sub-load information and the seventh sub-load information.

[0211] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0212] Fifth sub-load information is determined according to the second sub-load information and the seventh sub-load information.

[0213] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0214] Sixth sub-load information is determined according to the third sub-load information and the seventh sub-load information.

[0215] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0216] The product of the difference between the first preset value and the CPU stall information and the first sub-load information is used as the fourth sub-load information.

[0217] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0218] The product of the difference between the first preset value and the CPU stall information and the second sub-load information is used as the fifth sub-load information.

[0219] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0220] The product of the ratio of the CPU stall information to the cache miss information and the second preset value and the third sub-load information is used as the sixth sub-load information.

[0221] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0222] First bandwidth information of the memory is determined according to the fourth sub-load information and the first preset relationship.

[0223] Second bandwidth information of the memory is determined according to the fifth sub-load information and the second preset relationship.

[0224] The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0225] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0226] In a case where the sum of the first bandwidth information and the second bandwidth information is greater than the sixth sub-load information, the sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0227] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0228] Determine the target run cycle lengths for key tasks.

[0229] Determine the duration of the current run cycle.

[0230] Target load information is determined according to the duration of the target operation cycle, the duration of the current operation cycle, and the second load information.

[0231] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0232] First load adjustment information of the central processing unit and second load adjustment information of the graphics processing unit are determined according to a ratio of a duration of a current operation cycle to a duration of a target operation cycle.

[0233] The fourth sub-load information is adjusted using the first load adjustment information to obtain second sub-target load information.

[0234] The fifth sub-load information is adjusted using the second load adjustment information to obtain third sub-target load information.

[0235] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0236] When the duration of the current operation cycle is less than the duration of the target operation cycle, the first load adjustment information of the CPU and the second load adjustment information of the GPU are determined according to the ratio of the duration of the current operation cycle to the duration of the target operation cycle.

[0237] In an exemplary embodiment, a performance adjustment device is provided, in which the second determination module 200 is configured to:

[0238] Determine first bandwidth information of the memory according to the second sub-target load information and the first preset relationship.

[0239] Second bandwidth information of the memory is determined according to the third sub-target load information and the second preset relationship.

[0240] The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

[0241] In an exemplary embodiment, a performance adjustment device is provided, wherein the adjustment module 300 is configured to:

[0242] Adjust the operating frequency of the memory according to the first sub-target load information.

[0243] In an exemplary embodiment, a performance adjustment device is provided, wherein the adjustment module 300 is configured to:

[0244] According to the second sub-target load information, the operating frequency of the central processing unit is adjusted.

[0245] In an exemplary embodiment, a performance adjustment device is provided, wherein the adjustment module 300 is configured to:

[0246] The operating frequency of the graphics processor is adjusted according to the third sub-target load information.

[0247] In an exemplary embodiment, a performance adjustment device is provided, wherein the adjustment module 300 is configured to:

[0248] At the beginning of the next operation cycle of the critical task, the performance parameters of multiple hardware are adjusted according to the target load information.

[0249] In an exemplary embodiment, an electronic device is provided, such as a mobile phone, a laptop computer, a tablet computer, a wearable device, etc.

[0250] refer to Figure 10 As shown, electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0251] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the above-described method. The processor 420 may be, for example, a central processing unit. In addition, the processing component 402 may include one or more modules to facilitate interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402.

[0252] The memory 404 is configured to store various types of data to support operations on the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, videos, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0253] The power supply assembly 406 provides power to the various components of the electronic device 400. The power supply assembly 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0254] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera module and / or a rear camera module. When the electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front camera module and / or the rear camera module can receive external multimedia data. Each front camera module and the rear camera module can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0255] The audio component 410 is configured to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 400 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0256] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0257] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of components, such as the display and keypad of the electronic device 400. The sensor assembly 414 can also detect changes in the position of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and temperature changes of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0258] The communication component 416 is configured to facilitate wired or wireless communication between the electronic device 400 and other terminals. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0259] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the methods shown in the above embodiments or a combination thereof.

[0260] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as memory 404 including instructions. The instructions can be executed by processor 420 of electronic device 400 to perform the methods described in the above embodiments or combinations thereof. For example, the non-transitory computer-readable storage medium can be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage terminal. When the instructions in the storage medium are executed by the processor of the terminal, the terminal is enabled to perform the methods described in the above embodiments or combinations thereof.

[0261] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0262] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0263] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0264] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0265] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A performance adjustment method, characterized in that: The performance adjustment method includes: Identify key tasks in the system; determining target load information of a plurality of hardware devices during a current operation cycle of the critical task; In the next operation cycle of the critical task, performance parameters of the plurality of hardware are adjusted according to the target load information.

2. The performance adjustment method according to claim 1, characterized in that: The determining target load information of the plurality of hardware includes: Acquire first load information of the plurality of hardware in the current operation cycle; Correcting the first load information to obtain second load information; The target load information is determined according to the second load information.

3. The performance adjustment method according to claim 2, characterized in that: The plurality of hardware includes a central processing unit (CPU), a graphics processing unit (GPU), and a memory; the first load information includes first sub-load information of the CPU, second sub-load information of the graphics processing unit (GPU), and third sub-load information of the memory; the second load information includes fourth sub-load information of the CPU, fifth sub-load information of the graphics processing unit (GPU), and sixth sub-load information of the memory; and correcting the first load information to obtain the second load information includes: Obtaining seventh sub-load information cached in the current operation cycle; determining the fourth sub-load information according to the first sub-load information and the seventh sub-load information; and / or, determining the fifth sub-load information according to the second sub-load information and the seventh sub-load information; and / or, The sixth sub-load information is determined according to the third sub-load information and the seventh sub-load information.

4. The performance adjustment method according to claim 3, characterized in that: The seventh sub-load information includes CPU stall information and cache miss information; and determining the fourth sub-load information based on the first sub-load information and the seventh sub-load information includes: multiplying the difference between the first preset value and the CPU stall information by the first sub-load information as the fourth sub-load information; and / or, The determining the fifth sub-load information according to the second sub-load information and the seventh sub-load information includes: multiplying the difference between the first preset value and the CPU stall information by the second sub-load information as the fifth sub-load information; and / or, The determining the sixth sub-load information according to the third sub-load information and the seventh sub-load information includes: The product of the ratio of the CPU stall information to the cache miss information and the second preset value and the third sub-load information is used as the sixth sub-load information.

5. The performance adjustment method according to claim 3, characterized in that: The target load information includes first sub-target load information of the memory; and determining the target load information according to the second load information includes: determining first bandwidth information of the memory according to the fourth sub-load information and the first preset relationship; determining second bandwidth information of the memory according to the fifth sub-load information and the second preset relationship; The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

6. The performance adjustment method according to claim 5, characterized in that: The determining the sum of the first bandwidth information and the second bandwidth information as the first sub-target load information includes: In a case where the sum of the first bandwidth information and the second bandwidth information is greater than the sixth sub-load information, the sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

7. The performance adjustment method according to claim 3, characterized in that: The determining the target load information according to the second load information includes: Determine the target operating cycle duration of the critical tasks; Determining the duration of the current operation cycle; The target load information is determined according to the duration of the target operation cycle, the duration of the current operation cycle, and the second load information.

8. The performance adjustment method according to claim 7, characterized in that: The target load information includes second sub-target load information of the central processing unit and third sub-target load information of the graphics processing unit; and determining the target load information according to the duration of the target operation cycle, the duration of the current operation cycle, and the second load information includes: determining first load adjustment information of the central processing unit and second load adjustment information of the graphics processing unit according to a ratio of a duration of the current operation cycle to a duration of the target operation cycle; adjusting the fourth sub-load information using the first load adjustment information to obtain the second sub-target load information; The fifth sub-load information is adjusted using the second load adjustment information to obtain the third sub-target load information.

9. The performance adjustment method according to claim 8, characterized in that: The determining, based on the ratio of the current operating cycle to the target operating cycle, first load adjustment information of the central processing unit and second load adjustment information of the graphics processing unit includes: When the duration of the current operating cycle is less than the duration of the target operating cycle, the first load adjustment information of the central processing unit and the second load adjustment information of the graphics processing unit are determined based on the ratio of the duration of the current operating cycle to the duration of the target operating cycle.

10. The performance adjustment method according to claim 8, characterized in that: The target load information further includes the first sub-target load information in the memory; after adjusting the fifth sub-load information using the second load adjustment information to obtain the third sub-target load information, determining the target load information according to the target operation cycle, the current operation cycle, and the second load information further includes: determining first bandwidth information of the memory according to the second sub-target load information and a first preset relationship; Determining second bandwidth information of the memory according to the third sub-target load information and a second preset relationship; The sum of the first bandwidth information and the second bandwidth information is determined as the first sub-target load information.

11. The performance adjustment method according to any one of claims 1 to 10, characterized in that: The plurality of hardware components include a central processing unit (CPU), a graphics processing unit (GPU), and a memory; the target load information includes first sub-target load information of the memory, second sub-target load information of the CPU, and third sub-target load information of the graphics processing unit; and adjusting performance parameters of the plurality of hardware components according to the target load information includes: adjusting the operating frequency of the memory according to the first sub-target load information; and / or, adjusting the operating frequency of the central processing unit according to the second sub-target load information; and / or, The operating frequency of the graphics processor is adjusted according to the third sub-target load information.

12. The performance adjustment method according to any one of claims 1 to 10, characterized in that: The key tasks in the determination system include: Get the foreground application of the system; A thread for rendering in the foreground application is determined to be the critical task.

13. The performance adjustment method according to any one of claims 1 to 10, characterized in that: The step of adjusting the performance parameters of the plurality of hardware according to the target load information in the next operation cycle of the critical task includes: At the start of the next operation cycle of the critical task, the performance parameters of the plurality of hardware are adjusted according to the target load information.

14. A performance adjustment device, characterized in that: The performance adjustment device comprises: a first determining module, configured to determine a key task in a system; a second determining module, the second determining module being configured to determine target load information of a plurality of hardware devices in a current operation cycle of the critical task; An adjustment module is configured to adjust the performance parameters of the plurality of hardware according to the target load information in a next operation cycle of the critical task.

15. An electronic device, characterized in that: The electronic device comprises: CPU; Graphics processor; Memory; a memory for storing instructions executable by the central processing unit; Wherein, the central processing unit is configured to execute the performance adjustment method according to any one of claims 1 to 13.

16. A non-transitory computer-readable storage medium, characterized in that When the instructions in the storage medium are executed by a processor of a terminal, the terminal is enabled to execute the performance adjustment method according to any one of claims 1 to 13.

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