AXI bus memory access acceleration method and device, terminal and storage medium

Abstract

The invention provides an AXI bus memory access acceleration method and device, a terminal and a storage medium. The method comprises the steps of obtaining an access request of an AXI bus; performing address memory access arbitration on the access request according to a preset memory address range, and judging whether the access request is memory unit access or not; when the access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and judging whether the ID memory access type of the address memory access is a general memory access; and when the ID memory access is the general memory access, responding to the access request of the general memory access through a channel of a memory unit connected with a memory port. According to the method, when the AXI bus initiates the universal memory access, the access to the memory module can be faster by reducing the number of the passing switching nodes, so that the transmission time of accessing the memory by the bus is shortened, and the access speed of the bus memory is accelerated.

Description

Technical Field

[0001] The present application relates to the field of computer chip technology, and in particular to an AXI bus memory access acceleration method, device, terminal, and storage medium. Background Art

[0002] AXI (Advanced Extensible Interface) is a bus protocol, the most important component of the AMBA (Advanced Microcontroller Bus Architecture) protocol. It is an on-chip bus designed for high performance, high bandwidth, and low latency, and is currently a widely used bus transmission protocol. The AXI bus is a multi-channel transmission bus that sends addresses, read data, write data, and handshake signals through different channels. The order of different accesses can be disrupted, and IDs are used to indicate the ownership of each access. The master device can issue multiple read and write operations without receiving return data. The order of the read-back data can be disrupted, and unaligned data access is also supported.

[0003] In modern SoC (System on Chip) designs, the typical architecture includes a CPU (Central Processing Unit) module, a network on chip (NoC) module, memory modules, and other supporting auxiliary and peripheral modules. These modules are interconnected via high-speed buses (such as the AXI bus) to enable rapid data transmission and collaborative operation. The NoC module, as a key interconnect component within the SoC, is responsible for managing data transmission between different modules. Its performance directly impacts the efficiency and responsiveness of the entire system.

[0004] In the AXI bus architecture, a master device (Master) initiates access requests to the system's memory modules through the NoC module. To optimize access performance for a specific master device, existing technologies typically configure the NoC module's QoS (Quality of Service) mechanism to increase the priority level of that master device's port, allowing its access requests to be processed first. This approach can, to a certain extent, accelerate a specific master device's access to the memory module, thereby improving system performance.

[0005] However, despite the QoS mechanism increasing the priority of specific masters, data still needs to pass through multiple switching nodes within the NoC module before reaching the target memory module. The presence of these switching nodes inevitably increases data transmission latency, which is particularly significant in scenarios with high loads or multi-master competition. This latency not only limits overall system performance but can also prevent critical tasks from meeting real-time requirements.

[0006] Therefore, existing techniques for optimizing memory access performance by simply increasing QoS priority have certain limitations and cannot fundamentally address the latency issues introduced by switching nodes within the NoC module. Reducing latency in the data transmission path and improving overall system performance without increasing hardware complexity has become a pressing technical challenge in SoC design. Summary of the Invention

[0007] The present application provides an AXI bus memory access acceleration method, device, terminal and storage medium, which are used to solve the problem in the prior art that the NoC module increases the port priority level by configuration and needs to pass through the necessary switching nodes inside the memory module during the access process, thereby causing access delay.

[0008] In the first aspect, the present application provides an AXI bus memory access acceleration method, comprising: obtaining an access request of the AXI bus; performing address memory access arbitration on the access request according to a preset memory address range, and determining whether the access request is a memory unit access; when the access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a universal memory access; when the ID memory access is a universal memory access, responding to the access request of the universal memory access through a channel connected to the memory unit through a memory port.

[0009] In some embodiments of the first aspect of the present application, address memory access arbitration is performed on the access request according to a preset memory address range, and determining whether the access request is a memory unit access includes: receiving the access request; presetting a memory address range; obtaining the address of the access request; comparing the obtained address of the access request with the preset memory address range, and determining whether the address of the access request is within the memory address range, and performing an operation.

[0010] In some embodiments of the first aspect of the present application, when the address of the access request is within the memory address range, the access request is determined to be a memory unit access; when the address of the access request is not within the memory address range, the access request is determined to be a non-memory unit access, and the access request is transmitted to the NoC module.

[0011] In some embodiments of the first aspect of the present application, when the access request is a memory unit access, ID memory access arbitration is performed according to a preset ID signal access type, and whether the ID memory access type of the address memory access is a universal memory access is determined, including: when the access request is a memory unit access, obtaining the access ID of the memory unit access request; comparing the access ID with a preset ID access type mapping table, and determining whether the access type of the access request is a universal memory access; when the access ID is the ID corresponding to the universal memory access type in the ID access type mapping table, determining that the access type is a universal memory access; if not, determining that the access type is a non-universal memory access.

[0012] In some embodiments of the first aspect of the present application, the method further includes: when the ID memory access type is universal memory access, responding to the access request for the universal memory access through a channel connected to the memory unit through a memory port; when the ID memory access type is non-universal memory access, responding to the access request for the non-universal memory access through a channel connected to the NoC module.

[0013] In some embodiments of the first aspect of the present application, when the access request is a write access request, the AXI bus memory access acceleration method for the write access request includes: obtaining a write access request of the AXI bus; performing address memory access arbitration on the write access request according to a preset memory address range, and determining whether the write access request is a memory unit access; when the write access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal write access type, and determining whether the ID memory write access type of the address memory access is a universal memory access; when the ID memory write access is a universal memory access, responding to the write access request of the universal memory access through a channel connected to the memory unit through a memory port.

[0014] In some embodiments of the first aspect of the present application, address memory access arbitration is performed on the write access request according to a preset memory address range, and determining whether the write access request is a memory unit access includes: receiving the write access request; presetting a memory address range; obtaining the address of the write access request; comparing the obtained address of the write access request with the preset memory address range, and determining whether the address of the write access request is within the memory address range, and performing an operation.

[0015] In some embodiments of the first aspect of the present application, when the write access request is a memory unit access, ID memory access arbitration is performed according to a preset ID signal write access type, and whether the ID memory write access type of the address memory access is a universal memory access is determined, including: when the write access request is a memory unit access, obtaining the write access ID of the memory unit access request; comparing the write access ID with a preset ID access type mapping table, and determining whether the access type of the write access request is a universal memory access; including: when the write access ID is the ID corresponding to the universal memory access type in the ID access type mapping table, determining that the write access type is a universal memory access; if not, determining that the write access type is a non-universal memory access.

[0016] In some embodiments of the first aspect of the present application, when the access request is a read access request, the AXI bus memory access acceleration method for the read access request includes: obtaining a read access request of the AXI bus; performing address memory access arbitration on the read access request according to a preset memory address range, and determining whether the read access request is a memory unit access; when the read access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a universal memory access; when the ID memory access is a universal memory access, responding to the read access request of the universal memory access through a channel connected to the memory unit through a memory port.

[0017] In some embodiments of the first aspect of the present application, address memory access arbitration is performed on the read access request according to a preset memory address range, and determining whether the read access request is a memory unit access includes: receiving the read access request; presetting a memory address range; obtaining the address of the read access request; comparing the obtained address of the read access request with the preset memory address range, and determining whether the address of the read access request is within the memory address range, and performing an operation.

[0018] In some embodiments of the first aspect of the present application, when the read access request is a memory unit access, ID memory access arbitration is performed according to a preset ID signal access type, and whether the ID memory access type of the address memory access is a universal memory access is determined, including: when the read access request is a memory unit access, obtaining the read access ID of the memory unit access request; comparing the read access ID with a preset ID access type mapping table, and determining whether the access type of the read access request is a universal memory access; including: when the read access ID is the ID corresponding to the universal memory access type in the ID access type mapping table, determining that the read access type is a universal memory access; if not, determining that the read access type is a non-universal memory access.

[0019] In the second aspect, the present application provides an AXI bus memory access acceleration device, including: an instruction acquisition module for acquiring an access request of the AXI bus; a first access arbitration module for performing address memory access arbitration on the access request according to a preset memory address range, and extracting the address of the memory unit access; a second access arbitration module for performing ID memory access arbitration based on the result of the address memory access arbitration and in combination with a preset ID signal access type; an instruction response module for responding to the access request of the universal memory access through a channel connected to the memory unit through a memory port according to the result of the ID memory access arbitration when the ID memory access is a universal memory access.

[0020] In a third aspect, the present application provides an AXI bus memory access acceleration system, comprising: a master device, configured to initiate an access transaction to a slave device; an instruction acquisition module, configured to obtain an access request for the AXI bus; a first access arbitration module, configured to perform address memory access arbitration on the access request according to a preset memory address range, and extract the address of the memory unit access; a second access arbitration module, configured to perform ID memory access arbitration based on the result of the address memory access arbitration and in combination with a preset ID signal access type; an instruction response module, configured to respond to the access request for the universal memory access through a channel connected to the memory unit through a memory port according to the result of the ID memory access arbitration when the ID memory access is a universal memory access; and a slave device, configured to respond to the master device.

[0021] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method when the computer program is executed by a processor.

[0022] In a fifth aspect, the present application provides an electronic terminal, comprising: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal performs the method.

[0023] As described above, the AXI bus memory access acceleration method, device, terminal, and storage medium of the present application have the following beneficial effects:

[0024] The AXI bus memory access acceleration method, device, terminal and storage medium provided in this application can reach the memory module faster by reducing the number of switching nodes passed through when initiating general memory access on the AXI bus, thereby reducing the transmission time of bus access to memory and accelerating the access speed of bus memory; this application can improve system performance by reducing access latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a flow chart of an AXI bus memory access acceleration method in an embodiment of the present application.

[0026] Figure 2 Shown is a schematic diagram of the access arbitration process of an AXI bus memory access acceleration method in an embodiment of the present application.

[0027] Figure 3A Shown is a schematic diagram of the existing SoC system framework structure.

[0028] Figure 3B Shown is a schematic diagram of the SoC system framework structure after the memory access acceleration module is added in the embodiment of the present application.

[0029] Figure 4 Shown is a flow chart of S2 in the AXI bus memory access acceleration method described in this application.

[0030] Figure 5A Shown is a flow chart of S5 in the AXI bus memory access acceleration method described in this application.

[0031] Figure 5B Shown is a flow chart of the write access request acceleration method in the AXI bus memory access acceleration method described in this application.

[0032] Figure 6 Shown is a flow chart of S52 in the AXI bus memory access acceleration method described in this application.

[0033] Figure 7A Shown is a flow chart of S6 in the AXI bus memory access acceleration method described in this application.

[0034] Figure 7B Shown is a flow chart of the read access request acceleration method in the AXI bus memory access acceleration method described in this application.

[0035] Figure 8 Shown is a flow chart of S62 in the AXI bus memory access acceleration method described in this application.

[0036] Figure 9A Shown is a schematic diagram of the existing GPU system framework structure.

[0037] Figure 9B Shown is a schematic diagram of the GPU system framework structure after the memory access acceleration module is added in an embodiment of the present application.

[0038] Figure 10 Shown is a structural schematic diagram of an electronic terminal in one embodiment of the present application.

[0039] Figure 11 Shown is a structural diagram of an AXI bus memory access acceleration device in an embodiment of the present application.

[0040] Figure 12 Shown is a structural diagram of an AXI bus memory access acceleration system in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0042] It should be noted that the diagrams provided in the following embodiments are merely schematic illustrations of the basic concept of the present application. Therefore, the diagrams only show components relevant to the present application and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied at will, and the component layout may be more complex. The terms used herein are intended only to describe specific embodiments and are not intended to limit the present application.

[0043] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0044] In order to solve the problems in the above-mentioned background technology, the present application provides an AXI bus memory access acceleration method, device, terminal and storage medium, which aims to solve the problem in the prior art that the NoC module increases the port priority level by configuration and needs to pass through the necessary switching nodes inside the memory module in the process of accessing the memory module, thereby causing access delay. At the same time, in order to make the purpose, technical solution and advantages of the present application clearer, the technical solution in the embodiment of the present application is further described in detail through the following embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the invention.

[0045] Before further explaining the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0046] <1> AXI (Advanced Extensible Interface) is a bus protocol and the most important component of the Advanced Microcontroller Bus Architecture (AMBA). It is an on-chip bus designed for high performance, high bandwidth, and low latency. The AXI bus is a multi-channel transmission bus that transmits write addresses, write data, write responses, and read addresses, read data, and responses over separate channels. AXI is a high-performance protocol within AMBA. AXI technology enriches the existing AMBA standard to meet the requirements of ultra-high-performance and complex system-on-chip (SoC) designs.

[0047] <2> Master IP: The end that initiates read and write transactions at both ends of the bus is called the master device.

[0048] <3> Slave device (Slave IP), the end that responds to the transaction at both ends of the bus is the slave device.

[0049] <4> There are many different definitions of SoC, and due to its rich connotations and wide range of applications, it is difficult to give a precise definition. Generally speaking, SoC stands for System-on-Chip, or System-on-Chip, meaning it is a product, a dedicated integrated circuit that contains all the contents of a complete system and embedded software.

[0050] <5> NoC (Network on Chip) is a communication architecture used in SoC systems-on-chip. It provides data communication between processors, memory, I / O devices and other hardware modules within the chip.

[0051] <6> awid, write address ID (Identity document), this signal is the identification tag of the write address group of the signal, used to specify the order of certain special transmission tasks.

[0052] <7> awaddr, write address, gives the address of the first data in the write burst transfer.

[0053] <8> awvalid, write address valid, this signal indicates that the channel is sending valid write address and control information.

[0054] <9> awready, write address ready, this signal indicates that the slave is ready to accept an address and related control signals.

[0055] <10> arid, read address ID, this signal is the identification tag of the signal read address group, which is used to specify the order of certain special transmission tasks.

[0056] <11> araddr, read address, the read address gives the address of the first data in the read burst transfer.

[0057] <12> arvalid, read address valid, this signal indicates that the channel is sending valid read address and control information.

[0058] <13> arready, read address ready, this signal indicates that the slave is ready to accept an address and related control signals.

[0059] The present invention provides an AXI bus memory access acceleration method, an AXI bus memory access acceleration system, an AXI bus memory access acceleration device, a storage medium storing an executable program for implementing the AXI bus memory access acceleration method, and an electronic terminal. Regarding the implementation of the AXI bus memory access acceleration method, the present invention describes an exemplary implementation scenario for AXI bus memory access acceleration.

[0060] See also Figure 1 、 Figure 2 、 Figure 3A and Figure 3B , which respectively show a flowchart of an AXI bus memory access acceleration method in an embodiment of the present application, a flowchart of an access arbitration flow of an AXI bus memory access acceleration method in an embodiment of the present application, a schematic diagram of the existing SoC system framework structure, and a schematic diagram of the SoC system framework structure after adding a memory access acceleration module in an embodiment of the present application. The AXI bus memory access acceleration method in this embodiment mainly includes the following steps:

[0061] S1, obtains the access request of the AXI bus.

[0062] The AXI bus is a widely used bus standard within the AMBA bus architecture. AXI was designed to operate at high clock frequencies and achieve high data throughput even with long latency. The AXI bus separates read / write requests from read / write results, and separates the signals for writing and reading data, allowing simultaneous write and read operations, thereby maximizing bus throughput.

[0063] In this embodiment, the access request includes: a read access request and a write access request.

[0064] Specifically, the AXI bus protocol defines the access process between master and slave devices. First, after system startup or reset, the AXI bus and its associated components (such as master and slave devices) are initialized. AXI bus parameters, such as data width, address width, and burst length, are configured to suit specific system requirements.

[0065] The master device then waits for access to the memory or peripherals. Once it initiates an access request, it prepares the corresponding address, data, and control information. The master device generates a corresponding signal based on the access type (e.g., read or write) and sends the generated access request signal (e.g., address, data, control information, or status information) to the AXI bus.

[0066] For example, for a write access request, the master device generates signals related to the write address (AWADDR), write data (AWLEN), and write response (BRESP); and for a read access request, the master device generates signals related to the read address (ARADDR) and read data (ARLEN).

[0067] It should be noted that the AXI bus uses a bidirectional handshake protocol for data transmission. During each transmission, the data source (e.g., the master device) sets the Valid signal, while the data receiver (e.g., the slave device) sets the Ready signal. Data is transmitted on the bus only when both signals are valid. Furthermore, the AXI bus supports multiple concurrent accesses and out-of-order completion, which increases the flexibility and efficiency of data transmission. However, this also requires that the master and slave devices must be able to correctly handle concurrent access and out-of-order responses.

[0068] S2, performing address memory access arbitration on the access request according to a preset memory address range, and determining whether the access request is a memory unit access. Figure 4 , which is a flow chart of S2 in the AXI bus memory access acceleration method described in this application. Figure 4 As shown, S2 includes the following steps:

[0069] S21, receiving the access request;

[0070] S22, preset memory address range;

[0071] S23, obtaining the address of the access request;

[0072] S24, comparing the obtained address of the access request with the preset memory address range, determining whether the address of the access request is within the memory address range, and performing an operation.

[0073] In this embodiment, when the address of the access request is within the preset memory address range, the access request is determined to be a memory unit access; when the address of the access request is not within the memory address range, the access request is determined to be a non-memory unit access, and the access request is transmitted to the NoC module.

[0074] Specifically, a memory address range is first preset, and this memory address range is either valid or protected, and is typically defined by a start address and an end address. Next, an access request signal (including the target memory address and access type) generated and sent by the master device is received and identified. The access request can be received via an interrupt, a message queue, a direct memory access (DMA) controller, or other means. The target address and access type are then extracted from the received access request, along with relevant fields.

[0075] Next, based on the preset memory address range, it is determined whether the target address of the received access request is within a valid range. This can be done by traversing a preset address range table to check whether the target address is between the start address and the end address of any range.

[0076] It can be further seen that if it is confirmed that the target address of the access request is within the memory address range, the access request is determined to be a memory unit access request; further, if the access request is for a valid memory unit, the corresponding operation is performed according to the access type; if the request is invalid (that is, the target address is not within the preset range or the access type is not allowed), a non-memory unit access processing flow may be required.

[0077] When the address of the access request is not within the memory address range, the access request is determined to be a non-memory unit access, and the access request is transmitted to the NoC module.

[0078] S3, when the access request is a memory unit access, ID memory access arbitration is performed according to the preset ID signal access type, and it is determined whether the ID memory access type of the address memory access is a general memory access. The specific steps of S3 include:

[0079] S31, when the access request is a memory unit access, obtaining an access ID of the memory unit access request;

[0080] S32, compare the access ID with the preset ID access type mapping table, and determine whether the access type of the access request is universal memory access; when the access ID is the ID corresponding to the universal memory access type in the ID access type mapping table, determine that the access type is universal memory access; if not, determine that the access type is non-universal memory access.

[0081] In this embodiment, when the ID signal memory address is within the memory address range of the preset ID signal access type, the ID signal access type is determined to be universal memory access; when the ID signal memory address is not within the memory address range of the preset ID signal access type, the ID signal access type is determined to be non-universal memory access.

[0082] Furthermore, when the ID memory access type is universal memory access, the access request for the universal memory access is responded to through the channel connected to the memory unit through the memory port; when the ID memory access type is non-universal memory access, the access request for the non-universal memory access is responded to through the channel connected to the NoC module.

[0083] Specifically, after receiving a request to access a memory unit, the arbitration device checks the address in the request to see if it falls within a preset memory address range. This range is typically set during system initialization based on hardware specifications and operating system requirements. After confirming the address is legitimate, the arbitration device determines the access type, typically determined by a control signal or flag in the request.

[0084] Furthermore, if the address is legal, the access type is correct, and the access rights are met, the access request is allowed to be transmitted to the memory port for further execution, that is, a signal is sent to the memory module to execute the corresponding request command. Similarly, if the address is illegal, the access type is incorrect, or the access rights are insufficient, the access request is rejected and a signal is sent to the NoC module for processing.

[0085] It should be noted that the ID signal in this step is used as an arbitration judgment signal.

[0086] S4, when the ID memory access is a universal memory access, responding to the access request of the universal memory access through a channel connecting the memory port to the memory unit.

[0087] Specifically, according to the contents of step S3, once the access request is granted, the memory module locates the specific memory module's storage unit based on address decoding techniques (e.g., using row address selectors and column address selectors) and performs the corresponding read or write operation. Finally, the data is transferred to the CPU or from the CPU to the memory module via the memory bus, completing the entire memory access process.

[0088] Therefore, the present application aims to accelerate bus access to memory by adding an ID signal as an arbitration judgment signal and reducing the number of switching nodes.

[0089] The following describes the implementation process of the AXI bus memory access acceleration method by taking different access request types as examples.

[0090] (1) When the access request type is a write access request

[0091] See also Figure 5A 、 Figure 5B and Figure 6 .

[0092] S51: Obtain a write access request for the AXI bus.

[0093] S52, performing address memory access arbitration on the write access request according to a preset memory address range, and determining whether the write access request is a memory unit access. The S52 specifically includes:

[0094] S521, receiving the write access request;

[0095] S522, preset memory address range;

[0096] S523, obtaining the address of the write access request;

[0097] S524: Compare the acquired address of the write access request with the preset memory address range, determine whether the address of the write access request is within the memory address range, and perform an operation.

[0098] Specifically, first, a write access request is received from the CPU module; the write access request here includes the memory address to be accessed; and a memory address range is preset. Then, the address in the write access request is compared with the preset memory address range to see whether the address of the write access request is within the preset memory address range. If the write access request is within the preset memory address range, it is determined that the write access request is a memory unit write access; then, it is further arbitrated. If the write access request is not within the preset memory address range, it is determined that the write access request is not a memory unit write access; then, it is transmitted to the NoC write port and enters the NoC module for response.

[0099] S53, when the write access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal write access type, and determining whether the ID memory write access type of the address memory access is a general memory access. The S53 specifically includes:

[0100] S531, when the write access request is a memory unit access, obtaining a write access ID of the memory unit access request;

[0101] S532, compare the write access ID with the preset ID access type mapping table, and determine whether the access type of the write access request is universal memory access; when the write access ID is the ID corresponding to the universal memory access type in the ID access type mapping table, determine that the write access type is universal memory access; if not, determine that the write access type is non-universal memory access.

[0102] Specifically, first, in conjunction with the previous steps, ID memory access arbitration is performed on a write access request within a preset memory address range (i.e., the write access request is a memory unit write access). At this point, the write access ID of the memory unit access request is obtained; then, the write access ID is compared with a preset ID access type mapping table to determine whether the access type of the write access request is a general memory access.

[0103] The judgment criteria include: when the write access ID is an ID corresponding to the universal memory access type in the ID access type mapping table, determining that the write access type is universal memory access; otherwise, determining that the write access type is non-universal memory access.

[0104] S54: When the ID memory write access is a general memory access, respond to the write access request of the general memory access through a channel connecting the memory port to the memory unit.

[0105] Specifically, combining the aforementioned steps, once an access request is granted, the memory module locates the specific memory module's storage location using address decoding techniques (e.g., using row and column address selectors) and performs the corresponding write operation. Finally, the data is transferred from the CPU to the memory module via the memory bus, completing the entire memory write access process.

[0106] Here, the process of arbitrating the memory write address and write access ID is explained using an AXI bus processor as an example.

[0107] In this embodiment, the write ID is predefined. For write access request encoding, if the predefined write address memory range and predefined write ID type are universal memory access, the write access request is directed to the write port connected to the memory module. Write requests of other types and non-universal memory addresses are directed to the write port connected to the NoC module.

[0108] For example, a 4GB memory space is preferred. For the write access request encoding, the preset write address memory range (0x00000000 (AWMIN)-0xFFFF FFFF (AWMAX)) and the preset write ID type range (0b1xxxx, 0b10000 (AWIDMIN)-0b11111 (AWIDMAX)) are general memory access.

[0109] When the initiated awaddr is a memory address (0x10000000) (i.e., AWMIN ≤ awaddr ≤ AWMAX) and awid == 0b1xxxx (i.e., AWIDMIN ≤ awid ≤ AWIDMAX), the write access request is directed to the write port connected to the memory module. Write requests of other types and non-generic memory addresses are directed to the write port connected to the NoC module and responded to by the NoC module, as shown in Table 1.

[0110] Table 1 AWIDM[4:0] encoding method

[0111]

[0112] The core number of nn is: 0b00, 0b01, 0b10, or 0b11.

[0113] Therefore, for AXI write operations, first obtain the write access request of the AXI bus; then arbitrate the write address of the write access request according to the preset memory write address range to determine whether it is a memory unit write access; then arbitrate the write ID signal access type of the request for memory unit write access, and determine whether it is a general memory write access through the preset write ID signal access type definition; again respond to the general write access initiated to the memory unit through the write channel directly connected to the memory unit; finally, respond to other non-memory unit write access and memory unit non-general write access requests through the write channel connected to the NoC module.

[0114] (2) When the access request type is a read access request

[0115] See also Figure 7A 、 Figure 7B and Figure 8 .

[0116] S61: Obtain a read access request of the AXI bus.

[0117] S62, performing address memory access arbitration on the read access request according to a preset memory address range, and determining whether the read access request is a memory unit access. S62 specifically includes:

[0118] S621, receiving the read access request;

[0119] S622, preset memory address range;

[0120] S623, obtaining the address of the read access request;

[0121] S624: Compare the acquired address of the read access request with the preset memory address range, determine whether the address of the read access request is within the memory address range, and perform an operation.

[0122] Specifically, first, a read access request is received from the CPU module; the read access request here includes the memory address to be accessed, and a memory address range is preset. Then, the address in the read access request is compared with the preset memory address range to see whether the address of the read access request is within the preset memory address range. If the read access request is within the preset memory address range, it is determined that the read access request is a memory unit read access; then, it is further arbitrated. If the read access request is not within the preset memory address range, it is determined that the read access request is not a memory unit read access; then, it is transmitted to the NoC read port and enters the NoC module for response.

[0123] S63, when the read access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a general memory access. The S63 specifically includes:

[0124] S631: When the read access request is a memory unit access, obtain a read access ID of the memory unit access request.

[0125] S632, comparing the read access ID with a preset ID access type mapping table, and determining whether the access type of the read access request is general memory access;

[0126] The method comprises: when the read access ID is an ID corresponding to the universal memory access type in the ID access type mapping table, determining that the read access type is universal memory access; if not, determining that the read access type is non-universal memory access.

[0127] Specifically, first, in conjunction with the aforementioned steps, ID memory access arbitration is performed on a read access request within a preset memory address range (i.e., the read access request is a memory unit read access). At this point, the read access ID of the memory unit access request is obtained; then, the read access ID is compared with a preset ID access type mapping table to determine whether the access type of the read access request is a general memory access.

[0128] The judgment criteria include: when the read access ID is an ID corresponding to the universal memory access type in the ID access type mapping table, determining that the read access type is universal memory access; otherwise, determining that the read access type is non-universal memory access.

[0129] S64: When the ID memory access is a universal memory access, respond to the read access request of the universal memory access through a channel connecting the memory port to the memory unit.

[0130] Specifically, combining the aforementioned steps, once an access request is granted, the memory module locates the specific memory module's storage unit using address decoding techniques (e.g., using row and column address selectors) and performs the corresponding read operation. Finally, the data is transmitted to the CPU via the memory bus, completing the entire memory read access process.

[0131] Here, the process of arbitrating the memory read address and read access ID is explained by taking the AXI bus processor as an example.

[0132] In this embodiment, the read ID is also predefined. For read access request encoding, if the predefined read address memory range and predefined read ID type are universal memory access, the read access request is directed to the read port connected to the memory module. Read requests of other types and non-universal memory addresses are directed to the read port connected to the NoC module.

[0133] For example, a 4GB memory space is preferred. For read access request encoding, the preset read address memory range (0x00000000 (ARMIN)-0xFFFF FFFF (ARMAX)) and the preset read ID type range (0b1xxxnn, 0b100000 (ARIDMIN)-0b111111 (ARIDMAX)) are general memory access.

[0134] When the initiating araddr is a memory address (0x10000000) (i.e., ARMIN ≤ araddr ≤ ARMAX) and arid == 0b1xxxnn (i.e., ARIDMIN ≤ arid ≤ ARIDMAX), the read access request is directed to the read port connected to the memory module. All other read requests with non-generic memory addresses are directed to the read port connected to the NoC module and responded to by the NoC module, as shown in Table 2.

[0135] Table 2 ARIDM[5:0] encoding rules

[0136]

[0137] The core number of nn is: 0b00, 0b01, 0b10, or 0b11.

[0138] Therefore, for AXI read operations, first obtain the read access request of the AXI bus; then arbitrate the read address of the read access request according to the preset memory read address range to determine whether it is a memory unit read access; then arbitrate the read ID signal access type of the request for memory unit read access, and determine whether it is a general memory read access through the preset read ID signal access type definition; again respond to the general read access initiated to the memory unit through the read channel directly connected to the memory unit; finally, respond to other non-memory unit read access and memory unit non-general read access requests through the read channel connected to the NoC module.

[0139] Please note that Figure 9A and Figure 9B , respectively showing a schematic diagram of the existing GPU system framework structure and a schematic diagram of the GPU system framework structure after adding a memory access acceleration module in an embodiment of the present application. The bus system used in this application can be AXI3, AXI4, and other custom buses that require memory access. The application is not limited to the main port application of the CPU module, and can also be used for other modules with main ports that require external access, such as GPU (Graphics Processing Unit) modules.

[0140] In addition, the method provided in the present application can also accelerate access to a specific target module by setting different addresses and ID types. For example, the address can be set to an SRAM area, and a custom ID type for accessing SRAM can be added, so that access to the target area address and specific ID type can be quickly achieved, thereby reducing access delays and improving system performance.

[0141] To sum up, the AXI bus memory access acceleration method adopted in this application first obtains the access request of the AXI bus; then arbitrates the address of the access request according to the preset memory address range to determine whether it is a memory unit access; then performs ID signal access type arbitration on the request for memory unit access, and determines whether it is a general memory access through the preset ID signal access type definition; again responds to the general access initiated to the memory unit through the channel directly connected to the memory unit; finally, responds to other non-memory unit access and memory unit non-general access requests through the channel connected to the NoC module.

[0142] The AXI bus memory access acceleration method provided in the embodiment of the present application can be implemented on the terminal side or the server side. As for the hardware structure of the AXI bus memory access acceleration terminal, please refer to Figure 10 , is an optional hardware structure diagram of the AXI bus memory access acceleration terminal 100 provided in an embodiment of the present application. The terminal 100 can be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The AXI bus memory access acceleration terminal 100 includes: at least one processor 101, a memory 102, at least one network interface 104 and a user interface 106. The various components in the device are coupled together through a bus system 105. It can be understood that the bus system 105 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 105 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 10 Various buses are labeled as bus systems.

[0143] The user interface 106 may include a display, a keyboard, a mouse, keys, buttons, a touch panel or a touch screen.

[0144] It will be appreciated that the memory 102 may be a volatile memory or a non-volatile memory, and may also include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present application is intended to include, but is not limited to, these and any other suitable categories of memory.

[0145] The memory 102 in the embodiment of the present application is used to store various categories of data to support the operation of the AXI bus memory access acceleration terminal 100. Examples of these data include: any executable program for operating on the AXI bus memory access acceleration terminal 100, such as an operating system 1021 and an application 1022; the operating system 1021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 1022 can include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The AXI bus memory access acceleration method provided in the embodiment of the present application can be included in the application 1022.

[0146] The method disclosed in the above-mentioned embodiment of the present application can be applied to the processor 101 or implemented by the processor 101. The processor 101 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above-mentioned method can be completed by the integrated logic circuit of the hardware in the processor 101 or by instructions in the form of software. The above-mentioned processor 101 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 101 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor 101 can be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in conjunction with the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above-mentioned method in combination with its hardware.

[0147] In an exemplary embodiment, the AXI bus memory access acceleration terminal 100 can be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), and complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0148] like Figure 11 , which is a structural diagram of an AXI bus memory access acceleration device in an embodiment of the present application.

[0149] In this embodiment, the AXI bus memory access acceleration device includes: an instruction acquisition module 111, which is used to obtain an access request of the AXI bus; a first access arbitration module 112, which is used to perform address memory access arbitration on the access request according to a preset memory address range, and extract the address of the memory unit access; a second access arbitration module 113, which is used to perform ID memory access arbitration based on the result of the address memory access arbitration and in combination with a preset ID signal access type; an instruction response module 114, which is used to respond to the access request of the universal memory access through a channel connected to the memory unit through a memory port according to the result of the ID memory access arbitration when the ID memory access is a universal memory access.

[0150] It should be noted that the AXI bus memory access acceleration device provided in the above embodiment only uses the aforementioned division of program modules as an example to illustrate AXI bus memory access acceleration. In actual applications, the aforementioned processing can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program modules to complete all or part of the aforementioned processing. In addition, the AXI bus memory access acceleration device provided in the above embodiment and the AXI bus memory access acceleration method embodiment are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0151] like Figure 12 As shown, it is a structural diagram of an AXI bus memory access acceleration system in an embodiment of the present application. In this embodiment, the AXI bus memory access acceleration system includes: an AXI master end, which is used to initiate an access transaction to a slave device; wherein, an instruction acquisition module is used to obtain an access request of the AXI bus; a first access arbitration module, which is used to perform address memory access arbitration on the access request according to a preset memory address range, and extract the address of the memory unit access; a second access arbitration module, which is used to perform ID memory access arbitration based on the result of the address memory access arbitration and in combination with a preset ID signal access type; an instruction response module, which is used to respond to the access request of the universal memory access through a channel connected to the memory unit through a memory port according to the result of the ID memory access arbitration when the ID memory access is a universal memory access; and an AXI slave end, which is used to respond to the master device.

[0152] It should be noted that the AXI bus memory access acceleration system provided in the above embodiment only uses the division of the above-mentioned program modules as an example to illustrate the AXI bus memory access acceleration. In actual applications, the above-mentioned processing can be assigned to different program modules as needed, that is, the internal structure of the system can be divided into different program modules to complete all or part of the above-described processing. In addition, the AXI bus memory access acceleration system provided in the above embodiment and the AXI bus memory access acceleration method embodiment are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0153] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with a computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0154] In the embodiments provided herein, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a magnetic disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0155] In summary, the present application provides an AXI bus memory access acceleration method, device, terminal, and storage medium. When initiating a general memory access on the AXI bus, this application can reach the memory module more quickly by reducing the number of switch nodes traversed, thereby reducing the bus access memory transmission time and accelerating bus memory access speed. This application can also improve system performance by reducing access latency. Therefore, this application effectively overcomes the various shortcomings of the existing technology and has high industrial application value.

[0156] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. An AXI bus memory access acceleration method, characterized in that: include: Get access request to AXI bus; Performing address memory access arbitration on the access request according to a preset memory address range to determine whether the access request is a memory unit access; When the access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a general memory access; When the ID memory access is a universal memory access, the access request for the universal memory access is responded to through a channel connecting the memory port to the memory unit.

2. The AXI bus memory access acceleration method according to claim 1, wherein: Performing address memory access arbitration on the access request according to a preset memory address range to determine whether the access request is a memory unit access includes: receiving the access request; Preset memory address range; Obtaining the address of the access request; The obtained address of the access request is compared with the preset memory address range, and it is determined whether the address of the access request is within the memory address range, and an operation is performed.

3. The AXI bus memory access acceleration method according to claim 2, wherein: When the address of the access request is within the memory address range, determining that the access request is a memory unit access; When the address of the access request is not within the memory address range, the access request is determined to be a non-memory unit access, and the access request is transmitted to the NoC module.

4. The AXI bus memory access acceleration method according to claim 1, wherein: When the access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a general memory access includes: When the access request is a memory unit access, Obtaining an access ID for the memory unit access request; Compare the access ID with a preset ID access type mapping table, and determine whether the access type of the access request is general memory access; When the access ID is an ID corresponding to the universal memory access type in the ID access type mapping table, the access type is determined to be universal memory access; if not, the access type is determined to be non-universal memory access.

5. The AXI bus memory access acceleration method according to claim 4, wherein: The method further includes: when the ID memory access type is general memory access, responding to an access request for the general memory access through a channel connecting a memory port to a memory unit; When the ID memory access type is non-universal memory access, an access request for the non-universal memory access is responded to through a channel connected to the NoC module.

6. The AXI bus memory access acceleration method according to claim 1, wherein: When the access request is a write access request, the AXI bus memory access acceleration method for the write access request includes: Get write access request for AXI bus; Performing address memory access arbitration on the write access request according to a preset memory address range to determine whether the write access request is a memory unit access; When the write access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal write access type, and determining whether the ID memory write access type of the address memory access is a general memory access; When the ID memory write access is a universal memory access, a write access request for the universal memory access is responded to through a channel connecting the memory port to the memory unit.

7. The AXI bus memory access acceleration method according to claim 6, wherein: Performing address memory access arbitration on the write access request according to a preset memory address range to determine whether the write access request is a memory unit access includes: receiving the write access request; Preset memory address range; Obtaining the address of the write access request; The obtained address of the write access request is compared with the preset memory address range, and it is determined whether the address of the write access request is within the memory address range, and an operation is performed.

8. The AXI bus memory access acceleration method according to claim 6, wherein: When the write access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal write access type, and determining whether the ID memory write access type of the address memory access is a general memory access includes: When the write access request is a memory unit access, Obtaining a write access ID for the memory unit access request; Comparing the write access ID with a preset ID access type mapping table, and determining whether the access type of the write access request is general memory access; The method comprises: when the write access ID is an ID corresponding to the universal memory access type in the ID access type mapping table, determining that the write access type is universal memory access; if not, determining that the write access type is non-universal memory access.

9. The AXI bus memory access acceleration method according to claim 1, wherein: When the access request is a read access request, the AXI bus memory access acceleration method for the read access request includes: Get read access request of AXI bus; Performing address memory access arbitration on the read access request according to a preset memory address range to determine whether the read access request is a memory unit access; When the read access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a general memory access; When the ID memory access is a universal memory access, a read access request for the universal memory access is responded to through a channel connecting the memory port to the memory unit.

10. The AXI bus memory access acceleration method according to claim 9, wherein: Performing address memory access arbitration on the read access request according to a preset memory address range, and determining whether the read access request is a memory unit access includes: receiving the read access request; Preset memory address range; Obtaining the address of the read access request; The obtained address of the read access request is compared with the preset memory address range, and it is determined whether the address of the read access request is within the memory address range, and an operation is performed.

11. The AXI bus memory access acceleration method according to claim 9, wherein: When the read access request is a memory unit access, performing ID memory access arbitration according to a preset ID signal access type, and determining whether the ID memory access type of the address memory access is a general memory access includes: When the read access request is a memory cell access, Obtaining a read access ID for the memory unit access request; Comparing the read access ID with a preset ID access type mapping table, and determining whether the access type of the read access request is general memory access; The method comprises: when the read access ID is an ID corresponding to the universal memory access type in the ID access type mapping table, determining that the read access type is universal memory access; if not, determining that the read access type is non-universal memory access.

12. An AXI bus memory access acceleration device, characterized in that: include: Instruction acquisition module, used to obtain access requests of the AXI bus; A first access arbitration module, configured to perform address memory access arbitration on the access request according to a preset memory address range, and extract an address accessed by a memory unit; A second access arbitration module is used to perform ID memory access arbitration based on the result of the address memory access arbitration and in combination with a preset ID signal access type; The instruction response module is used to respond to the access request of the universal memory access through the channel connecting the memory port to the memory unit according to the result of the ID memory access arbitration when the ID memory access is a universal memory access.

13. An AXI bus memory access acceleration system, characterized in that: include: A master device, configured to initiate an access transaction to a slave device; wherein the master device comprises an instruction acquisition module configured to acquire an access request from an AXI bus; a first access arbitration module configured to perform address memory access arbitration on the access request according to a preset memory address range and extract the address of the memory unit access; a second access arbitration module configured to perform ID memory access arbitration based on the result of the address memory access arbitration and in combination with a preset ID signal access type; and an instruction response module configured to respond to the access request for the universal memory access via a channel connected to the memory unit via a memory port based on the result of the ID memory access arbitration and when the ID memory access is a universal memory access. A slave device is configured to respond to the master device.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

15. An electronic terminal, characterized in that: include: processor and memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory, so as to enable the terminal to perform the method according to any one of claims 1 to 11.

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