Hot-swap control system and method, electronic device, and storage medium

Abstract

The present disclosure provides a hot-swap control system and method, an electronic device, and a storage medium. A hardware detection module obtains target slot status information through a target controller, wherein the target slot status information includes the in-place status information of the target device and the port information of the integrated port where the target device is located. An information management module uses a multi-level storage architecture to store the target slot status information obtained by the hardware detection module. The multi-level storage architecture includes a temporary storage layer and a persistent storage layer. The port information is stored in the temporary storage layer, and the in-place status information is registered in the persistent storage layer. A control execution module dynamically configures the hot-swap controller register corresponding to the integrated port based on a preset interface, enabling or disabling the hot-swap controller function of the integrated port. Compared with related technologies, the present disclosure dynamically configures the SHPC register through a preset interface to achieve differentiated control of port-level hot-swap functions.

Description

Technical Field

[0001] The present disclosure relates to the field of server technology, and in particular to a hot-swap control system and method, an electronic device, and a storage medium. Background Art

[0002] The Peripheral Component Interconnect Express (PCIe) bus, as a core standard for connecting high-speed peripherals in modern server architectures, is widely used in high-performance computing, cloud computing, and enterprise-class storage systems. Its hot-swap functionality is crucial for ensuring high system availability and flexible maintenance. Current mainstream hot-swap management systems utilize native hot-swap control in conjunction with a Standard Hot Plug Controller (SHPC), covering the entire process from hardware status detection and firmware information management to operating system control. The SHPC controller, a dedicated hardware module, provides granular hot-swap process control and status feedback. However, related technologies often employ a unified strategy for enabling or disabling the SHPC, without differentiated configuration based on device type and physical topology. This reduces system compatibility and increases the risk of misoperation. Furthermore, they rely on manual register configuration and lack the ability to automatically identify device status. This leads to inconsistent topology information processing across heterogeneous CPU architectures, which can easily cause information conflicts between the BIOS and operating system and platform compatibility issues. Summary of the Invention

[0003] This disclosure provides a hot-swap control system and method, electronic device, and storage medium. Its primary purpose is to address the problem that related technologies often adopt a unified strategy for enabling or disabling SHPC, without differentiated configuration based on device type and physical topology, resulting in reduced system compatibility or increased risk of misoperation.

[0004] According to a first aspect of the present disclosure, a hot-swap control system is provided, the system comprising: a hardware detection module, an information management module, and a control execution module;

[0005] The hardware detection module obtains the target slot status information through the target controller, wherein the target slot status information includes the in-position status information of the target device and the port information of the integrated port where the target device is located;

[0006] The information management module uses a multi-level storage architecture to store the target slot status information obtained by the hardware detection module. The multi-level storage architecture includes a temporary storage layer and a persistent storage layer. The port information is saved in the temporary storage layer, and the in-place status information is registered in the persistent storage layer.

[0007] The control execution module dynamically configures the hot-swap controller register corresponding to the integrated port based on the preset interface, and enables or disables the hot-swap controller function of the integrated port.

[0008] Optionally, the target controller determines the presence status of the target device by detecting bandwidth allocation information of the target slot and generates presence status information.

[0009] Optionally, the hardware detection module executes a dynamic port mapping algorithm to parse the processor number and physical slot location of the target device, and stores the integrated port information in a normalized manner in a temporary storage layer.

[0010] Optionally, the persistent storage layer includes an ACPI table, registered target device presence status, and integrated port mapping relationships to form a namespace accessible to the operating system.

[0011] Optionally, the preset interface includes an interaction method defined in the ACPI specification, and the control execution module reads the in-place status information registered by the persistent storage layer through the preset interface.

[0012] Optionally, the dynamic configuration includes: obtaining in-place status information of the target device and corresponding integrated port information based on an interactive method, and enabling or disabling a hot-swap controller function of a specified integrated port.

[0013] Optionally, dynamic configuration uses a conditional enabling strategy, including:

[0014] Obtain the physical topology identifier of the target device through the preset interface;

[0015] Inject the control buffer after structured encoding;

[0016] Trigger the state machine of the hot-swap controller based on the topology parameters.

[0017] Optionally, enable safety protection mechanisms when configuring the hot-swap controller registers, including:

[0018] Use memory mapped input and output (MMIO) access mode to implement write protection for hot-swap controller registers;

[0019] After configuration is complete, read back the register status to confirm that the function is effective;

[0020] Perform parameter range validation and error handling logic.

[0021] Optionally, register write protection includes: 64-bit alignment of the access address and atomic operation guarantee.

[0022] Optionally, the target controller is a complex programmable logic device.

[0023] According to a second aspect of the present disclosure, a hot plug control method is provided, comprising:

[0024] Detecting the in-position status information of the target device and the port information of the integrated port where the target device is located through the target controller;

[0025] Store the port information in the temporary storage layer and register the in-place status information in the ACPI table of the persistence layer;

[0026] The operating system calls a preset interface to read the in-place status information and dynamically configures the hot-swap controller register corresponding to the integrated port.

[0027] Optionally, the target controller includes a complex programmable logic device; detecting the in-place status information of the target device through the target controller includes:

[0028] Monitor bandwidth allocation information of target slots;

[0029] Analyze the electrical characteristic parameters of the target device;

[0030] Call the preset device feature library to identify the device type of the target device.

[0031] Optionally, after detecting the port information, dynamic port mapping operations are performed, including:

[0032] Analyze the processor number and physical slot location of the target device;

[0033] Normalize the integrated port information under the heterogeneous processor architecture and store it in the temporary storage layer.

[0034] Optionally, the ACPI table registration operation of the persistence layer includes:

[0035] The mapping relationship between the target device status and the integrated port is encapsulated into a standard ACPI data structure; and a namespace accessible to the operating system is generated.

[0036] Optionally, the preset interface includes an interaction method defined in the ACPI specification, and the dynamic configuration operation includes:

[0037] Enables or disables the hot-swap controller function for a specified integrated port based on the target device presence and device type.

[0038] Optionally, dynamic configuration uses a conditional enabling strategy, including:

[0039] Obtain the physical topology identifier of the target device through the preset interface;

[0040] The topology identifier is structurally encoded and injected into the control buffer;

[0041] Triggers the state machine of the hot-swap controller based on the buffer parameters.

[0042] Optionally, enable safety protection mechanisms when configuring the hot-swap controller registers, including:

[0043] Use memory-mapped input and output to access registers and ensure that the access address is 64-bit aligned;

[0044] After configuration is complete, read back the register status to verify that the function is effective;

[0045] Perform parameter range validation and exception error handling.

[0046] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0047] at least one processor; and

[0048] a memory communicatively connected to the at least one processor; wherein,

[0049] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the hot plug control method described in the second aspect.

[0050] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the hot-swap control method described in the second aspect.

[0051] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the hot-swap control method as described in the second aspect.

[0052] The present disclosure provides a hot-swap control system and method, an electronic device and a storage medium. The hardware detection module of the present disclosure obtains slot status information in real time through a target controller, including device in-place status and port topology data. This design replaces the traditional manual configuration method to achieve automatic identification of device insertion / removal, and is particularly suitable for dynamic management scenarios of multiple slots under heterogeneous CPU architectures. The information management module adopts a hierarchical storage mechanism of a temporary storage layer and a persistent storage layer. The physical information of the port is temporarily stored in the temporary storage layer for fast access, and the in-place status information is registered to the ACPI Table for long-term call by the operating system. This design can not only meet the real-time data interaction requirements between the BIOS firmware and the operating system, but also ensure cross-platform compatibility through the ACPI specification, solving the problem of easy loss or inconsistency of information in related technologies. The control execution module dynamically configures the SHPC register through a preset interface to achieve differentiated control of the port-level hot-swap function.

[0053] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0055] Figure 1 A schematic diagram of the structure of a hot-swap control system provided by an embodiment of the present disclosure;

[0056] Figure 2 A flowchart of a hot-swap control method provided by an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0057] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0058] The following describes a hot-swap control system and method, an electronic device, and a storage medium according to embodiments of the present disclosure with reference to the accompanying drawings.

[0059] Figure 1 This is a schematic diagram of the structure of a hot-swap control system provided by an embodiment of the present disclosure. The system includes: a hardware detection module 11, an information management module 12, and a control execution module 13;

[0060] The hardware detection module 11 obtains target slot status information through the target controller, wherein the target slot status information includes in-place status information of the target device and port information of the integrated port where the target device is located.

[0061] In the disclosed embodiments, the hardware detection module serves as the core component of the system for acquiring basic PCIe device status information. Its core function is to monitor and collect information about the target PCIe slot status in real time through the target controller. The collected target slot status information specifically includes two key aspects: first, the target device's in-slot status information. This information determines whether the target PCIe device (such as an accelerator card or storage device) is physically connected to the slot and is in a valid connection state by detecting parameters such as the slot's electrical characteristics and signal connection status; and second, the port information of the integrated port where the target device resides. This information is used to accurately locate the device's position in the system architecture, including but not limited to the integrated port number, processor domain, and physical topological location. The hardware detection module automatically collects slot status through the target controller. This eliminates reliance on manual configuration and avoids potential errors caused by manual judgment, improving the accuracy and real-time nature of device status detection. Furthermore, the collected port information provides a foundation for the subsequent system to implement differentiated management of different devices, ensuring precise control of devices in different locations and laying the hardware awareness foundation for the dynamic adaptability of the entire hot-swap control system.

[0062] The information management module 12 uses a multi-level storage architecture to store the target slot status information obtained by the hardware detection module 11. The multi-level storage architecture includes a temporary storage layer and a persistent storage layer. The port information is saved to the temporary storage layer, and the in-place status information is registered in the persistent storage layer.

[0063] In the disclosed embodiments, the information management module is responsible for systematically storing and managing the target slot status information obtained by the hardware detection module. It implements hierarchical processing of different types of status information through a multi-level storage architecture. This multi-level storage architecture comprises at least two layers: a temporary storage layer and a persistent storage layer. The temporary storage layer stores the port information of the integrated port where the target device resides, ensuring the system's rapid access and dynamic update requirements for location information. The persistent storage layer registers the target device's in-place status information, ensuring that this critical status data is stably stored and continuously queryable throughout the system's operating cycle. The multi-level storage architecture enables categorized storage and differentiated management of status information. The temporary storage layer's rapid processing of port information ensures the system's real-time response efficiency when device topology changes occur. The persistent storage layer's stable registration of in-place status information provides a reliable information query basis for the operating system and upper-level applications, avoiding control logic errors caused by information loss or inconsistencies. Furthermore, the hierarchical storage mechanism reduces the coupling between the storage and access of different types of information, improving the system's flexibility and reliability in managing status information and providing data support for dynamic decision-making in the subsequent control execution layer.

[0064] The control execution module 13 dynamically configures the hot-swap controller register corresponding to the integrated port based on the preset interface, and enables or disables the hot-swap controller function of the integrated port.

[0065] In the embodiments of the present disclosure, the control execution module serves as the core unit for the system to dynamically control the hot-swap function. Its primary function is to dynamically configure the hot-swap controller registers corresponding to the integrated port based on a preset standardized interface, thereby enabling or disabling the hot-swap controller function of the integrated port according to actual needs. The preset interface provides a unified standard for interaction between the system and the hot-swap controller, ensuring the accurate transmission and execution of configuration instructions. Dynamic configuration of the registers directly affects the operating state of the hot-swap controller, enabling precise control of the hot-swap function of the integrated port. The control execution module dynamically configures the hot-swap controller registers through the preset interface. This eliminates the need for manual register modification, reduces errors caused by human intervention, and improves the efficiency and accuracy of hot-swap function configuration. Furthermore, it can flexibly enable or disable the hot-swap controller function based on the actual needs of the integrated port, supporting differentiated configurations for different integrated ports and enhancing the system's adaptability to diverse devices and application scenarios. Furthermore, the standardized preset interface reduces compatibility issues between the system and different types of hot-swap controllers and operating systems, ensuring stable system operation.

[0066] The present disclosure provides a hot-swap control system. The hardware detection module 11 of the present disclosure obtains slot status information, including device presence status and port topology data, in real time through a target controller. This design replaces traditional manual configuration methods and enables automatic identification of device insertion / removal, making it particularly suitable for dynamic management of multiple slots in heterogeneous CPU architectures. The information management module 12 utilizes a layered storage mechanism with a temporary storage layer and a persistent storage layer. Port physical information is temporarily stored in the temporary storage layer for fast access, while presence status information is registered in the ACPI table for long-term access by the operating system. This design not only meets the requirements for real-time data exchange between the BIOS firmware and the operating system, but also ensures cross-platform compatibility through the ACPI specification, resolving the issue of information loss or inconsistency in related technologies. The control execution module 13 dynamically configures the SHPC registers through a preset interface to achieve differentiated control of port-level hot-swap functionality. By defining a unified hardware abstraction interface, this solution shields underlying hardware differences, allowing the operating system to adapt to SHPC implementations from different vendors without modification.

[0067] As a specific implementation manner, the target controller determines the in-place status of the target device by detecting bandwidth allocation information of the target slot and generates in-place status information.

[0068] During implementation, the target controller monitors and analyzes the target PCIe slot's bandwidth allocation information in real time to determine the target device's presence and generates corresponding presence status information. Bandwidth allocation information is a key parameter reflecting the connection status between the PCIe slot and the device. Changes in bandwidth allocation information directly correlate to whether the device is physically connected to the slot and has established a valid communication link. When a target device is inserted into a slot and initialized, the slot's bandwidth allocation exhibits specific configuration characteristics. The target controller captures these characteristics to determine if the device is present. Conversely, if no bandwidth allocation characteristics matching the device's presence are detected, the device is deemed absent.

[0069] Using bandwidth allocation information as the basis for judgment can directly reflect the actual communication status between the device and the slot. Compared with the judgment method that simply relies on mechanical detection or a single signal, it improves the accuracy of in-place status identification.

[0070] As a specific implementation, the hardware detection module 11 executes a dynamic port mapping algorithm to analyze the processor number and physical slot location of the target device, and stores the integrated port information in a normalized manner in a temporary storage layer.

[0071] During implementation, the hardware detection module executes a dynamic port mapping algorithm to resolve the processor number and corresponding physical slot location of the target device. It then normalizes the integrated port information obtained and stores it in a temporary storage layer. Specifically, the dynamic port mapping algorithm first uses topology mapping logic to identify and locate the processor domain (such as CPU0 / CPU1) and physical slot location of the device, clarifying the physical distribution of the device within the system hardware architecture. Subsequently, to address the potential differences in slot information under heterogeneous processor architectures, dynamic remapping technology is used to standardize the identification information of the integrated port (such as port number, link allocation parameters, etc.), eliminating information format differences under different architectures. Finally, the normalized integrated port information is uniformly stored in a temporary storage layer (such as the PCD (Platform Configuration Database)), forming standardized topology data for subsequent modules to call.

[0072] This implementation method achieves accurate parsing and normalized management of integrated port information through a dynamic port mapping algorithm: on the one hand, through the combination of topology mapping and dynamic remapping, it solves the problem of inconsistent slot information under heterogeneous processor architecture, ensuring the uniformity and accuracy of integrated port information at the system level; on the other hand, the normalized information is stored in a temporary storage layer, providing a standardized data foundation for the hierarchical storage of the information management layer and the dynamic configuration of the control execution layer, reducing the information format conversion cost in cross-module interaction.

[0073] As a specific implementation, the persistent storage layer includes an ACPI table, and the registered target device presence status and integrated port mapping relationship form a namespace accessible to the operating system.

[0074] During implementation, the persistent storage layer includes an ACPI table (Advanced Configuration and Power Interface Table). The target device's on-site status and integrated port mapping relationships obtained by the hardware detection module are processed and registered in the ACPI table. Based on this registration information, a namespace accessible to the operating system is formed. Specifically, the target device's on-site status (such as whether it is physically connected to a PCIe slot) and the integrated port mapping relationship (such as the correspondence between the device's processor number, physical slot location, and integrated port) are structured and encoded and written into the ACPI table to achieve persistent storage of the information. At the same time, the ACPI table maps this information to a namespace recognizable to the operating system through preset specifications, enabling the operating system to query device status and port-related information through a standardized interface.

[0075] This implementation uses the ACPI table to build a persistent storage layer and form a namespace accessible to the operating system. On the one hand, the ACPI table, as a storage medium that complies with industry standards, ensures the stable storage of device status and port mapping relationships, avoiding the risk of information loss or tampering. On the other hand, the namespace accessible to the operating system provides a unified information interaction interface between upper-level software and underlying hardware, eliminating the differences in hardware information acquisition methods among different operating systems and improving system compatibility.

[0076] As a specific implementation, the preset interface includes an interaction method defined in the ACPI specification, and the control execution module 13 reads the in-place status information registered by the persistent storage layer through the preset interface.

[0077] During the specific implementation process, the preset interface includes an interaction method that complies with the definition of the ACPI (Advanced Configuration and Power Interface) specification. The control execution module reads the target device presence status information registered in the persistent storage layer through the preset interface. Specifically, the interaction methods defined by the ACPI specification include the standardized _OSC (Operating System Control) interaction mechanism and the customized ACPI Method. These methods constitute the communication link between the control execution module and the persistent storage layer. During operation, the control execution module relies on the above-mentioned interaction method and accesses the target device presence status information registered in the persistent storage layer (such as the ACPI table) in accordance with the data flow rules under the ACPI specification framework. This information is structured and stored in the specified field of the ACPI table, and a resolvable access path is provided to the control execution module through the ACPI namespace to ensure the standardization and accuracy of the information reading process.

[0078] By building a preset interface through the interaction method defined by the ACPI specification, the control execution module can reliably read the persistent storage layer information: On the one hand, as an industry standard, the ACPI specification unifies the information interaction format between the control execution module and the persistent storage layer, solves the problem of interface incompatibility under different hardware platforms or operating systems, and improves the system's cross-platform adaptability; on the other hand, the standardized interaction method ensures the accuracy and stability of in-place status information reading, avoids information misreading or loss due to interface differences, and provides a reliable decision-making basis for the control execution module to subsequently dynamically configure the hot-swap controller registers.

[0079] As a specific implementation, the dynamic configuration includes: obtaining the in-place status information of the target device and the corresponding integrated port information based on an interactive method, and enabling or disabling the hot-swap controller function of the specified integrated port.

[0080] In specific implementations, dynamic configuration is achieved as follows: the control execution module relies on a preset interaction method to obtain the target device's presence status information (such as whether the device is physically connected to a PCIe slot) and the device's corresponding integrated port information (such as the port number, processor domain, etc.) from the persistent storage layer, and based on this information, enables or disables the hot-swap controller function of the specified integrated port. Specifically, the interaction method follows the standardized communication mechanism within the ACPI specification framework (such as the _OSC interaction method). The control execution module uses this method to query the registered device presence status and port mapping relationship from the ACPI table to identify the integrated port that needs to be configured. Subsequently, based on the device's presence status (present / absent) and the characteristic parameters of the integrated port, the hot-swap controller register corresponding to the port is configured specifically. When the device is present and needs to support hot-swap functionality, the hot-swap controller is enabled by writing a register instruction; when the device is absent or hot-swap functionality is not required, the function is disabled through register configuration.

[0081] As a specific implementation method, dynamic configuration adopts a conditional enabling strategy, including: obtaining the physical topology identifier of the target device through a preset interface; injecting the structured encoding into the control buffer; and triggering the state machine of the hot-swap controller based on the topology parameters.

[0082] During the specific implementation process, the conditional enabling strategy adopted by dynamic configuration is realized through the following steps: First, the control execution module obtains the physical topology identifier of the target PCIe device with the help of a preset interface (an interaction method that complies with the ACPI specification). This identifier contains key information such as the socket domain where the device is located, the address of the corresponding integrated port, and the lane allocation parameters, which is used to accurately locate the position of the device in the system hardware architecture; then, the above physical topology identifier is structured and encoded according to the PCI Firmware Specification specification to form a standardized data format and injected into the control buffer defined by the operating system control (_OSC) to ensure the integrity and compatibility of the data during transmission; finally, based on the physical characteristic parameters of the slot in the physical topology identifier, the system triggers the compliance state machine of the hot-swap controller (SHPC), and through the logical judgment and action execution of the state machine, completes the strategic enabling or disabling of the hot-swap controller function of the specified integrated port.

[0083] As a specific implementation method, a security protection mechanism is enabled when configuring the hot-swap controller registers, including: using a memory-mapped input / output (MMIO) access method to implement write protection for the hot-swap controller registers; reading back the register status after configuration is completed to confirm that the function is effective; and executing parameter range verification and error handling logic.

[0084] In its implementation, the security protection mechanism enabled when configuring the hot-swap controller registers ensures the security and reliability of register operations through multi-dimensional technical means, including the following: 1. Memory-mapped input / output (MMIO) access for write protection: When configuring the hot-swap controller registers, the system establishes a communication link between the processor and the registers through MMIO, strictly adhering to 64-bit address alignment rules and using atomic operations to ensure the indivisibility of instruction execution. This access method prevents unauthorized writes or misoperations to registers through hardware-level address mapping and operation specifications, thus implementing write protection for registers at the bottom level.

[0085] 2. After configuration is complete, read back the register status to confirm that the function has taken effect: After the register configuration command is issued, the system immediately performs a status verification readback operation, rereading the current register value and comparing it with the expected configuration value. If the two are consistent, the configuration function is confirmed to have taken effect correctly. If there is a discrepancy, the exception handling process is triggered to ensure the accuracy of the configuration result.

[0086] 3. Execute parameter range verification and error handling logic: During configuration, the system first performs range verification on input configuration parameters (such as port numbers and enable / disable instructions) to prevent register anomalies caused by parameter out-of-bounds. Simultaneously, write protection is enabled to further block illegal operations. If readback verification detects an error or parameter verification fails, the system initiates pre-defined error handling logic, including but not limited to logging error information and restoring registers to default states, to prevent misconfiguration from impacting the hot-swap controller's functionality and overall system stability.

[0087] As a specific implementation, register write protection includes: 64-bit alignment of the access address and atomic operation guarantee.

[0088] In practice, register write protection is achieved through 64-bit alignment of access addresses and atomic operations. 64-bit address alignment requires that when accessing hot-swap controller registers, all operation addresses must be aligned to 64-bit boundaries, meaning the lower six bits of the access address are zero. This ensures accurate address resolution in memory-mapped input / output (MMIO) mode and prevents access anomalies or data truncation due to address misalignment. Atomic operations ensure that register write instructions are executed as indivisible units, uninterrupted by other processes or interrupts during instruction execution. This ensures the integrity and consistency of written data and prevents register value confusion caused by multi-threading or concurrent operations.

[0089] As a specific implementation, the target controller is a complex programmable logic device.

[0090] In specific implementations, the target controller used to detect target slot status information is a complex programmable logic device (CPLD). This device, through hardware-level logic circuit design, monitors the PCIe slot's bandwidth allocation in real time, analyzes the slot's electrical characteristics (such as signal levels and connection stability), and identifies the target device's presence based on pre-set logical judgment rules. Furthermore, the CPLD interacts with other hardware modules in the system (such as the processor and storage unit) through built-in interface circuitry, transmitting the detected target device's presence status and corresponding integrated port (IIOPort) information to the hardware detection module, providing raw data for subsequent information storage and control execution.

[0091] Figure 2 A flowchart of a hot-swap control method provided by an embodiment of the present disclosure is provided.

[0092] like Figure 2 As shown, the method comprises the following steps:

[0093] Step 201: Detecting the in-place status information of the target device and the port information of the integrated port where the target device is located through the target controller.

[0094] In the embodiment of the present disclosure, step 201 serves as the initial step for the system to obtain basic status information of the target device. Its core operation is to detect the target device's in-place status information and the port information of the integrated port where the device is located through the target controller. The in-place status information is used to indicate whether the target device is physically connected to the corresponding slot and is in an effective communication state; the port information of the integrated port is used to locate the specific position of the device in the system hardware architecture, including but not limited to key information such as the identification of the integrated port to which the device is connected and the processor domain to which it belongs. The target controller completes the real-time collection and preliminary processing of the above two types of information through hardware-level signal monitoring and logical judgment.

[0095] This step uses the target controller to automatically detect device status and port information. This eliminates manual troubleshooting, reduces errors caused by human judgment, and ensures information accuracy. Furthermore, the collected in-place status and port information provides raw data support for information storage and function configuration in subsequent steps, laying the foundation for intelligent hot-swap management. Furthermore, the real-time detection mechanism rapidly responds to device plugging and unplugging, ensuring the system's timely awareness of device status changes and laying the foundation for improved dynamic and timely hot-swap control.

[0096] Step 202: Store the port information in a temporary storage layer, and register the in-place status information in the ACPI table of the persistence layer.

[0097] In the disclosed embodiment, step 202 primarily implements differentiated storage management for the two types of information detected in the previous steps: storing the port information for the integrated port where the target device resides in a temporary storage layer, and simultaneously registering the target device's presence status information in the ACPI table in the persistent layer. The temporary storage layer temporarily stores port information, meeting the system's requirements for rapid access and dynamic updates to location information; the ACPI table in the persistent layer provides a stable storage medium for the presence status information, ensuring that it can be continuously queried and accessed throughout the system's operating cycle.

[0098] This step achieves organized and targeted information management through hierarchical storage of different types of information. The temporary storage layer rapidly stores and updates port information, ensuring the system's real-time responsiveness to hardware topology changes. The ACPI table registers in-place status information, providing a standardized information query interface for the operating system and upper-layer applications, ensuring information reliability and accessibility. This hierarchical storage mechanism reduces the coupling of information management, providing accurate and efficient data support for the dynamic configuration of subsequent control execution links, and improving the system's processing efficiency and utilization value of information.

[0099] Step 203: The operating system calls a preset interface to read the in-place status information and dynamically configures the hot-swap controller register corresponding to the integrated port.

[0100] In the disclosed embodiment, step 203 primarily involves the operating system invoking a pre-set interface to read the stored target device presence status information and, based on this information, dynamically configuring the hot-swap controller registers corresponding to the integrated port where the target device resides. The pre-set interface provides standardized interaction between the operating system and the underlying hardware, ensuring accurate reading of presence status information. Dynamic configuration involves making targeted settings in the hot-swap controller registers of the integrated port based on the read presence status (e.g., whether the device is present), thereby enabling or disabling the hot-swap function for that port.

[0101] By combining the operating system's call to a preset interface with dynamic configuration registers, automated hot-swap control is achieved. On the one hand, the use of the preset interface ensures reliable access to the operating system's in-place status information, eliminating compatibility barriers to information exchange across different system environments. On the other hand, dynamic configuration based on in-place status replaces manual intervention, enabling the hot-swap function to automatically adjust based on the device's actual state, improving the system's adaptability to device changes. Furthermore, this step, as a key link between the information management layer and the hardware execution layer, ensures the consistency and efficiency of the hot-swap control process, supporting the overall flexibility and maintainability of the system.

[0102] The present disclosure provides a hot-swap control method. The hardware detection module 11 of the present disclosure obtains slot status information, including device presence status and port topology data, in real time through a target controller. This design replaces traditional manual configuration methods, enabling automatic identification of device insertion / removal and is particularly suitable for dynamic management of multiple slots in heterogeneous CPU architectures. The information management module 12 utilizes a layered storage mechanism with a temporary storage layer and a persistent storage layer. Port physical information is temporarily stored in the temporary storage layer for fast access, while presence status information is registered in the ACPI table for long-term access by the operating system. This design not only meets the requirements for real-time data exchange between the BIOS firmware and the operating system, but also ensures cross-platform compatibility through the ACPI specification, resolving the issue of information loss or inconsistency in related technologies. The control execution module 13 dynamically configures the SHPC registers through a preset interface to achieve differentiated control of port-level hot-swap functionality. By defining a unified hardware abstraction interface, this solution shields underlying hardware differences, allowing the operating system to adapt to SHPC implementations from different vendors without modification.

[0103] Furthermore, in a possible implementation of this embodiment, the target controller includes a complex programmable logic device; the target controller detects the in-place status information of the target device, including: monitoring the bandwidth allocation information of the target slot; analyzing the electrical characteristic parameters of the target device; and calling a preset device feature library to identify the device type of the target device.

[0104] In specific implementation, the target controller utilizes a complex programmable logic device (CPLD) to acquire target device presence information through a multi-dimensional detection mechanism. This includes the following operations: 1. Monitoring the target slot's bandwidth allocation: The CPLD uses hardware logic circuitry to collect the target PCIe slot's bandwidth allocation parameters, including link width and transmission rate, in real time. These parameters dynamically change with the device's connection status and serve as a basis for determining whether the device is present. 2. Analyzing the target device's electrical characteristics: The CPLD continuously monitors and analyzes the slot's electrical characteristics, such as voltage, current, and signal integrity. By analyzing the changing characteristics of these electrical parameters (e.g., current surges upon device connection and signal level stability intervals), it helps determine the device's physical connection status. 3. Identifying the target device's type by invoking a pre-built device signature library: The system pre-builds a device signature library containing characteristic parameters for various PCIe devices (such as GPU accelerator cards, NVMe solid-state drives, and high-speed network adapters). The CPLD integrates the detected bandwidth allocation information with the electrical characteristics and compares them with the device signatures in the signature library to accurately identify the target device type, providing a basis for subsequent differentiated configuration.

[0105] Furthermore, in a possible implementation of this embodiment, after detecting the port information, a dynamic port mapping operation is performed, including: parsing the processor number and physical slot position of the target device; normalizing the integrated port information under the heterogeneous processor architecture and storing it in a temporary storage layer.

[0106] In the specific implementation process, after detecting and obtaining the port information of the integrated port where the target device is located, the system performs a dynamic port mapping operation. This operation is achieved through the following steps: 1. Resolving the processor number and physical slot location of the target device: The system uses a topology mapping algorithm to resolve the port information, determine the processor number (such as CPU0 or CPU1) to which the target device is connected, and locate the physical location of the PCIe slot corresponding to the device in the system hardware architecture, thus forming a preliminary topological identification of the device in a multi-processor environment. 2. Normalizing the integrated port information in heterogeneous processor architectures and storing it in a temporary storage layer: To address the issue of different PCIe slot information formats in different processor domains in heterogeneous CPU architectures, the system uses dynamic remapping technology to standardize the parsed integrated port information (including port numbers, link allocation parameters, etc.), eliminating information inconsistencies caused by architectural differences. The normalized topological data is uniformly stored in a temporary storage layer (such as the Platform Configuration Database (PCD)), forming standardized data that can be directly called by subsequent modules.

[0107] Furthermore, in a possible implementation of this embodiment, the ACPI table registration operation of the persistence layer includes: encapsulating the mapping relationship between the target device presence status and the integrated port into a standard ACPI data structure; and generating a namespace accessible to the operating system.

[0108] In specific implementation, the ACPI table registration operation at the persistence layer is accomplished through the following steps: 1. Encapsulation into a standard ACPI data structure: The system encapsulates the mapping between the target device's presence status (e.g., whether it is physically connected to a PCIe slot) and the device's integrated port (including information such as the device's integrated port number, processor domain, and physical topological location) in a structured manner according to the ACPI (Advanced Configuration and Power Interface) specification, creating an industry-standard data structure. This data structure ensures standardized transmission of hardware status information between the firmware and the operating system. 2. Generation of an operating system-accessible namespace: After completing the data structure encapsulation, the system registers the encapsulated information in the ACPI table and, based on the ACPI table specification, generates a namespace directly accessible to the operating system. This namespace, through unified identifiers and paths, enables the operating system to query the target device's presence status and corresponding integrated port information through pre-defined interfaces (e.g., ACPI Methods), thus transparently transmitting underlying hardware information to the operating system.

[0109] Furthermore, in a possible implementation of this embodiment, the preset interface includes an interaction method defined in the ACPI specification, and the dynamic configuration operation includes: enabling or disabling a hot-swap controller function of a specified integrated port based on the in-place status and device type of the target device.

[0110] In its implementation, the default interface uses interaction methods compliant with the ACPI (Advanced Configuration and Power Interface) specification (e.g., the _OSC (Operating System Control) interaction method). Dynamic configuration operations leverage this interface to precisely control the hot-swap controller function. Specifically, the following steps are included: 1. Information acquisition based on the ACPI specification interaction method: The operating system uses the ACPI specification interaction method to read the registered target device's presence status (e.g., whether the device is physically connected to a PCIe slot) and device type information (e.g., GPU accelerator card, NVMe solid-state drive, etc.) from the ACPI table. This interaction method adheres to the PCI Firmware Specification, ensuring compliance and compatibility. 2. Targeted enabling or disabling of the hot-swap controller function: The system configures the hot-swap controller (SHPC) function for a specific integrated port based on the acquired target device's presence status and device type. When a device is present and its type supports SHPC, the SHPC function is enabled by configuring the corresponding integrated port's hot-swap controller registers. When a device is absent or its type does not support SHPC, the function is disabled through register configuration to avoid inefficient resource usage.

[0111] Furthermore, in a possible implementation of this embodiment, the dynamic configuration adopts a conditional enabling strategy, including: obtaining the physical topology identifier of the target device through a preset interface; injecting the topology identifier into the control buffer after structured encoding; and triggering the state machine of the hot-swap controller based on the buffer parameters.

[0112] In practice, the conditional enablement strategy employed by dynamic configuration relies on pre-defined interfaces and standardized data processing flows, specifically including the following operations: 1. Obtaining the target device's physical topology identifier: The operating system retrieves the target PCIe device's physical topology identifier from the ACPI table through a pre-defined interface (an interaction method compliant with the ACPI specification). This identifier contains key information such as the device's socket domain, the address of the corresponding integrated port, and lane allocation parameters, enabling precise identification of the device's physical distribution and connectivity within the system's hardware architecture. 2. Structured encoding and control buffer injection: The system encodes the obtained physical topology identifier in accordance with the PCI Firmware Specification, converting it into standardized data that conforms to the Hot Swap Controller (SHPC) data exchange format. This encoded information is then injected into the control buffer defined by the Operating System Control (OSC) to ensure data integrity and format compatibility during transmission. 3. Triggering the Hot Swap Controller state machine based on buffer parameters: The Hot Swap Controller (SHPC) triggers its internal compliance state machine based on the physical topology parameters in the control buffer (such as slot physical characteristics and port link configuration). The state machine analyzes the parameters through preset logical judgment rules, automatically executes the operation of enabling or disabling the hot-swap function, and realizes the strategic management and control of the hot-swap controller function of the specified integrated port.

[0113] Furthermore, in a possible implementation of this embodiment, a security protection mechanism is enabled when configuring the hot-swap controller register, including: accessing the register using a memory-mapped input and output method, and ensuring that the access address is 64-bit aligned; reading back the register status after the configuration is completed to verify that the function is effective; performing parameter range verification and exception error handling.

[0114] During implementation, the security protection mechanism enabled during hot-swap controller register configuration utilizes multi-layered technical measures to ensure the security and accuracy of the configuration process. These include the following: 1. Memory-mapped input / output (MMIO) and 64-bit address alignment for register access: The system accesses hot-swap controller registers via memory-mapped input / output (MMIO). This method maps register addresses to the system memory address space, allowing the processor to directly manipulate the registers through memory access instructions. Furthermore, 64-bit alignment of the accessed addresses is strictly ensured, with the lower six bits of the address value being zero, complying with the hardware interface specification's address boundary requirements. This prevents access anomalies or data transmission errors caused by misaligned addresses. 2. A register status readback verification function is activated after configuration is complete: After writing a configuration instruction (such as enabling or disabling hot-swap functionality) to the hot-swap controller register, the system immediately performs a readback operation to compare the current register status with the expected configuration value. If the two values ​​match, the configuration is confirmed to have taken effect. If they differ, the configuration is deemed a failure and subsequent processing is triggered to ensure the accuracy of the configuration results. 3. Parameter range verification and exception error handling: Before issuing configuration commands, the system performs range verification on input parameters (such as port numbers and configuration command codes) to check whether the parameters are within the preset valid range. This prevents register misconfiguration due to parameter out-of-bounds. At the same time, register write protection is enabled to block unauthorized write operations. If readback verification detects an error or parameter verification fails, the system initiates the preset exception error handling logic, including error logging and restoring registers to default states, to prevent incorrect configuration from impacting the hot-swap controller's functionality and system stability.

[0115] It should be noted that the embodiments of the present disclosure may include multiple steps. For the convenience of description, these steps are numbered, but these numbers do not limit the execution time slots or execution order between the steps; these steps can be implemented in any order, and the embodiments of the present disclosure do not limit this.

[0116] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned hot-swap control method embodiments.

[0117] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned hot-swap control method embodiments when running.

[0118] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0119] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above hot-swap control method embodiments are implemented.

[0120] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned hot-swap control method embodiments are implemented.

[0121] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0122] The above is a detailed introduction to a hot-swap control system and method, electronic device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core idea of ​​the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A hot-swap control system, characterized in that: The system includes: a hardware detection module, an information management module, and a control execution module; The hardware detection module obtains target slot status information through the target controller, wherein the target slot status information includes in-position status information of the target device and integrated port information of the integrated port where the target device is located; The information management module uses a multi-level storage architecture to store the target slot status information obtained by the hardware detection module. The multi-level storage architecture includes a temporary storage layer and a persistent storage layer. The integrated port information is saved in the temporary storage layer, and the in-place status information is registered in the persistent storage layer. The control execution module dynamically configures the hot-swap controller register corresponding to the integrated port based on a preset interface, including: the preset interface includes an interaction method defined in the ACPI specification, and the control execution module obtains the in-place status information of the target device and the corresponding integrated port information based on the interaction method; The control execution module configures the hot-swap controller register based on the in-place status information and the integrated port information to enable or disable the hot-swap controller function of the integrated port, including: The control execution module obtains the physical topology identifier of the target device through the preset interface; injects the structured encoding of the physical topology identifier into the control buffer; triggers the state machine of the hot-swap controller based on the physical characteristic parameters of the slot in the physical topology identifier, and completes the enabling or disabling of the hot-swap controller function of the specified integrated port through the logical judgment and action execution of the state machine.

2. The hot-swap control system according to claim 1, characterized in that: The target controller determines the in-place status of the target device by detecting bandwidth allocation information of the target slot and generates in-place status information.

3. The hot-swap control system according to claim 2, characterized in that: The hardware detection module executes a dynamic port mapping algorithm to analyze the processor number and physical slot position of the target device, and stores the integrated port information in a normalized manner in a temporary storage layer.

4. The hot-swap control system according to claim 1, wherein: The persistent storage layer includes an ACPI table, and the registered target device status and integrated port mapping relationship form a namespace accessible to the operating system.

5. The hot-swap control system according to claim 1, characterized in that: The control execution module reads the in-place status information registered by the persistent storage layer through the preset interface.

6. The hot-swap control system according to claim 1, characterized in that: Enable safety protection mechanisms when configuring the hot-swap controller registers, including: Using a memory mapped input and output (MMIO) access method to implement write protection for the hot swap controller registers; After configuration is complete, read back the register status to confirm that the function is effective; Perform parameter range validation and error handling logic.

7. The hot-swap control system according to claim 1, characterized in that: The register write protection includes: 64-bit alignment of the access address and atomic operation guarantee.

8. The hot-swap control system according to any one of claims 1 to 7, characterized in that: The target controller is a complex programmable logic device.

9. A hot plug control method, characterized in that: The method is applied to the hot-swap control system according to any one of claims 1 to 8, and the method includes: Detecting, by a target controller, the in-place status information of a target device and the port information of the integrated port where the target device is located; Storing the port information in a temporary storage layer and registering the in-place status information in an ACPI table in a persistence layer; The operating system calls a preset interface to read the in-place status information and dynamically configures the hot-swap controller register corresponding to the integrated port.

10. The hot-swap control method according to claim 9, wherein: The target controller includes a complex programmable logic device; The detecting the in-place status information of the target device by the target controller includes: Monitor bandwidth allocation information of target slots; Analyzing electrical characteristic parameters of the target device; A preset device feature library is called to identify the device type of the target device.

11. The hot-swap control method according to claim 10, wherein: After detecting the port information, dynamic port mapping operations are performed, including: Analyze the processor number and physical slot location of the target device; Normalize the integrated port information under the heterogeneous processor architecture and store it in the temporary storage layer.

12. The hot-swap control method according to claim 9, wherein: The ACPI table registration operation of the persistence layer includes: The mapping relationship between the target device status and the integrated port is encapsulated into a standard ACPI data structure; and a namespace accessible to the operating system is generated.

13. The hot-swap control method according to claim 9, wherein: The preset interface includes the interaction method defined in the ACPI specification, and the dynamic configuration operation includes: Enables or disables the hot-swap controller function for a specified integrated port based on the target device presence and device type.

14. The hot-swap control method according to claim 13, wherein: The dynamic configuration adopts a conditional enabling strategy, including: Obtain the physical topology identifier of the target device through the preset interface; The topology identifier is structurally encoded and injected into the control buffer; Triggers the state machine of the hot-swap controller based on the buffer parameters.

15. The hot-swap control method according to claim 9, wherein: Enable safety protection mechanisms when configuring the hot-swap controller registers, including: Use memory-mapped input and output to access registers and ensure that the access address is 64-bit aligned; After configuration is complete, read back the register status to verify that the function is effective; Perform parameter range validation and exception error handling.

16. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to execute the hot-swap control method according to any one of claims 9 to 15.

17. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the hot-swap control method according to any one of claims 9 to 15.

18. A computer program product, characterized in that The invention comprises a computer program, which implements the hot-swap control method according to any one of claims 9 to 15 when executed by a processor.

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