UVM-based RDMA queue management module verification system and method

Abstract

The invention provides an RDMA queue management module verification system and method based on a UVM. The system comprises a test case base class, a to-be-tested design top layer and a plurality of instantiation interfaces, the test case base class is provided with a pre-constructed verification environment; the verification environment comprises a reference model assembly, a scoreboard assembly and an agent assembly; the proxy component is used for generating an excitation signal corresponding to the current test module and driving the excitation signal to a to-be-tested design top layer and the reference model component; the reference model assembly is used for generating an expected signal according to the received excitation signal and sending the expected signal to the scoreboard assembly; the scoreboard assembly is used for comparing the expected signal with an actual signal output by the design top layer to be tested to obtain a verification result corresponding to the current test module; the to-be-tested design top layer is used for generating a corresponding actual signal according to the received excitation signal and inputting the actual signal to the scoreboard assembly. The construction efficiency and flexibility of the verification environment are improved, and the detection capability is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a UVM (Universal Verification Methodology)-based RDMA (Remote Direct Memory Access) queue management module verification system and method. Background Art

[0002] With the rapid development of technologies such as cloud computing, big data, and artificial intelligence, modern data centers and high-performance computing systems are increasingly demanding network communication efficiency. Remote Direct Memory Access (RDMA), as a highly efficient communication technology, significantly reduces network communication latency and improves system throughput by bypassing the CPU and directly accessing remote memory. RDMA technology uses queue pairs (QPs) as the minimum communication unit and utilizes work queues (WQs) and work queue elements (WQEs) to transmit and manage data. However, as the workload of RDMA network cards increases, the queue manager (QM) must handle thousands of work queues, dynamically schedule multiple queue pairs (including send queues (SQs), receive queues (RQs), and completion queues (CQs), and maintain the status of each queue in high-concurrency scenarios. The functional correctness and stability of the queue manager directly impact the data transmission efficiency and reliability of the entire RDMA system. Therefore, how to efficiently and comprehensively verify the functionality of the RDMA queue manager has become a pressing technical challenge.

[0003] In the prior art, traditional verification methods based on hardware description languages (such as Verilog or VHDL) are the primary means of verifying the RDMA queue management module. This method verifies the various functions of the queue management module by building a simulation test platform to simulate the communication process of the RDMA network card. In addition, with the development of verification technology, the Universal Verification Methodology (UVM) based on the SystemVerilog language has gradually become the mainstream solution for digital circuit verification. UVM provides a standardized and reusable verification platform architecture that supports transaction-level modeling (TLM), constrained random testing (Constrained Random Testing), and functional coverage analysis, which can significantly improve verification efficiency and quality. The UVM verification methodology simplifies the verification environment setup process by defining reusable verification components (such as drivers, monitors, agents, etc.), and supports automated test generation and coverage-driven verification, thereby improving the comprehensiveness and reliability of verification.

[0004] Although the UVM verification methodology has achieved significant results in digital circuit verification, its direct application to the verification of RDMA queue management modules still faces many challenges. First, the verification environment of the RDMA queue management module is complex, involving the dynamic scheduling and state maintenance of multiple queue pairs. Traditional verification methods have difficulty in efficiently building a reusable verification environment. Second, there are many boundary conditions and abnormal scenarios in the RDMA communication process (such as queue full / empty, DMA timeout, etc.). Traditional verification methods have limited coverage of such scenarios, making it difficult to fully verify the functional correctness of the queue management module. In addition, existing simulation tests lack automated mechanisms to detect problems such as data contention or deadlock, making it difficult to reproduce boundary conditions in high-concurrency scenarios, further reducing the adequacy of verification. These issues collectively lead to low coverage of traditional verification methods, making it difficult to effectively discover and locate key defects in the RDMA queue management module, thereby affecting the reliability and performance of the entire RDMA system. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a UVM-based RDMA queue management module verification system and method.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a UVM-based RDMA queue management module verification system, comprising: a test case base class, a top level of a design to be tested, and a plurality of instantiation interfaces;

[0008] The test case base class is set up with a pre-built verification environment; the verification environment includes: a reference model component, a scoreboard component, and an agent component; the agent component is used to generate a stimulus signal corresponding to the current test module and drive the stimulus signal to the top level of the design under test and the reference model component respectively; the reference model component is used to generate the corresponding expected signal based on the received stimulus signal and send the expected signal to the scoreboard component; the scoreboard component is used to compare the expected signal with the actual signal output by the top level of the design under test to obtain the verification result corresponding to the current test module;

[0009] The top layer of the design to be tested is used to design and integrate multiple modules to be tested in the RDMA queue management module, generate corresponding actual signals based on the received stimulus signals, and input the actual signals into the scoreboard component; the current test module is a submodule of the multiple modules to be tested;

[0010] The multiple instantiation interfaces are used to connect the current test module in the top level of the design under test with the proxy component accordingly.

[0011] Optionally, the proxy component is configured to drive the stimulus signal to the current test module in the top layer of the design under test through the corresponding instantiation interface, and to drive the stimulus signal to the reference model component through the TLM interface.

[0012] Optionally, a test case base class is used to create multiple test cases based on verification requirements;

[0013] Use multiple test cases to generate corresponding configuration information;

[0014] Distribute the corresponding configuration information to the corresponding environment and build a verification environment.

[0015] Optionally, the proxy component includes: a sending queue dequeue request proxy component, a receiving queue dequeue request proxy component, a sending completion queue enqueue request proxy component, a receiving completion queue enqueue request proxy component, and a queue status update management proxy component;

[0016] The sending queue dequeue request agent component, receiving queue dequeue request agent component, sending completion queue enqueue request agent component, receiving completion queue enqueue request agent component and queue status update management agent component have the same structure, but the corresponding configuration information and generated incentive signals are different.

[0017] Optionally, the verification environment further includes: a functional coverage group definition component;

[0018] The functional coverage group definition component is used to monitor whether the actual signal output from the top layer of the design under test complies with the signal rules through the monitoring interface;

[0019] When the actual signal does not conform to the signal rules, the top-level configuration function abnormality signal of the design under test is output.

[0020] Optionally, the sending queue dequeue request agent component, the receiving queue dequeue request agent component, the sending completion queue enqueue request agent component, the receiving completion queue enqueue request agent component and the queue status update management agent component all include: a sequencer, a driver and a monitor;

[0021] The sequence generator is used to generate corresponding excitation signals;

[0022] The driver is used to drive the stimulus signal to the corresponding current test module through the corresponding instantiation interface;

[0023] The monitor is used to drive the stimulus signal to the reference model component and input the actual signal output by the current test module to the scoreboard component.

[0024] In a second aspect, the present invention provides a UVM-based RDMA queue management module verification method, which is applied to an RDMA queue management module verification system, comprising:

[0025] S101, the RDMA queue management module verifies that the system obtains a power-on signal and an initialization signal;

[0026] S102, the RDMA queue management module verification system calls the corresponding proxy component according to the target to be tested, generates a corresponding stimulus signal through the proxy component, and drives the stimulus signal to the reference model component and the current test module corresponding to the target to be tested;

[0027] S103, the reference model component generates a corresponding expected signal according to the received excitation signal, and transmits the expected signal to the scoreboard component;

[0028] S104, the current test module generates an actual signal according to the received stimulus signal, and sends the actual signal to the scoreboard component;

[0029] S105: The scoreboard component compares the expected signal with the actual signal to obtain a verification result.

[0030] Optionally, the UVM-based RDMA queue management module verification method further includes:

[0031] Monitor whether the actual signal complies with the signal rules by defining components through functional coverage groups;

[0032] When the actual signal does not conform to the signal rules, the top-level configuration function abnormality signal of the design under test is output.

[0033] Optionally, S105 includes:

[0034] The scoreboard component determines whether the expected signal is consistent with the actual signal;

[0035] When the expected signal is consistent with the actual signal, a first verification signal is output; the first verification signal is used to indicate that the target to be measured has been verified to be correct;

[0036] When the expected signal is inconsistent with the actual signal, a second verification signal is output; the second verification signal is used to indicate that the verification of the target to be measured is incorrect.

[0037] The present invention provides a UVM-based RDMA queue management module verification system and method, wherein the UVM-based RDMA queue management module verification system comprises: a test case base class, a top-level design to be tested, and multiple instantiation interfaces; the test case base class is provided with a pre-built verification environment; the verification environment comprises: a reference model component, a scoreboard component, and an agent component; the agent component is used to generate an excitation signal corresponding to a current test module, and drive the excitation signal to the top-level design to be tested and the reference model component respectively; the reference model component is used to generate a corresponding expected signal according to the received excitation signal, and send the expected signal to the scoreboard component; the scoreboard component is used to compare the expected signal with the actual signal output by the top-level design to be tested, and obtain a verification result corresponding to the current test module; the top-level design to be tested is used to design and integrate multiple modules to be tested in the RDMA queue management module, and generate a corresponding actual signal according to the received excitation signal, and input the actual signal to the scoreboard component; the current test module is a submodule among the multiple modules to be tested; and the multiple instantiation interfaces are used to connect the current test module in the top-level design to be tested with the agent component accordingly. In this invention, by using a proxy component to generate stimulus signals corresponding to the current test module, each test case can independently configure its stimulus signal, simplifying the test environment setup process and improving the flexibility and reusability of the verification environment. Furthermore, by driving the stimulus signal to the top-level design under test and the reference model component, the consistency and accuracy of the verification process are ensured. Secondly, the reference model component generates an expected signal based on the received stimulus signal and compares it with the actual signal generated by the design under test. This approach not only effectively detects functional correctness issues but also allows for the simulation of various complex edge cases and abnormal scenarios through carefully designed stimulus signals, ensuring comprehensive coverage of various conditions that may arise during RDMA communication. Finally, a scoreboard component compares the expected signal generated by the reference model component with the actual signal generated by the top-level design under test, automatically identifying any differences between the two. This approach effectively identifies data races or deadlocks that may exist in high-concurrency scenarios without manual intervention. Furthermore, by connecting the current test module in the top-level design under test with the proxy component through an instantiated interface, the accuracy and consistency of signal transmission are ensured, further enhancing the ability to detect concurrency issues. In summary, by combining agent components, reference model components, and scoreboard components, not only the efficiency and flexibility of building the verification environment are improved, but also the coverage and detection capabilities of boundary conditions, abnormal scenarios, and concurrent issues are significantly enhanced.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A schematic diagram of the structure of a UVM-based RDMA queue management module verification system provided by an embodiment of the present invention;

[0040] Figure 2 The schematic diagram of the structure of the sending queue dequeue request agent component is shown exemplarily;

[0041] Figure 3 A schematic diagram of a flow chart of a UVM-based RDMA queue management module verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0043] In order to improve the construction efficiency and flexibility of the verification environment corresponding to the RDMA queue management module, and at the same time enhance the coverage and detection capabilities of the verification environment for boundary conditions, abnormal scenarios and concurrency issues, an embodiment of the present invention provides an RDMA queue management module verification system based on UVM. Figure 1 A schematic diagram of the structure of a UVM-based RDMA queue management module verification system provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the UVM-based RDMA queue management module verification system includes: a test case base class, a top level of the design to be tested, and multiple instantiation interfaces;

[0044] The test case base class is set up with a pre-built verification environment; the verification environment includes: a reference model component, a scoreboard component, and an agent component; the agent component is used to generate a stimulus signal corresponding to the current test module and drive the stimulus signal to the top level of the design under test and the reference model component respectively; the reference model component is used to generate the corresponding expected signal based on the received stimulus signal and send the expected signal to the scoreboard component; the scoreboard component is used to compare the expected signal with the actual signal output by the top level of the design under test to obtain the verification result corresponding to the current test module;

[0045] The top layer of the design to be tested is used to design and integrate multiple modules to be tested in the RDMA queue management module, generate corresponding actual signals based on the received stimulus signals, and input the actual signals into the scoreboard component; the current test module is a submodule of the multiple modules to be tested;

[0046] The multiple instantiation interfaces are used to connect the current test module in the top level of the design under test with the proxy component accordingly.

[0047] In addition, the top level of the design under test includes a send queue management module, a receive queue management module, a send completion queue management module, and a receive completion queue management module. Data between the reference model component and the scoreboard component is transmitted through TLM (Transaction Level Modeling), and each component exchanges data through ports and export ports in UVM. Multiple instantiated interfaces include: a send queue dequeue request interface (txq_deq_if), a receive queue dequeue request interface (rxq_deq_if), a send completion queue enqueue request interface (tcq_enq_if), a receive completion queue enqueue request interface (rcq_enq_if), a queue status update interface (axi_lite_if), and a functional coverage group detection interface (cover_if).

[0048] Furthermore, the design of each component in the above-mentioned UVM-based RDMA queue management module verification system follows the existing UVM verification methodology, and according to the needs of the basic structure of RDMA queue management, the corresponding structural components and component internal logic are designed, and the connection between components, basic function testing and other operations are completed to ensure the normal data flow between components during the verification process.

[0049] The send queue management module is designed to manage the status of RDMA send queues. When an external analog driver adds an element to a send queue through the AXI interface, it indicates that the send queue has a new data send task to be processed. At this time, the send queue management module sends a doorbell signal through the doorbell mechanism, notifying the next-level send engine module of the new data send task. The hardware send engine then inputs a send queue dequeue request to the queue manager. The send queue management module sends the corresponding send queue address in memory and queue element status as a dequeue response to the next-level hardware module for further data processing. The receive queue management module manages the status of RDMA-related receive queues. When the next-level hardware module sends a dequeue request to the receive queue management module, it indicates that a new data receive task is waiting to be processed. The receive queue management module generates a dequeue response for the corresponding receive queue and passes it to the next-level module for processing. The send completion queue management module handles the status of the RDMA send completion queue. When the hardware completes a data send task, it inputs an enqueue request for the corresponding queue to the send completion queue management module, which then updates the send completion queue status. The receive completion queue management module is used to process the status of the RDMA receive completion queue. When the hardware completes the task of receiving data, it inputs the queue enqueue request of the corresponding queue to the receive completion queue management module, and the receive completion queue updates the status of the receive completion queue.

[0050] Multiple proxy components are derived from the test case base class, including the transmit queue dequeue request proxy component (txq_deq_agt), receive queue dequeue request proxy component (rxq_deq_agt), transmit completion queue enqueue request proxy component (tcq_enq_agt), receive completion queue enqueue request proxy component (rcq_enq_agt), queue status update management proxy component (axi_lite_agt), functional coverage group definition component (rdma_qm_coverage), and RDMA queue management reference model component (rdma_qm_refmod). In addition, an additional queue management scoreboard component (qm_scoreboard) is included.

[0051] An embodiment of the present invention provides a UVM-based RDMA queue management module verification system. By using a proxy component to generate stimulus signals corresponding to the current test module, each test case can independently configure its stimulus signal, simplifying the test environment setup process and improving the flexibility and reusability of the verification environment. Furthermore, by driving the stimulus signal to the top-level design under test and the reference model component, the consistency and accuracy of the verification process are ensured. Secondly, the reference model component generates an expected signal based on the received stimulus signal and compares it with the actual signal generated by the design under test. This approach not only effectively detects functional correctness issues but also allows for the simulation of various complex edge cases and abnormal scenarios through carefully designed stimulus signals, ensuring comprehensive coverage of various conditions that may arise during RDMA communication. Finally, a scoreboard component compares the expected signal generated by the reference model component with the actual signal generated by the top-level design under test, automatically identifying any discrepancies between the two. This method effectively identifies potential data races or deadlocks in high-concurrency scenarios without manual intervention. Furthermore, by connecting the current test module in the top-level design under test with the proxy component through an instantiated interface, the accuracy and consistency of signal transmission are ensured, further enhancing the ability to detect concurrency issues. In summary, by combining agent components, reference model components, and scoreboard components, not only the efficiency and flexibility of building the verification environment are improved, but also the coverage and detection capabilities of boundary conditions, abnormal scenarios, and concurrent issues are significantly enhanced.

[0052] Optionally, the proxy component is configured to drive the stimulus signal to the current test module in the top layer of the design under test through the corresponding instantiation interface, and to drive the stimulus signal to the reference model component through the TLM interface.

[0053] Optionally, a test case base class is used to create multiple test cases based on verification requirements;

[0054] Use multiple test cases to generate corresponding configuration information;

[0055] Distribute the corresponding configuration information to the corresponding environment and build a verification environment.

[0056] Optionally, the proxy component includes: a sending queue dequeue request proxy component, a receiving queue dequeue request proxy component, a sending completion queue enqueue request proxy component, a receiving completion queue enqueue request proxy component, and a queue status update management proxy component;

[0057] The sending queue dequeue request agent component, receiving queue dequeue request agent component, sending completion queue enqueue request agent component, receiving completion queue enqueue request agent component and queue status update management agent component have the same structure, but the corresponding configuration information and generated incentive signals are different.

[0058] In order to illustrate the specific structures of the sending queue dequeue request agent component, the receiving queue dequeue request agent component, the sending completion queue enqueue request agent component, the receiving completion queue enqueue request agent component and the queue status update management agent component, and since the structures of the above components are the same, Figure 2 The schematic diagram of the structure of the sending queue dequeue request agent component is shown as an example. Figure 2 As shown, the send queue out request agent component specifically includes: a send queue out request sequencer, a send queue out request driver and a send queue out request monitor. The send queue out request driver is connected to the send queue out request interface, and the send queue out request monitor is connected to the reference model component.

[0059] The receive queue dequeue request agent component (rxq_deq_agt) includes a receive queue dequeue request sequencer (rxq_sequencer), a receive queue dequeue request driver (rxq_driver), and a receive queue dequeue request monitor (rxq_monitor). The receive queue dequeue request sequencer generates different dequeue request data (stimulus signals) based on the target under test (DUT) and passes them to the receive queue dequeue request driver. The receive queue dequeue request driver then drives the generated dequeue request data to the receive queue dequeue request interface. This interface then feeds the DUT (DUT top layer) with the request, simulating a real-world dequeue request transmission. The receive queue dequeue request monitor continuously monitors the DUT's input and output of dequeue request data through the receive queue dequeue request interface and transmits this data to the queue management scoreboard component (scoreboard component) for comparison of the receive queue dequeue request data.

[0060] The Send Completion Queue Enqueue Request Agent (tcq_enq_agt) includes a Send Completion Queue Enqueue Request Sequencer (tcq_sequencer), a Send Completion Queue Enqueue Request Driver (tcq_driver), and a Send Completion Queue Enqueue Request Monitor (tcq_monitor). The Send Completion Queue Enqueue Request Sequencer generates different enqueue request data (stimulus signals) based on different test targets and passes them to the Send Completion Queue Enqueue Request Driver. The Send Completion Queue Enqueue Request Driver then drives the generated enqueue request data to the Send Completion Queue Enqueue Request Interface, which then feeds the device under test (DUT) into the Enqueue Request Interface, simulating the initiation of an enqueue request after a real hardware data transmission task completes. The Send Completion Queue Enqueue Request Monitor continuously monitors the input and output of the DUT's Send Completion Queue Enqueue Request data through the Send Completion Queue Enqueue Request Interface and transmits this data to the Queue Management Scoreboard Component (scoreboard component) for comparison of Send Completion Queue Enqueue Request data.

[0061] The Receive Completion Queue Enqueue Request Agent (rcq_enq_agt) includes a Receive Completion Queue Enqueue Request Sequencer (rcq_sequencer), a Receive Completion Queue Enqueue Request Driver (rcq_driver), and a Receive Completion Queue Enqueue Request Monitor (rcq_monitor). The Receive Completion Queue Enqueue Request Sequencer generates different enqueue request data (stimulus signals) based on different targets under test and transmits them to the Receive Completion Queue Enqueue Request Driver. The Receive Completion Queue Enqueue Request Driver then drives the generated enqueue request data to the Receive Completion Queue Enqueue Request Interface, which then feeds the device under test (DUT) with the enqueue request, simulating the initiation of an enqueue request after a real hardware data transmission task completes. The Receive Completion Queue Enqueue Request Monitor continuously monitors the DUT's input and output of the Receive Completion Queue Enqueue Request data through the Receive Completion Queue Enqueue Request Interface and transmits the monitored input and output data to the Queue Management Scoreboard Component (scoreboard component) through the Receive Completion Queue Enqueue Request Interface for comparison of the Receive Completion Queue Enqueue Request data.

[0062] The queue status update management agent component (axi_lite_agt) includes a queue status update sequencer (axi_sequencer), a queue status update driver (axi_driver), and a queue status update monitor (axi_monitor). The queue status update sequencer generates different queue status update data based on different test targets and passes it to the queue status update driver. The queue status update driver then drives the obtained queue status update data to the queue status update interface and inputs it to the device under test (DUT) through the queue status update interface, simulating the situation where real hardware receives driver-related queue updates. The queue status update monitor continuously monitors the DUT's input and output of queue status update data through the queue status update interface and passes the monitored queue status update input and output data to the queue management scoreboard component (scoreboard component) through the queue status update interface for comparison of queue status update data.

[0063] Optionally, the verification environment also includes: a functional coverage group definition component. The functional coverage group definition component (rdma_qm_coverage) will define some functional points that need to be verified according to different test verification requirements, and then monitor the data on the coverage group monitoring interface (cover_if) to determine whether the defined functional points are covered based on the data changes.

[0064] Exemplarily, the functional coverage group definition component is used to monitor whether the actual signal outputted from the top layer of the design under test complies with the signal rules through the monitoring interface;

[0065] When the actual signal does not conform to the signal rules, the top-level configuration function abnormality signal of the design under test is output.

[0066] Optionally, the sending queue dequeue request agent component, the receiving queue dequeue request agent component, the sending completion queue enqueue request agent component, the receiving completion queue enqueue request agent component and the queue status update management agent component all include: a sequencer, a driver and a monitor;

[0067] The sequence generator is used to generate corresponding excitation signals;

[0068] The driver is used to drive the stimulus signal to the corresponding current test module through the corresponding instantiation interface;

[0069] The monitor is used to drive the stimulus signal to the reference model component and input the actual signal output by the current test module to the scoreboard component.

[0070] The UVM-based RDMA queue management module verification system utilizes a powerful UVM verification platform meticulously built using the SystemVerilog language. This platform deeply integrates data transmission, processing, and checking functions, providing a one-stop solution for RDMA queue management module verification. The platform's component design incorporates a highly portable queue status update agent component and queue entry and exit request agents. In particular, the queue entry and exit request agents are designed to work seamlessly with a wide variety of test cases, performing various randomization operations on queue entry and exit request data, significantly expanding the scope of verification scenarios. This verification system strictly adheres to the UVM verification methodology, ensuring comprehensive and accurate verification of the RDMA queue management module. Compared to traditional verification techniques, it offers significant advantages. Firstly, it provides a comprehensive RDMA queue management module verification solution, changing the fragmented and unsystematic nature of traditional verification approaches. Secondly, the adoption of the UVM verification environment significantly enhances verification flexibility. Verifiers do not need to perform complex configurations and can achieve high code coverage and function coverage at a low configuration cost, effectively improving verification efficiency while ensuring the completeness of the verification work, making the verification of the RDMA queue management module more efficient and reliable.

[0071] In a second aspect, an embodiment of the present invention further provides a UVM-based RDMA queue management module verification method. Figure 3 A schematic diagram of a UVM-based RDMA queue management module verification method provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, including:

[0072] S101 : The RDMA queue management module verifies that the system obtains a power-on signal and an initialization signal.

[0073] S102, the RDMA queue management module verification system calls the corresponding proxy component according to the target to be tested, generates a corresponding stimulus signal through the proxy component, and drives the stimulus signal to the reference model component and the current test module corresponding to the target to be tested.

[0074] S103: The reference model component generates a corresponding expected signal according to the received excitation signal, and transmits the expected signal to the scoreboard component.

[0075] S104: The current test module generates an actual signal according to the received stimulus signal, and sends the actual signal to the scoreboard component.

[0076] S105: The scoreboard component compares the expected signal with the actual signal to obtain a verification result.

[0077] Optionally, the UVM-based RDMA queue management module verification method further includes:

[0078] Monitor whether the actual signal complies with the signal rules by defining components through functional coverage groups;

[0079] When the actual signal does not conform to the signal rules, the top-level configuration function abnormality signal of the design under test is output.

[0080] Optionally, S105 includes:

[0081] The scoreboard component determines whether the expected signal is consistent with the actual signal;

[0082] When the expected signal is consistent with the actual signal, a first verification signal is output; the first verification signal is used to indicate that the target to be measured has been verified to be correct;

[0083] When the expected signal is inconsistent with the actual signal, a second verification signal is output; the second verification signal is used to indicate that the verification of the target to be measured is incorrect.

[0084] The verification process is exemplarily described below by taking the dequeue request signal corresponding to the sending / receiving queue management module and the enqueue request signal corresponding to the sending / receiving completion queue management module as examples.

[0085] In one implementation, the following description is made using the dequeue request signal corresponding to the sending / receiving queue management module as an example:

[0086] Step 1: Power on and initialize the RDMA queue management module to verify the system;

[0087] Step 2: Wait for the RDMA queue management module to complete verification system initialization, call the queue status update management agent component, generate send / receive queue status information, simulate the driver updating the queue status information through the queue status update interface, and send the generated queue status information to the top level of the design under test through the queue status update interface;

[0088] Step 3: After updating the send / receive queue status information, call the send / receive queue dequeue request agent component to generate a dequeue request and drive it to the top layer of the design under test as the send / receive queue dequeue request signal input;

[0089] Step 4: After starting to input data, the queue dequeue request agent component generates subsequent dequeue request signals based on the configuration of different test cases to achieve the most complete verification and coverage collection possible;

[0090] Step 5: All agent components continuously monitor the input and output signals on the interface and compare the actual signals monitored with the expected signals generated by the reference model components. If the comparison fails, a simulation log indicating the received data comparison failed is printed. If the comparison passes, a simulation log indicating the received data comparison succeeds is printed.

[0091] Step 6: After all test cases are tested, the log of the entire process is output as a log file, and the code and function coverage are collected, and finally the simulation ends.

[0092] In another implementation scheme, the following is explained by taking the queue request signal corresponding to the sending / receiving completion queue management module as an example:

[0093] Step 7: Call the send / receive completion queue agent component to generate a send / receive queue enqueue request signal, simulating the situation where the hardware needs to update the queue status after completing the data transmission task. The generated queue enqueue request signal is sent to the top level of the design under test through the interface;

[0094] Step 8: After the enqueue request signal is input, the queue enqueue request agent component generates subsequent enqueue request signals based on the configuration of different test cases to achieve the most complete verification and coverage collection possible;

[0095] Step 9: After the queue request is input, the queue response is obtained, and the queue status update management component is called to generate the corresponding queue status read signal. The read signal is sent to the top level of the design under test through the interface driver to read the latest queue status;

[0096] Step 10: All agent components continuously monitor the input and output signals on the interface, compare the monitored output signals with the expected results generated by the reference model components, print the comparison results and record them in the simulation log;

[0097] Step 11: After all test cases are tested, the log of the entire process is output as a log file, and the code and function coverage are collected, and finally the simulation ends.

[0098] The above-mentioned UVM-based RDMA queue management module verification method has brought significant changes to the verification of the queue management module in the top level of the design to be tested by building a module-level verification system. The verification system supports directly taking the design code module of the queue management module to be verified as the verification object, abandoning the practice of integrating the entire chip as the design to be tested in traditional verification, and only needs to integrate the queue management module itself into the top level of the design to be tested. This method effectively reduces the dependence of the top level of the design to be tested on other parts, so that the verifiable nodes of the top level of the design to be tested can be executed in advance. In the past, verification often required the integration of the entire electronic control unit chip or other design components, but the system of the present invention breaks this limitation. Since there is no need for such complex integration, the verification work can be carried out early in the design stage of the queue management module, which greatly advances the intervention time of the verification and reduces the dependency conditions that need to be met for verification.

[0099] Furthermore, the RDMA queue management module verification system can combine different functional modes to generate random configuration data or implement random changes in mode switching data. This allows the RDMA queue management module verification system to comprehensively and effectively cover the various functional modes within the queue management module, ensuring the randomness and completeness of the incentives for the corresponding management modules. This high-quality incentive directly drives improvements in verification quality, enabling more comprehensive and in-depth testing of the management modules at the top level of the design under test during the verification process, laying a solid foundation for their ultimate stable operation and performance assurance.

[0100] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with certain aspects of the present invention.

[0101] In the description of this specification, the reference terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0102] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the above-mentioned disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0103] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the scope of protection of the present invention.

Claims

1. A UVM-based RDMA queue management module verification system, characterized in that: include: Test case base class, top level of the design under test, and multiple instantiation interfaces; The test case base class is provided with a pre-built verification environment; The verification environment includes: a reference model component, a scoreboard component, and an agent component; the agent component is used to generate a stimulus signal corresponding to the current test module and drive the stimulus signal to the top layer of the design under test and the reference model component respectively; the reference model component is used to generate a corresponding expected signal based on the received stimulus signal and send the expected signal to the scoreboard component; the scoreboard component is used to compare the expected signal with the actual signal output by the top layer of the design under test to obtain a verification result corresponding to the current test module; The top layer of the design to be tested is used to design and integrate multiple modules to be tested in the RDMA queue management module, generate the corresponding actual signal according to the received stimulus signal, and input the actual signal into the scoreboard component; the current test module is a submodule among the multiple modules to be tested; The multiple instantiation interfaces are used to connect the current test module in the top level of the design to be tested with the proxy component in a corresponding manner.

2. The RDMA queue management module verification system based on UVM according to claim 1, wherein The proxy component is configured to drive the stimulus signal to the current test module in the top layer of the design under test through the corresponding instantiation interface, and to drive the stimulus signal to the reference model component through the TLM interface.

3. The RDMA queue management module verification system based on UVM according to claim 1, wherein The test case base class is used to create multiple test cases according to verification requirements; Generating corresponding configuration information using the multiple test cases; Distribute the corresponding configuration information to the corresponding environment to construct the verification environment.

4. The RDMA queue management module verification system based on UVM according to claim 1, wherein The agent components include: a sending queue dequeue request agent component, a receiving queue dequeue request agent component, a sending completion queue enqueue request agent component, a receiving completion queue enqueue request agent component and a queue status update management agent component; The sending queue dequeue request agent component, the receiving queue dequeue request agent component, the sending completion queue enqueue request agent component, the receiving completion queue enqueue request agent component and the queue status update management agent component have the same structure, but the corresponding configuration information and the generated excitation signal are different.

5. The RDMA queue management module verification system based on UVM according to claim 1, wherein The verification environment further includes: a functional coverage group definition component; The functional coverage group definition component is used to monitor whether the actual signal output by the top layer of the design to be tested complies with the signal rule through the monitoring interface; When the actual signal does not comply with the signal rule, a top-level configuration function abnormality signal of the design to be tested is output.

6. The UVM-based RDMA queue management module verification system according to claim 4, wherein: The sending queue dequeue request agent component, the receiving queue dequeue request agent component, the sending completion queue enqueue request agent component, the receiving completion queue enqueue request agent component and the queue status update management agent component all include: a sequencer, a driver and a monitor; The sequence generator is used to generate corresponding excitation signals; The driver is used to drive the stimulus signal to the corresponding current test module through the corresponding instantiated interface; The monitor is used to drive the excitation signal to the reference model component and input the actual signal output by the current test module to the scoreboard component.

7. A UVM-based RDMA queue management module verification method, applied to an RDMA queue management module verification system, characterized in that: include: S101, the RDMA queue management module verifies that the system obtains a power-on signal and an initialization signal; S102: The RDMA queue management module verification system calls a corresponding proxy component according to the target to be tested, generates a corresponding stimulus signal through the proxy component, and drives the stimulus signal to the reference model component and the current test module corresponding to the target to be tested respectively; S103, the reference model component generates a corresponding expected signal according to the received excitation signal, and transmits the expected signal to the scoreboard component; S104: The current test module generates an actual signal according to the received stimulus signal, and sends the actual signal to the scoreboard component; S105: The scoreboard component compares the expected signal with the actual signal to obtain a verification result.

8. The UVM-based RDMA queue management module verification method according to claim 7, wherein: Also includes: Monitoring whether the actual signal complies with the signal rule by defining a component of a functional coverage group; When the actual signal does not comply with the signal rule, a top-level configuration function abnormality signal of the design to be tested is output.

9. The RDMA queue management module verification method based on UVM according to claim 7, wherein S105 includes: The scoreboard component determines whether the expected signal is consistent with the actual signal; When the expected signal is consistent with the actual signal, a first verification signal is output; the first verification signal is used to indicate that the target to be measured is verified to be correct; When the expected signal is inconsistent with the actual signal, a second verification signal is output; the second verification signal is used to indicate that the verification of the target to be measured is incorrect.

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