2.5D substrate packaging structure and packaging method

Abstract

The present application provides a 2.5D substrate packaging structure and packaging method, which relate to the field of semiconductor packaging. The 2.5D substrate packaging structure includes an interposer, a buffer portion, a second electrical connection portion and a bump. A wiring layer and a first electrical connection portion electrically connected to the wiring layer are provided on the interposer, and the buffer portion is provided on a side of the first electrical connection portion away from the wiring layer. The second electrical connection portion is provided on a side of the buffer portion away from the first electrical connection portion; the second electrical connection portion is electrically connected to the first electrical connection portion. The bump is located on a side of the second electrical connection portion away from the buffer portion and is electrically connected to the second electrical connection portion. By providing the buffer portion, the contact area between the bump and the first electrical connection portion can be reduced, electromigration can be mitigated, and the buffer portion can improve the structural support and buffering performance, and can absorb the mounting pressure to avoid cracks in the first electrical connection portion.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D substrate packaging structure and a packaging method. Background Art

[0002] With the rapid development of the semiconductor industry, chiplet technology adopts a new design approach, packaging small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips increases and the number of chips integrated in a single package increases significantly, various 2.5D and 3D packaging technologies are used as multi-chip packaging solutions, connecting the pads of adjacent chips within a single package through rewiring layers.

[0003] In the current structure for creating microbumps after opening pads on the rewiring layer, the bottom of the copper pillar bump is completely connected to the pad electrode of the wiring layer. This causes stress on the copper pillar bump to act directly on the pad electrode, leading to pad electrode cracking. Furthermore, the metal at the bottom of the copper pillar bump is completely in contact with the pad electrode of the wiring layer, which can cause electromigration and significantly reduce the life of the copper pillar bump. Summary of the Invention

[0004] The object of the present invention is to provide a 2.5D substrate packaging structure and packaging method, which can alleviate problems such as electron migration and help improve the life of bumps.

[0005] In a first aspect, the present invention provides a 2.5D substrate packaging structure, comprising:

[0006] an interposer, wherein a wiring layer and a first electrical connection portion electrically connected to the wiring layer are provided on the interposer;

[0007] a buffer portion, the buffer portion being provided on a side of the first electrical connection portion away from the wiring layer;

[0008] a second electrical connection portion, the second electrical connection portion being disposed on a side of the buffer portion away from the first electrical connection portion; the second electrical connection portion being electrically connected to the first electrical connection portion;

[0009] The bump is located on a side of the second electrical connection portion away from the buffer portion and is electrically connected to the second electrical connection portion.

[0010] In an optional embodiment, the second electrical connection portion includes a first covering portion and a second covering portion that are connected, the first covering portion is provided on a side of the buffer portion away from the wiring layer, and the bump is connected to the first covering portion; the second covering portion covers the side wall of the buffer portion, and the second covering portion is electrically connected to the first electrical connection portion.

[0011] In an optional embodiment, a first groove is provided on a surface of the buffer portion away from the intermediary layer, and the first covering portion includes a first branch and a second branch connected to each other, the first branch covering the bottom and wall of the groove; the second branch is connected to the periphery of the first branch and extends to the surface of the buffer portion; the second branch and the second covering portion are connected.

[0012] In an optional embodiment, the buffer portion includes metal layers and dielectric layers alternately stacked; wherein the surface layer of the buffer portion away from the wiring layer is a dielectric layer, and the second electrical connection portion is connected to the dielectric layer on the surface.

[0013] In an optional embodiment, the metal layer includes a first metal layer, a second metal layer and a third metal layer, and the dielectric layer includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer;

[0014] The first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the third metal layer and the fourth dielectric layer are sequentially arranged on the first electrical connection portion; the second electrical connection portion is connected to the fourth dielectric layer.

[0015] In an optional embodiment, the second covering portion is connected to side walls of the first metal layer, the second metal layer, and the third metal layer, respectively.

[0016] In an optional embodiment, the first metal layer is a titanium layer, the second metal layer is a titanium-tungsten layer, and the third metal layer is a gold layer.

[0017] In an optional embodiment, a plurality of metal pillars are spaced apart in the buffer portion, and one end of at least one of the metal pillars is electrically connected to the first electrical connection portion, and the other end thereof is electrically connected to the second electrical connection portion.

[0018] In an optional embodiment, the metal pillar and the metal layer are arranged to intersect each other, and an interface alloy metal is formed at the junction.

[0019] In an optional embodiment, the sidewalls of the buffer portion are covered with a protective layer.

[0020] In an optional embodiment, the interposer is provided with multiple wiring layers;

[0021] Alternatively, the interposer is made of organic dielectric material, and the interposer includes a plurality of stacked dielectric layers, each of which is provided with a wiring layer, and the wiring layers in adjacent dielectric layers are electrically connected; the first electrical connection portion, the buffer portion, the second electrical connection portion and the bump are sequentially provided on the surface dielectric layer.

[0022] In an optional embodiment, at least one side surface of the interposer is provided with the first electrical connection portion, the buffer portion, the second electrical connection portion and the bump in sequence.

[0023] In an optional embodiment, a second groove is provided on the intermediary layer, and the first electrical connection portion is provided in the second groove, or the first electrical connection portion is provided in the second groove and extends to the surface of the intermediary layer.

[0024] In an optional embodiment, a chip and a plastic package are further included, the chip and the bump are electrically connected, and the plastic package covers the chip.

[0025] In a second aspect, the present invention provides a 2.5D substrate packaging method for preparing the above-mentioned 2.5D substrate packaging structure.

[0026] The 2.5D substrate packaging structure and packaging method provided by the embodiments of the present invention have the following beneficial effects:

[0027] The 2.5D substrate packaging structure and packaging method provided by embodiments of the present invention form a buffer portion on the first electrical connection, reducing the metal contact area between the bump and the first electrical connection, effectively preventing electromigration and improving the bump life. Furthermore, the buffer portion provides excellent support and cushioning properties, absorbing chip placement pressure and preventing direct impact of placement pressure and soldering stress on the first electrical connection, which could lead to cracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic diagram of a first structural embodiment of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of a first structure of a buffer portion of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of a second structural embodiment of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0032] Figure 4 A second structural schematic diagram of the buffer portion of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of a third structure of the buffer portion of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0034] Figure 6 A fourth structural schematic diagram of the buffer portion of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0035] Figure 7 A fifth structural schematic diagram of the buffer portion of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0036] Figure 8 A sixth structural diagram of the buffer portion of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0037] Figure 9 A schematic diagram of a third structural embodiment of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0038] Figure 10 A schematic diagram of a fourth structural embodiment of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0039] Figure 11 A schematic diagram of a structure in which multiple chips are mounted on a 2.5D substrate packaging structure according to an embodiment of the present invention;

[0040] Figure 12 A schematic diagram of the distribution structure of multiple chips in a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0041] Figure 13 One of the process diagrams of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0042] Figure 14 for Figure 13 A partial enlarged schematic diagram of point A in the middle;

[0043] Figure 15 A second schematic diagram of a manufacturing process for a 2.5D substrate packaging structure according to an embodiment of the present invention;

[0044] Figure 16 for Figure 15 A partial enlarged schematic diagram of point B in the middle;

[0045] Figure 17 for Figure 15 A partial enlarged schematic diagram of point C in the middle;

[0046] Figure 18 The third process diagram of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0047] Figure 19 for Figure 18A partial enlarged schematic diagram of point E in the middle;

[0048] Figure 20 A fourth schematic diagram of a manufacturing process of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0049] Figure 21 A fifth process diagram of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0050] Figure 22 One of the process diagrams of a buffer portion of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0051] Figure 23 A second schematic diagram of a manufacturing process of a buffer portion of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0052] Figure 24 One of the process diagrams of another buffer portion of the 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0053] Figure 25 A second schematic diagram of a manufacturing process of another buffer portion of a 2.5D substrate packaging structure provided by an embodiment of the present invention;

[0054] Figure 26 A third schematic diagram of a manufacturing process of another buffer portion of a 2.5D substrate packaging structure provided by an embodiment of the present invention.

[0055] Icons: 110-intermediate layer; 1111-first surface; 1112-second surface; 111-wiring layer; 112-first electrical connection portion; 113-third subdivision; 114-fourth subdivision; 115-second groove; 117-conductive pillar; 120-buffer portion; 121-first groove; 130-metal layer; 131-first metal layer; 132-second metal layer; 133-third metal layer; 135-metal pillar; 140-dielectric layer; 141-first dielectric layer; 142-second dielectric layer; 143-third dielectric layer; 144-fourth dielectric layer; 14 6-protective layer; 150-second electrical connection; 151-first covering part; 152-first subsection; 153-second subsection; 154-second covering part; 160-bump; 171-chip; 172-plastic package; 173-substrate; 174-metal ring; 175-bottom glue; 176-component; 101-plated hole; 102-fifth dielectric layer; 103-sixth dielectric layer; 104-graphic layer opening; 105-first wiring layer; 106-seventh dielectric layer; 107-carrier; 108-bonding glue; 109-second wiring layer; 210-dielectric layer. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0058] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0059] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0060] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0061] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0062] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0063] Please combine Figure 1 and Figure 2 A 2.5D substrate package structure proposed in an embodiment of the present invention includes an interposer 110, a buffer 120, a second electrical connection 150, and a bump 160. Interposer 110 is provided with a wiring layer 111 and a first electrical connection 112 electrically connected to wiring layer 111. Buffer 120 is located on the side of first electrical connection 112 away from wiring layer 111. Second electrical connection 150 is located on the side of buffer 120 away from first electrical connection 112 and is electrically connected to first electrical connection 112. Bump 160 is located on the side of second electrical connection 150 away from buffer 120 and is electrically connected to second electrical connection 150. The provision of buffer 120 reduces the metal contact area between bump 160 and first electrical connection 112, effectively mitigating electromigration. Buffer 120 also improves structural support and cushioning performance, absorbing mounting pressure and soldering stress to prevent cracks in first electrical connection 112.

[0064] First electrical connector 112 is used to electrically connect bump 160 to wiring layer 111. Bump 160 is used to attach chip 171. Second electrical connector 150 improves the bonding strength between bump 160 and buffer 120, and enhances the electrical conductivity between bump 160 and first electrical connector 112, thereby improving electrical transmission capability.

[0065] The second electrical connection portion 150 includes a first covering portion 151 and a second covering portion 154. The first covering portion 151 is located on the side of the buffer portion 120 away from the wiring layer 111, and the bump 160 is connected to the first covering portion 151. The second covering portion 154 covers the sidewalls of the buffer portion 120 and is electrically connected to the first electrical connection portion 112. Optionally, the first covering portion 151 and the second covering portion 154 can be integrally formed to improve structural stability and enhance bonding with the buffer portion 120.

[0066] The first electrical connection 112 is a UBM (Under Bump Metallurgy) metal layer. Compared to conventional techniques in which the copper pillar bump is directly positioned on the UBM metal layer, whereby the copper pillar bump is in full contact with the UBM metal layer, the buffer portion 120 in this embodiment is constructed from an insulating material, including but not limited to at least one of polymer insulating materials such as polyimide, benzocyclobutene, and epoxy resin. The second covering portion 154 extends along the sidewalls of the buffer portion 120 and electrically connects to the first electrical connection 112, thereby achieving electrical connection between the bump 160 and the UBM metal layer. This arrangement reduces the contact area between the bump 160 and the UBM metal layer, resolving the problem of severe electron migration in conventional techniques where the copper pillar bump is in full contact with the UBM metal layer. The provision of the buffer portion 120 in this embodiment reduces electron migration in the bump 160 and improves its service life.

[0067] Optionally, a first groove 121 is formed on the side of the buffer portion 120 facing away from the interposer 110. The first covering portion 151 includes a first sub-portion 152 and a second sub-portion 153 connected to each other. The first sub-portion 152 covers the bottom and walls of the groove. The second sub-portion 153 extends from the periphery of the first sub-portion 152 to the surface of the buffer portion 120. The second sub-portion 153 is connected to the second covering portion 154. The provision of the first groove 121 helps to increase the bonding strength between the first electrical connection portion 112 and the buffer portion 120.

[0068] Combine Figure 3 and Figure 4 Optionally, the buffer portion 120 includes metal layers 130 and dielectric layers 140 that are alternately stacked. The surface layer of the buffer portion 120 away from the wiring layer 111 is the dielectric layer 140, and the second electrical connection portion 150 is connected to the surface dielectric layer 140. In other words, the side of the buffer portion 120 close to the first electrical connection portion 112 is the dielectric layer 140, and the side of the buffer portion 120 close to the second electrical connection portion 150 is the dielectric layer 140. The metal layers 130 and dielectric layers 140 are alternately stacked. The number of stacked layers can be set according to actual conditions and is not specifically limited here.

[0069] It is understood that the buffer portion 120 includes multiple metal layers 130, such as one, two, three, four, or more layers. The materials of each metal layer 130 can be the same or different. In this embodiment, the different materials of each metal layer 130 can fully utilize the characteristics of each metal material and enhance the overall performance of the buffer portion 120. The materials of the metal layer 130 include, but are not limited to, any one or more of titanium, titanium tungsten, copper, nickel, and vanadium.

[0070] Optionally, the metal layer 130 includes a first metal layer 131, a second metal layer 132, and a third metal layer 133, and the dielectric layer 140 includes a first dielectric layer 141, a second dielectric layer 142, a third dielectric layer 143, and a fourth dielectric layer 144. The first dielectric layer 141, the first metal layer 131, the second dielectric layer 142, the second metal layer 132, the third dielectric layer 143, the third metal layer 133, and the fourth dielectric layer 144 are sequentially arranged on the first electrical connection 112; the second electrical connection 150 is connected to the fourth dielectric layer 144. The first metal layer 131 is a titanium layer, which provides better bonding. The second metal layer 132 is a titanium-tungsten layer, which provides better heat dissipation. The third metal layer 133 is a gold layer, which provides better electrical conductivity.

[0071] Optionally, the fourth dielectric layer 144 is provided with a first groove 121 to improve bonding with the second electrical connection portion 150. The second covering portion 154 is connected to the sidewalls of the first metal layer 131, the second metal layer 132, and the third metal layer 133, respectively, to improve electrical conductivity and electrical transmission performance.

[0072] It can be understood that the multi-layer metal layer 130 can improve the heat dissipation, support and electrical conductivity of the buffer portion 120 .

[0073] In some embodiments, the metal layer 130 in the buffer portion 120 may also be arranged in a vertical direction, such as Figure 5 As shown, a plurality of metal pillars 135 are formed in the buffer portion 120 .

[0074] Or, as Figure 6 As shown, the buffer portion 120 includes both spaced metal layers 130 and vertically arranged metal pillars 135. In other words, the metal layers 130 and dielectric layers 140 in the buffer portion 120 can be alternately arranged in the horizontal or vertical direction, or in both the horizontal and vertical directions, forming a grid arrangement.

[0075] It's easy to understand that the buffer 120 is designed with metal layers 130 and metal pillars 135 intersecting vertically and horizontally. Interfacial alloy metals are formed at the intersections between the metal pillars 135 and the metal layers 130. If the number of metal layers 130 is N and the number of metal pillars 135 is M, the product of M and N is the number of intersections. M and N are natural numbers greater than or equal to 1.

[0076] Table 1, using three metal layers 130 and four metal pillars 135 as an example, illustrates the formation of different interface alloys at 12 different junctions within buffer 120. This cross-design creates different interface alloys at these junctions, improving buffer 120's electrical conductivity, support, and heat dissipation.

[0077] Table 1:

[0078]

[0079] Please combine Figure 7 Multiple metal pillars 135 are spaced apart within the buffer portion 120. One end of each metal pillar 135 is electrically connected to the first electrical connection portion 112, and the other end is electrically connected to the second electrical connection portion 150. Furthermore, metal layers 130 and dielectric layers 140 are arranged alternately in the vertical direction within the buffer portion 120. This further enhances support, heat dissipation, and electrical conductivity.

[0080] Optionally, the sidewalls of the buffer portion 120 are covered with a protective layer 146. The protective layer 146 is made of the same material as the dielectric layer 140 and wraps around the outer metal pillars 135. In other words, the outer surface of the buffer portion 120 is wrapped with the protective layer 146 to prevent the sidewalls from being oxidized.

[0081] It should be noted that the second electrical connection 150 is a metal layer. Optionally, the second electrical connection 150 can be a multi-layer metal layer, including but not limited to at least any two or more of copper, titanium, nickel, vanadium, chromium, gold, titanium, and tungsten formed in a stacked manner.

[0082] Optionally, a multi-layer wiring layer 111 is provided in the interposer 110 . Figure 2 While only one wiring layer 111 is shown, multiple wiring layers 111 can be arranged as needed in the actual process. The number of wiring layers 111 is not limited, and one, two, three, four, or more wiring layers 111 can be designed as needed, without specific limitations here. Adjacent wiring layers 111 are electrically connected, and first electrical connection 112 is electrically connected to the surface wiring layer 111.

[0083] Combine Figure 8 Among the multiple metal pillars 135, some are connected to both the first electrical connection 112 and the second electrical connection 150. Other metal pillars 135 are connected only to the first electrical connection 112, with their other ends not connected to the second electrical connection 150. This design reduces the metal contact area between the bump 160 and the first electrical connection 112, thereby mitigating electromigration. Alternatively, the metal pillars 135 located on the periphery (grown in the fourth subsection 114) are not connected to the second electrical connection 150, while the metal pillars 135 located in the center (grown in the third subsection 113) are connected to the second electrical connection 150. This mitigates electromigration at the periphery of the bump 160 and improves its service life. It is understood that the probability of microcracks occurring at the bottom periphery of the bump 160 structure is higher than at the center. Therefore, in this embodiment, the metal pillars 135 located on the periphery are not connected to the second electrical connection 150.

[0084] Or, combined Figure 9The interposer 110 can be made of an organic dielectric material. The interposer 110 comprises multiple stacked dielectric layers 210, each with a wiring layer 111 within it. The wiring layers 111 within adjacent dielectric layers 210 are electrically connected. The surface dielectric layer 210 is sequentially provided with a first electrical connector 112, a buffer 120, a second electrical connector 150, and bumps 160. The organic dielectric material includes at least one of polyimide and benzocyclobutene. The wiring layer is made of a metallic conductive material, such as copper.

[0085] Optionally, at least one side of the interposer 110 is provided with a first electrical connection portion 112, a buffer portion 120, a second electrical connection portion 150 and a bump 160 in sequence. That is, in the package structure provided in this embodiment, the electrical connection structure with the buffer portion 120 may be provided on one side of the interposer 110, and an existing bump structure may be used on the other side. Figure 9 Alternatively, the electrical connection structure with the buffer portion 120 is provided on both sides of the interposer 110. The electrical connection structure includes a first electrical connection portion 112, a buffer portion 120, a second electrical connection portion 150 and a bump 160.

[0086] Optionally, the interposer 110 is provided with a second groove 115, and the first electrical connection portion 112 is provided in the second groove 115, or the first electrical connection portion 112 is provided in the second groove 115 and extends to the surface of the interposer 110. This is conducive to improving the bonding between the first electrical connection portion 112 and the interposer 110.

[0087] Optionally, in this embodiment, the first electrical connection portion 112 includes a connected third sub-portion 113 and a fourth sub-portion 114. The third sub-portion 113 covers the bottom and walls of the second groove 115, and the fourth sub-portion 114 extends to the surface of the interposer 110. The fourth sub-portion 114 is connected to the second covering portion 154, or the fourth sub-portion 114 is connected to the protective layer 146 of the buffer portion 120.

[0088] Optionally, the first electrical connection portion 112 and the second electrical connection portion 150 are made of any one or more of copper, titanium, nickel, vanadium, chromium, gold, titanium, and tungsten. The various dielectric layers 140 can be made of insulating materials such as at least one of silicon nitride, silicon oxynitride, polyimide, and benzocyclobutene.

[0089] It should be noted that if the sidewalls of the buffer portion 120 are covered with the second covering portion 154, the material of the second covering portion 154 is a conductive material, such as one or more of gold, copper, vanadium, chromium, titanium, and tungsten. This can reduce the metal contact area between the bump 160 and the first electrical connection portion 112, effectively reducing electron migration. If the sidewalls of the buffer portion 120 are covered with the protective layer 146, the protective layer 146 is made of the same material as the dielectric layer 140, and serves to prevent sidewall oxidation.

[0090] Optionally, the chip 171 and the plastic package 172 are further included. The chip 171 and the bump 160 are electrically connected, and the plastic package 172 covers the chip 171 .

[0091] Optionally, the plastic package 172 exposes a surface of the chip 171 away from the interposer 110 to improve heat dissipation.

[0092] Combine Figure 10 Optionally, the 2.5D substrate packaging structure further includes a substrate 173, a metal ring 174, an underfill 175, and components 176. The bump 160 on the side of the interposer 110 away from the chip 171 is electrically connected to the substrate 173. The underfill 175 is disposed between the interposer 110 and the substrate 173 and extends to the sidewall of the interposer 110. The metal ring 174 is connected to the substrate 173 and is disposed on the periphery of the interposer 110. The components 176 are disposed on the substrate 173. The components 176 and the chip 171 may be located on the same side of the interposer 110 or on different sides. In this embodiment, the components 176 are disposed between the interposer 110 and the metal ring 174.

[0093] Combine Figure 11 and Figure 12 In the 2.5D substrate packaging structure provided in this embodiment, multiple chips 171 can be mounted on a single substrate, and the multiple chips 171 can be chips 171 with different functions or different types.

[0094] Combine Figure 13 and Figure 14 , an embodiment of the present invention further provides a packaging method, the steps of which are roughly as follows:

[0095] Step S1 : providing an interposer 110 ; a wiring layer 111 and a first electrical connection portion 112 electrically connected to the wiring layer 111 are provided on the interposer 110 .

[0096] Interposer 110 is made of a silicon- or germanium-based substrate material and can be made of silicon oxide, phosphosilicate glass, fluorine-containing glass, or glass. Interposer 110 has a thickness of 600 to 1500 μm. Interposer 110 includes a first surface 1111 and a second surface 1112 disposed opposite each other along its thickness.

[0097] Electroplating holes 101 are formed on the interposer 110 using a dry etching or chemical etching process. The electroplating holes 101 can be blind holes or through holes. Optionally, blind electroplating holes 101 are formed on the first surface 1111, and the depth of the electroplating holes 101 is set according to actual needs. Dry etching can use carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3) or hydrogen (H2) to form the electroplating holes 101. Alternatively, the electroplating holes 101 can be formed by chemical etching using a mixture of hydrofluoric acid (HF), buffered oxide etchant, sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).

[0098] By using an electroplating process, the interposer 110 structure is placed in an electroplating solution, and metal is electroplated in the electroplating holes 101 to form conductive pillars 117. The conductive pillars 117 are made of copper or other metals.

[0099] The first surface 1111 of the interposer 110 is dry-etched to make the heads of the conductive pillars 117 protrude from the first surface 1111 , with a protrusion height of 2 um to 30 um.

[0100] A fifth dielectric layer 102 is deposited on the first surface 1111 using a vapor deposition method such as PVCD, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The fifth dielectric layer 102 covers the heads of the conductive pillars 117 and is flush with the end faces of the heads of the conductive pillars 117. The fifth dielectric layer 102 is an insulating layer made of any one or more of silicon dioxide, silicon nitride, silicon oxynitride, polyimide, and benzocyclobutene.

[0101] The sixth dielectric layer 103 is formed on the fifth dielectric layer 102 by spray coating or spin coating, and the pattern layer opening 104 is formed on the sixth dielectric layer 103 by exposure and development process. The pattern layer opening 104 exposes the end surface of the conductive pillar 117 .

[0102] Metal is filled in the pattern layer opening 104 by electroplating, sputtering or chemical plating to form a wiring layer 111 , which is the first wiring layer 105 in this case.

[0103] Combine Figure 15 and Figure 16 A seventh dielectric layer 106 is formed on the sixth dielectric layer 103 by spray coating or spin coating. An opening is formed in the seventh dielectric layer 106 by exposure and development steps, exposing a portion of the first wiring layer 105. A metal is then filled into the opening by electroplating, sputtering, or chemical plating to form a first electrical connector 112. The first electrical connector 112 is electrically connected to the first wiring layer 105.

[0104] Step S2 , forming a buffer portion 120 on the first electrical connection portion 112 .

[0105] The dielectric layer 140 is deposited on the first electrical connection portion 112 by using a vapor deposition method such as PVCD, PVD, CVD, MOCVD, ALD, LPCVD or PECVD to form the buffer portion 120 .

[0106] Combine Figure 17 In step S3 , a second electrical connection portion 150 electrically connected to the first electrical connection portion 112 is formed on the buffer portion 120 .

[0107] Optionally, a first groove 121 is formed in the buffer portion 120 by exposure, development, or dry etching. A metal is then filled into the first groove 121 by electroplating, sputtering, or chemical plating to form the second electrical connection 150. The second electrical connection 150 extends from the top surface to the side of the buffer portion 120 and is electrically connected to the first electrical connection 112.

[0108] Step S4 , forming a bump 160 on the second electrical connection portion 150 ; the bump 160 is electrically connected to the second electrical connection portion 150 .

[0109] A ball planting process, which can be electroplating or printing, is used to form spherical or hemispherical bumps 160 on the second electrical connection portion 150, completing the process of the first surface 1111 of the interposer 110. The bumps 160 can be made of SnAg, SnAgCu, or Sn-Bi.

[0110] If it is necessary to form bumps 160 on the second surface 1112 of the interposer 110 , the packaging method further includes step S5 : attaching the tool 107 .

[0111] Combine Figures 18 and 19 A carrier 107 is provided. A layer of bonding adhesive 108 is applied to the surface of the carrier 107. The bonding adhesive 108 can be separated by irradiating ultraviolet light or laser debonding. The side of the interposer 110 with the bumps 160 is mounted on the carrier 107. The carrier 107 can be a metal carrier 107, a glass carrier 107, or the like.

[0112] The second surface 1112 is polished using a chemical polishing process. A polishing slurry such as ammonia, HF, or citric acid is used. Under the pressure of the polishing pad and the centrifugal force, the polishing slurry thins the interposer 110, exposing the conductive pillars 117 from the second surface 1112. At this point, the second surface 1112 and the end faces of the conductive pillars 117 are flush.

[0113] The second surface 1112 is micro-etched by dry etching or chemical etching, so that the end surface of the conductive pillar 117 protrudes from the second surface 1112 with a protrusion height of 2 μm to 30 μm.

[0114] A second wiring layer 109 electrically connected to the conductive pillars 117 and a first electrical connection portion 112 electrically connected to the second wiring layer 109 are formed on the second surface 1112 of the interposer 110. Bumps 160 are formed on the first electrical connection portion 112.

[0115] It should be noted that the process of forming the second wiring layer 109, the first electrical connection portion 112 and the electrical connection structure on the first electrical connection portion 112 on the second surface 1112 side of the interposer 110 is similar to the preparation process on the first surface 1111 side or similar to the existing process.

[0116] Optionally, in this embodiment, a fifth dielectric layer 102 is formed on one side of the second surface 1112, flush with the end faces of the conductive pillars 117. A sixth dielectric layer 103 is formed on the fifth dielectric layer 102. The sixth dielectric layer 103 is exposed and developed to form a patterned layer opening 104. A second wiring layer 109 is formed within the patterned layer opening 104. A seventh dielectric layer 106 is formed on the sixth dielectric layer 103. The seventh dielectric layer 106 is exposed and developed to form an opening. A first electrical connector 112 is formed within the opening. A buffer 120, a second electrical connector 150, and a bump 160 are sequentially formed on the first electrical connector 112. This completes the double-sided fabrication process.

[0117] Combine Figure 20 and Figure 21 , a chip 171 is mounted on at least one side of the interposer 110. The chip 171 is mounted on the bump 160 using a hot press bonding process or a flip chip bonding process, and the soldering structure between the chip 171 and the bump 160 is protected using a dispensing process.

[0118] The chip 171 is encapsulated by a plastic encapsulation process to form a plastic encapsulation body 172 .

[0119] Thinning the plastic package 172 to expose the surface of the chip 171. The plastic package 172 is thinned by mechanical grinding or chemical grinding to expose the back of the chip 171 to improve heat dissipation performance.

[0120] The carrier 107 is removed by ultraviolet light irradiation or laser debonding.

[0121] Using cutting technology, the products are cut and separated into individual pieces to complete the process.

[0122] Optionally, the above process steps may be adjusted appropriately according to the specific structural differences of the buffer portion 120. For example, if Figure 4 The buffer portion 120 shown in FIG. 1 is generally described as follows:

[0123] Combine Figure 22 and Figure 23After forming the first electrical connector 112 on the seventh dielectric layer 106, a first dielectric layer 141, a first metal layer 131, a second dielectric layer 142, a second metal layer 132, a third dielectric layer 143, a third metal layer 133, and a fourth dielectric layer 144 are sequentially formed on the first electrical connector 112. A first recess 121 is formed by micro-etching in the fourth dielectric layer 144. A second electrical connector 150 is formed by electroplating in the first recess 121. The second electrical connector 150 extends to the sidewall and is electrically connected to the first electrical connector 112. A bump 160 is then implanted on the second electrical connector 150.

[0124] Accordingly, to prepare Figure 8 The buffer portion 120 shown in FIG. 1 is generally described as follows:

[0125] Combine Figures 24 to 26 After forming the first electrical connection 112 on the seventh dielectric layer 106, a plurality of metal pillars 135 are formed on the first electrical connection 112. A second alternating stacking structure of metal layers 130 and dielectric layers 140 is then formed on the first electrical connection 112. The second alternating stacking structure includes a layer of dielectric layer 140, a layer of metal layer 130, a layer of dielectric layer 140, a layer of metal layer 130, ..., a layer of dielectric layer 140. The top dielectric layer 140 is higher than the end surface of the metal pillar 135. Figure 25 When the fourth dielectric layer 144 is formed, a ring-shaped protective layer 146 covering the outer metal pillar 135 is formed at the same time.

[0126] A first recess 121 is formed in the topmost dielectric layer 140 by micro-etching or exposure and development. The first recess 121 exposes the end surface of the metal pillar 135. A second electrical connector 150 is formed by electroplating in the first recess 121. The second electrical connector 150 is electrically connected to at least one metal pillar 135. The second electrical connector 150 extends outward from the second recess 115 to connect with the upper end surface of the annular protective layer 146. A bump 160 is then implanted on the second electrical connector 150.

[0127] The 2.5D substrate packaging structure and packaging method provided by the embodiments of the present invention have the following beneficial effects, including:

[0128] The 2.5D substrate package structure and packaging method provided by embodiments of the present invention form a buffer portion 120 on the first electrical connection 112, reducing the metal contact area between the bump 160 and the first electrical connection 112, effectively preventing electromigration and improving the lifespan of the bump 160. Furthermore, the buffer portion 120 provides excellent support and cushioning properties, absorbing the mounting pressure of the chip 171 and preventing direct impact of mounting pressure and soldering stress on the first electrical connection 112, which could lead to cracks. Furthermore, the use of multiple metal layers 130 within the buffer portion 120 further enhances heat dissipation, support, and electrical conductivity, mitigating warping and deformation of the package structure, and improving package quality and structural lifespan.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the scope of protection of the present invention.

Claims

1. A 2.5D substrate packaging structure, characterized in that: include: an interposer, wherein a wiring layer and a first electrical connection portion electrically connected to the wiring layer are provided on the interposer; a buffer portion, the buffer portion being provided on a side of the first electrical connection portion away from the wiring layer; a second electrical connection portion, the second electrical connection portion being disposed on a side of the buffer portion away from the first electrical connection portion; the second electrical connection portion being electrically connected to the first electrical connection portion; a bump, the bump being located on a side of the second electrical connection portion away from the buffer portion and being electrically connected to the second electrical connection portion; A metal column and a metal layer are provided in the buffer portion. The metal column and the metal layer are arranged crosswise and form an interface alloy metal at the junction.

2. The 2.5D substrate packaging structure according to claim 1, wherein: The second electrical connection portion includes a first covering portion and a second covering portion connected to each other, the first covering portion is arranged on a side of the buffer portion away from the wiring layer, and the bump is connected to the first covering portion; the second covering portion covers the side wall of the buffer portion, and the second covering portion is electrically connected to the first electrical connection portion.

3. The 2.5D substrate packaging structure according to claim 2, wherein: A first groove is provided on the surface of the buffer portion on one side away from the intermediary layer, and the first covering portion includes a first branch and a second branch connected to each other, the first branch covering the bottom and wall of the groove; the second branch is connected to the periphery of the first branch and extends to the surface of the buffer portion; the second branch is connected to the second covering portion.

4. The 2.5D substrate packaging structure according to claim 2, wherein: The buffer portion includes metal layers and dielectric layers alternately stacked. The surface layer of the buffer portion away from the wiring layer is a dielectric layer, and the second electrical connection portion is connected to the dielectric layer on the surface.

5. The 2.5D substrate packaging structure according to claim 4, wherein: The metal layer includes a first metal layer, a second metal layer and a third metal layer, and the dielectric layer includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer; The first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the third metal layer and the fourth dielectric layer are sequentially arranged on the first electrical connection portion; the second electrical connection portion is connected to the fourth dielectric layer.

6. The 2.5D substrate packaging structure according to claim 5, wherein: The second covering portion is connected to side walls of the first metal layer, the second metal layer, and the third metal layer, respectively.

7. The 2.5D substrate packaging structure according to claim 5, wherein: The first metal layer is a titanium layer, the second metal layer is a titanium-tungsten layer, and the third metal layer is a gold layer.

8. The 2.5D substrate packaging structure according to any one of claims 1 to 7, wherein: One end of at least one of the metal pillars is electrically connected to the first electrical connection portion, and the other end is electrically connected to the second electrical connection portion.

9. The 2.5D substrate packaging structure according to any one of claims 1 to 7, wherein: The outer peripheral surface of the buffer portion is covered with a protective layer.

10. The 2.5D substrate packaging structure according to any one of claims 1 to 7, wherein: The interposer is provided with multiple wiring layers; Alternatively, the interposer is made of organic dielectric material, and the interposer includes a plurality of stacked dielectric layers, each of which is provided with a wiring layer, and the wiring layers in adjacent dielectric layers are electrically connected; the first electrical connection portion, the buffer portion, the second electrical connection portion and the bump are sequentially provided on the surface dielectric layer.

11. The 2.5D substrate packaging structure according to any one of claims 1 to 7, characterized in that: The first electrical connection portion, the buffer portion, the second electrical connection portion and the bump are sequentially provided on at least one side surface of the interposer.

12. The 2.5D substrate packaging structure according to any one of claims 1 to 7, wherein: The intermediary layer is provided with a second groove, and the first electrical connection portion is provided in the second groove, or the first electrical connection portion is provided in the second groove and extends to the surface of the intermediary layer.

13. The 2.5D substrate packaging structure according to any one of claims 1 to 7, characterized in that: It also includes a chip and a plastic package, wherein the chip and the bump are electrically connected, and the plastic package covers the chip.

14. A packaging method, characterized in that: Used to prepare the 2.5D substrate packaging structure as claimed in any one of claims 1 to 13.

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