Low-noise low-offset high-bandwidth offset stable amplifier and control method thereof

Abstract

The invention discloses a low-noise low-offset high-bandwidth offset stable amplifier and a control method thereof. The amplifier comprises a high-bandwidth main amplifier, a high-gain auxiliary amplifier, an active integrator, a digital automatic trimming module and a resistance module. The control method comprises the following steps: performing coarse offset calibration on the high-bandwidth main amplifier to obtain a calibrated high-bandwidth main amplifier; performing conversion processing on the input equivalent offset voltage with low-frequency noise, and outputting a detection current signal; performing offset compensation processing on the detection current signal to generate offset compensation current; and the calibrated high-bandwidth main amplifier carries out suppression processing on the input equivalent offset voltage with low-frequency noise according to the offset compensation current, and outputs an output voltage with high bandwidth. According to the embodiment of the invention, the performance of ultra-low imbalance and ultra-low noise can be continuously provided in a complex and changeable working environment. The method can be widely applied to the technical field of analog integrated circuits.

Description

Technical Field

[0001] The present application relates to the field of analog integrated circuit technology, and in particular to a low-noise, low-offset, high-bandwidth offset-stabilized amplifier and a control method thereof. Background Art

[0002] Related technologies use automatic trimming schemes to achieve low-cost offset correction, but these techniques cannot guarantee offset consistency across different operating environments and lack the ability to suppress circuit noise. To further reduce offset and suppress low-frequency noise, dynamic offset cancellation techniques are needed. These techniques primarily include chopping and auto-zeroing. Existing offset-stabilized amplifiers typically employ a dual-path design: dynamic offset cancellation is used in an auxiliary signal path to achieve low offset, and the auxiliary signal path is then used to suppress the offset of the main signal path. This offset-stabilized structure effectively suppresses offset and 1 / f noise while increasing the operational bandwidth of the operational amplifier. However, bandwidth expansion is still limited by existing dynamic offset cancellation techniques. Taking auto-zeroing technology as an example, switch sampling can cause noise aliasing, raising the noise floor within the operating bandwidth. Chopping technology, on the other hand, requires setting the chopping frequency far above the operating bandwidth to migrate low-frequency noise to the high-frequency region. When the operating bandwidth reaches hundreds of kHz, the chopping frequency must be higher than 1MHz, which exacerbates non-ideal effects such as charge injection and clock feedthrough, and significantly increases circuit power consumption. Furthermore, increasing the chopping frequency reduces the amplifier gain in the auxiliary signal path, weakening the ability to suppress offset voltage. Existing technologies have proposed setting the chopping frequency within the operating bandwidth, but this does not reduce the in-band integrated noise, and the ripple caused by chopping cannot be filtered out. In summary, as the operating bandwidth continues to increase, the ability of related technical solutions to suppress offset and noise gradually weakens, and other non-ideal effects are also triggered, resulting in a significant decline in the overall performance of the op amp.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to provide a low-noise, low-offset, high-bandwidth offset-stable amplifier and a control method thereof, which can continuously provide ultra-low offset and ultra-low noise performance in a complex and changeable working environment.

[0005] To achieve the above objectives, an embodiment of the present application provides a low-noise, low-offset, high-bandwidth offset-stable amplifier in one aspect. The amplifier includes a high-bandwidth main amplifier, a high-gain auxiliary amplifier, an active integrator, a digital automatic trimming module, and a resistor module. The output of the high-gain auxiliary amplifier is connected to the input of the active integrator, the first output of the active integrator is connected to the first input of the high-bandwidth main amplifier, the second output of the active integrator is connected to the first input of the high-gain auxiliary amplifier, the third output of the active integrator is connected to the input of the digital automatic trimming module, the first output of the digital automatic trimming module is connected to the second input of the high-bandwidth main amplifier, the second output of the digital automatic trimming module is connected to the second input of the high-gain auxiliary amplifier, the first output of the resistor module is connected to the third input of the high-gain auxiliary amplifier, the second output of the resistor module is connected to the third input of the high-bandwidth main amplifier, and the third output of the resistor module is connected to the output of the high-bandwidth main amplifier.

[0006] The digital automatic adjustment module is used to perform coarse offset calibration on the high-bandwidth main amplifier;

[0007] The high-gain auxiliary amplifier is used to convert the input equivalent offset voltage with low-frequency noise and output a detection current signal;

[0008] The active integrator is used to perform offset compensation processing on the detection current signal to generate an offset compensation current;

[0009] The high-bandwidth main amplifier is used to suppress the input equivalent offset voltage with low-frequency noise according to the offset compensation current after the offset coarse calibration, and output an output voltage with a high bandwidth;

[0010] The resistance module is used to control the amplification gain coefficient of the high-bandwidth main amplifier.

[0011] In some embodiments, the high-bandwidth main amplifier includes a first switch, a second switch, a first on-chip capacitor, a second on-chip capacitor, a rail-to-rail input stage, an offset compensation input stage, and a rail-to-rail output stage. The negative phase output terminal of the rail-to-rail input stage and the negative phase output terminal of the offset compensation input stage are connected to the positive phase input terminal of the rail-to-rail output stage. The positive phase output terminal of the rail-to-rail input stage and the positive phase output terminal of the offset compensation input stage are connected to the negative phase input terminal of the rail-to-rail output stage. The negative phase output terminal of the rail-to-rail output stage is connected to the positive phase input terminal of the rail-to-rail input stage and the negative phase input terminal of the rail-to-rail output stage through resistors. The first and second ends of the first and second on-chip capacitors are connected to the active integrator, respectively. The first and second ends of the first and second on-chip capacitors are grounded.

[0012] In some embodiments, the equivalent transconductance value of the offset compensation input stage is less than the equivalent transconductance value of the rail-to-rail input stage, and during the coarse offset calibration of the high-bandwidth main amplifier, the equivalent transconductance value of the offset compensation input stage is pulled up until the coarse offset calibration is completed, and the equivalent transconductance value of the offset compensation input stage is restored, wherein:

[0013] The rail-to-rail input stage is used to provide a low-frequency gain coefficient, pre-process the input equivalent offset voltage with low-frequency noise, and transmit it to the rail-to-rail output stage;

[0014] The offset compensation input stage is used to obtain the output signal of the active integrator and suppress the low-frequency noise of the high-bandwidth main amplifier;

[0015] The rail-to-rail output stage is used to improve the output swing and driving capability of the high-bandwidth main amplifier.

[0016] In some embodiments, an equivalent circuit of the offset compensation input stage includes a first bias current source, a second bias current source, a third bias current source, a third switch, a fourth switch, a third resistor, a fourth resistor, a first transistor, and a second transistor. A first terminal of the first bias current source is connected to a high-level signal. A second terminal of the first bias current source, a second terminal of the third switch, a second terminal of the third resistor, a first terminal of the fourth switch, and a first terminal of the fourth resistor are connected. A first terminal of the third switch and a first terminal of the third resistor are connected to a source of the first transistor. A second terminal of the fourth switch and a second terminal of the fourth resistor are connected to a source of the second transistor. A drain of the first transistor is connected to a first terminal of the second bias current source. A drain of the second transistor is connected to a first terminal of the third bias current source. A second terminal of the second bias current source and a second terminal of the third bias current source are both grounded.

[0017] In some embodiments, the high-gain auxiliary amplifier includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a third on-chip capacitor, a fourth on-chip capacitor, an input chopper, a rail-to-rail input amplifier stage, an auto-zero input stage, and an output chopper, wherein the first end of the fifth switch and the first end of the sixth switch are respectively connected to the high-bandwidth main amplifier, the second end of the fifth switch and the first end of the seventh switch are connected to the first end of the input chopper, the second end of the sixth switch and the second end of the seventh switch are connected to the second end of the input chopper, the first output end of the input chopper is connected to the positive-phase input end of the rail-to-rail input amplifier stage, and the second output end of the input chopper is connected to the negative-phase input end of the rail-to-rail input amplifier stage. The negative phase output terminal of the rail-to-rail input amplifier stage, the first input terminal of the output chopper, and the negative phase output terminal of the auto-zero input stage are connected to the digital automatic trimming module; the positive phase output terminal of the rail-to-rail input amplifier stage, the second input terminal of the output chopper, and the positive phase output terminal of the auto-zero input stage are connected to the digital automatic trimming module; the negative phase input terminal of the auto-zero input stage and the second end of the third on-chip capacitor are connected to the first end of the eighth switch; the positive phase input terminal of the auto-zero input stage and the first end of the fourth on-chip capacitor are connected to the first end of the ninth switch; the first end of the third on-chip capacitor and the second end of the fourth on-chip capacitor are both grounded; and the second end of the eighth switch and the second end of the ninth switch are respectively connected to the active integrator.

[0018] In some embodiments, the equivalent transconductance value of the auto-zero input stage is less than the equivalent transconductance value of the rail-to-rail input amplifier stage, and during the coarse offset calibration of the high-bandwidth main amplifier, the equivalent transconductance value of the auto-zero input stage is pulled up until the coarse offset calibration is completed and the equivalent transconductance value of the auto-zero input stage is restored, wherein:

[0019] The auto-zero input stage and the rail-to-rail input amplifier stage are used to eliminate the offset of the high-gain auxiliary amplifier and suppress the low-frequency noise of the high-gain auxiliary amplifier;

[0020] The input chopper and the output chopper are used to eliminate low-frequency aliasing noise generated by self-zeroing.

[0021] In some embodiments, the active integrator includes an operational amplifier, a fifth on-chip capacitor, a sixth on-chip capacitor, a seventh on-chip capacitor, an eighth on-chip capacitor, a first gating switch, a second gating switch, a tenth switch, and an eleventh switch, wherein the first end of the tenth switch, the first end of the fifth on-chip capacitor, the first end of the seventh on-chip capacitor, and the negative phase input of the operational amplifier are connected to the high-gain auxiliary amplifier, the second end of the tenth switch, the second end of the seventh on-chip capacitor, and the second end of the first gating switch are connected to the high-bandwidth main amplifier, and the second end of the fifth on-chip capacitor, the first end of the first gating switch and the high-gain auxiliary amplifier are connected. The first gate switch is connected to the digital automatic adjustment module, the positive phase output terminal of the operational amplifier and the third end of the first gate switch are connected to the digital automatic adjustment module, the negative phase output terminal of the operational amplifier and the first end of the second gate switch are connected to the digital automatic adjustment module, the positive phase input terminal of the operational amplifier, the first end of the sixth on-chip capacitor, the first end of the eighth on-chip capacitor and the first end of the eleventh switch are connected, the second end of the sixth on-chip capacitor and the second end of the second gate switch are connected to the high-gain auxiliary amplifier, and the second end of the eighth on-chip capacitor, the second end of the eleventh switch, and the third end of the second gate switch are connected to the high-bandwidth main amplifier.

[0022] In some embodiments, the digital automatic adjustment module includes a comparator circuit, a current steering DAC circuit, a SAR control logic circuit, and a current DAC control signal generating circuit, wherein the positive input terminal and the negative input terminal of the comparator circuit are both connected to the high-gain auxiliary amplifier, the output terminal of the comparator circuit is connected to the input terminal of the SAR control logic circuit, the first output terminal of the SAR control logic circuit is feedback-connected to the comparator circuit, the second output terminal of the SAR control logic circuit is connected to the input terminal of the current DAC control signal generating circuit, the current steering DAC circuit is connected to the current DAC control signal generating circuit, and the current steering DAC circuit is further connected to the high-gain auxiliary amplifier and the high-bandwidth main amplifier, respectively, wherein:

[0023] The comparator circuit is used to compare the positive and negative output terminal voltages of the active integrator to obtain a comparison result;

[0024] The SAR control logic circuit is used to perform SAR logic control according to the comparison result to obtain an offset calibration control word;

[0025] The current DAC control signal generating circuit is used to generate a switch control signal according to the comparison result;

[0026] The current-steering DAC circuit is used to perform coarse offset calibration on the high-gain auxiliary amplifier and the high-bandwidth main amplifier according to the offset calibration control word and the switch control signal.

[0027] In some embodiments, the current-steering DAC circuit includes a fourth bias current source, a fifth bias current source, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, and a seventeenth switch, wherein a first terminal of the fourth bias current source is connected to a high level, a second terminal of the fourth bias current source, a first terminal of the twelfth switch, a first terminal of the thirteenth switch, and a first terminal of the fourteenth switch are connected, a second terminal of the twelfth switch is connected to a first terminal of the fifteenth switch, a second terminal of the thirteenth switch is connected to a first terminal of the sixteenth switch, a second terminal of the fourteenth switch is connected to a first terminal of the seventeenth switch, a second terminal of the fifteenth switch, a second terminal of the sixteenth switch, and a second terminal of the seventeenth switch are connected to a first terminal of the fifth bias current source, and a second terminal of the fifth bias current source is grounded.

[0028] To achieve the above objectives, another aspect of the present invention provides a control method for a low-noise, low-offset, high-bandwidth offset-stable amplifier. The control method comprises the following steps:

[0029] performing a coarse offset calibration on the high-bandwidth main amplifier to obtain a calibrated high-bandwidth main amplifier;

[0030] Convert the input equivalent offset voltage with low-frequency noise and output a detection current signal;

[0031] performing offset compensation processing on the detection current signal to generate an offset compensation current;

[0032] The calibrated high-bandwidth main amplifier suppresses the input equivalent offset voltage with low-frequency noise according to the offset compensation current, and outputs an output voltage with a high bandwidth.

[0033] The embodiments of the present application include at least the following beneficial effects: The present application provides a low-noise, low-offset, high-bandwidth offset-stable amplifier and a control method thereof. The scheme disconnects an auxiliary signal path composed of a high-gain auxiliary amplifier and an active integrator from a main signal path composed of a high-bandwidth main amplifier during a calibration phase, wherein the main signal path processes a continuously input signal, while the auxiliary signal path performs self-zeroing, thereby reducing the offset and noise of the high-gain auxiliary amplifier to an extremely low level; during an offset stabilization phase, the auxiliary signal path is connected in parallel with the main signal path, and the equivalent offset and low-frequency noise at the input end of the high-bandwidth main amplifier are detected by the high-gain auxiliary amplifier and converted into a current signal. After the active integrator integrates the current signal, compensation is provided to the high-bandwidth main amplifier in the form of current through the offset compensation input stage, thereby eliminating the offset and noise of the high-bandwidth main amplifier; by periodically alternating between the calibration phase and the offset stabilization phase, the low-noise, low-offset, high-bandwidth offset-stable amplifier can continuously provide ultra-low offset and ultra-low noise performance in a complex and changing working environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 1 is a schematic structural diagram of a low-noise, low-offset, high-bandwidth offset-stable amplifier provided in an embodiment of the present application;

[0035] Figure 2 This is a flowchart of the steps of a control method for a low-noise, low-offset, high-bandwidth offset-stabilized amplifier provided by an embodiment of the present application;

[0036] Figure 3 1 is a schematic diagram of the circuit structure of a high-bandwidth main amplifier provided in an embodiment of the present application;

[0037] Figure 4 1 is a schematic diagram of the circuit structure of the offset compensation input stage provided in an embodiment of the present application;

[0038] Figure 5 1 is a schematic diagram of the circuit structure of a high-gain auxiliary amplifier provided in an embodiment of the present application;

[0039] Figure 6 1 is a schematic diagram of the circuit structure of the active integrator provided in an embodiment of the present application;

[0040] Figure 7 Schematic diagram of the internal components of the digital automatic adjustment module provided in an embodiment of the present application;

[0041] Figure 8 1 is a schematic diagram of the circuit structure of a comparator provided in an embodiment of the present application;

[0042] Figure 9 Schematic diagram of the circuit structure of the current-steering DAC unit provided in an embodiment of the present application.

[0043] Description of the figures: 1. High-bandwidth main amplifier; 11. Rail-to-rail input stage; 12. Offset compensation input stage; 13. Rail-to-rail output stage; 2. High-gain auxiliary amplifier; 21. Rail-to-rail input amplifier stage; 22. Auto-zero input stage; 3. Active integrator; 31. Operational amplifier; 4. Digital automatic adjustment module; 41. Comparator circuit; 42. Current-steering DAC circuit; 43. SAR control logic circuit; 44. Current DAC control signal generation circuit. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0045] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0046] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0048] First, it's important to note that in modern electronic systems, operational amplifiers (op amps), as high-gain, differential-input analog integrated circuits, are widely used in signal conditioning, filtering, and sensor interfaces. With the rapid development of industrial automation, medical testing, and new energy vehicles, the demand for low-noise, low-offset, and high-bandwidth amplifiers has become increasingly prominent. This is especially true when operating for extended periods or in extreme environments, where op amps must maintain high precision and stability. Low noise effectively improves the signal-to-noise ratio; low offset ensures the reliability of high-precision measurements; and high bandwidth meets the demands of high-speed signal processing. However, existing amplifiers face significant challenges in achieving these three characteristics simultaneously.

[0049] In view of this, an embodiment of the present application provides a low-noise, low-offset, high-bandwidth offset-stable amplifier, including a high-bandwidth main amplifier, a high-gain auxiliary amplifier, an active integrator, a digital automatic trimming module, and a resistor module; the high-bandwidth main amplifier is composed of a rail-to-rail input stage, an offset compensation input stage, and a rail-to-rail output stage; the high-gain auxiliary amplifier is used to detect input equivalent offset and noise; the active integrator uses time-division multiplexing to perform auto-zeroing to eliminate the offset of the high-gain auxiliary amplifier during the calibration phase and eliminate the offset of the high-bandwidth main amplifier during the offset stabilization phase; the digital automatic trimming module includes a comparator circuit, a current-steering DAC, and a digital control circuit, which performs coarse offset calibration on the amplifier after the circuit is powered on; and the resistor module provides closed-loop feedback. The embodiment of the present invention can exhibit low-noise characteristics within a wide bandwidth, effectively suppress offset and 1 / f noise, and meet the application requirements of ultra-high precision and low noise interference in high-bandwidth working scenarios.

[0050] Reference Figure 1 , Figure 1 A flow chart of a low noise, low offset, high bandwidth offset stable amplifier provided by an embodiment of the present invention, referring to Figure 1The amplifier includes a high-bandwidth main amplifier 1, a high-gain auxiliary amplifier 2, an active integrator 3, a digital automatic adjustment module 4, and a resistance module. The output end of the high-gain auxiliary amplifier is connected to the input end of the active integrator, the first output end of the active integrator is connected to the first input end of the high-bandwidth main amplifier, the second output end of the active integrator is connected to the first input end of the high-gain auxiliary amplifier, the third output end of the active integrator is connected to the input end of the digital automatic adjustment module, the first output end of the digital automatic adjustment module is connected to the second input end of the high-bandwidth main amplifier, the second output end of the digital automatic adjustment module is connected to the second input end of the high-gain auxiliary amplifier, the first output end of the resistance module is connected to the third input end of the high-gain auxiliary amplifier, the second output end of the resistance module is connected to the third input end of the high-bandwidth main amplifier, and the third output end of the resistance module is connected to the output end of the high-bandwidth main amplifier, wherein:

[0051] The digital automatic trimming module is used to perform coarse offset calibration on the high-bandwidth main amplifier;

[0052] Specifically, the digital automatic adjustment module includes a comparator circuit 41, a current steering DAC circuit 42, a SAR control logic circuit 43 and a current DAC control signal generating circuit 44, wherein the positive input terminal of the comparator circuit and the negative input terminal of the comparator circuit are both connected to the high-gain auxiliary amplifier, the output terminal of the comparator circuit is connected to the input terminal of the SAR control logic circuit, the first output terminal of the SAR control logic circuit is connected to the feedback of the comparator circuit, the second output terminal of the SAR control logic circuit is connected to the input terminal of the current DAC control signal generating circuit, the current steering DAC circuit is connected to the current DAC control signal generating circuit, and the current steering DAC circuit is also connected to the high-gain auxiliary amplifier and the high-bandwidth main amplifier respectively, wherein the comparator circuit is used to compare the positive and negative output terminal voltages of the active integrator to obtain a comparison result; the SAR control logic circuit is used to execute SAR logic control according to the comparison result to obtain an offset calibration control word; the current DAC control signal generating circuit is used to generate a switch control signal according to the comparison result; and the current steering DAC circuit is used to perform coarse offset calibration on the high-gain auxiliary amplifier and the high-bandwidth main amplifier according to the offset calibration control word and the switch control signal.

[0053] In this embodiment, the digital automatic adjustment module includes a comparator circuit, a current-steering DAC circuit, a SAR control logic circuit, and a current DAC control signal generation circuit. After the circuit is powered on, the amplifier performs coarse offset calibration. During the power-on calibration phase, the comparator circuit compares the positive and negative output voltages of the active integrator and sends the comparison result to the SAR control logic circuit. The SAR control logic circuit executes SAR logic to determine the offset calibration control word. The current DAC control signal generation circuit then generates a switch control signal. The current-steering DAC is used to sequentially perform coarse offset calibration on the high-gain auxiliary amplifier and the high-bandwidth main amplifier in the form of current feedback.

[0054] The comparator circuit is a two-stage structure consisting of a preamplifier, a latch-structured comparator, and a capacitor. The comparator circuit utilizes auto-zeroing technology to store the preamplifier's output offset, resulting in a high-precision comparator with minimal footprint and low power consumption. The current DAC control signal generation circuit uses digital logic to generate the switch control signal. During the switching process, logic gates are introduced for level detection, enabling more robust crosspoint control. This reduces glitches caused by the current-steering DAC output current switching, thereby improving the stability of the precision system.

[0055] Furthermore, it should be noted that the current steering DAC circuit includes a fourth bias current source I bp42 , the fifth bias current source I bn42 , a twelfth switch K421, a thirteenth switch K422, a fourteenth switch K423, a fifteenth switch K424, a sixteenth switch K425 and a seventeenth switch K426, wherein a first end of the fourth bias current source is connected to a high level, a second end of the fourth bias current source, a first end of the twelfth switch, a first end of the thirteenth switch and a first end of the fourteenth switch are connected, a second end of the twelfth switch is connected to a first end of the fifteenth switch, a second end of the thirteenth switch is connected to a first end of the sixteenth switch, a second end of the fourteenth switch is connected to a first end of the seventeenth switch, a second end of the fifteenth switch, a second end of the sixteenth switch and a second end of the seventeenth switch are connected to a first end of the fifth bias current source, and a second end of the fifth bias current source is grounded.

[0056] More specifically, Figure 7As shown, in an embodiment of the present invention, a low-noise, low-offset, high-bandwidth offset-stabilized amplifier, the digital automatic adjustment module includes a comparator circuit, a current-steering DAC, a SAR control logic circuit, and a current DAC control signal generation circuit. The comparator circuit input is connected to the active integrator output, the comparator circuit output is connected to the SAR control logic circuit, the SAR control logic circuit provides a control signal to the comparator circuit, the SAR control logic circuit output is connected to the current DAC control signal generation circuit, and the current DAC control signal generation circuit output is connected to the current-steering DAC. The current-steering DAC provides current to the high-bandwidth main amplifier and the high-gain auxiliary amplifier, respectively.

[0057] like Figure 8 As shown, the low noise, low offset, high bandwidth offset stable amplifier of this embodiment, the comparator is biased by the current source I bp411 , I bp412 , P-type metal oxide semiconductor field effect transistors M411, M412, M413, M414, M415, M416, N-type metal oxide semiconductor field effect transistors M417, M418, M419, M4110, M4111, M4112, switches K411, K412, K413, K414, K415, K416, capacitors C411, C412, and resistors R411, R412. One end of the switch K411 is connected to the input signal, and the other end is connected to the gate of the transistor M411 and one end of the switch K413. One end of the switch K412 is connected to the input signal, and the other end is connected to the gate of the transistor M412 and the other end of the switch K413. The source of the transistor M411 and the source of the transistor M412 are connected to the bias current source I bp411 The drain of the transistor M411 and one end of the resistor R411 are connected to one end of the capacitor C412, the other end of the resistor R411 is grounded, the other end of the capacitor C412 and one end of the switch K416 are connected to the gate of the transistor M414, the other end of the switch K416 is connected to the drain of the transistor M414, the drain of the transistor M412 and one end of the resistor R412 are connected to one end of the capacitor C411, the other end of the resistor R412 is grounded, the other end of the capacitor C411 and one end of the switch K415 are connected to the gate of the transistor M413, the other end of the switch K415 is connected to the drain of the transistor M413, the source of the transistor M413 and the source of the transistor M414 are connected to one end of the switch K414, and the other end of the switch K414 is connected to the bias current source I bp412The drain of transistor M413 is connected to the source of transistor M415 and the drain of transistor M4111. The drain of transistor M414 is connected to the source of transistor M416 and the drain of transistor M4112. The gate of transistor M415 is connected to the drain of transistor M416, the gate of transistor M417, the drain of transistor M418, and the drain of transistor M4110. The gate of transistor M416 is connected to the drain of transistor M415, the gate of transistor M418, the drain of transistor M417, and the drain of transistor M419. The sources of transistors M417, M418, M419, M4110, M4111, and M4112 are grounded. The gates of transistors M419, M4110, M4111, and M4112 are controlled by the ΦZ signal.

[0058] In this embodiment, the comparator circuit has a two-stage structure and utilizes an auto-zeroing technique to store the output offset of the pre-amplifier, thereby achieving a high-precision comparator with an extremely small area and extremely low power consumption. In the ΦZ stage, the two input terminals of the comparator circuit are disconnected from the external environment and short-circuited by switch K413. The offsets of transistors M411 and M412 are stored on the plates of capacitors C411 and C412. At this time, switch K414 is disconnected, and the second-stage comparator is in a reset state. In the ΦA stage, the two input terminals of the comparator circuit are connected to the external environment, switch K414 is closed, and the second-stage comparator is in an operating state. The voltage stored on the plates of capacitors C411 and C412 eliminates the offset of the first-stage pre-amplifier, improving the accuracy of the comparator.

[0059] like Figure 9 As shown, the low-noise, low-offset, high-bandwidth offset-stable amplifier of this embodiment, the current-steering DAC unit includes two bias current sources I bp42 , I bn42 And switches K421, K422, K423, K424, K425, K426. Among them, one end of the switches K421, K422, K423 is connected together and connected to the bias current source I bp42 The other end of switch K421 is connected to the positive output of DAC, the other end of switch K422 is connected to one end of switch K425, the other end of switch K421 is connected to the positive output of DAC, one end of switches K424, K425 and K426 are connected together and connected to the bias current source I bn42 The other end of the switch K424 is connected to the positive output end of the DAC, and the other end of the switch K426 is connected to the negative output end of the DAC.

[0060] In this embodiment, the current steering DAC unit has three states: one is the positive output terminal with current flowing out and the negative output terminal with current flowing in; the second is the positive output terminal with current flowing in and the negative output terminal with current flowing out; the third is the output terminal is off and the middle branch is open. The bias current source of the current steering DAC has special requirements for the cross point design of the switch control signal. When the bias current source is completely turned off, there will be a large output current fluctuation when it is restored. Therefore, it is necessary to ensure that the bias current source I bp42 and I bn42 Always on.

[0061] according to Figure 9 The switch position shown can list the control signal truth table, as shown in Table 1, where the control word SF controls the current direction, the control word B determines whether the current flows, and the switches K421, K422, K423, K424, K425, and K426 are turned on at a high level.

[0062] Table 1 Current steering DAC unit control logic truth table

[0063] SF B K421 K422 K423 K424 K425 K426 X 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 0 1 0 0

[0064] In this embodiment, a logic gate circuit is introduced to detect the level status during the switching process of the switch control signal. According to Table 1, an exclusive OR logic circuit can be used to determine whether the DAC output current switch is on. If it is on, K422 and K425 are controlled to be off. This ensures that the current source is always on when the DAC output is on, thereby achieving more robust crosspoint control, reducing the glitches caused by the current-steering DAC output current switching, and thus improving the stability of the precision system.

[0065] The high-gain auxiliary amplifier is used to convert the input equivalent offset voltage with low-frequency noise and output a detection current signal;

[0066] Specifically, the high-gain auxiliary amplifier includes a fifth switch K21, a sixth switch K22, a seventh switch K23, an eighth switch K24, a ninth switch K25, a third on-chip capacitor C3, a fourth on-chip capacitor C4, an input chopper CH1, a rail-to-rail input amplifier stage 21, an auto-zero input stage 22, and an output chopper CH2, wherein the first end of the fifth switch and the first end of the sixth switch are respectively connected to the high-bandwidth main amplifier, the second end of the fifth switch and the first end of the seventh switch are connected to the first end of the input chopper, the second end of the sixth switch and the second end of the seventh switch are connected to the second end of the input chopper, the first output end of the input chopper is connected to the non-inverting input end of the rail-to-rail input amplifier stage, and the second end of the input chopper is connected to the positive-inverting input end of the rail-to-rail input amplifier stage. The output end is connected to the negative phase input end of the rail-to-rail input amplifier stage, the negative phase output end of the rail-to-rail input amplifier stage, the first input end of the output chopper, and the negative phase output end of the auto-zero input stage are connected to the digital automatic adjustment module, the positive phase output end of the rail-to-rail input amplifier stage, the second input end of the output chopper, and the positive phase output end of the auto-zero input stage are connected to the digital automatic adjustment module, the negative phase input end of the auto-zero input stage and the second end of the third on-chip capacitor are connected to the first end of the eighth switch, the positive phase input end of the auto-zero input stage and the first end of the fourth on-chip capacitor are connected to the first end of the ninth switch, the first end of the third on-chip capacitor and the second end of the fourth on-chip capacitor are both grounded, and the second end of the eighth switch and the second end of the ninth switch are respectively connected to the active integrator.

[0067] In this embodiment, the high-gain auxiliary amplifier includes an input chopper, a rail-to-rail input amplifier stage, an auto-zero input stage, and an output chopper. The input end of the auto-zero input stage is connected to an active integrator, and the output end of the auto-zero input stage is connected to the output end of the rail-to-rail input amplifier stage, so as to eliminate the offset of the high-gain auxiliary amplifier and suppress low-frequency noise. The chopper is located at the input and output of the rail-to-rail input amplifier stage, so as to eliminate the low-frequency aliasing noise generated by auto-zeroing.

[0068] Furthermore, it should be noted that the equivalent transconductance value of the auto-zero input stage is smaller than the equivalent transconductance value of the rail-to-rail input amplifier stage, and during the coarse offset calibration of the high-bandwidth main amplifier, the equivalent transconductance value of the auto-zero input stage is pulled up until the coarse offset calibration is completed and the equivalent transconductance value of the auto-zero input stage is restored. The auto-zero input stage and the rail-to-rail input amplifier stage are used to eliminate the offset of the high-gain auxiliary amplifier and suppress the low-frequency noise of the high-gain auxiliary amplifier; the input chopper and the output chopper are used to eliminate the low-frequency aliasing noise generated by the auto-zero.

[0069] In this embodiment, the equivalent transconductance of the auto-zero input stage is much smaller than the equivalent transconductance of the rail-to-rail input amplifier stage of the high-gain auxiliary amplifier. The auto-zero input stage is controlled by the digital automatic trimming module. During the coarse offset calibration after power-on, the equivalent transconductance of the auto-zero input stage is temporarily increased and then restored to the designed low transconductance value after the calibration is completed.

[0070] More specifically, Figure 5 As shown, the low-noise, low-offset, high-bandwidth offset-stable amplifier and the high-gain auxiliary amplifier in the embodiment of the present invention include five switches K21, K22, K23, K24, and K25, two on-chip capacitors C3 and C4, an input chopper CH1, a rail-to-rail input amplifier stage, an auto-zero input stage, and an output chopper CH2, wherein the switches K21 and K22 are disconnected during the calibration phase and closed during the offset stabilization phase; the switches K23, K24, and K25 are closed during the calibration phase and disconnected during the offset stabilization phase; the capacitors C3 and C4 are used to ensure that the voltage at the connection point remains unchanged after the switch is disconnected; one end of the switches K21 and K22 is disconnected. They are respectively connected to the input terminals of the rail-to-rail input stage. The other ends of switches K21 and K22 are respectively connected to the two ends of switch K23 and are also respectively connected to the input terminals of input chopper CH1. The output terminal of input chopper CH1 is connected to the input terminal of rail-to-rail input amplifier stage. The output terminal of rail-to-rail input amplifier stage is connected to the output terminal of auto-zero input stage and is also connected to output chopper CH2. One end of switches K24 and K25 is respectively connected to the input terminal of auto-zero input stage and is also connected to one side plate of capacitors C3 and C4. The other ends of switches K24 and K25 are respectively connected to the output of active integrator. The other side plates of capacitors C3 and C4 are connected to power supply ground.

[0071] In this embodiment, the self-zeroing input stage is designed using the same circuit technology as the offset compensation input stage.

[0072] The active integrator is used to perform offset compensation processing on the detection current signal to generate an offset compensation current;

[0073] Specifically, the active integrator includes an operational amplifier 31, a fifth on-chip capacitor C int11 , the sixth on-chip capacitor C int12 , the seventh on-chip capacitor C int21 、The eighth on-chip capacitor C int22, a first selection switch K31, a second selection switch K32, a tenth switch K33 and an eleventh switch K34, wherein the first end of the tenth switch, the first end of the fifth on-chip capacitor, the first end of the seventh on-chip capacitor, and the negative phase input end of the operational amplifier are connected to the high-gain auxiliary amplifier, the second end of the tenth switch, the second end of the seventh on-chip capacitor, and the second end of the first selection switch are connected to the high-bandwidth main amplifier, the second end of the fifth on-chip capacitor and the first end of the first selection switch are connected to the high-gain auxiliary amplifier, the positive phase output end of the operational amplifier and the third end of the first selection switch are connected to the digital automatic adjustment module, the negative phase output end of the operational amplifier and the first end of the second selection switch are connected to the digital automatic adjustment module, the positive phase input end of the operational amplifier, the first end of the sixth on-chip capacitor, the first end of the eighth on-chip capacitor are connected to the first end of the eleventh switch, the second end of the sixth on-chip capacitor and the second end of the second selection switch are connected to the high-gain auxiliary amplifier, and the second end of the eighth on-chip capacitor, the second end of the eleventh switch, and the third end of the second selection switch are connected to the high-bandwidth main amplifier.

[0074] In this embodiment, the active integrator is composed of an operational amplifier, on-chip capacitors, and a selection switch. Time division multiplexing is used. During the calibration phase, the active integrator is connected to a first set of on-chip capacitors to form a closed-loop feedback loop, and its output is connected to the auto-zero input stage through a switch. During the offset stabilization phase, the active integrator is connected to a second set of on-chip capacitors to form a closed-loop feedback loop, and its output is connected to the offset compensation input stage through a switch.

[0075] Among them, the noise aliasing bandwidth caused by auto-zeroing is G m / C int , where G m is the equivalent transconductance of the auto-zero input stage, C int is the capacitance of the on-chip capacitor of the active integrator. The auto-zero input stage has a low equivalent transconductance, and the on-chip capacitor has a high capacitance. The two together reduce the noise aliasing bandwidth, thereby reducing the low-frequency integrated noise. The chopping frequency of the input chopper and the output chopper is set to 0.5 times the auto-zeroing frequency and is designed to be higher than the noise aliasing bandwidth to shift the aliasing noise to a higher frequency, thereby achieving a lower noise level near DC.

[0076] More specifically, Figure 6 As shown, the low-noise, low-offset, high-bandwidth offset-stable amplifier in the embodiment of the present invention, the active integrator includes an operational amplifier, an on-chip capacitor C int11 、C int12 、C int21 and C int22, select switches K31, K32 and switches K33, K34. The positive input terminal of the operational amplifier is connected to the capacitor C int12 、C int22 , one end of the switch K34 is connected to the negative input terminal of the operational amplifier and the capacitor C int11 、C int21 , one end of the switch K33 is connected, the positive and negative output terminals of the operational amplifier are connected to the selection switches K31 and K32 respectively, the selection switch K31 is a single-pole double-set switch, in which the first static contact is connected to the capacitor △ int21 and switch K33, the second static contact is connected to capacitor C int11 The selection switch K32 is a single-pole double-set switch, in which the first static contact is connected to the capacitor C int22 and switch K34, the second static contact is connected to capacitor C int12 .

[0077] In this embodiment, during the coarse offset calibration after power-on, switches K33 and K34 are closed to prevent charge accumulation on the plates from generating a potential difference. After the coarse offset calibration after power-on is completed, the active integrator uses time division multiplexing. During the calibration phase, the active integrator connects capacitor C by gating switches K31 and K32. int11 、C int12 The closed-loop feedback is formed, and its output is connected to the self-zeroing input stage. In the offset stabilization stage, the active integrator is connected to the capacitor C through the gate switches K31 and K32. int21 and C int22 A closed-loop feedback is formed, and the output is connected to the offset compensation input stage.

[0078] The high-bandwidth main amplifier is used to suppress the input equivalent offset voltage with low-frequency noise according to the offset compensation current after the offset coarse calibration, and output an output voltage with a high bandwidth;

[0079] Specifically, the high-bandwidth main amplifier includes a first switch K11, a second switch K12, a first on-chip capacitor C1, a second on-chip capacitor C2, a rail-to-rail input stage 11, an offset compensation input stage 12, and a rail-to-rail output stage 13. The negative phase output terminal of the rail-to-rail input stage and the negative phase output terminal of the offset compensation input stage are connected to the positive phase input terminal of the rail-to-rail output stage. The positive phase output terminal of the rail-to-rail input stage and the positive phase output terminal of the offset compensation input stage are connected to the negative phase input terminal of the rail-to-rail output stage. The negative phase output terminal of the rail-to-rail output stage is connected to the rail-to-rail positive phase input terminal through resistors. The positive-phase input terminal of the input stage is connected to a high-gain auxiliary amplifier, the positive-phase output terminal of the rail-to-rail output stage is connected to the negative-phase input terminal of the rail-to-rail input stage through a resistor, the negative-phase input terminal of the offset compensation input stage and the second end of the first on-chip capacitor are connected to the first end of the first switch, the positive-phase input terminal of the offset compensation input stage and the first end of the second on-chip capacitor are connected to the first end of the second switch, the second end of the first switch and the second end of the second switch are respectively connected to the active integrator, and the first end of the first on-chip capacitor and the second end of the second on-chip capacitor are both grounded.

[0080] In this embodiment, the high-bandwidth main amplifier includes a rail-to-rail input stage, an offset compensation input stage, and a rail-to-rail output stage. The rail-to-rail input stage provides high low-frequency gain, is used to process the signal input to the amplifier, and outputs the signal to the rail-to-rail output stage; the rail-to-rail output stage is used to improve the output swing and drive capability of the amplifier; the offset compensation input stage receives the output signal of the active integrator and generates an offset compensation current, thereby eliminating the offset of the high-bandwidth main amplifier and suppressing low-frequency noise.

[0081] Furthermore, it should be noted that the equivalent transconductance value of the offset compensation input stage is smaller than the equivalent transconductance value of the rail-to-rail input stage, and during the coarse offset calibration of the high-bandwidth main amplifier, the equivalent transconductance value of the offset compensation input stage is pulled up until the coarse offset calibration is completed, and the equivalent transconductance value of the offset compensation input stage is restored, wherein: the rail-to-rail input stage is used to provide a low-frequency gain coefficient, pre-process the input equivalent offset voltage with low-frequency noise, and transmit it to the rail-to-rail output stage; the offset compensation input stage is used to obtain the output signal of the active integrator and suppress the low-frequency noise of the high-bandwidth main amplifier; the rail-to-rail output stage is used to improve the output swing and driving capability of the high-bandwidth main amplifier.

[0082] In this embodiment, the equivalent transconductance of the offset compensation input stage is much smaller than the equivalent transconductance of the rail-to-rail input stage of the high-bandwidth main amplifier. The offset compensation input stage is controlled by a digital automatic adjustment module. During the coarse offset calibration after power-on, the equivalent transconductance of the offset compensation input stage is temporarily increased and then restored to the designed low transconductance value after the calibration is completed.

[0083] The equivalent circuit of the offset compensation input stage includes a first bias current source I bp, the second bias current source I bn1 , the third bias current source I bn2 , a third switch K121, a fourth switch K122, a third resistor R121, a fourth resistor R122, a first transistor M121 and a second transistor M122, a first end of the first bias current source is connected to a high-level signal, a second end of the first bias current source, a second end of the third switch, a second end of the third resistor, a first end of the fourth switch and a first end of the fourth resistor are connected, a first end of the third switch and a first end of the third resistor are connected to the source of the first transistor, a second end of the fourth switch and a second end of the fourth resistor are connected to the source of the second transistor, a drain of the first transistor is connected to the first end of the second bias current source, a drain of the second transistor is connected to the first end of the third bias current source, and a second end of the second bias current source and a second end of the third bias current source are both grounded.

[0084] More specifically, Figure 3 As shown, in an embodiment of the present invention, a low-noise, low-offset, high-bandwidth offset-stable amplifier comprises a high-bandwidth main amplifier comprising two switches K11 and K12, two on-chip capacitors C1 and C2, a rail-to-rail input stage, an offset compensation input stage, and a rail-to-rail output stage. The switches K11 and K12 are closed during the offset stabilization phase and opened during the calibration phase. The capacitors C1 and C2 are used to ensure that the voltage at the connection point remains unchanged after the switches are opened. The specific connection method is as follows: the input of the rail-to-rail input stage receives an input signal, one end of each switch K11 and K12 is connected to the input of the offset compensation input stage and to one plate of each capacitor C1 and C2, respectively, and the other end is connected to the output of the active integrator. The other plates of each capacitor C1 and C2 are connected to the power supply ground. The output of the rail-to-rail input stage and the output of the offset compensation input stage are connected to the input of the rail-to-rail output stage.

[0085] like Figure 4 As shown, the low-noise, low-offset, high-bandwidth offset-stable amplifier in the embodiment of the present invention has an offset compensation input stage consisting of two P-type metal oxide semiconductor field effect transistors M121 and M122 with the same channel length and width, two resistors R121 and R122 with the same length and width, two identical switches K121 and K122, three adjustable bias current sources I bn1 , I bn2 , I bp The specific connection method is: the gates of M121 and M122 are connected to the two output terminals of the active integrator respectively, the drains of M121 and M122 are connected to the two output terminals of the offset compensation input stage respectively, and are connected to the adjustable bias current source I bn1 , I bn2One end of the resistor R121 is connected to the source of M121 and one end of the switch K121. The other end of the resistor R121 is connected to one end of the resistor R122, the other end of the switch K121, and the adjustable bias current source I bp The switch K121 is connected to the resistor R121 in parallel, and the end of the resistor R122 not connected to the resistor R121 is connected to the other end of the switch K122 and the source of M122. The switch K122 is connected to the resistor R122 in parallel.

[0086] In this embodiment, the P-type metal oxide semiconductor field effect transistors M121, M122 and the resistors R121, R122 respectively form source negative feedback. By designing the size and width-to-length ratio of M121, M122, R121, and R122, the equivalent transconductance of the offset compensation input stage is much smaller than the equivalent transconductance of the rail-to-rail input stage. The switches K121, K122 and the three adjustable bias current sources I bn1 , I bn2 , I bp Under the control of the digital automatic adjustment module, during the offset coarse calibration after power-on, switches K121 and K122 are closed, thereby short-circuiting resistors R121 and R122, and the adjustable bias current source I bn1 , I bn2 , I bp It is adjusted to provide a larger bias current to improve the equivalent transconductance of the offset compensation input stage. After the offset coarse calibration is completed, the switches K121 and K122 are disconnected, and the adjustable bias current source I bn1 , I bn2 , I bp is regulated to provide the bias current required for normal operation.

[0087] The resistor module is used to control the amplification gain factor of the high bandwidth main amplifier.

[0088] Specifically, the resistor module includes a first resistor R1 and a second resistor R2. The first resistor serves as a feedback resistor and the second resistor serves as an input resistor. The two resistors constitute a resistance feedback. The amplification gain of the closed-loop amplifier is determined by the ratio of the feedback resistor to the input resistor.

[0089] See also Figure 2 The present application also provides a method for controlling a low-noise, low-offset, high-bandwidth offset-stable amplifier, which can realize the above-mentioned low-noise, low-offset, high-bandwidth offset-stable amplifier. The system includes:

[0090] S100, performing a coarse offset calibration on the high-bandwidth main amplifier to obtain a calibrated high-bandwidth main amplifier;

[0091] S200, converting the input equivalent offset voltage with low-frequency noise and outputting a detection current signal;

[0092] S300, performing offset compensation processing on the detection current signal to generate an offset compensation current;

[0093] S400, the calibrated high-bandwidth main amplifier suppresses an input equivalent offset voltage having low-frequency noise according to an offset compensation current, and outputs an output voltage having a high bandwidth;

[0094] In summary, the overall topology of the embodiment of the present invention is an offset-stable amplifier structure, in which the high-bandwidth main amplifier is always in the signal path and can continuously and uninterruptedly process input signals in a wide bandwidth range; the high-bandwidth main amplifier operates stably under the closed-loop feedback formed by the resistance module, and its low offset and low noise performance are implemented as follows: first, in the circuit power-on initialization stage, the digital automatic adjustment module performs coarse offset calibration on the high-bandwidth main amplifier to reduce the input equivalent offset voltage to below a preset threshold; then, the amplifier enters a normal working state, which includes two working cycles: a calibration stage and an offset stabilization stage that operate alternately; in the calibration stage, the auxiliary signal path composed of the high-gain auxiliary amplifier and the active integrator is disconnected from the main signal path composed of the high-bandwidth main amplifier, wherein the main signal path processes the continuously input signal, while the auxiliary signal path performs auto-zeroing to stabilize the high-gain auxiliary amplifier. The offset and noise of the high-bandwidth main amplifier are reduced to extremely low levels. During the offset stabilization phase, the auxiliary signal path is connected in parallel with the main signal path. The equivalent offset and low-frequency noise at the input of the high-bandwidth main amplifier are detected by the high-gain auxiliary amplifier and converted into a current signal. The active integrator integrates the current signal and then provides compensation to the high-bandwidth main amplifier in the form of current through the offset compensation input stage, thereby eliminating the offset and noise of the high-bandwidth main amplifier. By periodically alternating between the calibration phase and the offset stabilization phase, the low-noise, low-offset, high-bandwidth offset-stable amplifier can continuously provide ultra-low offset and ultra-low noise performance in complex and changing operating environments. The active integrator uses time-division multiplexing to perform slow-settling auto-zeroing to eliminate the offset of the high-gain auxiliary amplifier during the calibration phase and to perform offset cancellation on the high-bandwidth main amplifier during the offset stabilization phase. The digital automatic trimming module performs coarse offset calibration on the amplifier after power-on.

[0095] Through the slow-established Auto-zeroing design, the noise aliasing bandwidth can be effectively reduced and the degree of noise aliasing can be reduced, thereby significantly reducing the in-band integrated noise; on the basis of reducing the in-band integrated noise, combined with chopping technology, the noise near DC is moved to a higher frequency, thereby completely eliminating 1 / f noise; in the amplifier that has adopted Auto-zeroing to reduce offset, chopping technology is introduced to greatly alleviate the ripple caused by chopping, and it is filtered out by an active integrator, thereby eliminating the adverse effects of chopping and eliminating complex modules such as ripple suppression circuits; through the design of time-division multiplexing of the active integrator, the circuit complexity is reduced, and the chip area and power consumption are saved; by introducing a digital automatic adjustment module, the amplifier is roughly calibrated for offset after power-on, effectively avoiding abnormal saturation of internal nodes of the circuit, and improving the stability of the precision system and the robustness of the offset suppression scheme. Through the above-mentioned multiple technical improvements, the present invention presents low-noise characteristics in a wide bandwidth range, can effectively suppress offset and 1 / f noise, and meet the application of ultra-high precision and low noise interference in high-bandwidth working scenarios.

[0096] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0097] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A low noise, low offset, high bandwidth offset stable amplifier, characterized in that: The amplifier includes a high-bandwidth main amplifier, a high-gain auxiliary amplifier, an active integrator, a digital automatic adjustment module, and a resistance module. The output of the high-gain auxiliary amplifier is connected to the input of the active integrator, the first output of the active integrator is connected to the first input of the high-bandwidth main amplifier, the second output of the active integrator is connected to the first input of the high-gain auxiliary amplifier, the third output of the active integrator is connected to the input of the digital automatic adjustment module, the first output of the digital automatic adjustment module is connected to the second input of the high-bandwidth main amplifier, the second output of the digital automatic adjustment module is connected to the second input of the high-gain auxiliary amplifier, the first output of the resistance module is connected to the third input of the high-gain auxiliary amplifier, the second output of the resistance module is connected to the third input of the high-bandwidth main amplifier, and the third output of the resistance module is connected to the output of the high-bandwidth main amplifier, wherein: The digital automatic adjustment module is used to perform coarse offset calibration on the high-bandwidth main amplifier; The high-gain auxiliary amplifier is used to convert the input equivalent offset voltage with low-frequency noise and output a detection current signal; The active integrator is used to perform offset compensation processing on the detection current signal to generate an offset compensation current; The high-bandwidth main amplifier is used to suppress the input equivalent offset voltage with low-frequency noise according to the offset compensation current after the offset coarse calibration, and output an output voltage with a high bandwidth; The resistance module is used to control the amplification gain coefficient of the high-bandwidth main amplifier.

2. The amplifier according to claim 1, wherein The high-bandwidth main amplifier includes a first switch, a second switch, a first on-chip capacitor, a second on-chip capacitor, a rail-to-rail input stage, an offset compensation input stage, and a rail-to-rail output stage. The negative phase output terminal of the rail-to-rail input stage and the negative phase output terminal of the offset compensation input stage are connected to the positive phase input terminal of the rail-to-rail output stage. The positive phase output terminal of the rail-to-rail input stage and the positive phase output terminal of the offset compensation input stage are connected to the negative phase input terminal of the rail-to-rail output stage. The negative phase output terminal of the rail-to-rail output stage is connected to the positive phase input terminal of the rail-to-rail input stage and the high gain input stage through resistors. The auxiliary amplifier is connected, the positive-phase output terminal of the rail-to-rail output stage is connected to the negative-phase input terminal of the rail-to-rail input stage through a resistor, the negative-phase input terminal of the offset compensation input stage and the second end of the first on-chip capacitor are connected to the first end of the first switch, the positive-phase input terminal of the offset compensation input stage and the first end of the second on-chip capacitor are connected to the first end of the second switch, the second end of the first switch and the second end of the second switch are respectively connected to the active integrator, and the first end of the first on-chip capacitor and the second end of the second on-chip capacitor are both grounded.

3. The amplifier according to claim 2, characterized in that The equivalent transconductance value of the offset compensation input stage is less than the equivalent transconductance value of the rail-to-rail input stage, and during the coarse offset calibration of the high-bandwidth main amplifier, the equivalent transconductance value of the offset compensation input stage is pulled up until the coarse offset calibration is completed and the equivalent transconductance value of the offset compensation input stage is restored, wherein: The rail-to-rail input stage is used to provide a low-frequency gain coefficient, pre-process the input equivalent offset voltage with low-frequency noise, and transmit it to the rail-to-rail output stage; The offset compensation input stage is used to obtain the output signal of the active integrator and suppress the low-frequency noise of the high-bandwidth main amplifier; The rail-to-rail output stage is used to improve the output swing and driving capability of the high-bandwidth main amplifier.

4. The amplifier according to claim 2, wherein: The equivalent circuit of the offset compensation input stage includes a first bias current source, a second bias current source, a third bias current source, a third switch, a fourth switch, a third resistor, a fourth resistor, a first transistor, and a second transistor. The first terminal of the first bias current source is connected to a high-level signal. The second terminal of the first bias current source, the second terminal of the third switch, the second terminal of the third resistor, the first terminal of the fourth switch, and the first terminal of the fourth resistor are connected. The first terminal of the third switch and the first terminal of the third resistor are connected to the source of the first transistor. The second terminal of the fourth switch and the second terminal of the fourth resistor are connected to the source of the second transistor. The drain of the first transistor is connected to the first terminal of the second bias current source. The drain of the second transistor is connected to the first terminal of the third bias current source. The second terminal of the second bias current source and the second terminal of the third bias current source are both grounded.

5. The amplifier according to claim 1, wherein The high-gain auxiliary amplifier includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a third on-chip capacitor, a fourth on-chip capacitor, an input chopper, a rail-to-rail input amplifier stage, an auto-zero input stage, and an output chopper, wherein the first end of the fifth switch and the first end of the sixth switch are respectively connected to the high-bandwidth main amplifier, the second end of the fifth switch and the first end of the seventh switch are connected to the first end of the input chopper, the second end of the sixth switch and the second end of the seventh switch are connected to the second end of the input chopper, the first output end of the input chopper is connected to the positive phase input end of the rail-to-rail input amplifier stage, the second output end of the input chopper is connected to the negative phase input end of the rail-to-rail input amplifier stage, and the output chopper is connected to the rail-to-rail input amplifier stage. The negative phase output terminal of the rail-to-rail input amplifier stage, the first input terminal of the output chopper, and the negative phase output terminal of the auto-zero input stage are connected to the digital automatic trimming module; the positive phase output terminal of the rail-to-rail input amplifier stage, the second input terminal of the output chopper, and the positive phase output terminal of the auto-zero input stage are connected to the digital automatic trimming module; the negative phase input terminal of the auto-zero input stage and the second end of the third on-chip capacitor are connected to the first end of the eighth switch; the positive phase input terminal of the auto-zero input stage and the first end of the fourth on-chip capacitor are connected to the first end of the ninth switch; the first end of the third on-chip capacitor and the second end of the fourth on-chip capacitor are both grounded; and the second end of the eighth switch and the second end of the ninth switch are respectively connected to the active integrator.

6. The amplifier according to claim 5, characterized in that The equivalent transconductance value of the auto-zero input stage is less than the equivalent transconductance value of the rail-to-rail input amplifier stage, and during the coarse offset calibration of the high-bandwidth main amplifier, the equivalent transconductance value of the auto-zero input stage is pulled up until the coarse offset calibration is completed and the equivalent transconductance value of the auto-zero input stage is restored, wherein: The auto-zero input stage and the rail-to-rail input amplifier stage are used to eliminate the offset of the high-gain auxiliary amplifier and suppress the low-frequency noise of the high-gain auxiliary amplifier; The input chopper and the output chopper are used to eliminate low-frequency aliasing noise generated by self-zeroing.

7. The amplifier according to claim 1, wherein The active integrator includes an operational amplifier, a fifth on-chip capacitor, a sixth on-chip capacitor, a seventh on-chip capacitor, an eighth on-chip capacitor, a first gating switch, a second gating switch, a tenth switch, and an eleventh switch, wherein the first end of the tenth switch, the first end of the fifth on-chip capacitor, the first end of the seventh on-chip capacitor, and the negative phase input of the operational amplifier are connected to the high-gain auxiliary amplifier, the second end of the tenth switch, the second end of the seventh on-chip capacitor, and the second end of the first gating switch are connected to the high-bandwidth main amplifier, the second end of the fifth on-chip capacitor, the first end of the first gating switch and the high-gain auxiliary amplifier The positive-phase output terminal of the operational amplifier and the third terminal of the first selection switch are connected to the digital automatic adjustment module, the negative-phase output terminal of the operational amplifier and the first terminal of the second selection switch are connected to the digital automatic adjustment module, the positive-phase input terminal of the operational amplifier, the first terminal of the sixth on-chip capacitor, the first terminal of the eighth on-chip capacitor are connected to the first terminal of the eleventh switch, the second terminal of the sixth on-chip capacitor and the second terminal of the second selection switch are connected to the high-gain auxiliary amplifier, and the second terminal of the eighth on-chip capacitor, the second terminal of the eleventh switch, and the third terminal of the second selection switch are connected to the high-bandwidth main amplifier.

8. The amplifier according to claim 1, wherein The digital automatic adjustment module includes a comparator circuit, a current steering DAC circuit, a SAR control logic circuit, and a current DAC control signal generating circuit, wherein the positive input terminal and the negative input terminal of the comparator circuit are both connected to the high-gain auxiliary amplifier, the output terminal of the comparator circuit is connected to the input terminal of the SAR control logic circuit, the first output terminal of the SAR control logic circuit is feedback-connected to the comparator circuit, the second output terminal of the SAR control logic circuit is connected to the input terminal of the current DAC control signal generating circuit, the current steering DAC circuit is connected to the current DAC control signal generating circuit, and the current steering DAC circuit is also connected to the high-gain auxiliary amplifier and the high-bandwidth main amplifier, respectively. The comparator circuit is used to compare the positive and negative output terminal voltages of the active integrator to obtain a comparison result; The SAR control logic circuit is used to perform SAR logic control according to the comparison result to obtain an offset calibration control word; The current DAC control signal generating circuit is used to generate a switch control signal according to the comparison result; The current-steering DAC circuit is used to perform coarse offset calibration on the high-gain auxiliary amplifier and the high-bandwidth main amplifier according to the offset calibration control word and the switch control signal.

9. The amplifier according to claim 8, characterized in that The current-steering DAC circuit includes a fourth bias current source, a fifth bias current source, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, and a seventeenth switch. A first terminal of the fourth bias current source is connected to a high level. A second terminal of the fourth bias current source, a first terminal of the twelfth switch, a first terminal of the thirteenth switch, and a first terminal of the fourteenth switch are connected. A second terminal of the twelfth switch is connected to a first terminal of the fifteenth switch. A second terminal of the thirteenth switch is connected to a first terminal of the sixteenth switch. A second terminal of the fourteenth switch is connected to a first terminal of the seventeenth switch. A second terminal of the fifteenth switch, a second terminal of the sixteenth switch, and a second terminal of the seventeenth switch are connected to a first terminal of the fifth bias current source. A second terminal of the fifth bias current source is grounded.

10. A control method for a low-noise, low-offset, high-bandwidth offset-stable amplifier, characterized in that: The control method comprises the following steps: performing a coarse offset calibration on the high-bandwidth main amplifier to obtain a calibrated high-bandwidth main amplifier; Convert the input equivalent offset voltage with low-frequency noise and output a detection current signal; performing offset compensation processing on the detection current signal to generate an offset compensation current; The calibrated high-bandwidth main amplifier suppresses the input equivalent offset voltage with low-frequency noise according to the offset compensation current, and outputs an output voltage with a high bandwidth.

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