A clock disciplining system and method

Abstract

The application discloses a clock disciplining frequency synthesizer system and method, and belongs to the technical field of frequency synthesis. The system comprises a clock disciplining frequency synthesizer circuit, wherein the clock disciplining frequency synthesizer circuit comprises a clock disciplining circuit, the clock disciplining circuit is connected with a frequency synthesizer circuit, and the frequency synthesizer circuit is connected with a frequency selection circuit; the clock disciplining circuit is used for providing a basic frequency signal, the frequency synthesizer circuit is used for generating a plurality of target output frequencies and performing frequency switching and locking, and the frequency selection circuit is used for selecting a required output frequency and outputting. The system has a clock disciplining function, can be synchronized with a Beidou system, realizes multi-system unlimited distance synchronization, has high frequency synthesizer frequency precision, and the frequency precision can be as high as the Beidou clock frequency accuracy; the overall system cost is reduced through optimization of component selection and design, high-integration design and double-sided board layout greatly reduce the system volume, and the system has high stability; the system has fast frequency switching and fast locking time.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of frequency synthesis technology, in particular to a clock taming frequency synthesis system and method. BACKGROUND

[0002] With the rapid development of information technology, frequency synthesis (frequency synthesis) technology plays an increasingly key role in modern communication systems. The progress of frequency synthesis technology not only promotes the technological innovation in the fields of wireless communication, satellite navigation, radar system, etc., but also provides stable and reliable clock signals for modern electronic devices. Frequency synthesizer converts a reference frequency signal into multiple different output frequencies, accurately modulates and demodulates signals, and thus ensures the efficient operation of communication systems and the accuracy of data transmission. In communication systems, the main functions of frequency synthesizer include: 1. Generating various frequency signals: providing multiple frequency outputs required by the system to support different communication protocols and standards; 2. Providing clock synchronization: ensuring time synchronization between modules in the system to avoid time errors in data transmission; 3. Implementing signal modulation and demodulation: adjusting the frequency signal to realize signal modulation and demodulation, improving signal transmission quality. These functions are crucial to ensure the accuracy of data transmission and the overall stability of the system.

[0003] With the development of communication technology, the existing scheme cannot meet the development needs, and the existing scheme has some common disadvantages: 1. Insufficient accuracy: the frequency source in the existing system may not be able to provide sufficiently accurate signals, resulting in communication system synchronization problems; 2. High cost: high-precision frequency synthesizer requires expensive components and complex design, increasing system cost; 3. Large size: low-integration frequency synthesizer system is large in size, not suitable for application scenarios with strict size requirements. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide a clock taming frequency synthesis system and method.

[0005] The purpose of the present application is achieved by the following technical solutions: The present application provides a clock taming frequency synthesis system, comprising a clock taming frequency synthesis circuit, the clock taming frequency synthesis circuit comprising a clock taming circuit, the clock taming circuit connected to a frequency synthesis circuit, the frequency synthesis circuit connected to a frequency selection circuit; the clock taming circuit is used to provide a basic frequency signal, the frequency synthesis circuit is used to generate multiple target output frequencies and perform frequency switching and locking, and the frequency selection circuit is used to select the required output frequency and output;

[0006] The clock taming circuit comprises a GPS system, when the GPS antenna receives the satellite signal, the satellite signal is sent to the GPS receiver, the GPS receiver demodulates the 1PPS signal from the satellite signal; at this time, the GPS receiver outputs the 1PPS signal to the field programmable gate array (FPGA), the field programmable gate array (FPGA) collects the 1PPS signal and the signal of the voltage controlled crystal oscillator (VCXO) power divider output at the same time to compare the error; then the field programmable gate array (FPGA) outputs the digital error signal to the digital-to-analog converter (D / A), the digital-to-analog converter (D / A) outputs an analog voltage to control the output of the voltage controlled crystal oscillator (VCXO), forming a cycle; the cycle is repeated for multiple times until the output frequency accuracy of the voltage controlled crystal oscillator (VCXO) and the frequency accuracy of the 1PPS signal are within the preset difference, the voltage controlled crystal oscillator (VCXO) outputs the clock reference signal; the clock reference signal is divided into two paths and sent to the first phase-locked loop circuit (PLL1) and the second phase-locked loop circuit (PLL2) after filtering, then the target frequency signal is outputted by the program control of the first phase-locked loop circuit (PLL1) and the second phase-locked loop circuit (PLL2), for the signal in the first preset frequency range, the signal outputted by the first phase-locked loop circuit (PLL1) and the second phase-locked loop circuit (PLL2) is inputted into the frequency mixer to obtain; finally, the required output frequency is selected by the frequency selection circuit and outputted.

[0007] Preferably, the clock taming frequency synthesis circuit further comprises a field programmable gate array (FPGA), a digital-to-analog converter (D / A), a voltage controlled crystal oscillator (VCXO) and a first power divider; the GPS system is connected to the field programmable gate array (FPGA); the field programmable gate array (FPGA) is connected to the digital-to-analog converter (D / A); the digital-to-analog converter (D / A) is connected to the voltage controlled crystal oscillator (VCXO); the voltage controlled crystal oscillator (VCXO) is connected to the first power divider; the first power divider is connected to the field programmable gate array (FPGA) and the frequency synthesis circuit.

[0008] Preferably, the frequency synthesis circuit comprises a second power divider, the input of the second power divider is connected to the output of the clock taming frequency synthesizer circuit, the output of the second power divider is connected to the first self-made low pass filter and the first low pass filter; the first self-made low pass filter is connected to the second low pass filter, and the first low pass filter is connected to the second self-made low pass filter; the second low pass filter is connected to the first phase-locked loop circuit PLL1, and the second self-made low pass filter is connected to the second phase-locked loop circuit PLL2; the output of the first phase-locked loop circuit PLL1 is connected to the third low pass filter, and the output of the second phase-locked loop circuit PLL2 is connected to the fourth low pass filter; the third low pass filter is connected to the first single-pole double-throw switch, and the fourth low pass filter is connected to the second single-pole double-throw switch; the first single-pole double-throw switch is connected to the first amplifier and the first single-pole triple-throw switch, and the second single-pole double-throw switch is connected to the frequency mixer and the first single-pole triple-throw switch; the first amplifier is connected to the fifth low pass filter, the fifth low pass filter is connected to the frequency mixer, and the frequency mixer is connected to the first single-pole triple-throw switch; the first single-pole triple-throw switch is connected to the switch filter bank; and the switch filter bank is connected to the frequency selection circuit.

[0009] Preferably, the frequency selection circuit comprises a second single-pole triple-throw switch, the input of the second single-pole triple-throw switch is connected to the output of the frequency synthesis circuit, and the output of the second single-pole triple-throw switch is connected to the frequency quadrupler, the frequency doubler and the fourth amplifier; the frequency quadrupler is connected to the first band pass filter, the frequency doubler is connected to the second band pass filter, and the fourth amplifier is connected to the third single-pole triple-throw switch; the first band pass filter is connected to the second amplifier, and the second band pass filter is connected to the third amplifier; the output of the second amplifier and the output of the third amplifier are both connected to the third single-pole triple-throw switch; and the third single-pole triple-throw switch outputs the required output frequency.

[0010] Preferably, the first phase-locked loop circuit PLL1 comprises a first phase detector PD, a sixth low pass filter, a first voltage controlled oscillator VCO and a first frequency divider; the input of the first phase detector PD is connected to the output of the second low pass filter and the output of the first frequency divider, and the output of the first phase detector PD is connected to the sixth low pass filter; the sixth low pass filter is connected to the first voltage controlled oscillator VCO; the first voltage controlled oscillator VCO is connected to the input of the first frequency divider and the input of the third low pass filter;

[0011] The second phase-locked loop circuit PLL2 comprises a second phase discriminator PD, a seventh low-pass filter, a second voltage-controlled oscillator VCO and a second frequency divider; the input end of the second phase discriminator PD is connected with the output end of the second self-made low-pass filter and the output end of the second frequency divider, and the output end of the second phase discriminator PD is connected with the seventh low-pass filter; the seventh low-pass filter is connected with the second voltage-controlled oscillator VCO; the second voltage-controlled oscillator VCO is connected with the input end of the second frequency divider and the input end of the fourth low-pass filter;

[0012] The output frequency of the first voltage-controlled oscillator VCO and the second voltage-controlled oscillator VCO is greater than the output frequency of the voltage-controlled crystal oscillator VCXO.

[0013] Preferably, the first self-made low-pass filter comprises a first capacitive circuit, a first inductive circuit, a second capacitive circuit and a second inductive circuit; the front-stage input circuit is connected with the first capacitive circuit and the first inductive circuit; the output end of the first inductive circuit is connected with the second capacitive circuit and the second inductive circuit; the output end of the second inductive circuit is connected with the rear-stage circuit; and the circuit structure of the first self-made low-pass filter and the second self-made low-pass filter is the same.

[0014] Preferably, the clock taming frequency synthesizer circuit is arranged on a clock taming frequency synthesizer structure, and the clock taming frequency synthesizer structure adopts a double-face cavity structure; the front face of the clock taming frequency synthesizer structure is a mixed-pressure multi-layer PCB circuit board, and the back face is a microwave surface; the mixed-pressure multi-layer PCB circuit board is provided with a tamed clock circuit structure, a field programmable gate array FPGA circuit structure, a first phase-locked loop circuit PLL1 structure, a second phase-locked loop circuit PLL2 structure and a DC / DC power supply circuit structure.

[0015] Preferably, a micro-assembly printed board is embedded in the microwave surface and connected with the mixed-pressure multi-layer PCB circuit board through inter-inserted low-frequency connectors and low-high-frequency connectors; the microwave surface is provided with a radio frequency microwave circuit structure, a radio frequency output connector, a microwave circuit soft substrate, an amplifier, a switch, a filter, a frequency doubler and a frequency quadrupler.

[0016] Preferably, the microwave surface is covered by double-layer cover plates, the first layer of cover plates is fixed by M1.6 countersunk screws, and the second layer of cover plates is covered by laser sealing.

[0017] The second aspect of the present application provides a clock taming frequency synthesizer method, which is used in any clock taming frequency synthesizer system and comprises the following steps:

[0018] S1: The GPS receiver receives satellite signals, demodulates a 1PPS signal and outputs, to provide an accurate reference for a frequency source;

[0019] S2: Field programmable gate array (FPGA) compares signal error, adjusts the output of voltage-controlled crystal oscillator (VCXO) according to the signal error, and continuously adjusts the accuracy of the output signal to obtain a clock reference signal;

[0020] S3: Directly obtain or mix frequency to obtain a target output frequency signal through the first phase-locked loop circuit (PLL1) and the second phase-locked loop circuit (PLL2);

[0021] S4: Select a required signal path for amplification and filtering to obtain a required output frequency signal and output.

[0022] The beneficial effects of the present application are:

[0023] 1) It has a clock taming function, can be synchronized with the Beidou system, realizes multi-system unlimited distance synchronization, has high frequency accuracy, and the frequency accuracy can be as accurate as the Beidou clock frequency; through optimization of component selection and design, the overall system cost is reduced, high integration design and double-sided board layout greatly reduce the system volume, and the stability is high; the frequency switching is fast, and the locking time is fast.

[0024] 2) A low-cost voltage-controlled oscillator (VCO) is used, the crystal oscillator circuit and the control circuit are designed with high integration, a frequency synthesizer and an FPGA controller share a crystal oscillator scheme, and the system cost and volume are reduced.

[0025] 3) Through the combination of double-phase-locked loop circuits and frequency mixing, fast frequency switching and short-time locking are realized, and the response speed and stability of the system are improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a clock taming frequency synthesizer circuit schematic diagram;

[0027] Figure 2 It is a clock taming frequency synthesizer structure front layout diagram;

[0028] Figure 3 It is a clock taming frequency synthesizer structure back layout diagram;

[0029] Figure 4 It is a clock taming frequency synthesizer method flow chart;

[0030] Figure 5 It is a self-made low-pass filter circuit schematic diagram;

[0031] In the figure, 1 is a tamed clock circuit structure; 2 is a field programmable gate array (FPGA) circuit structure; 3 is a first phase-locked loop circuit (PLL1) structure; 4 is a second phase-locked loop circuit (PLL2) structure; 5 is a DC / DC power supply circuit structure; 6 is a radio frequency microwave circuit structure; and 7 is a radio frequency output connector. DETAILED DESCRIPTION

[0032] The technical solutions of the present application will be described clearly and completely in combination with the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0033] The present application realizes a high-precision frequency synthesizer with an ultra-low-cost solution. This solution uses an ultra-low-cost voltage-controlled crystal oscillator (VCXO) and combines crystal oscillator circuit and control circuit for high-integration design, realizing high-integration and low-cost design. The present application has the following advantages: 1. Clock taming function: by introducing advanced clock taming technology, the precision of the frequency synthesizer is greatly improved, ensuring synchronization with the Beidou system, thereby realizing high-precision clock signal output. 2. Low-cost voltage-controlled oscillator: selecting a low-cost but reliable voltage-controlled oscillator reduces the overall cost of the system. 3. High-integration design: high-integration design of the frequency synthesizer and other circuits reduces the size of the system and improves reliability. 4. High stability: through improved design and selection of high-efficiency materials, the stability of the system is improved, adapting to various environmental conditions.

[0034] This new solution not only reduces the cost, but also significantly improves the stability of the system while ensuring high precision and small size. Overall, the frequency synthesizer solution proposed in the present application has the advantages of high precision, low cost, small size, and strong stability, which is very suitable for the needs of modern communication systems.

[0035] Referring to Figures 1-4 The first aspect of the present application provides: a clock taming frequency synthesis system, comprising a clock taming frequency synthesis circuit, the clock taming frequency synthesis circuit comprising a clock taming circuit, the clock taming circuit connected to a frequency synthesis circuit, the frequency synthesis circuit connected to a frequency selection circuit; the clock taming circuit is used to provide a base frequency signal, the frequency synthesis circuit is used to generate a plurality of target output frequencies and perform frequency switching and locking, and the frequency selection circuit is used to select the required output frequency and output;

[0036] The clock taming circuit comprises a GPS system, when a satellite signal is received by a GPS antenna, the satellite signal is sent to a GPS receiver, the GPS receiver demodulates a 1PPS signal from the satellite signal; at this time, the GPS receiver outputs the 1PPS signal to a field programmable gate array (FPGA), the FPGA simultaneously collects the 1PPS signal and a signal output by a voltage controlled crystal oscillator (VCXO) for error comparison; then the FPGA outputs a digital error signal to a digital-to-analog converter (D / A), the D / A outputs an analog voltage to control the output of the VCXO, forming a cycle; the cycle is repeated multiple times until the difference between the output frequency accuracy of the VCXO and the frequency accuracy of the 1PPS signal is within a preset difference, the VCXO outputs a clock reference signal; the clock reference signal is divided into two paths and sent to a first phase-locked loop circuit (PLL1) and a second phase-locked loop circuit (PLL2) after filtering, then the first PLL1 and the second PLL2 output target frequency signals through program control, for signals within a first preset frequency range, the signals output by the first PLL1 and the second PLL2 are input to a frequency mixer to obtain; finally, a frequency selection circuit is used to select and output a required output frequency.

[0037] In the embodiment, the core of the system comprises a low-cost voltage-controlled crystal oscillator (VCXO), a high-integration frequency synthesis circuit and an advanced clock taming module; the voltage-controlled crystal oscillator (VCXO) provides a basic frequency signal; the frequency synthesis circuit generates a plurality of required output frequencies, supports frequency switching and locking; and the clock taming module improves the frequency accuracy and synchronization performance of the system, and ensures synchronization with the Beidou system. The specific working principle of the system is as follows: the GPS antenna receives satellite signals and sends them to the GPS receiver; the GPS receiver demodulates a 1PPS signal from the satellite signals; the GPS receiver outputs the 1PPS signal to the FPGA; the FPGA collects the 1PPS signal and the signal output by the VCXO power divider, and compares their relative errors (since the 1PPS signal is a high-accuracy frequency signal, the 1PPS signal is used as a reference signal for comparison); after comparing the errors, the FPGA outputs a digital error signal to the D / A (digital-to-analog converter); the D / A outputs an analog voltage to control the output of the VCXO, so that the circuit forms a loop, and after repeated cycles, the output frequency accuracy of the VCXO approaches the frequency accuracy of the 1PPS. The VCXO output signal (clock reference signal) is divided into two paths by the power divider and then filtered, further purifying the VCXO output signal, and sending the signal to PLL1 and PLL2 (frequency synthesis circuit) as their clock reference signal. The required frequency signals are output by program control, and the signals that can be directly obtained are sent to the single-pole three-throw switch after filtering and switching. If a higher frequency is required, the signals of PLL1 and PLL2 are sent to the frequency mixer to add the two signals to obtain a higher frequency, which is sent to the single-pole three-throw switch. After selecting the required frequency output by program control, the signal is sent to the switch filter group for signal purification, and then sent to the single-pole three-throw switch to select the required line. Among them, three circuits are provided, the first is a four times frequency filter amplifier circuit, the second is a two times frequency filter amplifier circuit, and the third is a straight-through amplifier circuit. The required circuit is selected for the final output according to the demand.

[0038] In some embodiments, the clock taming frequency synthesis circuit further comprises a field programmable gate array (FPGA), a digital-to-analog converter (D / A), a voltage-controlled crystal oscillator (VCXO) and a first power divider; the GPS system is connected to the field programmable gate array (FPGA); the field programmable gate array (FPGA) is connected to the digital-to-analog converter (D / A); the digital-to-analog converter (D / A) is connected to the voltage-controlled crystal oscillator (VCXO); the voltage-controlled crystal oscillator (VCXO) is connected to the first power divider; and the first power divider is connected to the field programmable gate array (FPGA) and the frequency synthesis circuit.

[0039] In some embodiments, the frequency synthesis circuit includes a second power divider, an input of the second power divider is connected to an output of the clock taming frequency synthesis circuit, outputs of the second power divider are connected to a first self-made low pass filter and a first low pass filter; the first self-made low pass filter is connected to a second low pass filter, the first low pass filter is connected to a second self-made low pass filter; the second low pass filter is connected to a first phase-locked loop circuit PLL1, the second self-made low pass filter is connected to a second phase-locked loop circuit PLL2; an output of the first phase-locked loop circuit PLL1 is connected to a third low pass filter, an output of the second phase-locked loop circuit PLL2 is connected to a fourth low pass filter; the third low pass filter is connected to a first single-pole double-throw switch, the fourth low pass filter is connected to a second single-pole double-throw switch; the first single-pole double-throw switch is connected to a first amplifier and a first single-pole triple-throw switch, the second single-pole double-throw switch is connected to a frequency mixer and a first single-pole triple-throw switch; the first amplifier is connected to a fifth low pass filter, the fifth low pass filter is connected to the frequency mixer, the frequency mixer is connected to the first single-pole triple-throw switch; the first single-pole triple-throw switch is connected to a switch filter bank; the switch filter bank is connected to a frequency selection circuit.

[0040] In some embodiments, the frequency selection circuit includes a second single-pole triple-throw switch, an input of the second single-pole triple-throw switch is connected to an output of the frequency synthesis circuit, outputs of the second single-pole triple-throw switch are connected to a frequency quadrupler, a frequency doubler and a fourth amplifier; the frequency quadrupler is connected to a first band pass filter, the frequency doubler is connected to a second band pass filter, the fourth amplifier is connected to a third single-pole triple-throw switch; the first band pass filter is connected to a second amplifier, the second band pass filter is connected to a third amplifier; outputs of the second amplifier and the third amplifier are both connected to the third single-pole triple-throw switch; the third single-pole triple-throw switch outputs a required output frequency.

[0041] In some embodiments, the first phase-locked loop circuit PLL1 includes a first phase detector PD, a sixth low pass filter, a first voltage controlled oscillator VCO and a first frequency divider; an input of the first phase detector PD is connected to an output of the second low pass filter and an output of the first frequency divider, an output of the first phase detector PD is connected to the sixth low pass filter; the sixth low pass filter is connected to the first voltage controlled oscillator VCO; the first voltage controlled oscillator VCO is connected to an input of the first frequency divider and an input of the third low pass filter;

[0042] The second phase-locked loop circuit PLL2 comprises a second phase discriminator PD, a seventh low-pass filter, a second voltage-controlled oscillator VCO and a second frequency divider; the input end of the second phase discriminator PD is connected with the output end of the second self-made low-pass filter and the output end of the second frequency divider, and the output end of the second phase discriminator PD is connected with the seventh low-pass filter; the seventh low-pass filter is connected with the second voltage-controlled oscillator VCO; the second voltage-controlled oscillator VCO is connected with the input end of the second frequency divider and the input end of the fourth low-pass filter;

[0043] The output frequency of the first voltage-controlled oscillator VCO and the second voltage-controlled oscillator VCO is greater than the output frequency of the voltage-controlled crystal oscillator VCXO.

[0044] In the embodiment, the output frequency of the voltage-controlled crystal oscillator VCXO is relatively low, and is only 100MHz. The output frequency of the voltage-controlled oscillator VCO is very high, and can be dozens of MHz to 15GHz.

[0045] In some embodiments, the first self-made low-pass filter comprises a first capacitive circuit, a first inductive circuit, a second capacitive circuit and a second inductive circuit; the front-stage input circuit is connected with the first capacitive circuit and the first inductive circuit; the output end of the first inductive circuit is connected with the second capacitive circuit and the second inductive circuit; the output end of the second inductive circuit is connected with the rear-stage circuit; and the circuit structure of the first self-made low-pass filter and the second self-made low-pass filter is the same.

[0046] In the embodiment, as shown in Figure 5 The capacitive circuit has the characteristic of preventing low-frequency signals from passing through by high-frequency signals, and the inductive circuit has the characteristic of preventing high-frequency signals from passing through by low-frequency signals, so when the high-frequency signals outside the band come, the capacitive circuit guides the unnecessary high-frequency signals outside the band to the ground of the circuit to attenuate the unnecessary signals outside the band, and the inductive circuit prevents the interference signals outside the band from passing through and only allows the necessary signals to pass through. The capacitive circuit and the inductive circuit are combined to form a self-made low-pass filter.

[0047] In some embodiments, the clock taming frequency synthesizer circuit is arranged on a clock taming frequency synthesizer structure, and the clock taming frequency synthesizer structure adopts a double-face cavity structure; the front face of the clock taming frequency synthesizer structure is a mixed-voltage multilayer PCB circuit board, and the back face is a microwave surface; the mixed-voltage multilayer PCB circuit board is provided with a taming clock circuit structure 1, a field programmable gate array FPGA circuit structure 2, a first phase-locked loop circuit PLL1 structure 3, a second phase-locked loop circuit PLL2 structure 4 and a DC / DC power supply circuit structure 5.

[0048] In the embodiment, as shown in Figure 2 and Figure 3As shown, the clock taming frequency comprehensive structure adopts a double-sided cavity structure, the front side is a mixed-voltage multilayer PCB circuit board, the board adopts front and back device layout, contains variable taming clock circuit, PLL circuit (including VCO), control power supply circuit and various circuits; the back side of the product is a microwave surface, which is embedded with a micro assembly printed board as a filter, amplifier, frequency multiplier and the like of the radio frequency microwave channel. The low frequency connector and the low-high frequency connector are interconnected with the front control power supply and the radio frequency signal. The mixed-voltage multilayer PCB circuit board is installed on the front side of the structure, the PCB is fixed on the front side of the structure cavity by 4 M1.6 screws, the front PCB circuit board layout contains taming clock circuit, control circuit, PLL1, PLL2, DC / DC power supply circuit, the base frequency generated by the taming clock circuit is sent to PLL1 and PLL2, the required frequency is generated by PLL1 and PLL2 and sent to the back microwave circuit through radio frequency vertical interconnection for filtering, amplification, switching selection and the like; the front DC / DC circuit supplies power for the taming clock circuit, the control circuit, PLL1, PLL2 and the back microwave circuit, the back power supply interconnection adopts a glass bead vertical power feeding mode (the front side adopts direct welding and the back side adopts gold wire bonding connection), the front PCB is covered by a shielding cover plate and is fastened and installed by screws.

[0049] In some embodiments, the microwave surface is embedded with a micro assembly printed board connected with the mixed-voltage multilayer PCB circuit board through the low frequency connector and the low-high frequency connector; the microwave surface is provided with a radio frequency microwave circuit structure 6, a radio frequency output connector 7, a microwave circuit soft substrate, an amplifier, a switch, a filter, a frequency doubler and a frequency quadrupler.

[0050] In the embodiment, the back side of the structure is subjected to slotting and hollowing operations in a micro assembly manner, the soft substrate PCB is adhered to the structure by conductive adhesive, then high temperature baking and curing are performed, the integrated circuit is adhered to the structure and then gold wire bonding is performed, the back circuit board contains a microwave circuit soft substrate, an amplifier, a switch, a filter, a 2 frequency multiplier, a 4 frequency multiplier, an output connector and vertical interconnection; the signals generated by PLL1 and PLL2 are sent to the back side through radio frequency vertical interconnection, then pass through the required circuit for switching selection and then are output through the radio frequency connector; due to the very high working frequency of the back side and the bare chip circuit, two cover plates are required for covering, the first layer is fixed by M1.6 countersunk screws and the second layer is covered by laser sealing. In terms of system layout design, double-sided board layout is adopted to reasonably layout various circuit modules and reduce the overall size. The space occupation of the system is reduced and the overall integration and reliability are improved. The double path phase-locked loop circuit is combined with frequency mixing to realize fast frequency switching and short time locking. The response speed and stability of the system are improved and the system is suitable for high frequency dynamic adjustment demand applications.

[0051] In some embodiments, the microwave surface is covered by double-layer cover plates, the first layer of cover plates is fixed by M1.6 countersunk head screws, and the second layer of cover plates is covered by laser sealing.

[0052] The second aspect of the present application provides: a clock taming frequency synthesis method, for any one of the clock taming frequency synthesis systems, comprising the following steps:

[0053] S1: the GPS receiver receives satellite signals, demodulates 1PPS signals and outputs, providing accurate reference for the frequency source;

[0054] S2: the field programmable gate array (FPGA) compares signal errors, adjusts the output of the voltage-controlled crystal oscillator (VCXO) according to the signal errors, and continuously adjusts the accuracy of the output signal to obtain a clock reference signal;

[0055] S3: the target output frequency signal is directly obtained or mixed to obtain through the control of the first phase-locked loop circuit (PLL1) and the second phase-locked loop circuit (PLL2);

[0056] S4: the required signal path is selected for amplification and filtering to obtain the required output frequency signal and output.

[0057] The above only describes the preferred embodiments of the present application, and it should be understood that the present application is not limited to the forms disclosed herein, and should not be considered as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concepts described herein by the above-mentioned teaching or related technical or knowledge. Any modification and change made by the person skilled in the art without departing from the spirit and scope of the present application shall be within the protection scope of the appended claims of the present application.

Claims

1. A clock disciplining system characterized by: The clock disciplining frequency synthesizer comprises a clock disciplining circuit, a frequency synthesizing circuit connected to the clock disciplining circuit, and a frequency selecting circuit connected to the frequency synthesizing circuit; the clock disciplining circuit is used to provide a base frequency signal, the frequency synthesizing circuit is used to generate a plurality of target output frequencies and perform frequency switching and locking, and the frequency selecting circuit is used to select a required output frequency and output the same; The clock disciplining frequency synthesizer comprises a clock disciplining circuit, a frequency synthesizing circuit connected to the clock disciplining circuit, and a frequency selecting circuit connected to the frequency synthesizing circuit; the clock disciplining circuit is used to provide a base frequency signal, the frequency synthesizing circuit is used to generate a plurality of target output frequencies and perform frequency switching and locking, and the frequency selecting circuit is used to select a required output frequency and output the same; The clock disciplining frequency synthesizer is arranged on a clock disciplining frequency synthesizing structure, and the clock disciplining frequency synthesizing structure adopts a double-face cavity structure; a front surface of the clock disciplining frequency synthesizing structure is a mixed-pressing multi-layer PCB circuit board, and a back surface thereof is a microwave surface; the mixed-pressing multi-layer PCB circuit board is provided with a clock disciplining circuit structure (1), an FPGA circuit structure (2), a first PLL circuit structure (3), a second PLL circuit structure (4), and a DC / DC power supply circuit structure (5).

2. The clock domain system of claim 1, wherein: The clock disciplining frequency synthesizer further comprises an FPGA, a D / A converter, a VCXO, and a first power divider; the GPS system is connected to the FPGA; the FPGA is connected to the D / A converter; the D / A converter is connected to the VCXO; the VCXO is connected to the first power divider; and the first power divider is connected to the FPGA and the frequency synthesizing circuit.

3. The clock domain system of claim 1, wherein: The frequency synthesis circuit comprises a second power divider, an input end of the second power divider is connected with an output end of the clock taming frequency synthesizer circuit, and output ends of the second power divider are connected with a first self-made low-pass filter and a first low-pass filter; the first self-made low-pass filter is connected with a second low-pass filter, and the first low-pass filter is connected with a second self-made low-pass filter; the second low-pass filter is connected with a first phase-locked loop circuit PLL1, and the second self-made low-pass filter is connected with a second phase-locked loop circuit PLL2; an output end of the first phase-locked loop circuit PLL1 is connected with a third low-pass filter, and an output end of the second phase-locked loop circuit PLL2 is connected with a fourth low-pass filter; the third low-pass filter is connected with a first single-pole double-throw switch, and the fourth low-pass filter is connected with a second single-pole double-throw switch; the first single-pole double-throw switch is connected with a first amplifier and a first single-pole triple-throw switch, and the second single-pole double-throw switch is connected with a frequency mixer and the first single-pole triple-throw switch; the first amplifier is connected with a fifth low-pass filter, the fifth low-pass filter is connected with the frequency mixer, and the frequency mixer is connected with the first single-pole triple-throw switch; the first single-pole triple-throw switch is connected with a switch filter group; and the switch filter group is connected with a frequency selection circuit. The first self-made low-pass filter comprises a first capacitive circuit, a first inductive circuit, a second capacitive circuit and a second inductive circuit; a front-stage input circuit is connected with the first capacitive circuit and the first inductive circuit; an output end of the first inductive circuit is connected with the second capacitive circuit and the second inductive circuit; an output end of the second inductive circuit is connected with a rear-stage circuit; and the first self-made low-pass filter and the second self-made low-pass filter have the same circuit structure.

4. The clock domain system of claim 1, wherein: The frequency selection circuit comprises a second single-pole triple-throw switch, an input end of the second single-pole triple-throw switch is connected with an output end of the frequency synthesis circuit, output ends of the second single-pole triple-throw switch are connected with a frequency quadrupler, a frequency doubler and a fourth amplifier; the frequency quadrupler is connected with a first band-pass filter, the frequency doubler is connected with a second band-pass filter, and the fourth amplifier is connected with a third single-pole triple-throw switch; the first band-pass filter is connected with a second amplifier, and the second band-pass filter is connected with a third amplifier; output ends of the second amplifier and the third amplifier are both connected with the third single-pole triple-throw switch; and the third single-pole triple-throw switch outputs a required output frequency.

5. The clock domain system of claim 3, wherein: The first phase-locked loop circuit PLL1 comprises a first phase detector PD, a sixth low-pass filter, a first voltage-controlled oscillator VCO and a first frequency divider; an input end of the first phase detector PD is connected with an output end of the second low-pass filter and an output end of the first frequency divider, and an output end of the first phase detector PD is connected with the sixth low-pass filter; the sixth low-pass filter is connected with the first voltage-controlled oscillator VCO; and the first voltage-controlled oscillator VCO is connected with an input end of the first frequency divider and an input end of the third low-pass filter. The second phase-locked loop circuit PLL2 comprises a second phase discriminator PD, a seventh low-pass filter, a second voltage-controlled oscillator VCO and a second frequency divider; the input end of the second phase discriminator PD is connected with the output end of the second self-made low-pass filter and the output end of the second frequency divider, the output end of the second phase discriminator PD is connected with the seventh low-pass filter; the seventh low-pass filter is connected with the second voltage-controlled oscillator VCO; the second voltage-controlled oscillator VCO is connected with the input end of the second frequency divider and the input end of the fourth low-pass filter. The output frequency of the first voltage-controlled oscillator VCO and the second voltage-controlled oscillator VCO is greater than the output frequency of the voltage-controlled crystal oscillator VCXO.

6. The clock domain system of claim 1, wherein: The microwave surface is connected with the mixed multi-layer PCB circuit board through the intercalation low-frequency connector and the low-high frequency connector; the microwave surface is provided with a radio frequency microwave circuit structure (6), a radio frequency output connector (7), a microwave circuit soft substrate, an amplifier, a switch, a filter, a frequency doubler and a frequency quadrupler.

7. The clock domain system of claim 6, wherein: The microwave surface is covered by double-layer cover plates, the first layer of cover plates is fixed by M1.6 countersunk screws, and the second layer of cover plates is covered by laser sealing.

8. A clock disciplining method, characterized by: The clock disciplining frequency synthesis system according to any one of claims 1-7, The method comprises the following steps: S1: the GPS receiver receives satellite signals, demodulates a 1PPS signal and outputs, and provides an accurate reference for a frequency source; S2: a field programmable gate array FPGA compares a signal error, adjusts the output of a voltage-controlled crystal oscillator VCXO according to the signal error, and continuously adjusts the accuracy of the output signal to obtain a clock reference signal; S3: a target output frequency signal is directly obtained or mixed by controlling the first phase-locked loop circuit PLL1 and the second phase-locked loop circuit PLL2; S4: a required signal path is selected for amplification and filtering to obtain a required output frequency signal and output.

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