Semiconductor memory device

Abstract

Provided is a semiconductor memory device having a structure that can be manufactured more easily. The semiconductor device includes first to third wirings, first to third conductors, first to fourth insulators, and first to fourth semiconductors. The first to third wirings and the first conductor extend along a first plane. The first insulator surrounds the third wiring along the first plane. The first semiconductor sandwiches the first insulator together with the third wiring. The second insulator is provided between the second wiring and the first semiconductor. The third insulator surrounds the first conductor along the first plane. The second conductor is in contact with the first semiconductor. The second semiconductor sandwiches the third insulator together with the first conductor, and is in contact with the second conductor. And the fourth insulators are distributed on the second wiring, the first semiconductor and the second semiconductor along the first plane. The third semiconductor is in contact with the first wiring. The fourth semiconductor is in contact with the third semiconductor and sandwiches the fourth insulator together with the second semiconductor. The third conductor is in contact with the fourth semiconductor.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-022982 (filing date: February 19, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment generally relates to a semiconductor memory device. Background Art

[0004] Semiconductor memory devices containing three-dimensionally arranged memory cells are known. Examples of semiconductor memory devices include random access memory (RAM). Examples of RAM memory cells include memory cells having a gain cell structure. Memory devices containing three-dimensionally arranged memory cells having a gain cell structure and their manufacturing methods are complex. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor memory device having a structure that can be manufactured more easily.

[0006] A semiconductor memory device according to one embodiment includes a first wiring, a second wiring, a third wiring, a first conductor, a first insulator, a first semiconductor, a second insulator, a third insulator, a second conductor, a second semiconductor, a fourth insulator, a third semiconductor, a fourth semiconductor, and a third conductor.

[0007] The first wiring extends along a first plane defined by a first axis and a second axis intersecting the first axis, the first axis extending in a first direction. The second wiring extends along the first plane and is positioned closer to the first direction than the first wiring. The third wiring extends along the first plane and is positioned closer to the first direction than the second wiring. The first conductor extends along the first plane and is positioned closer to the first direction than the second wiring. The first insulator surrounds the third wiring along the first plane, with a portion located between the third and second wirings. The first semiconductor and the third wiring sandwich the first insulator. The second insulator is located between the second wiring and the first semiconductor. The third insulator surrounds the first conductor along the first plane. The second conductor is in contact with the first semiconductor. The second semiconductor and the first conductor sandwich the third insulator and are in contact with the second conductor. The fourth insulator is distributed along the first plane on the second wiring, the first semiconductor, and the second semiconductor. The third semiconductor is in contact with the first wiring and includes a portion sandwiching a fourth insulator with the second wiring, and a portion sandwiching the fourth insulator with the first semiconductor. The fourth semiconductor is in contact with the third semiconductor and sandwiches the fourth insulator with the second semiconductor. The third conductor is in contact with the fourth semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Functional blocks of the semiconductor memory device according to the first embodiment are shown.

[0009] Figure 2 Components of a memory cell of the semiconductor memory device according to the first embodiment and connections between the components are shown.

[0010] Figure 3 The structure of a portion of the semiconductor memory device according to the first embodiment along the xy plane is shown.

[0011] Figure 4 、 Figure 5 、 Figure 6 as well as Figure 7 A cross-sectional structure of a portion of the semiconductor memory device according to the first embodiment is shown.

[0012] Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36 、 Figure 37 、 Figure 38 、 Figure 39 、 Figure 40 、 Figure 41 、 Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46 、 Figure 47 、 Figure 48 、 Figure 49 、 Figure 50 、 Figure 51 、 Figure 52 、 Figure 53 、 Figure 54 、 Figure 55 、 Figure 56 、 Figure 57 、 Figure 58 、 Figure 59 、 Figure 60 、 Figure 61 、 Figure 62 、 Figure 63 、 Figure 64 、 Figure 65 、 Figure 66 、 Figure 67 as well as Figure 68 A structure of a part of the semiconductor memory device according to the first embodiment during the manufacturing process is shown.

[0013] Figure 69 A structure during a partial manufacturing process of a semiconductor memory device according to a first modification of the first embodiment is shown.

[0014] Figure 70 A structure along the xy plane of a portion of a semiconductor memory device according to a first modification of the first embodiment is shown.

[0015] Figure 71 、 Figure 72 、 Figure 73 、 Figure 74 、 Figure 75 、 Figure 76 、 Figure 77、 Figure 78 、 Figure 79 、 Figure 80 、 Figure 81 、 Figure 82 、 Figure 83 、 Figure 84 、 Figure 85 、 Figure 86 、 Figure 87 、 Figure 88 、 Figure 89 、 Figure 90 、 Figure 91 、 Figure 92 as well as Figure 93 A structure during a partial manufacturing process of a semiconductor memory device according to a second modification of the first embodiment is shown. DETAILED DESCRIPTION

[0016] In the following, embodiments are described with reference to the accompanying drawings. For multiple components having substantially the same function and configuration in a particular embodiment or different embodiments, additional numbers or letters may be added to the end of the reference numerals to distinguish them from each other.

[0017] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from reality. In addition, the drawings may also include portions where the relationship and ratio of dimensions differ from each other.

[0018] The following description uses an xyz orthogonal coordinate system to describe the embodiments. The x-axis extends in the x-direction. The y-axis extends in the y-direction. The z-axis extends in the z-direction. The positive direction of the vertical axis of a figure is sometimes referred to as the upper side, and the negative direction is sometimes referred to as the lower side. The positive direction of the horizontal axis of a figure is sometimes referred to as the right side, and the negative direction is sometimes referred to as the left side. Furthermore, the side with the larger coordinate on the z-axis is sometimes referred to as the upper side, and the side with the smaller coordinate is sometimes referred to as the lower side.

[0019] 1. First Implementation

[0020] 1.1. Structure (composition)

[0021] Figure 1 FIG. 2 shows the functional blocks of the semiconductor memory device of the first embodiment. The semiconductor memory device 1 is a device for storing data. Figure 1 As shown, semiconductor memory device 1 includes a memory cell array 11 , an input / output circuit 12 , a control circuit 13 , a voltage generation circuit 14 , a row selection circuit 15 , a column selection circuit 16 , a write circuit 17 , a read circuit 18 , and a sense amplifier 19 .

[0022] Memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Each memory cell MC can store one bit of data. Each memory cell MC is connected to one bit line BL and one word line WL. Memory cells MC are connected between bit lines BL and a source line (not shown). Word lines WL are associated with rows. Bit lines BL are associated with columns. Selecting a row and a column determines a memory cell MC.

[0023] The input / output circuit 12 is a circuit for inputting and outputting data and signals. The input / output circuit 12 receives a control signal CNT, a command CMD, an address signal ADD, and data DAT from outside the semiconductor memory device 1 .

[0024] The control circuit 13 controls the operation of the semiconductor memory device 1. The control circuit 13 receives a command CMD and a control signal CNT from the input / output circuit 12. The control circuit 13 controls the write circuit 17 and the read circuit 18 according to the control indicated by the command CMD and the control signal CNT.

[0025] The voltage generation circuit 14 is a circuit that generates various voltages used in the semiconductor memory device 1. The voltage generation circuit 14 generates a plurality of voltages of different magnitudes under the control of the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0026] The row selection circuit 15 is a circuit for selecting a row of memory cells MC. The row selection circuit 15 receives the address signal ADD from the input / output circuit 12. The row selection circuit 15 uses the voltage received from the voltage generation circuit 14 to select one word line WL associated with the row specified by the received address signal ADD.

[0027] The column selection circuit 16 is a circuit for selecting a column of memory cells MC. The column selection circuit 16 receives the address signal ADD from the input / output circuit 12. The column selection circuit 16 uses the voltage received from the voltage generation circuit 14 to select the bit line BL associated with the column specified by the received address signal ADD.

[0028] The write circuit 17 controls the writing of data into the memory cell MC. The write circuit 17 receives the data to be written from the input / output circuit 12. The write circuit 17 supplies the voltage received from the voltage generating circuit 14 to the column selecting circuit 16 based on the control of the control circuit 13 and the data.

[0029] The read circuit 18 is a circuit that performs control for reading data from the memory cell MC. The read circuit 18 supplies the voltage received from the voltage generating circuit 14 to the column selecting circuit 16 under the control of the control circuit 13. The read circuit 18 supplies a plurality of control signals for data reading to the sense amplifier 19.

[0030] Sense amplifier 19 is a circuit used to determine the data stored in memory cell MC. Sense amplifier 19 includes multiple sense amplifier circuits. Sense amplifier 19 receives multiple voltages from voltage generator circuit 14 and operates using these voltages. During the data read period, sense amplifier 19 amplifies the potential on bit line BL to determine the data stored in the memory cell MC being read. The determined data is provided to input / output circuit 12.

[0031] 1.1.1 Storage Unit

[0032] Figure 2 Components and connections of a memory cell in a semiconductor memory device according to Embodiment 1 are shown. Hereinafter, one of a source and a drain of a transistor may be referred to as one end of the transistor, and the other may be referred to as the other end of the transistor.

[0033] like Figure 2 As shown, the memory cell MC has a gain cell structure. Specifically, the memory cell MC includes a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) TrS, a p-type floating gate MOSFET TrC, and an n-type MOSFET TG.

[0034] The transistor TrS is connected to one source line CSL at one end and to the wiring SG at the gate.

[0035] Transistor TrC includes a floating gate insulated from its surroundings. One end of transistor TrC is connected to the other end of transistor TrS. The other end of transistor TrC is connected to bit line BL. Transistor TrC is connected to wiring CG at its control gate. Wiring CG is connected to a word line WL.

[0036] The transistor TrT is connected to the floating gate of the transistor TrC at one end, connected to the bit line BL at the other end, and connected to the wiring TG at the gate of the transistor TrT.

[0037] 1.1.2. Memory Cell Array

[0038] Figure 3 The structure of a portion of the semiconductor memory device according to the first embodiment along the xy plane is shown. Figures 4 to 7A cross-sectional structure of a portion of the semiconductor memory device according to the first embodiment is shown. Figure 4 Shown along Figure 3 The structure of line IV-IV in FIG. 1 shows the structure along the xz plane. Figure 5 Shown along Figure 3 The structure of the VV line in FIG. 1 shows the structure along the xz plane. Figure 6 Shown along Figure 3 The structure of the VI-VI line in FIG. 1 shows the structure along the xz plane. Figure 7 Shown along Figure 3 The structure of line VII-VII in FIG. 1 shows the structure along the yz plane.

[0039] like Figure 3 As shown, the semiconductor memory device 1 includes a plurality of unit structures US. Each unit structure US functions as a memory cell MC. The unit structures US extend in the Y direction and are arranged in the X direction. The two unit structures US arranged in the Y direction have a structure symmetrical about the x-axis and share a part of the structure. The following describes the lower unit structure US among the unit structures US arranged in the Y direction. Each unit structure US includes semiconductors 21, 22, 24, 35, 37, 42, 44, conductors 26, 38, 46, and insulators 28, 31, 32, 36, 41. The semiconductor memory device 1 also includes an insulator 48.

[0040] In each unit structure US, semiconductors 21 , 22 , and 24 , conductors 25 and 26 , and insulator 28 are arranged in the Y direction.

[0041] The semiconductor 21 extends along the xy plane. In one example, the semiconductor 21 has a shape based on a circle or an ellipse along the xy plane. The semiconductor 21 includes one first portion 21a and two second portions 21b. The first portion 21a has a shape in which a portion of the upper side of the circle or ellipse is missing. Therefore, the shape of the lower half of the first portion 21a is different from the shape of the upper half. The upper end of the first portion 21a has a contour that follows the contour of the semiconductor 22. In one example, the semiconductor 21 includes silicon. The semiconductor 21 is doped with impurities and has conductivity. In one example, the semiconductor 21 includes p-type impurities. Examples of p-type impurities include boron. The semiconductor 21 functions as a wiring and functions as at least a portion of the source line CSL.

[0042] A conductor may be provided in place of semiconductor 21. In one example, the conductor comprises titanium nitride. Alternatively, a central conductor and semiconductors doped with p-type impurities located on the sides of the conductor may be provided in place of semiconductor 22. Examples of p-type impurities include boron.

[0043] Each second portion 21b is connected to the upper end of the first portion 21a at the lower side and is continuous with the first portion 21a. The second portion 21b has a shape along the outline of the semiconductor 22 and extends along the semiconductor 22. The second portions 21b are spaced apart from each other.

[0044] Semiconductor 22 extends along the xy plane. In one example, semiconductor 22 has a shape based on a circle or an ellipse along the xy plane. Semiconductor 22 includes one first portion 22a and two second portions 22b. First portion 22a has a shape with a portion of the upper side of the circle or ellipse missing. Therefore, the shape of the lower half of first portion 22a is different from the shape of the upper half. The upper end of first portion 22a has a contour that follows the contour of semiconductor 24. The lower end of first portion 22a is located between second portions 21b of semiconductor 21. In one example, semiconductor 22 includes silicon. Semiconductor 22 is doped with impurities and has conductivity. In one example, semiconductor 22 includes p-type impurities. Examples of p-type impurities include boron. Semiconductor 22 functions as at least a portion of wiring SG. In another example, semiconductor 22 includes n-type impurities. Examples of n-type impurities include arsenic.

[0045] A conductor may be provided in place of semiconductor 22. In one example, the conductor comprises titanium nitride. Alternatively, a central conductor and impurity-doped semiconductors located on the sides of the conductor may be provided in place of semiconductor 22. The impurities, like those in semiconductor 22, may be either n-type or p-type.

[0046] The second portion 22b is connected to the upper end of the first portion 22a at the lower side and is continuous with the first portion 22a. The second portion 22b is curved. The second portion 22b has a larger curvature than the radius of the first portion 22a. The second portions 22b are spaced apart.

[0047] Semiconductor 24 extends along the xy plane. Semiconductor 24 functions as at least a portion of wiring CG. In one example, semiconductor 24 has a circular or elliptical shape. The lower end of semiconductor 24 is located between second portions 22b of semiconductor 22. In one example, semiconductor 24 comprises silicon. Semiconductor 24 is doped with impurities to provide conductivity. In one example, semiconductor 24 comprises p-type impurities. Examples of p-type impurities include boron. In another example, semiconductor 24 comprises n-type impurities. Examples of n-type impurities include arsenic.

[0048] A conductor may be provided in place of semiconductor 24. In one example, the conductor comprises titanium nitride. Alternatively, a central conductor and impurity-doped semiconductors located on the sides of the conductor may be provided in place of semiconductor 24. Like semiconductor 24, the impurity may be either n-type or p-type.

[0049] The conductor 26 extends along the xy plane. In one example, the conductor 26 has a circular or elliptical shape along the xy plane. In one example, the conductor 26 includes titanium nitride. The conductor 26 functions as at least a portion of the wiring TG.

[0050] Insulator 28 extends along the xy plane. In one example, insulator 28 has a circular or elliptical shape along the xy plane. In one example, insulator 28 comprises silicon oxide.

[0051] Insulator 31 surrounds semiconductor 24 along the xy plane and extends along the contour of semiconductor 24. Insulator 31 extends over the entire surface of semiconductor 24 along the xy plane. Insulator 31 has a ring-shaped shape along the xy plane. Insulator 31 has a radius or curvature along the xy plane that is larger than that of semiconductor 24. In one example, insulator 31 comprises silicon oxide. Insulator 31 functions as a blocking insulator for transistor TrT. Insulator 31 has a thickness sufficient to prevent electrons stored in semiconductor 35 from escaping through insulator 31. In one example, insulator 31 has a thickness of 6 nm or greater.

[0052] Insulator 32 surrounds conductor 26 along the xy plane and extends along the contour of conductor 26. Insulator 32 extends over the entire surface of conductor 26 along the xy plane. Insulator 32 has a radius or curvature along the xy plane that is larger than that of conductor 26. Insulator 32 has a ring-shaped shape along the xy plane. In one example, insulator 32 comprises silicon oxide. Insulator 32 functions as a gate insulator for transistor TrT.

[0053] Semiconductor 35 extends along the contour of insulator 31 on the right or left side of insulator 31. Semiconductor 35 curves along the contour of semiconductor 24. Semiconductor 35 extends across the entire surface of insulator 31 along the xy plane. Semiconductor 35 has a curvature along the xy plane that is greater than the radius or curvature of each of semiconductor 24 and insulator 31. Semiconductor 35 covers a portion of insulator 31. The set of two semiconductors 35 in contact with each insulator 31 does not cover the lower and upper ends of insulator 31. In one example, semiconductor 35 comprises silicon. Semiconductor 35 functions as the floating gate of transistor TrC.

[0054] Insulator 36 is located between semiconductor 22 and semiconductor 35. Insulator 36 is in contact with semiconductor 22, semiconductor 35, and insulator 31. Insulator 36 has a shape that follows the contour of second portion 22 b of semiconductor 22. Insulator 36 has a curvature greater than the radius of first portion 22 a and second portion 22 b of semiconductor 22. Insulator 36 covers the surface of second portion 22 b of semiconductor 22 that faces semiconductor 35, insulating semiconductor 22 from semiconductor 35. In one example, insulator 36 comprises silicon oxide.

[0055] Semiconductor 37 extends along the xy plane along the outline of insulator 32. Semiconductor 37 partially surrounds insulator 32. Semiconductor 37 curves along the outline of conductor 26. In one example, semiconductor 37 has a ring-like shape with an open portion at its lower end. Semiconductor 37 is in contact with insulator 31. In one example, semiconductor 37 is in contact with insulator 31 at the open portion. Semiconductor 37 is made of a material with a high energy bandgap. In one example, semiconductor 37 is made of a material with an energy bandgap of 2.0 eV or greater. In one example, semiconductor 37 is made of a titanium oxide semiconductor. In another example, semiconductor 37 is made of a semiconductor selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). If semiconductor 37 is a titanium oxide semiconductor or a metal oxide semiconductor selected from the group consisting of indium, gallium, zinc, and oxygen, leakage of charge stored in semiconductor 37 to semiconductor 35 can be suppressed. Semiconductor 37 functions as the channel of transistor TrT.

[0056] Conductor 38 is located between semiconductor 35 and semiconductor 37. Conductor 38 is in contact with semiconductor 35, semiconductor 37, and insulator 31. Conductor 38 has a shape that follows the contour of semiconductor 37. Conductor 38 is curved. Conductor 38 has a curvature greater than the radius of conductor 26, the radius of insulator 32, and the radius (or curvature) of semiconductor 37. In one example, conductor 38 comprises titanium nitride.

[0057] Insulator 41 extends along the xy plane along semiconductor 22, insulator 36, semiconductor 35, conductor 38, and semiconductor 37. Insulator 41 is in contact with semiconductor 22, insulator 36, semiconductor 35, conductor 38, and semiconductor 37. Insulator 41 covers the surfaces of semiconductor 22, insulator 36, semiconductor 35, conductor 38, and semiconductor 37.

[0058] The insulator 41 is curved. The insulator 41 has a shape along the outline of the semiconductor 22 at a portion around the semiconductor 22. The insulator 41 has a curvature greater than the radius or curvature of the semiconductor 22 at a portion around the semiconductor 22.

[0059] The insulator 41 has a shape along the outline of the semiconductor 35 at a portion around the semiconductor 35. The insulator 41 has a curvature greater than the radius or curvature of the semiconductor 35 at a portion around the semiconductor 35.

[0060] The insulator 41 has a shape along the outline of the semiconductor 37 at a portion around the semiconductor 37. The insulator 41 has a curvature larger than the radius or curvature of the semiconductor 37 at a portion around the semiconductor 37.

[0061] The insulator 41 has an open ring shape at the upper end, and the insulator 41 does not cover the semiconductor 37 at the opening.

[0062] In one example, the insulator 41 comprises silicon oxide. The insulator 41 has a thickness sufficient to prevent electrons stored in the semiconductor 35 from escaping through the insulator 31. In one example, the insulator 41 has a thickness of 6 nm or greater. The insulator 41 functions as a gate insulator for the transistor TrS in the portion surrounding the semiconductor 22. Furthermore, the insulator 41 electrically insulates the semiconductor 37 from the semiconductor 44 in the portion surrounding the semiconductor 37.

[0063] Semiconductor 42 extends along a portion of insulator 41 along the xy plane. Semiconductor 42 is in contact with insulator 41. Semiconductor 42 covers the entire portion of the sides (i.e., the right and left sides) of semiconductor 22 in insulator 41. Semiconductor 42 does not cover the lower end portion of insulator 41. Semiconductor 42 covers the entire portion of the sides (i.e., the right and left sides) of semiconductor 24 in insulator 41. Semiconductor 42 covers the portion below the side (i.e., the right and left sides) of semiconductor 37 in insulator 41.

[0064] Semiconductor 42 is curved. Semiconductor 42 has a shape along the outline of semiconductor 22 at a portion around semiconductor 22. Semiconductor 42 has a curvature greater than the radius or curvature of semiconductor 22 at a portion around semiconductor 22.

[0065] The semiconductor 42 has a shape along the outline of the semiconductor 35 at a portion around the semiconductor 35. The semiconductor 42 has a curvature greater than the radius or curvature of the semiconductor 35 at a portion around the semiconductor 35.

[0066] The semiconductor 42 has a shape along the outline of the semiconductor 37 at a portion around the semiconductor 37. The semiconductor 42 has a curvature greater than the radius or curvature of the semiconductor 37 at a portion around the semiconductor 37.

[0067] Semiconductor 42 is in contact with semiconductor 21 and with second portion 21b of semiconductor 21. In one example, semiconductor 42 comprises silicon. The portion of semiconductor 42 surrounding semiconductor 22 functions as the channel of transistor TrS. The portion of semiconductor 42 surrounding semiconductor 35 functions as the channel of transistor TrC.

[0068] Semiconductor 44 extends along a portion of insulator 41 along the xy plane. Semiconductor 44 is in contact with insulator 41. Semiconductor 44 covers a portion of the lateral (i.e., right and left) portions of conductor 26 in insulator 41. Semiconductor 44 covers the portions of the lateral portions of conductor 26 in insulator 41 that are not covered by semiconductor 42. Semiconductor 44 has a shape that follows the contour of semiconductor 37. Semiconductor 44 has a curvature that is greater than the radius or curvature of semiconductor 37. Semiconductor 44 does not cover the uppermost portion of insulator 41 at its uppermost portion. As described later, semiconductor 44 is deposited using a different process from semiconductor 42 and can therefore have different properties from those of semiconductor 42. Examples of properties include density and impurity concentration. In one example, semiconductor 44 comprises silicon. Semiconductor 44 is doped with impurities to have conductivity. In one example, semiconductor 44 contains p-type impurities. Examples of p-type impurities include boron. In one example, semiconductor 42 comprises silicon containing boron. The semiconductor 44 functions as a wiring connecting the bit line BL and the source or drain of the transistor TrT.

[0069] Conductor 46 extends in the X direction. Conductor 46 surrounds insulator 28. Conductor 46 has a shape formed by combining multiple circles or ellipses with their upper and lower portions missing in the X direction. Conductor 46 contacts semiconductor 37 at its lower and upper ends. Conductor 46 contacts semiconductor 44 at its lower and upper ends. In one example, conductor 46 comprises titanium nitride. Conductor 46 is shared by two unit structures US arranged in the Y direction.

[0070] The insulator 48 fills the region where the semiconductors 21, 22, 24, 35, 37, 42, 44, the conductors 26, 38, 46, and the insulators 28, 31, 32, 36, 41 are not provided. In one example, the insulator 48 includes silicon nitride.

[0071] The combination of the semiconductor 22, the portion of the insulator 41 covering the semiconductor 22, and the portion of the semiconductor 42 lateral to the semiconductor 22 functions as a transistor TrS. The semiconductor 42 portion functions as the channel of the transistor TrS. The insulator 41 portion functions as the gate insulator of the transistor TrS.

[0072] The combination of semiconductor 24, the portion of insulator 31 lateral to semiconductor 24, semiconductor 35, the portion of insulator 41 lateral to semiconductor 24, and the portion of semiconductor 42 lateral to semiconductor 24 functions as a transistor TrC. The portion of insulator 31 functions as a blocking insulator for transistor TrC. Semiconductor 35 functions as a floating gate for transistor TrC. The portion of insulator 41 lateral to semiconductor 24 functions as a tunnel insulator for transistor TrC. The portion of semiconductor 42 lateral to semiconductor 24 functions as a channel for transistor TrC.

[0073] The combination of the conductor 26, the portion of the insulator 32 lateral to the conductor 26, and the portion of the semiconductor 37 lateral to the semiconductor 26 functions as a transistor TrG. The portion of the semiconductor 37 functions as the channel of the transistor TrT. The portion of the insulator 32 functions as the gate insulator of the transistor TrT.

[0074] like Figures 4 to 7 As shown, there are repeatedly arranged in the Z direction Figure 3 The semiconductor memory device 1 further includes a substrate 51 and insulators 52 and 54 .

[0075] The substrate 51 extends along the xy plane. In one example, the substrate 51 comprises silicon.

[0076] The insulator 52 is located on the upper surface of the substrate 51. In one example, the insulator 52 comprises silicon oxide.

[0077] The insulator 54 extends along the xy plane. In one example, the insulator 54 comprises silicon oxide. Figure 3 The layers of the structure shown are alternately arranged one by one on the upper surface of the insulator 52. Figure 3 The layer where the structure shown is located is referred to as the layer where the memory cell MC is located. Figures 4 to 7 The following example shows three groups of layers where the insulator 54 and the memory cell MC are located. The semiconductor memory device 1 has holes HP, HS, HC, HT, and HB.

[0078] like Figures 4 to 7As shown, the hole HS extends in the Z direction. The hole HS is filled with the semiconductor 22. Hereinafter, the portion in the hole HS in the semiconductor 22 is sometimes referred to as the central portion 221. The portion of the semiconductor 22 other than the central portion 221 is sometimes referred to as the protrusion 222. The protrusion 222 surrounds the central portion 221 along the xy plane. The protrusion 222 protrudes from the central portion 221 in a direction away from the central portion 221. The protrusion 222 is connected to the central portion 221 and is continuous with the central portion 221. The protrusion 222 is located in the layer where the memory cell MC is located. The protrusion 222 is located between the insulators 54 arranged in the Z direction. The protrusions 222 located in different layers are connected through the central portion 221. The protrusion 222 is connected to the insulator 41 and the insulator 31. Figure 3 The illustrated first portion 22 a includes a central portion 221 and a protruding portion 222 . Figure 3 The second portion 22 b is shown to include a protrusion 222 .

[0079] like Figure 5 and Figure 7 As shown, the hole HC extends in the Z direction and is filled with the semiconductor 24 .

[0080] like Figure 6 and Figure 7 As shown, the hole HT extends in the Z direction. The hole HT is filled with a portion of the conductor 26. Hereinafter, the portion in the hole HT in the conductor 26 is sometimes referred to as the central portion 261. The portion other than the central portion 261 in the conductor 26 is sometimes referred to as the protrusion 262. The protrusion 262 surrounds the central portion 261 along the xy plane. The protrusion 262 protrudes from the central portion 261 in a direction away from the central portion 261. The protrusion 262 is connected to the central portion 261 and is continuous with the central portion 261. The protrusion 262 is located in the layer where the memory cell MC is located. The protrusion 262 is located between the insulators 54 arranged in the Z direction. The protrusions 262 located in different layers are connected through the central portion 261. The protrusion 262 is connected to the insulator 32.

[0081] The insulator 32 covers the surface of the conductor 26 along the z-axis.

[0082] like Figure 7As shown, the hole HP extends in the Z direction. The hole HP is filled with a portion of the semiconductor 21. Hereinafter, the portion in the hole HP in the semiconductor 21 is sometimes referred to as the central portion 211. The portion of the semiconductor 21 other than the central portion 211 is sometimes referred to as the protrusion 212. The protrusion 212 surrounds the central portion 211 along the xy plane. The protrusion 212 protrudes from the central portion 211 in a direction away from the central portion 211. The protrusion 212 is connected to the central portion 211 and is continuous with the central portion 211. The protrusion 212 is located in the layer where the memory cell MC is located. The protrusion 212 is located between the insulators 54 arranged in the Z direction. The protrusions 212 located in different layers are connected through the central portion 211. The protrusion 212 is connected to the insulator 41.

[0083] The hole HB extends in the Z direction and is filled with the insulator 28 .

[0084] Manufacturing method

[0085] Figures 8 to 68 An example of the structure during a part of the manufacturing process of the semiconductor memory device according to the first embodiment is shown.

[0086] Figure 8 Show Figure 3 A portion of the area shown. Figure 9 Show Figure 4 The area shown.

[0087] like Figure 8 and Figure 9 As shown, insulator 52 is formed on the upper surface of substrate 51. Next, insulators 48A and 54A are alternately deposited one after another on the upper surface of insulator 52. Insulator 48A is an element that will be formed into insulator 48 in a subsequent process. Insulator 54A is an element that will be formed into insulator 54 in a subsequent process.

[0088] Figure 10 Show Figure 3 A portion of the area shown. Figure 11 Show Figure 4 The area shown. Figure 12 Show Figure 7 The area shown.

[0089] like Figures 10 to 12 As shown, holes HP, HS, HC, HT, and HB are formed in insulators 54A and 48A. Examples of formation methods include a combination of photolithography and RIE (Reactive Ion Etching). Holes HP, HS, HC, HT, and HB penetrate insulators 54A and 48A and extend in the Z direction. Forming holes HS, HC, HT, and HB transforms insulator 54A into insulator 54.

[0090] Holes HP, HS, HC, HT, and HB are filled with a sacrificial material SM1. In one example, sacrificial material SM1 comprises silicon oxide and / or polysilicon. Alternatively, sacrificial material SM1 may comprise polysilicon and silicon oxide covering the polysilicon. Examples of filling methods include CVD (Chemical Vapor Deposition).

[0091] The sacrificial material SM1 in the holes HS, HC, and HT is removed. Examples of removal methods include a combination of photolithography and RIE. Specifically, a mask having an opening is formed on the upper surface of the structure obtained through the steps thus far using photolithography. The mask has openings above the holes HS, HC, and HT. Next, RIE using the mask is used to remove the sacrificial material SM1 below the openings. Subsequent steps involving the removal of one or more sacrificial materials similar to the sacrificial material SM1 in the holes HP, HS, HC, and HT are performed in the same manner.

[0092] The portions of insulator 48A exposed in holes HS, HC, and HT are removed. Examples of removal methods include wet etching. This removal forms a space SP1 around holes HS, HC, and HT in insulator 48A (i.e., the layer where memory cell MC is located). Space SP1 has a ring-like shape surrounding holes HS, HC, and HT.

[0093] The semiconductor 42A is formed in the space SP1. The semiconductor 42A is an element to be formed into the semiconductor 42 in a subsequent process. Examples of the formation method include CVD.

[0094] The semiconductor 42A formed in the holes HS, HC, and HT during the formation of the semiconductor 42A is removed, whereby the holes HS, HC, and HT are formed again.

[0095] Figure 13 Show Figure 3 A portion of the area shown. Figure 14 Show Figure 4 The area shown. Figure 15 Show Figure 7 The area shown.

[0096] like Figures 13 to 15 As shown, a sacrificial material SM2 is deposited in the holes HS, HC, and HT. In one example, the sacrificial material SM2 comprises silicon oxide and / or polysilicon. Examples of deposition methods include CVD. Through the deposition, the holes HS, HC, and HT are filled with the sacrificial material SM2.

[0097] The sacrificial material SM1 in the hole HB is removed. Examples of the removal method include CVD. By removing, the hole HB is formed again.

[0098] The portion of insulator 48A exposed in hole HB is removed. Examples of removal methods include wet etching. This removal forms a space SP3 around hole HB in the layer where insulator 48A is located. Space SP3 has a ring-shaped shape surrounding hole HB. The removal is continued until space SP3 reaches semiconductor 42A. Semiconductor 42A is exposed in space SP3.

[0099] The portion of semiconductor 42A exposed at space SP3 is removed. Examples of removal methods include wet etching. The wet etching solution reaches semiconductor 42A from space SP3. The wet etching removes the upper portion of semiconductor 42A at the layer where insulator 48A is located. This removal causes the surface of semiconductor 42A exposed at space SP3 to recede. This removal transforms semiconductor 42A into semiconductor 42B. This removal also expands space SP3 at the layer where insulator 48A is located.

[0100] A sacrificial material SM3 is deposited in the space SP3. In one example, the sacrificial material SM3 includes silicon nitride. Examples of deposition methods include CVD. Through the deposition, the space SP3 is filled with the sacrificial material SM3.

[0101] The sacrificial material SM3 formed in the hole HB during the formation of the sacrificial material SM3 is removed, thereby forming the hole HB again.

[0102] A sacrificial material SM4 is deposited in the hole HB. In one example, the sacrificial material SM4 comprises silicon oxide and / or polysilicon. Examples of deposition methods include CVD. Through the deposition, the hole HB is filled with the sacrificial material SM4.

[0103] Figure 16 Show Figure 3 A portion of the area shown. Figure 17 Show Figure 4 The area shown. Figure 18 Show Figure 7 The area shown.

[0104] like Figures 16 to 18 As shown, the sacrificial material SM2 is removed. Examples of the removal method include a combination of a photolithography process and RIE. By removing, holes HS, HC, and HT are formed again. By forming holes HS, HC, and HT, semiconductor 42B is exposed in holes HS, HC, and HT.

[0105] The portions of semiconductor 42B exposed in holes HS, HC, and HT are removed. Examples of removal methods include wet etching. Removal is performed until semiconductor 42B reaches the thickness of semiconductor 42. This removal causes the surface of semiconductor 42B exposed in holes HS, HC, and HT to recede. This removal forms a space SP4 at the layer where insulator 48A is located, in the area where semiconductor 42B was previously located. Through this space SP4, sacrificial material SM3 is exposed in the region above hole HT in semiconductor 42B at the layer where insulator 48A is located.

[0106] The insulator 41 is formed on the surface of the semiconductor 42B exposed in the space SP4. Examples of this formation include oxidation of the surface of the semiconductor 42B. In the region above the hole HT in the sacrificial material SM3, the insulator 41 is not formed on the surface exposed in the space SP4. This is because the sacrificial material SM3 contains a material different from that of the semiconductor 42B.

[0107] The semiconductor 35A is deposited on the portion of the insulator 41 exposed in the space SP4. The semiconductor 35A is an element to be formed into the semiconductor 35 in a subsequent process. Examples of the deposition method include CVD.

[0108] The semiconductor 35A formed in the holes HS, HC, and HT during the deposition of the semiconductor 35A is removed. Thus, the holes HS, HC, and HT are formed again.

[0109] Figure 19 Show Figure 3 A portion of the area shown. Figure 20 Show Figure 4 The area shown. Figure 21 Show Figure 5 The area shown. Figure 22 Show Figure 7 The area shown.

[0110] like Figure 19 、 Figure 20 、 Figure 21 as well as Figure 22 As shown, a sacrificial material SM6 is deposited in the holes HS and HT. In one example, the sacrificial material SM6 comprises silicon oxide and / or polysilicon. Examples of deposition methods include CVD. Through the deposition, the holes HS and HT are filled with the sacrificial material SM6.

[0111] The hole HC is not buried. In an example of a method for this, after the holes HS, HC, and HT are buried with the sacrificial material SM6, the sacrificial material SM6 in the hole HC is removed.

[0112] The insulator 31 is formed over the portion of the semiconductor 35A exposed in the hole HC. Examples of the formation method include oxidation of the semiconductor 35A.

[0113] The semiconductor 24 is deposited in the hole HC. Examples of the deposition method include CVD. The hole HC is filled with the semiconductor 24 by the deposition.

[0114] Figure 23 Show Figure 3 A portion of the area shown. Figure 24 Show Figure 4 The area shown. Figure 25 Show Figure 7 The area shown.

[0115] like Figures 23 to 25 As shown, the sacrificial material SM6 in the hole HS is removed. Examples of the removal method include RIE. By removing, the hole HS is formed again. By forming the hole HS, the semiconductor 35A is exposed in the hole HS at the layer where the insulator 48A is located.

[0116] The portion of semiconductor 35A exposed in hole HS is removed. Examples of removal methods include wet etching. This removal forms a space SP6 around hole HS in the layer where insulator 48A is located. Space SP6 has a ring-shaped shape surrounding hole HS. This removal exposes insulator 41 in space SP6.

[0117] By partially removing semiconductor 35A, space SP6 expands to the area above hole HS in semiconductor 35A. Space SP6 removes the lower portion of the portion of semiconductor 35A that is lateral (i.e., right and left) to semiconductor 24. As a result, semiconductor 35A is exposed lateral to semiconductor 24.

[0118] Figure 26 Show Figure 3 A portion of the area shown. Figure 26 As shown, the insulator 36 is formed on the portion of the semiconductor 35A exposed by the space SP6. Examples of the formation method include oxidation of the semiconductor 35A.

[0119] Figure 27 Show Figure 3 A portion of the area shown. Figure 28 Show Figure 4 The area shown. Figure 29 Show Figure 7 The area shown.

[0120] like Figures 27 to 29 As shown, the semiconductor 22 is deposited in the hole HS and the space SP6. Examples of the deposition method include CVD. By the deposition, the hole HS and the space SP6 are filled with the semiconductor 22.

[0121] Figure 30 Show Figure 3A portion of the area shown. Figure 31 Show Figure 6 The area shown. Figure 32 Show Figure 7 The area shown.

[0122] like Figures 30 to 32 As shown, the sacrificial material SM6 in the hole HT is removed. Examples of the removal method include RIE. By removing, the hole HT is formed again. By forming the hole HT, the semiconductor 35A is exposed in the hole HS at the layer where the insulator 48A is located.

[0123] Figure 33 Show Figure 3 A portion of the area shown. Figure 34 Show Figure 6 The area shown. Figure 35 Show Figure 7 The area shown.

[0124] like Figures 33 to 35 As shown, the portion of semiconductor 35A exposed in hole HT is removed. Examples of removal methods include wet etching. This removal forms a space SP7 around hole HT at the layer where insulator 48A is located. Space SP7 has a ring-shaped shape surrounding hole HT. This removal exposes insulator 41, sacrificial material SM3, and insulator 31 at space SP67.

[0125] By partially removing the semiconductor 35A, the upper portion of the semiconductor 35A on the sides (ie, right and left sides) of the semiconductor 24 is removed from the space SP7 .

[0126] Figure 36 Show Figure 3 A portion of the area shown. Figure 37 Show Figure 6 The area shown. Figure 38 Show Figure 7 The area shown.

[0127] like Figures 36 to 38 As shown, a sacrificial material SM7 is deposited in the space SP7. In one example, the sacrificial material SM7 is silicon nitride. Examples of deposition methods include CVD. Through the deposition, the space SP7 is filled with the sacrificial material SM7.

[0128] A sacrificial material SM8 is deposited in the hole HT. In one example, the sacrificial material SM8 includes silicon oxide and / or polysilicon. Examples of deposition methods include CVD. Through the deposition, the hole HT is filled with the sacrificial material SM8.

[0129] Figure 39 Show Figure 3A portion of the area shown. Figure 40 Show Figure 7 The area shown.

[0130] like Figure 39 and Figure 40 As shown, the sacrificial material SM4 in the hole HB is removed. Examples of the removal method include RIE. By removing, the hole HB is formed again. By forming the hole HB, the sacrificial material SM3 is exposed in the hole HB at the layer where the insulator 48A is located.

[0131] Figure 41 Show Figure 3 A portion of the area shown. Figure 42 Show Figure 7 The area shown.

[0132] like Figure 41 and Figure 42 As shown, the sacrificial material SM3 is removed. Examples of removal methods include wet etching. By removing, a space SP8 is formed in the region where the sacrificial material SM3 was located at the layer where the insulator 48A is located. In the space SP8, the insulator 48A is exposed.

[0133] The portion of insulator 48A exposed at space SP8 is removed. Examples of removal methods include wet etching. This removal expands space SP8 within the layer where insulator 48A is located. Partial removal of insulator 48A continues until the portion between holes HB arranged in the X direction in insulator 48A is removed. As a result, space SP8 has a shape formed by combining the annular shapes surrounding holes HB. Sacrificial material SM8, insulator 41, and semiconductor 42B are exposed at space SP8.

[0134] The partial removal of the insulator 48A also removes the upper portion of the sacrificial material SM7 on the sides (i.e., the right and left sides) of the sacrificial material SM8. As a result, the space SP8 includes a portion SP81 at the upper portion of the sacrificial material SM7 on the sides of the sacrificial material SM8.

[0135] Figure 43 Show Figure 3 A portion of the area shown. Figure 44 Show Figure 6 The area shown.

[0136] like Figure 43 and Figure 44As shown, the portion of semiconductor 42B exposed in space SP8 is removed. Examples of removal methods include wet etching. This removal expands space SP8 throughout the area where semiconductor 42B was previously located, encompassing portion SP82. The lower end of portion SP82 reaches near the lower end of sacrificial material SM8. The partial removal of semiconductor 42B also leaves insulator 41.

[0137] Figure 45 Show Figure 3 A portion of the area shown. Figure 46 Show Figure 6 The area shown.

[0138] like Figure 45 and Figure 46 As shown, the semiconductor 44 is deposited in the portion SP82 of the space SP8. Examples of the deposition method include CVD. By the deposition, the space SP8 is filled with the semiconductor 44.

[0139] Figure 47 Show Figure 3 A portion of the area shown. Figure 48 Show Figure 7 The area shown.

[0140] like Figure 47 and Figure 48 As shown, the conductor 46 is deposited in the entire area of the space SP8 except for the portion SP82. Examples of the deposition method include CVD. By the deposition, the entire area of the space SP8 except for the portion SP82 is filled with the conductor 46.

[0141] The conductor 46 deposited in the hole HB during the deposition of the conductor 46 is removed. Thus, the hole HB is formed again.

[0142] Insulator 28 is deposited in hole HB. Examples of the deposition method include CVD. Hole HB is filled with insulator 28 by the deposition.

[0143] Figure 49 Show Figure 3 A portion of the area shown. Figure 50 Show Figure 7 The area shown.

[0144] like Figure 49 and Figure 50 As shown, the sacrificial material SM1 in the hole HP is removed. Examples of the removal method include RIE. By removing, the hole HP is formed again. By forming the hole HP, the insulator 48A is exposed in the hole HP at the layer where the insulator 48A is located.

[0145] Figure 51 Show Figure 3 A portion of the area shown. Figure 52 Show Figure 7 The area shown.

[0146] like Figure 51 and Figure 52 As shown, the portion of insulator 48A exposed in hole HP is removed. Examples of removal methods include wet etching. This removal forms a space SP9 around hole HP in the layer where insulator 48A is located. Space SP9 has a ring-shaped shape surrounding hole HP. In space SP9, a portion of semiconductor 42B along the lower end of semiconductor 22 is exposed. By partially removing insulator 48A, insulator 48A becomes insulator 48.

[0147] Figure 53 Show Figure 3 A portion of the area shown. Figure 54 Show Figure 7 The area shown.

[0148] like Figure 53 and Figure 54 As shown, the portion of semiconductor 42B exposed in space SP9 is removed. Examples of removal methods include wet etching. As a result of this removal, space SP9 expands to include a portion SP91 at the lower portion of semiconductor 42B, lateral to semiconductor 22. Portion SP91 is located between insulator 41 and insulator 48. By partially removing semiconductor 42B, semiconductor 42B becomes semiconductor 42.

[0149] Figure 55 Show Figure 3 A portion of the area shown. Figure 56 Show Figure 7 The area shown.

[0150] like Figure 55 and Figure 56 As shown, the semiconductor 21 is deposited in the hole HP and the space SP9. Examples of the deposition method include CVD. By the deposition, the hole HP and the space SP9 are filled with the semiconductor 21. The semiconductor 21 is in contact with the semiconductor 42 at a portion SP91 of the space SP9.

[0151] Figure 57 Show Figure 3 A portion of the area shown. Figure 58 Show Figure 6 The area shown. Figure 59 Show Figure 7 The area shown.

[0152] like Figures 57 to 59As shown, the sacrificial material SM8 in the hole HT is removed. Examples of the removal method include RIE. By removing, the hole HT is formed again. By forming the hole HT, the sacrificial material SM7 and the conductor 46 are exposed in the hole HT.

[0153] Figure 60 Show Figure 3 A portion of the area shown. Figure 61 Show Figure 6 The area shown. Figure 62 Show Figure 7 The area shown.

[0154] like Figures 60 to 62 As shown, sacrificial material SM7 is removed. Examples of removal methods include wet etching. This removal forms a space SP11 at the layer where insulator 48 is located, in the area where sacrificial material SM7 was located. Insulators 31 and 41, conductor 46, and semiconductor 35 are exposed at space SP11.

[0155] Figure 63 Show Figure 3 A portion of the area shown. Figure 64 Show Figure 6 The area shown. Figure 65 Show Figure 7 The area shown.

[0156] like Figures 63 to 65 As shown, conductor 38A is deposited in space SP11. Conductor 38A is an element that will be formed into conductor 38 in a subsequent process. Examples of deposition methods include CVD. The portion of conductor 38A exposed in space SP11 is removed. This removal causes the surface of conductor 38A exposed in space SP11 to recede. As a result, conductor 38A remains on the surface of semiconductor 35 and on the surface of insulator 41, at the layer where insulator 48 is located.

[0157] By partially removing the conductor 38A, the portion of the conductor 46 exposed by the space SP11 is removed at the layer where the insulator 48A is located. By the removal, the space SP11 is expanded to the area where the portion of the conductor 46 was located.

[0158] Figure 66 Show Figure 3 A portion of the area shown. Figure 67 Show Figure 6 The area shown. Figure 68 Show Figure 7 The area shown.

[0159] like Figures 66 to 68As shown, semiconductor 37 is formed on the surface of conductor 38A and the surface of conductor 46. Examples of the formation method include oxidation of the surface of conductor 38A and sputtering of a metal oxide. In one example, the formation of semiconductor 37 is continued until the entire portion of conductor 38A above insulator 41 becomes semiconductor 37. By forming semiconductor 37, a portion of conductor 38A becomes conductor 38.

[0160] like Figures 3 to 7 As shown, an insulator 32 is deposited on the surface of a semiconductor 37. Examples of the deposition method include CVD.

[0161] The conductor 26 is deposited in the hole HB. Examples of the deposition method include CVD. By depositing the conductor 26, the hole HB is filled with the conductor 26. Thus, the Figures 3 to 7 The structure shown.

[0162] 1.3. Advantages (Effects)

[0163] According to the first embodiment, semiconductor 22, which functions as the gate of transistor TrS, is insulated from semiconductor 24 by insulator 31 surrounding semiconductor 24, which functions as the gate of transistor TrC. Semiconductor 24 is insulated from conductor 26, which functions as the gate of transistor TrT, by insulator 31 and insulator 32 surrounding conductor 26. Furthermore, semiconductor 35, which functions as the floating gate of transistor TrC, is insulated from semiconductor 22 by insulator 36 and is in contact with semiconductor 37, which functions as the channel of transistor TrT. Furthermore, the pair of semiconductors 42 and 44 faces semiconductors 22 and 35, as well as semiconductor 37, via insulator 41. This structure enables the realization of a memory cell MC comprising a pair of transistors Trc and TrT forming a gain unit structure, and transistor TrS connected in series with the gain unit structure.

[0164] Furthermore, the memory cell MC is constructed by combining the deposition and removal of semiconductors, insulators, and conductors using the holes HS, HC, and HT as the center. This formation method facilitates the formation of multiple memory cells MC in multiple layers aligned in the direction of the holes HS, HC, and HT. This is because the deposition and removal of semiconductors, insulators, and conductors can be performed in parallel across multiple layers.

[0165] 1.4. Modifications

[0166] 1.4.1. First Modification

[0167] Can also replace the above reference Figure 43 and Figure 44 The process described below is referred to Figure 69 Describe the process. Figure 69A first modified example of the structure of the manufacturing process of the storage device of the first embodiment is shown. Figure 69 Show Figure 3 A portion of the area shown.

[0168] like Figure 69 As shown, the portion of the semiconductor 42B exposed in the space SP8 is removed more than that in the above reference Figure 43 and Figure 44 The removal in the above-described process continues for a longer period of time. As a result, the space SP8 reaches the side regions of the semiconductor 24 .

[0169] According to the shape of space SP82, as Figure 70 As shown above, Figure 45 and 46 The semiconductor 44 formed by the described process reaches the side of the semiconductor 24 .

[0170] 1.4.2. Second Modification

[0171] Figures 71 to 93 An example of the structure during a partial manufacturing process of a storage device according to a second modification of the first embodiment is shown.

[0172] Refer to above Figure 49 and Figure 50 The process described is continued below. Figures 71 to 75 Describe the process. Figure 71 Show Figure 3 A portion of the area shown. Figure 72 Show Figure 4 The area shown. Figure 73 Show Figure 5 The area shown. Figure 74 Show Figure 6 The area shown. Figure 75 Show Figure 7 The area shown.

[0173] like Figures 71 to 75 As shown, insulator 48A is removed. Examples of removal methods include wet etching. This removal forms a space SP13 in the layer where insulator 48A was located (i.e., the layer where memory cell MC is located). Semiconductors 42B and 44, as well as conductor 46, are exposed in space SP13.

[0174] By removing the insulator 48A, the hole HP is formed again, and the insulator 54 is exposed at the hole HP and the space SP13.

[0175] Figure 76 Show Figure 3 A portion of the area shown. Figure 77 Show Figure 4The area shown. Figure 78 Show Figure 5 The area shown. Figure 79 Show Figure 6 The area shown. Figure 80 Show Figure 7 The area shown.

[0176] like Figures 76 to 80 As shown, insulator 61A is deposited. In one example, insulator 61A comprises silicon oxide. Examples of deposition methods include CVD. Insulator 61A covers the surfaces of semiconductors 42B and 44, conductor 46, and insulator 54. Insulator 61A is very thin. Therefore, in one example, space SP13 is not filled with insulator 61A.

[0177] Figure 81 Show Figure 3 A portion of the area shown. Figure 82 Show Figure 4 The area shown. Figure 83 Show Figure 5 The area shown. Figure 84 Show Figure 6 The area shown. Figure 85 Show Figure 7 The area shown.

[0178] like Figures 81 to 85 As shown, a conductor 62A is deposited in the space SP13. In one example, the conductor 62A comprises titanium nitride. Examples of deposition methods include CVD. By deposition, the space SP13 is filled with the conductor 62A.

[0179] The conductor 62A formed in the hole HP during the formation of the conductor 62A is removed. Thus, the hole HP is formed again. The conductor 62A is exposed in the hole HP.

[0180] Figure 86 Show Figure 3 A portion of the area shown. Figure 87 Show Figure 4 The area shown.

[0181] like Figure 86 and Figure 84 As shown, the portion of conductor 62A exposed in hole HP is removed. Examples of removal methods include wet etching. This removal forms a space SP14 around hole HP in the layer where memory cell MC is located (the layer where insulator 48A was previously located). Space SP14 has a shape formed by combining the ring-shaped shapes surrounding hole HP. In space SP14, the portion of insulator 61A along the lower end of semiconductor 22 is exposed.

[0182] Figure 88 Show Figure 3 A portion of the area shown. Figure 89 Show Figure 4 The area shown.

[0183] like Figure 88 and Figure 89 As shown, the portion of insulator 61A exposed in space SP14 and hole HP is removed. Examples of the removal method include wet etching. By partially removing insulator 61A, insulator 61A becomes insulator 61. Semiconductor 42B is exposed in space SP14.

[0184] Figure 90 Show Figure 3 A portion of the area shown. Figure 91 Show Figure 4 The area shown.

[0185] like Figure 90 and Figure 91 As shown, the portion of semiconductor 42B exposed in space SP14 is removed. Examples of removal methods include wet etching. This removal expands the entire area below the portion of semiconductor 42B lateral to semiconductor 22, including portion SP141. Portion SP141 is located between insulator 41 and insulator 61. By partially removing semiconductor 42B, semiconductor 42B becomes semiconductor 42. Insulator 61 is exposed in space SP141.

[0186] Figure 92 Show Figure 3 A portion of the area shown. Figure 93 Show Figure 4 The area shown.

[0187] like Figure 92 and Figure 93 As shown, semiconductor 64 is deposited in hole HP and space SP14. In one example, semiconductor 64 comprises silicon. Semiconductor 64 is doped with impurities to provide conductivity. In one example, semiconductor 64 comprises p-type impurities. Examples of p-type impurities include boron. Examples of deposition methods include CVD.

[0188] Refer to above Figure 92 and Figure 93 The process described above is continued with reference to Figures 57 to 59 Describe the process.

[0189] According to the second modification, it is possible to suppress the influence of noise on each other between memory cells MC adjacent to each other along the xy plane.

[0190] 1.3. Other variations

[0191] Alternatively, transistors TrS and TrC may be n-type, and transistor TrT may be p-type. In this example, semiconductor 44 is doped with n-type impurities. Examples of n-type impurities include phosphorus. Furthermore, semiconductors 21, 22, and 24 may also be doped with n-type impurities instead of p-type impurities.

[0192] Alternatively, you can refer to Figures 36 to 38 The process described above deposits the sacrificial material SM7 while depositing the conductor 38A. In this case, the semiconductor 37 has the same shape as the SM7. The manufacturing process continues until the above reference Figures 66 to 68 Describe the process.

[0193] The hole HP may be filled with a metal instead of the semiconductor 21 .

[0194] The two semiconductors 35 on both sides of the semiconductor 24 may be connected on the upper side of the semiconductor 24. In this structure, the semiconductor 37 surrounding the conductor 26 may be connected on the lower side of the conductor 26 without having an opening.

[0195] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the scope equivalent to the invention described in the claims.

[0196] [Explanation of Reference Numerals]

[0197] 1: semiconductor memory device, 11: memory cell array, 12: input / output circuit, 13: control circuit, 14: voltage generation circuit, 15: row selection circuit, 16: column selection circuit, 17: write circuit, 18: read circuit, 19: sense amplifier, MC: memory cell, WL: word line, BL: bit line, TrS: transistor, TrC: transistor, TrT: transistor, CSL: source line, SG: wiring, CG: wiring, TG: wiring, US: unit structure, 21: semiconductor, 22: semiconductor, 24: semiconductor, 26: conductor, 28: insulator, 31: insulator, 32: insulator, 35: semiconductor, 36: insulator, 37: semiconductor, 38: conductor, 41: insulator, 42: semiconductor, 44: semiconductor, 46: conductor, 48: insulator.

Claims

1. A semiconductor memory device comprising: a first wiring extending along a first plane formed by a first axis and a second axis intersecting the first axis, wherein the first axis extends along a first direction; a second wiring extending along the first plane and arranged closer to the first direction than the first wiring; a third wiring extending along the first plane and arranged closer to the first direction than the second wiring; a first conductor extending along the first plane and disposed closer to the first direction than the second wiring; a first insulator surrounding the third wiring along the first plane and having a portion located between the third wiring and the second wiring; a first semiconductor sandwiching the first insulator together with the third wiring; a second insulator between the second wiring and the first semiconductor; a third insulator surrounding the first conductor along the first plane; a second conductor in contact with the first semiconductor; a second semiconductor, which sandwiches the third insulator together with the first conductor and is in contact with the second conductor; a fourth insulator distributed on the second wiring, the first semiconductor, and the second semiconductor along the first plane; a third semiconductor that is in contact with the first wiring and includes a portion sandwiching the fourth insulator together with the second wiring and a portion sandwiching the fourth insulator together with the first semiconductor; a fourth semiconductor, which is in contact with the third semiconductor and sandwiches the fourth insulator together with the second semiconductor; as well as A third conductor is in contact with the fourth semiconductor.

2. The semiconductor memory device according to claim 1, wherein The fourth insulator covers a portion of the second wiring that faces the first wiring.

3. The semiconductor memory device according to claim 1, wherein The first insulator covers a portion of the third wiring that faces the second wiring.

4. The semiconductor memory device according to claim 1, wherein The second insulator covers a portion of the second wiring facing the first semiconductor.

5. The semiconductor memory device according to claim 1, wherein The first insulator covers a portion of the third wiring that faces the first electrical conductor. The semiconductor memory device according to claim 1 , wherein: The third insulator covers a portion of the first conductor that faces the third wiring.

7. The semiconductor memory device according to claim 1, wherein The third insulator covers a portion of the first electrical conductor that faces the third electrical conductor.

8. The semiconductor memory device according to claim 1, wherein The second wiring includes a portion aligned with the third wiring along the first axis.

9. The semiconductor memory device according to claim 1, wherein The first wiring includes a portion aligned with the second wiring along the first axis.

10. The semiconductor memory device according to claim 1, wherein The second wiring, the third wiring, and the first conductor are bent along the first plane.

11. The semiconductor memory device according to claim 10, wherein The third semiconductor includes a portion bent along the second wiring, a portion bent along the third wiring, and a portion bent along the first conductor.

12. The semiconductor memory device according to claim 10, wherein The first semiconductor is bent along the third wiring.

13. The semiconductor memory device according to claim 10, wherein The second semiconductor includes a portion bent along the first conductor.

14. The semiconductor memory device according to claim 10, wherein The fourth semiconductor is bent along the first conductor.

15. The semiconductor memory device according to claim 1, wherein The device further includes a fifth insulator that surrounds the first wiring, the third semiconductor, the fourth semiconductor, and the third conductor along the first plane.

16. The semiconductor memory device according to claim 1, wherein A surface where the third semiconductor and the fourth semiconductor are in contact is arranged parallel to the first conductor along the first axis.

17. The semiconductor memory device according to claim 1, wherein A surface where the third semiconductor and the fourth semiconductor are in contact is arranged along the first axis and parallel to the third wiring.

18. The semiconductor memory device according to claim 1, wherein The device further includes a sixth insulator extending along the first plane and distributed in a region on the first wiring, a region on the third semiconductor, a region on the fourth semiconductor, and a region on the third conductor.

19. The semiconductor memory device according to claim 18, wherein A fourth conductor is further provided, which surrounds the sixth insulator along the first plane.

Images