Semiconductor device and manufacturing method thereof
By setting the doping region and conductive channels in the semiconductor device, the second deep trench structure is eliminated, and the problems of complex and high cost of isolation structure are solved, and the effects of area reduction and cost reduction are achieved.
Patent Information
- Application Number
- CN202510627160.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-08-19
AI Technical Summary
The isolation structure of the existing integrated embedded semiconductor devices is relatively complex in structure and process, has high production cost, and the isolation structure occupies a large area.
By setting doping regions in the inner and outer layers of the semiconductor body, a conductive channel is formed to connect the buried layer and the epitaxial layer, the production of the second deep trench structure is eliminated, and the first and second trench structures are adopted, which reduces the occupied area of the isolation structure and reduces the process cost.
While maintaining the high-voltage isolation characteristics, the area of the isolation structure is reduced, the process cost is reduced, and flexible application is achieved by controlling the conduction or cutoff of the conductive channel.
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Figure CN120512906A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] Existing integrated embedded semiconductor devices employ isolation structures to isolate different types of devices within a single chip or integrated circuit. Traditionally, a first deep trench structure (extending deep into the substrate layer) brings the substrate within the semiconductor body to the surface, while a second deep trench structure (extending deep into the buried layer) brings the buried layer within the semiconductor body to the surface. Applying a voltage forms an isolation region within the second deep trench structure. Simultaneously, an isolation trench structure is provided between the first and second deep trench structures to increase the breakdown voltage from the buried layer to the substrate.
[0003] In the above semiconductor device, the trenches in the first deep trench structure and the isolation trench structure can be formed simultaneously using the same mask, while the second deep trench structure needs to be formed in steps using another mask.
[0004] However, the isolation structure used in the above-mentioned semiconductor device is relatively complex in both structure and process, and has a high manufacturing cost. Moreover, although the area required for the isolation structure is reduced compared to traditional well isolation, the area cost is still relatively high in actual application.
[0005] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention
[0006] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the area occupied by the isolation structure and further reduce the process cost.
[0007] In order to achieve the above object, a specific embodiment of the present invention provides the following technical solutions:
[0008] A semiconductor device comprising:
[0009] A semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;
[0010] a first trench extending from the top surface of the epitaxial layer into the substrate, wherein a first trench structure is disposed in the first trench, the first trench structure comprising a first conductive material having a first doping type, and the first conductive material electrically connecting the substrate to the top surface of the epitaxial layer;
[0011] a second trench extending from the top surface of the epitaxial layer into the substrate, wherein a trench isolation structure is disposed in the second trench, the trench isolation structure comprising a second conductive material having a first doping type, the second conductive material being isolated from the semiconductor body;
[0012] a doped region formed in the epitaxial layer and located within a range enclosed by the second trench, the doped region being disposed close to a sidewall of the second trench and having a second doping type;
[0013] When a voltage is applied to the second conductive material in the second trench, a conductive channel is formed between the doped region and the buried layer along the sidewall of the second trench, and the conductive channel electrically connects the buried layer to the top surface of the epitaxial layer.
[0014] In one or more embodiments of the present invention, the doped region is electrically connected to the second conductive material in the second trench.
[0015] In one or more embodiments of the present invention, the doped region and the buried layer are separated by the epitaxial layer.
[0016] In one or more embodiments of the present invention, the doped region includes a well region and a heavily doped region located in the well region. The heavily doped region is formed on the surface of the well region, and the doping concentration of the heavily doped region is greater than the doping concentration of the well region.
[0017] In one or more embodiments of the present invention, the heavily doped region is electrically connected to the second conductive material in the second trench.
[0018] In one or more embodiments of the present invention, the first trench structure further includes a first dielectric layer, the first dielectric layer is formed at least on the sidewalls of the first trench, and the first conductive material is disposed on the first dielectric layer and electrically connected to the substrate.
[0019] In one or more embodiments of the present invention, the trench isolation structure further includes a second dielectric layer, which is formed on the bottom wall and side walls of the second trench, and the second conductive material is disposed in the second dielectric layer and isolated from the semiconductor body by the second dielectric layer.
[0020] In one or more embodiments of the present invention, both the first trench and the second trench are provided through the buried layer, and the depth of the second trench is smaller than the depth of the first trench.
[0021] A method for manufacturing a semiconductor device, comprising:
[0022] Providing a semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;
[0023] forming a first trench and a second trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer into the substrate, the second trench extending from the top surface of the epitaxial layer into the substrate and having a depth less than a depth of the first trench;
[0024] forming a first trench structure in the first trench and a trench isolation structure in the second trench, wherein the first trench structure comprises a first conductive material having a first doping type, the first conductive material electrically connecting the substrate to a top surface of the epitaxial layer, and the trench isolation structure comprises a second conductive material having the first doping type, the second conductive material being isolated from the semiconductor body;
[0025] A doped region with a second doping type is formed in the epitaxial layer, and the doped region is located within a range surrounded by the second trench and close to a sidewall of the second trench.
[0026] In one or more embodiments of the present invention, the doped region and the second conductive material in the second trench are electrically connected.
[0027] Compared with the prior art, the semiconductor device and its manufacturing method of the present invention, by setting a doped region in the epitaxial layer in the semiconductor body, make the doped region, buried layer, epitaxial layer and isolation trench structure constitute MOSFET. When voltage is applied to the second conductive material in the second trench, a conductive channel will be formed between the doped region and the buried layer along the side wall of the second trench, thereby electrically connecting the buried layer to the top surface of the epitaxial layer to realize the extraction of the buried layer. This setting reduces the occupied area of the isolation structure (including the first trench, the first trench structure, the second trench, and the trench isolation structure), and eliminates the production of the second deep trench structure in the prior art, thereby reducing the process cost.
[0028] The semiconductor device and its manufacturing method of the present invention can control the conduction or disconnection of the conductive channel between the doped region and the buried layer by changing the positive or negative voltage applied to the second conductive material in the second trench, thereby enabling the semiconductor device to be flexibly used in the required application scenario.
[0029] The semiconductor device and the manufacturing method thereof of the present invention can save the original manufacturing process step of the second deep trench structure while maintaining the high-voltage isolation characteristics of the existing semiconductor device, and has a very obvious cost advantage. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0031] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
[0032] Figure 2 is a process flow chart of a method for manufacturing a semiconductor device in one embodiment of the present invention;
[0033] Figure 3a-Figure 3i FIG. 1 is a structural diagram of steps of a method for manufacturing a semiconductor device in one embodiment of the present invention. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0035] As mentioned in the background technology, the isolation structure used in existing integrated embedded semiconductor devices is relatively complex in both structure and process, and has a high manufacturing cost. Compared with traditional well isolation, although the area required for the isolation structure is reduced, in actual application, the area cost is still relatively high.
[0036] Based on this, the present invention provides a semiconductor device and a manufacturing method thereof, wherein the doped region is arranged in the epitaxial layer in the semiconductor body, so that the doped region, the buried layer, the epitaxial layer and the isolation trench structure constitute a MOSFET. When a voltage is applied to the second conductive material in the second trench, a conductive channel will be formed between the doped region and the buried layer along the side wall of the second trench, thereby electrically connecting the buried layer to the top surface of the epitaxial layer to realize the lead-out of the buried layer. This arrangement reduces the occupied area of the isolation structure (including the first trench, the first trench structure, the second trench, and the trench isolation structure) while maintaining the high-voltage isolation characteristics in the existing semiconductor device, and eliminates the production of the second deep trench structure in the existing technology, thereby reducing the process cost.
[0037] The semiconductor device and the method for manufacturing the semiconductor device of the present invention are described in detail below with reference to the accompanying drawings.
[0038] like Figure 1 As shown, the present invention provides a semiconductor device including a semiconductor body 10 , a first trench 20 , a second trench 30 and a doped region 40 .
[0039] The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having the first doping type disposed on the buried layer 12. The second doping type is opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or a combination thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. The buried layer 12 may have a blanket structure having substantially the same horizontal extension as the substrate 11 and being laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure. The epitaxial layer 13 may be used to form different device regions.
[0040] Both the first trench 20 and the second trench 30 are formed in the semiconductor body 10, wherein the second trench 30 is located within the area enclosed by the first trench 20 and has a width smaller than that of the first trench 20. The first trench 20 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a relatively deep depth. The second trench 30 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a relatively shallow depth. Both the second trench 30 and the first trench 20 are disposed through the buried layer 12, and the depth of the second trench 30 is smaller than that of the first trench 20.
[0041] It is understood that the trench depth is proportional to the trench width, and the wider the trench width, the deeper the trench is in the semiconductor body 10. The first trench 20 and the second trench 30 can be formed in the same process.
[0042] A first trench structure is disposed in the first trench 20 . The first trench structure includes a first conductive material 21 having a first doping type, and the first conductive material 21 is configured to electrically connect the substrate 11 to the top surface of the epitaxial layer 13 .
[0043] like Figure 1As shown, the first trench structure includes a first dielectric layer 22 and a first conductive material 21 having a first doping type. The first dielectric layer 22 is formed on the sidewalls of the first trench 20 and on a portion of the bottom wall of the first trench 20. The first dielectric layer 22 may include an oxide layer; or the first dielectric layer 22 may include an oxide layer and a dielectric layer such as a TEOS mask layer, wherein the dielectric layer is located on the surface of the oxide layer. The first conductive material 21 fills the first trench 20, that is, extends from the top surface of the epitaxial layer 13 to the bottom of the first trench 20 and contacts the substrate 11. With this arrangement, the first conductive material 21 can serve as a pickup structure for the substrate 11 to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. In this embodiment, the first conductive material 21 is polysilicon.
[0044] A trench isolation structure is disposed in the second trench 30 . The trench isolation structure includes a second conductive material 31 having a first doping type. The second conductive material 31 is isolated from the semiconductor body 10 .
[0045] like Figure 1 As shown, the trench isolation structure includes a second dielectric layer 32 and a second conductive material 31 having a first doping type. The second dielectric layer 32 is formed on the sidewalls and bottom wall of the second trench 30. In this embodiment, the second dielectric layer 32 may also include an oxide layer; or, the second dielectric layer 32 may also include an oxide layer and a dielectric layer such as a TEOS mask layer, with the dielectric layer located on the surface of the oxide layer.
[0046] It can be understood that the formation of the oxide layer in the second dielectric layer 32 and the formation of the oxide layer in the first dielectric layer 22 can be completed in the same process, so that in essence the oxide layer 32a in the second dielectric layer 32 and the oxide layer 22a in the first dielectric layer 22 are formed of the same layer structure using the same material and process; similarly, the formation of the dielectric layer in the second dielectric layer 32 and the formation of the dielectric layer in the first dielectric layer 22 can be completed in the same process, and the dielectric layer in the second dielectric layer 32 and the dielectric layer in the first dielectric layer 22 are also formed of the same layer structure using the same material and process. In order to facilitate a clear description of the semiconductor device structure, the oxide layer and the dielectric layer located in the first trench 20 are labeled as follows in the present invention. Figure 1 22a and 22b are used to represent the oxide layer and the dielectric layer located in the second trench 30. Figure 1 In the figure, 32a and 32b are used to represent them respectively.
[0047] The second dielectric layer 32 in the second trench 30 can be formed simultaneously with the formation of the first dielectric layer 22 in the first trench 20. A second conductive material 31 fills the second trench 30 and is located within the second dielectric layer 32. The second conductive material 31 in the second trench 30 can be formed simultaneously with the formation of the first conductive material 21 in the first trench 20. The second conductive material 31 is isolated from the semiconductor body 10 by the second dielectric layer 32. In this embodiment, the second conductive material 31 is polysilicon.
[0048] The doped region 40 is formed in the epitaxial layer 13 and is located within the area enclosed by the second trench 30. In this embodiment, the doped region 40 is disposed near the sidewalls of the second trench 30 and is separated from the buried layer 12 by the epitaxial layer 13. The doped region 40 has the second doping type.
[0049] like Figure 1 As shown, the doping type of the doped region 40 is the same as the doping type of the buried layer 12, and both are opposite to the doping type of the epitaxial layer 13. One end of the trench isolation structure in the second trench 30 extends to the area where the doped region 40 is located, and the other end extends to the area where the buried layer 12 is located. The trench isolation structure includes a second conductive material 31 and a second dielectric layer 32 located between the second conductive material 31 and the doped region 40, the epitaxial layer 13, and the buried layer 12. Therefore, the second conductive material 31, the second dielectric layer 32, the doped region 40, the epitaxial layer 13, and the buried layer 12 together constitute a MOSFET (metal-oxide semiconductor field-effect transistor).
[0050] Therefore, when voltage is applied to the second conductive material 31 in the second trench 30, a conductive channel is formed between the doped region 40 and the buried layer 12 along the side wall of the second trench 30. The conductive channel is the inversion layer of the epitaxial layer 13, which can connect the doped region 40 and the buried layer 12, and electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.
[0051] It is understood that MOSFET includes N-channel MOSFET and P-channel MOSFET. In one embodiment, when the second conductive material 31 is P-type doped, the doped region 40 is N-type doped, the epitaxial layer 13 is P-type doped, and the buried layer 12 is N-type doped, the MOSFET in this embodiment is an N-channel MOSFET. Therefore, the second conductive material 31 acts as a gate, and a positive voltage is applied to the gate. When the gate voltage is higher than the threshold voltage (Vth), the N-channel MOSFET is in a forward conduction state. And as the positive voltage applied to the second conductive material 31 increases, the conductive channel can be widened, thereby improving the conduction performance between the doped region 40 and the buried layer 12 and reducing the loss in the process of transmitting the voltage applied to the doped region 40 to the buried layer 12. Of course, if a negative voltage is applied to the gate, the N-channel MOSFET is in a cut-off state. Therefore, by changing the positive and negative voltage applied to the second conductive material in the second trench, the conduction or cut-off of the conductive channel between the doped region 40 and the buried layer 12 can be controlled, so that the semiconductor device can be flexibly applied in the required application scenario.
[0052] In another embodiment, when the second conductive material 31 is N-type doped, the doped region 40 is P-type doped, the epitaxial layer 13 is N-type doped, and the buried layer 12 is P-type doped, the MOSFET in this embodiment is a P-channel MOSFET. Therefore, the second conductive material 31 acts as a gate, a negative voltage is applied to the gate, and when the gate voltage is less than the threshold voltage (Vth), the P-channel MOSFET is in a forward conduction state. And as the negative voltage applied to the second conductive material 31 increases, the conductive channel can be widened, thereby improving the conduction performance between the doped region 40 and the buried layer 12 and reducing the loss in the process of transmitting the voltage applied to the doped region 40 to the buried layer 12. Similarly, if a positive voltage is applied to the gate, the P-channel MOSFET is in a cut-off state. Therefore, by changing the positive and negative voltage applied to the second conductive material in the second trench, the conduction or cut-off of the conductive channel between the doped region 40 and the buried layer 12 can be controlled, so that the semiconductor device can be flexibly applied in the required application scenario.
[0053] Preferably, in one embodiment, the doped region 40 is electrically connected to the second conductive material 31 in the second trench 30. This configuration allows only one voltage to be applied to simultaneously widen the conductive channel and transmit the voltage to the buried layer 12 with minimal loss.
[0054] In order to reduce the contact resistance, in a preferred embodiment of the present invention, the doped region 40 may include a well region 41 and a heavily doped region 42 located in the well region 41. The heavily doped region 42 is formed on the surface of the well region 41, and the doping concentration of the heavily doped region 42 is greater than the doping concentration of the well region 41. The carrier concentration (electrons) of the heavily doped region 42 is much higher than that of the well region 41. The provision of the heavily doped region 42 can significantly reduce the contact resistance between the source / drain (Source / Drain) and the subsequent metal electrode, thereby improving device performance and avoiding voltage drop or heat generation problems caused by high-resistance contact. The well region 41 and the heavily doped region 42 can be formed together when forming device structures located in different device regions, such as NMOS or PMOS.
[0055] Preferably, the heavily doped region 42 in the doped region 40 is electrically connected to the second conductive material 31 in the second trench 30 .
[0056] The semiconductor device of the present invention, by setting a doped region in the epitaxial layer in the semiconductor body, makes the doped region, buried layer, epitaxial layer and isolation trench structure form a MOSFET. When voltage is applied to the second conductive material in the second trench, a conductive channel will be formed between the doped region and the buried layer along the side wall of the second trench, thereby electrically connecting the buried layer to the top surface of the epitaxial layer to achieve the extraction of the buried layer. This setting reduces the occupied area of the isolation structure (including the first trench, the first trench structure, the second trench, and the trench isolation structure) and reduces the process cost.
[0057] The semiconductor device of the present invention can control the conduction or disconnection of the conductive channel between the doped region and the buried layer by changing the positive or negative voltage applied to the second conductive material in the second trench, thereby enabling the semiconductor device to be flexibly applied in the required application scenario.
[0058] like Figure 2 As shown, the present invention also proposes a method for manufacturing a semiconductor device, comprising the following specific steps:
[0059] S1 , providing a semiconductor body, wherein the semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer.
[0060] S2 , forming a first trench and a second trench in the semiconductor body, wherein the first trench extends from the top surface of the epitaxial layer into the substrate, and the second trench extends from the top surface of the epitaxial layer into the substrate and has a depth less than that of the first trench.
[0061] S3, forming a first trench structure in the first trench and a trench isolation structure in the second trench, the first trench structure including a first conductive material having a first doping type, the first conductive material electrically connecting the substrate to the top surface of the epitaxial layer, the trench isolation structure including a second conductive material having the first doping type, the second conductive material being isolated from the semiconductor body.
[0062] S4, forming a doped region with a second doping type in the epitaxial layer, wherein the doped region is located within a range surrounded by the second trench and close to a sidewall of the second trench.
[0063] After step S4, the method may further include forming different device structures in the epitaxial layer of the semiconductor body, and / or electrically connecting the doped region and the second conductive material in the second trench.
[0064] Figures 3a to 3i The process of manufacturing a semiconductor device according to the method for manufacturing a semiconductor device of the present invention is shown. Figures 3a to 3i The process shown can be used to make Figure 1 The semiconductor device shown in the above Figure 1 The description of the semiconductor device may be incorporated herein.
[0065] like Figure 3a As shown, a semiconductor body 10 is provided. The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having the first doping type disposed on the buried layer 12. A device region is formed in the epitaxial layer 13. The second doping type is opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or a combination thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. The buried layer 12 may have a blanket structure, extending substantially the same horizontally as the substrate 11 and being laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure. The epitaxial layer 13 may be used to form different device regions.
[0066] A hard mask layer 15 is formed on the top surface of the epitaxial layer 13. Forming the hard mask layer 15 may include: growing or depositing a first oxide layer 151 on the top surface of the epitaxial layer 13, the first oxide layer 151 having a thickness of 100A to 200A; and depositing a first nitride layer 152 on the first oxide layer 151, the first nitride layer 152 having a thickness of 1000A to 3000A. Preferably, the first oxide layer 151 has a thickness of 200A and the first nitride layer 152 has a thickness of 1600A. It is understood that the first oxide layer 151 may be densified to achieve a better effect of the hard mask layer. In some embodiments, the substrate 11, the buried layer 12, and the epitaxial layer 13 are formed of silicon material, the first oxide layer 151 is formed of silicon dioxide, and the first nitride layer 152 is formed of silicon nitride.
[0067] like Figure 3b As shown, a first soft mask layer can be used to perform a single etching of the hard mask layer 15 and the semiconductor body 10 to simultaneously form a first trench 20 and a second trench 30 in the hard mask layer 15 and the semiconductor body 10, penetrating the first hard mask layer 15 and extending deep into the semiconductor body 10. The first trench 20 extends from the top surface of the epitaxial layer 13 into the substrate 11. The second trench 30 extends from the top surface of the epitaxial layer 13 into the substrate 11 but is less than the depth of the first trench 20 within the semiconductor body 10. The width of the second trench 30 is less than the width of the first trench 20. In some embodiments, the first soft mask layer can be a photoresist. After the first trench 20 and the second trench 30 are etched, the first soft mask layer is stripped.
[0068] like Figure 3c As shown, a second oxide layer 22a / 32a is grown on the sidewalls and bottom walls of the first trench 20 and the second trench 30. 。 The second oxide layer 22a and the second oxide layer 32a have the same layer structure. However, to facilitate a clear description of the semiconductor device structure above, the second oxide layer located in the first trench 20 is denoted by 22a, and the second oxide layer located in the second trench 30 is denoted by 32a. Exemplarily, the sidewalls and bottom walls of the first trench 20 and the second trench 30 are oxidized using a thermal oxidation process, and the thickness of the second oxide layer 22a / 32a is approximately 3000 Å to 5000 Å. Preferably, the thickness of the second oxide layer 22a / 32a is 4000 Å.
[0069] like Figure 3dAs shown, a first dielectric layer 22b / 32b is deposited in the first trench 20 and the second trench 30 so that the first dielectric layer 22b / 32b is formed on the sidewalls and bottom walls of the first trench 20 and the second trench 30. The first dielectric layer 22b and the first dielectric layer 32b are of the same layer structure, but for the convenience of a clear description of the semiconductor device structure above, the first dielectric layer located in the first trench 20 is indicated by the number 22b, and the first dielectric layer located in the second trench 30 is indicated by the number 32b. In this step, the first dielectric layer 22b / 32b is also deposited on the surface of the hard mask layer 15 at the same time. Exemplarily, a high aspect ratio process (HARP) can be used to perform chemical vapor deposition of the first dielectric layer 22b / 32b. The thickness of the first dielectric layer 22b / 32b on the sidewalls of the first trench 20 and the second trench 30 can be 5000A to 6000A. At this point, there is still 0.4 μm to 0.8 μm of space within the first trench 20, and the second trench 30 still has a top opening space of less than 0.3 μm, with an air gap formed therein to facilitate subsequent filling with conductive material. In one embodiment, the first dielectric layer 22 b / 32 b may be a TEOS mask layer. The first dielectric layer 22 b / 32 b and the second oxide layer 22 a / 32 a together form the first dielectric layer 22 and the second dielectric layer 32.
[0070] like Figure 3e As shown, the first dielectric layer 22b and the second oxide layer 22a in the first trench 20 are anisotropically etched to at least partially remove the first dielectric layer 22b and the second oxide layer 22a on the bottom wall of the first trench 20, thereby opening at least a portion of the bottom of the first trench 20. It will be appreciated that due to the narrow opening distance of the second trench 30, less etching plasma enters the second trench 30, which is insufficient to open the bottom of the second trench 30. In this process step, the etch-back process forms a V-shape at the top of the second trench 30, which is more effective for subsequent filling with conductive material. The first nitride layer 152 on the top can be used as an etch stop layer or protective layer, and its loss during etching may be less than 500A.
[0071] Optionally, after forming the first dielectric layer 22 b / 32 b , an annealing process may be performed to densify the first dielectric layer 22 b / 32 b and / or the second oxide layer 22 a / 32 a to achieve a better isolation effect.
[0072] Optionally, low energy boron implantation (eg, 5E15 / 5 KeV / 0 degree tilt) may be performed on the bottom of the first trench 20 to increase the doping level at the bottom of the first trench 20 , thereby providing a better connection to the substrate 11 .
[0073] like Figure 3fAs shown, the deposition of the first (second) conductive material 21 (31) having the first doping type is performed, so that the first (second) conductive material 21 (31) fills the first trench 20 and the second trench 30. It can be understood that since the first conductive material filled in the first trench and the second conductive material filled in the second trench are the same material and have the same doping type, the filling can be completed in the same step. The first conductive material 21 in the first trench 20 is in full contact with the substrate 11 and is electrically connected. The second conductive material 31 in the second trench 30 is electrically isolated from the semiconductor body 10 by the first dielectric layer 32b and the second oxide layer 32a.
[0074] Optionally, to better achieve electrical extraction of the substrate 11, a conductive material may be deposited in the first trench 20 in two steps. For example, after the first deposition of the conductive material, the conductive material may be dry-etched back to further widen the opening width at the top of the first trench 20 and the second trench 30, thereby achieving better filling of the conductive material and reducing the gaps in the first trench 20 and the second trench 30. The conductive material is preferably polysilicon.
[0075] like Figure 3g As shown, excess conductive material and a portion of first nitride layer 152 can be removed through a chemical mechanical polishing (CMP) process. First nitride layer 152 serves as a stop layer for the CMP process. The loss of first nitride layer 152 depends on the polishing selectivity rate, with normal loss being less than 500 Å. Because conductive material may also be deposited on substrate 11 of semiconductor body 10 during deposition, the conductive material on first nitride layer 152 is removed simultaneously with the removal of conductive material on substrate 11 of semiconductor body 10, resulting in improved wafer warpage and reduced stress.
[0076] like Figure 3h As shown, the conductive material is subjected to an anisotropic plasma dry etch process using the hard mask layer 15 as an etch protection layer. The etch back maintains the top surface of the conductive material at the same level as the top surface of the epitaxial layer 13. The anisotropic plasma dry etch ensures that no excess second conductive material 73 remains on the top surface of the first nitride layer 152. In some embodiments, the chemical mechanical polishing process can be omitted and the etch back process can be performed directly. The etch back process can more effectively remove excess conductive material.
[0077] like Figure 3iAs shown, the remaining first nitride layer 152 in the hard mask layer 15 on the surface of the epitaxial layer 13 is removed by a wet process using H3PO4. Then, the first oxide layer 151 in the hard mask layer 15 is removed by a wet process using diluted HF. The second oxide layer 22a, the first dielectric layer 22b, and the first conductive material 21 in the first trench 20 can form a first trench structure. Since the first conductive material 21 extends from the top surface of the epitaxial layer 13 to the bottom of the first trench 20 and contacts the substrate 11, the first conductive material 21 can serve as a pickup structure for the substrate 11 to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. The second oxide layer 32a, the first dielectric layer 32b, and the second conductive material 31 in the second trench 30 can form a trench isolation structure.
[0078] like Figure 1 As shown, the normal processes of the subsequent CMOS device are carried out within the range enclosed by the second trench 30 and the isolation trench structure: such as pad oxide, STI (shallow trench isolation structure), LOCOS, well implantation, gate, LDD implantation, spacer formation, source / drain implantation, silicide formation, ILD (interlayer dielectric layer), contact formation, BEoL metal layer and passivation, etc.
[0079] During the well implantation process, a well region 41 having the second doping type is formed in the epitaxial layer 13 within the area surrounded by the second trench 30 and close to the sidewall of the second trench 30 .
[0080] During the source / drain implantation process, a heavily doped region 42 is formed on the surface of the well region 41. The heavily doped region 42 has the same doping type as the well region 41 but a higher doping concentration than the well region 41. The heavily doped region 42 and the well region 41 together constitute a doped region 40, which together with the buried layer 12, the epitaxial layer 13, the second conductive material 31 in the second trench 30, and the second dielectric layer 32 constitute a MOSFET (metal-oxide semiconductor field-effect transistor).
[0081] During the contact formation process, the doped region 40 and the second conductive material 31 in the second trench 30 may be electrically connected.
[0082] Since the normal processes of the above-mentioned CMOS devices can be manufactured using existing processes, and the process is not the innovation of this application, it will not be elaborated in detail here.
[0083] The semiconductor device and the manufacturing method thereof of the present invention can save the original manufacturing process step of the second deep trench structure while maintaining the high-voltage isolation characteristics of the existing semiconductor device, and has a very obvious cost advantage.
[0084] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.
[0085] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
Claims
1. A semiconductor device, characterized in that: include: A semiconductor body (10) comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate (11), and an epitaxial layer (13) having a first doping type disposed on the buried layer (12); a first trench (20) extending from the top surface of the epitaxial layer (13) into the substrate (11), wherein a first trench structure is provided in the first trench (20), the first trench structure comprising a first conductive material (21) having a first doping type, the first conductive material (21) electrically connecting the substrate (11) to the top surface of the epitaxial layer (13); a second trench (30) extending from the top surface of the epitaxial layer (13) into the substrate (11), wherein a trench isolation structure is provided in the second trench (30), wherein the trench isolation structure comprises a second conductive material (31) having a first doping type, and wherein the second conductive material (31) is isolated from the semiconductor body (10); a doping region (40) formed in the epitaxial layer (13) and located within a range surrounded by the second trench (30), the doping region (40) being arranged close to a sidewall of the second trench (30), and the doping region (40) having a second doping type; When a voltage is applied to the second conductive material (31) in the second trench (30), a conductive channel is formed between the doped region (40) and the buried layer (12) along the sidewall of the second trench (30), and the conductive channel electrically connects the buried layer (12) to the top surface of the epitaxial layer (13).
2. The semiconductor device according to claim 1, wherein The doped region (40) is electrically connected to the second conductive material (31) in the second trench (30).
3. The semiconductor device according to claim 1, wherein The doped region (40) and the buried layer (12) are separated by the epitaxial layer (13).
4. The semiconductor device according to claim 1, wherein The doping region (40) comprises a well region (41) and a heavily doped region (42) located within the well region (41); the heavily doped region (42) is formed on a surface layer of the well region (41); and the doping concentration of the heavily doped region (42) is greater than the doping concentration of the well region (41).
5. The semiconductor device according to claim 4, wherein The heavily doped region (42) is electrically connected to the second conductive material (31) in the second trench (30). The semiconductor device according to claim 1 , wherein: The first trench (20) structure further includes a first dielectric layer (22), wherein the first dielectric layer (22) is formed at least on the sidewall of the first trench (20), and the first conductive material (21) is disposed on the first dielectric layer (22) and electrically connected to the substrate (11).
7. The semiconductor device according to claim 1, wherein The trench isolation structure further includes a second dielectric layer (32), the second dielectric layer (32) being formed on the bottom wall and side walls of the second trench (30), and the second conductive material (31) being arranged in the second dielectric layer (32) and isolated from the semiconductor body (10) by the second dielectric layer (32).
8. The semiconductor device according to claim 1, wherein The first trench (20) and the second trench (30) are both arranged through the buried layer (12), and the depth of the second trench (30) is smaller than the depth of the first trench (20).
9. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body (10) is provided, wherein the semiconductor body (10) comprises a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate (11), and an epitaxial layer (13) having a first doping type disposed on the buried layer (12); forming a first trench (20) and a second trench (30) in the semiconductor body (10), wherein the first trench (20) extends from the top surface of the epitaxial layer (13) into the substrate (11), and the second trench (30) extends from the top surface of the epitaxial layer (13) into the substrate (11) and has a depth less than that of the first trench (20); forming a first trench structure in the first trench (20) and forming a trench isolation structure in the second trench (30), wherein the first trench structure comprises a first conductive material (21) having a first doping type, the first conductive material (21) electrically connecting the substrate (11) to the top surface of the epitaxial layer (13), and the trench isolation structure comprises a second conductive material (31) having the first doping type, the second conductive material (31) being isolated from the semiconductor body (10); A doping region (40) having a second doping type is formed in the epitaxial layer (13), and the doping region (40) is located within a range enclosed by the second trench (30) and close to a sidewall of the second trench (30).
10. The method for manufacturing a semiconductor device according to claim 9, wherein: The doped region (40) and the second conductive material (31) in the second trench (30) are electrically connected.