Reconfigurable transistor based on two-dimensional heterojunction, preparation method and application of reconfigurable transistor in photoelectric logic operation

Abstract

The invention discloses a reconfigurable transistor based on a two-dimensional heterojunction, a preparation method and application of the reconfigurable transistor in photoelectric logic operation. The reconfigurable transistor based on the two-dimensional heterojunction comprises a substrate, a MoS2 sheet, a TiS3 sheet, a source electrode and a drain electrode, the TiS3 sheet is located on the MoS2 sheet and partially stacked, the other end of the TiS3 sheet is connected with the source electrode, the other end of the MoS2 sheet is connected with the drain electrode, and the reconfigurable transistor based on the two-dimensional heterojunction is prepared by adopting a PC film transfer method. The reconfigurable transistor has optical gating and electric gating characteristics at the same time, different logic outputs can be obtained by adjusting grid voltage and optical power density serving as logic input, logic switching voltage can be changed at the same time, and therefore various logic gate circuits can be dynamically reconfigured under the same device.

Description

Technical Field

[0001] The present invention belongs to the field of photoelectric gate control logic devices and relates to a reconfigurable transistor based on a two-dimensional heterojunction, a preparation method and an application thereof in photoelectric logic operations. Background Art

[0002] Logic gates are the foundation of modern digital computers, enabling operations such as AND, OR, and NOT. Simple logic gates are composed of transistors. These transistors are combined to produce a high or low signal after passing through them, representing two signals with high and low levels. These high and low levels can represent logical "true" and "false," or binary 1 and 0, respectively, thus performing logical operations.

[0003] Optoelectronic logic gates convert optical signals into electrical outputs and can perform a range of operations, including AND, OR, NAND, NOR, XOR, and XNOR. Early research on optoelectronic logic gates used device architectures such as PN, PIN, and avalanche photodiodes, combining silicon nanowires, compound semiconductors, and metal oxide materials. However, these devices are based on unidirectional photocarrier transport and are only suitable for single logic operations in a single device. Multiple logic operations can only be achieved by combining circuit layouts of multiple optoelectronic devices. Current research in related fields has evolved from 1D-1L operations to MD-ML systems, and the research objects are also focused on carbon allotropes, organic matter, two-dimensional materials, and perovskites. The main reason is that these materials can be easily and quickly designed into heterojunctions, which promotes the generation and transport of photocarriers.

[0004] The appeal of optoelectronic logic gates lies in their potential to surpass traditional silicon-based logic devices, which may be limited by their electronic properties and materials. Optoelectronic logic gates offer significant advantages in integrating light for information transmission, making them well-suited for applications in next-generation optical computing, high-performance computing, and real-time data-intensive tasks.

[0005] Reconfigurable logic systems, such as field-programmable gate arrays, allow the internal interconnections of basic logic blocks to be reversibly reprogrammed and their operation to be actively modified even after fabrication. In semiconductor design, these systems suffer from limitations such as low power consumption and low device density. However, optically based logic operating systems, such as optoelectronic logic gates, can address the limitations of static optoelectronic logic gates, such as low chip density and limited versatility. Consequently, they are being evaluated as third-generation optoelectronic logic gate drive systems. Reconfigurable optoelectronic logic gate systems lack fixed logic operations based on device structure and circuit layout, and can actively switch logic operations using additional stimuli such as electric fields and light.

[0006] For pure electric gating, a field-effect transistor based on MoS2 has realized a CMOS NOT gate operating at 550°C through graphene electrodes and h-BN packaging. Its electrically controlled logic function directly regulates carrier transport through voltage signals, demonstrating high-temperature stability and flexibility (Zou Y, Li P, Su C, et al. Flexible high-temperature MoS2 field-effect transistors and logic gates [J]. ACS nano, 2024, 18 (13): 9627-9635.). However, defects at the metal-MoS2 interface may lead to problems such as unstable contact resistance, and the doping process is also relatively complex. For pure optical gating, the high light absorption coefficient and tunable band gap of two-dimensional MoS2 make it suitable for light-controlled logic gates, which can achieve switching functions by photoexciting carriers. However, a high-power light source is required to maintain a stable logic state, which consumes a lot of power. At the same time, the optical path and electrical signal need to be designed separately, which increases the system complexity. Summary of the Invention

[0007] The present invention aims to provide a reconfigurable transistor based on a two-dimensional heterojunction, a method for its preparation, and its application in optoelectronic logic operations. The reconfigurable transistor of the present invention has both optical and electrical gating characteristics. The combination of optical and electrical signals can implement a new logical operation, capable of performing both AND and OR logic operations.

[0008] The technical solutions for achieving the purpose of the present invention are as follows:

[0009] A reconfigurable transistor based on a two-dimensional heterojunction includes: a substrate, a MoS2 thin sheet, a TiS3 thin sheet, a source electrode, and a drain electrode; wherein the TiS3 thin sheet is located on the MoS2 thin sheet and partially stacked, the other end of the TiS3 thin sheet is connected to the source electrode, and the other end of the MoS2 thin sheet is connected to the drain electrode.

[0010] The substrate described in the present invention is a substrate material commonly used in the art, such as Si / SiO2, quartz glass, sapphire, mica, etc.

[0011] Preferably, the thickness of the TiS3 flakes is 1 nm to 200 nm.

[0012] Preferably, the thickness of the MoS2 flakes is 1 nm to 200 nm.

[0013] Preferably, the source electrode and the drain electrode are one or a combination of Cr, Ti, Ni, Au, Pd, Pt or Ag, and have a thickness of 5 nm to 100 nm.

[0014] The method for preparing the above-mentioned reconfigurable transistor based on the two-dimensional heterojunction comprises the following steps:

[0015] Step 1: obtain TiS3 flakes and MoS2 flakes of desired thickness by mechanical exfoliation;

[0016] Step 2: Design and deposit source and drain electrodes on both sides of the substrate;

[0017] Step 3: First, find the TiS3 flake to be transferred under a microscope and align the polycarbonate (PC) film on top of it. Then, slowly lower the PC film so that it contacts the target material. Gradually raise the temperature to 120±5°C, maintain it for 3±1 minutes, and then slowly cool it down. When the temperature reaches below 80°C, lift the PC film. At this time, the TiS3 flake has been picked up on the PC film. Repeat this process to pick up the MoS2 flake to form a TiS3-MoS2 heterostructure.

[0018] In step 4, the TiS3-MoS2 heterostructure is released onto the source electrode and the drain electrode, so that the other end of TiS3 is connected to the source electrode and the other end of MoS2 is connected to the drain electrode. The PC film and the electrodes are attached and heated to 180°C and then lifted up. Finally, the substrate with the residual PC film is placed in chloroform for cleaning to obtain a reconfigurable transistor based on a two-dimensional heterojunction.

[0019] Preferably, in step 2, the electrode pattern is defined by using photolithography technology, electron beam exposure technology or laser direct writing technology, and the source and drain electrodes are prepared by combining electron beam evaporation and lift-off process.

[0020] The above-mentioned application of reconfigurable transistors based on two-dimensional heterojunction in photoelectric logic operations.

[0021] Furthermore, the specific method of the above application is: by applying low light power density, high light power density, gate voltage (V gs ) as the logic input terminal, the output current (I out ) as the logic output terminal, bias voltage (V ds ) as the logic switching voltage to implement the logical operations of AND gate and OR gate; where the logic input is defined as follows:

[0022] For optical power density, low optical power density is defined as the "0" state and high optical power density is defined as the "1" state, where low optical power density is 3.75mW / cm 2 , high optical power density of 43mW / cm 2 ;

[0023] When V gs =-30V is defined as "0" state, when V gs = +30V is defined as "1" state;

[0024] According to the negative and positive photocurrent output, when I out >0 is defined as "0" state, when I out <0 is defined as "1" state;

[0025] When the logic switching voltage V ds =0V corresponds to the "OR" gate, V ds =-50mV corresponds to the "AND" gate.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] The present invention uses a transistor composed of a TiS3-MoS2 heterostructure as a core component (TiS3 thin slices and MoS2 thin slices are obtained by mechanical peeling), and changes the gate voltage (V gs ) and applying different powers of light (high and low), two logical operations, AND and OR, can be performed in one device. The combination of optical signals and electrical signals can realize a new logical operation. In optoelectronic logic gates, there are significant advantages in integrating and using light for information transmission, which makes them very suitable for applications in next-generation optical computing, high-performance computing and real-time data-intensive tasks. Programmed inputs can switch optoelectronic gates between "OR" and "AND" operations in a single device, a feature often called reconfigurable logic gates. Reconfigurable logic gates are very valuable in programmable logic circuits, such as field programmable gate arrays (FPGAs), programmed array logic (PALs) and complex programmable logic devices (CPLDs). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the device; wherein (a) is a structural schematic diagram of the transistor, and (b) is an optical micrograph of the TiS3-MoS2 transistor prepared in Example.

[0029] Figure 2 These are the Raman spectra and PL spectra of MoS2, TiS3-MoS2, and TiS3 prepared in the examples; (a) is the Raman test results of TiS3, MoS2, and TiS3-MoS2, and (b) is the photoluminescence test results of MoS2 and TiS3-MoS2.

[0030] Figure 3 To apply V gs =0V, IV characteristic curves of the device when it changes from 1V to 1V (the optical power density is 1.63mW / cm 2 , 7.37mW / cm 2 、29.37mW / cm 2 , 52.72mW / cm 2、66.1mW / cm 2 、85.6mW / cm 2 、107mW / cm 2 ); (a) is the IV characteristic curve, (b) is the V ds =IT curve of the device at 0V.

[0031] Figure 4 The device is adjusted by changing the gate voltage; (a) is the IV characteristic curve under different gate voltages, and (b) is the IT curve of the device under different gate voltages.

[0032] Figure 5 It is a logic circuit symbol drawn through a truth table, including an AND gate and an OR gate. DETAILED DESCRIPTION

[0033] The present invention will be further described below in conjunction with specific embodiments and accompanying drawings.

[0034] Figure 1 It is a schematic diagram of the reconfigurable transistor based on two-dimensional heterojunction of the present invention; wherein (a) is a structural schematic diagram, which is a transistor based on TiS3-MoS2 heterojunction, including: a substrate, a MoS2 thin sheet, a TiS3 thin sheet, a source electrode, and a drain electrode; (b) is an optical micrograph of the TiS3-MoS2 transistor prepared in the embodiment, wherein the TiS3 thin sheet is located on the MoS2 thin sheet and partially stacked, the other end of the TiS3 is connected to the source electrode, and the other end of the MoS2 is connected to the drain electrode.

[0035] Example

[0036] 1. Preparation of a reconfigurable transistor based on a two-dimensional heterojunction, namely a TiS3-MoS2 heterojunction transistor, with the following specific steps:

[0037] Step 1, preparation of clean silicon wafer: select a 285nm thick Si / SiO2 wafer as the substrate, use acetone, ethanol, and deionized water to ultrasonicate for 10 minutes respectively, and then blow dry with a nitrogen gun for later use.

[0038] Step 2, preparation and transfer of TiS3 thin sheets: Place the TiS3 single crystal on the prepared scotch tape and stick it repeatedly 5 to 6 times. Use the adhesion of the tape to mechanically peel off a 30nm thick TiS3 thin sheet, then transfer it using a blue film. Finally, transfer the prepared TiS3 thin sheet to the Si / SiO2 substrate.

[0039] Step 3, Preparation and Transfer of MoS2 Flakes: Use blue tape to repeatedly dissociate bulk MoS2 until the MoS2 on the blue tape exhibits a blue or light green color. Press the MoS2 region on the blue tape onto a substrate. Heat the MoS2-attached substrate on a 120°C hotplate for 3 minutes and cool for 8 minutes. Then, remove the blue tape to obtain a MoS2-containing substrate.

[0040] Step 4, preparation of TiS3-MoS2 van der Waals heterojunction:

[0041] (1) Observe under a microscope and move the selected TiS3 thin film to the center of the field of view. Slowly lower the PC film so that it contacts the target material. Gradually heat it to 120℃, maintain it for 3 minutes, and then slowly cool it down. When the temperature reaches below 80℃, lift the PC film. At this time, you can see that the TiS3 thin film has been picked up on the PC film.

[0042] (2) Place the PC film with TiS3 flakes on a microscope-assisted three-dimensional displacement platform. Under microscope observation, move the selected MoS2 flakes to the center of the field of view, align them with the TiS3 flakes on the PC film to be transferred, and use the three-dimensional displacement platform to gradually move the TiS3 flakes on the PC film closer to the MoS2 flakes.

[0043] (3) Heat the substrate to 120°C and wait for 3 minutes to allow the TiS3 flakes to come into close contact with the MoS2 flakes. Lift the glass slide to separate the MoS2 from the substrate and stack them to form a TiS3-MoS2 van der Waals heterojunction.

[0044] Step 5, preparation of source and drain electrodes: Spin-coat the clean silicon wafer with photoresist using a spin coater and heat it at 100°C for 5 minutes; Use a photolithography machine for precise exposure and then development; Deposit 50nm of Au using electron beam evaporation technology; Then, clean it in acetone to remove the photoresist, and then blow it dry with a nitrogen gun to obtain clean source and drain electrodes.

[0045] Step 6, Preparation of Heterojunction Transistor: The TiS3-MoS2 heterostructure is released onto the source and drain electrodes, and the PC film and electrodes are bonded and heated to 180°C. The substrate with the residual PC film is then washed in chloroform to remove the remaining PC film, resulting in a TiS3-MoS2 heterojunction transistor.

[0046] 2. Device performance test

[0047] Figure 2These are the Raman and PL spectra of MoS2, TiS3-MoS2, and TiS3 prepared in the examples; among them, (a) is the Raman test results of TiS3, MoS2, and TiS3-MoS2, and it can be seen that the characteristic peaks of the two materials coexist in the TiS3-MoS2 heterostructure; (b) is the photoluminescence test results of MoS2 and TiS3-MoS2, and it can be seen that the luminescence peak of the TiS3-MoS2 heterostructure is blue-shifted relative to the single material MoS2.

[0048] Figure 3 To apply V gs =0V, curve obtained by adjusting the optical power density; Figure 3 (a) is the IV characteristic curve of the device when the optical power density changes from -1V to 1V (1.63mW / cm 2 , 7.37mW / cm 2 、29.37mW / cm 2 , 52.72mW / cm 2 、66.1mW / cm 2 、85.6mW / cm 2 、107mW / cm 2 ), it can be seen that due to the photovoltaic effect, with the increase of light power density (up to 52.72mW / cm 2 ), the current and voltage increase accordingly, and at higher optical power density (>52.72mW / cm 2 ), current and voltage are 66.1mW / cm 2 It starts to decrease at the light power density of , so it can be seen that the device has positive and negative photovoltaic photoelectric adjustable, Figure 3 (b) is the value of V ds =IT curve of the device when 0V.

[0049] Figure 4 To adjust device performance by changing the gate voltage; Figure 4 (a) is the IV curve of the device under pure electrical control, Figure 4 (b) is the IT curve of the device.

[0050] By adjusting the logic input: V gs and optical power density, and obtain different logic output I out , while changing the logic switching voltage V ds The logical truth table is obtained, see Table 1.

[0051] Table 1 Logical truth table

[0052]

[0053] Define low optical power density as "0" state and high optical power density as "1" state. In this experiment, the low optical power density is 3.75mW / cm 2 , high optical power density of 43mW / cm 2 ;

[0054] When V gs =-30V is defined as "0" state, when V gs = +30V is defined as "1" state;

[0055] Taking into account the negative and positive photocurrent output, when I out >0 is defined as "0" state, when I out When <0, it is defined as "1" state.

[0056] Figure 5 It is a logic circuit symbol drawn by the logic truth table. Logic switching voltage V ds =0V corresponds to the "OR" gate, V ds = -50mV corresponds to an "AND" gate. A programming input can switch the photogate between "OR" and "AND" operation in a single device.

[0057] The above-described embodiment merely represents one embodiment of the present invention. While the description is relatively specific and detailed, it should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present invention, and these modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A reconfigurable transistor based on a two-dimensional heterojunction, characterized in that: include: A substrate, a MoS2 thin sheet, a TiS3 thin sheet, a source electrode, and a drain electrode; wherein the TiS3 thin sheet is located on the MoS2 thin sheet and partially stacked, the other end of the TiS3 thin sheet is connected to the source electrode, and the other end of the MoS2 thin sheet is connected to the drain electrode.

2. The reconfigurable transistor according to claim 1, wherein: The substrate is Si / SiO2, quartz glass, sapphire or mica.

3. The reconfigurable transistor according to claim 1, wherein The thickness of TiS3 flakes is 1 nm~200 nm.

4. The reconfigurable transistor according to claim 1, wherein The thickness of the MoS2 flakes is 1 nm to 200 nm.

5. The reconfigurable transistor according to claim 1, wherein The source electrode is one or more of Cr, Ti, Ni, Au, Pd, Pt or Ag; the drain electrode is one or more of Cr, Ti, Ni, Au, Pd, Pt or Ag; the thickness of the source electrode or drain electrode is 5 nm~100 nm.

6. The method for preparing a reconfigurable transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step 1: obtain TiS3 flakes and MoS2 flakes of desired thickness by mechanical exfoliation; Step 2: Design and deposit source and drain electrodes on both sides of the substrate; Step 3: First, find the TiS3 thin sheet to be transferred under a microscope and align the PC film on top of it. Then, slowly lower the PC film so that it contacts the target material and gradually heat it to 120±5°C. After maintaining it for 3±1 minutes, slowly cool it down. When the temperature reaches below 80°C, lift the PC film. At this point, the TiS3 thin sheet has been picked up on the PC film. Repeat this process to pick up the MoS2 thin sheet to form a TiS3-MoS2 heterostructure. In step 4, the TiS3-MoS2 heterostructure is released onto the source electrode and the drain electrode, so that the other end of the TiS3 is connected to the source electrode and the other end of the MoS2 is connected to the drain electrode. The PC film and the electrodes are attached and heated to 180°C and then lifted up. Finally, the substrate with the residual PC film is placed in chloroform for cleaning to obtain a reconfigurable transistor based on a two-dimensional heterojunction.

7. The preparation method according to claim 6, characterized in that In step 2, the electrode pattern is defined by using photolithography technology, electron beam exposure technology or laser direct writing technology, and the source and drain electrodes are prepared by combining electron beam evaporation and lift-off process.

8. Application of the reconfigurable transistor according to claim 1 in photoelectric logic operations.

9. The use according to claim 8, characterized in that The specific method is: by applying low light power density, high light power density, V gs As a logic input, I out As a logic output, V ds As a logic switching voltage, it implements the logic operations of AND gate and OR gate. The logic input is defined as follows: For optical power density, low optical power density is defined as "0" state and high optical power density is defined as "1" state, where low optical power density is 3.75 mW / cm 2 , high optical power density of 43 mW / cm 2 ; When V gs =-30 V is defined as "0" state, when V gs = +30 V is defined as "1" state; According to the negative and positive photocurrent output, when I out >0 is defined as "0" state, when I out <0 is defined as "1" state; When the logic switching voltage V ds =0 V corresponds to an "OR" gate, V ds = -50 mV corresponds to an "AND" gate.

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