A data storage, reading method and data storage, reading circuit

Abstract

The application discloses a data storage and reading method and circuit, and relates to the technical field of data storage. The data storage method comprises the following steps: acquiring a storage address and original data corresponding to the storage address; determining a first parity check code and a third check code of the storage address; determining storage data according to the storage address, the original data, the first parity check code and the third check code; and saving the storage data to a storage unit corresponding to the storage address. Through the data storage and reading method and circuit, it can be determined that the data error source is the storage address or the storage data, the one-correcting and two-checking function of the saved original data can be realized, and the additional storage space can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, in particular to a data storage and reading method and circuit. BACKGROUND

[0002] In order to accurately save and read data, the characteristics of error correction code are needed to record data, so as to verify the correctness of the data when saving and reading the data. Independent error detection algorithms can generate corresponding error correction codes for data and addresses respectively, so as to guarantee the correctness of the data and the data storage address. Generally, the error correction codes generated based on the data and the data storage address are saved in the storage space, which occupies a large amount of storage space, and the logic circuit for processing the corresponding error correction codes has a large overhead and a long calculation timing path, which is not suitable for high-speed operation scenarios. Therefore, there is an urgent need for a data storage and reading method and circuit to solve the above problems. SUMMARY

[0003] In order to solve the problem of excessive storage space occupied by error correction codes and unsuitability for high-speed scenarios, the present application provides the following technical solutions:

[0004] In a first aspect, a data storage method is provided, comprising:

[0005] obtaining a storage address and original data corresponding to the storage address;

[0006] determining a first parity check code and a third check code of the storage address;

[0007] determining storage data according to the storage address, the original data, the first parity check code and the third check code;

[0008] saving the storage data to a storage unit corresponding to the storage address.

[0009] Further, determining the storage data according to the storage address, the original data, the first parity check code and the third check code comprises:

[0010] determining a first check code corresponding to the storage address using an independent error detection algorithm;

[0011] determining a second check code corresponding to the original data using an independent error detection algorithm;

[0012] performing an exclusive OR operation on the first check code and the second check code to obtain the third check code;

[0013] determining the storage data according to the original data, the first parity check code and the third check code.

[0014] Further, the storage data is determined according to the original data, the first parity check code and the third check code, and the method comprises:

[0015] The original data, the first parity check code and the third check code are spliced to obtain the storage data.

[0016] In a second aspect, a data reading method is provided, which is applied to reading the storage data saved by the data storage method according to the first aspect, and the method comprises:

[0017] An address is obtained, and the storage data saved at the address is read;

[0018] The storage data is split to obtain at least the to-be-checked data;

[0019] The to-be-checked data is checked according to the storage address and the storage data;

[0020] If the to-be-checked data passes the check, the to-be-checked data is taken as the original data.

[0021] Further, the storage data is split to obtain the third check code, and the to-be-checked data is checked according to the storage address and the storage data, and the method comprises:

[0022] An address check code is calculated based on the storage address by using an independent error detection algorithm;

[0023] The address check code is XORed with the third check code to obtain a data check code;

[0024] The data check code is decoded by using the independent error detection algorithm to obtain decoded data;

[0025] The decoded data is compared with the to-be-checked data;

[0026] If the decoded data matches the to-be-checked data, it is determined that the to-be-checked data passes the check;

[0027] Further, the to-be-checked data is checked according to the storage address and the storage data, and the method further comprises:

[0028] If the decoded data does not match the to-be-checked data, an error check is performed on the to-be-checked data by using the independent error detection algorithm;

[0029] If the error check result of the to-be-checked data is a single-bit error, an error bit of the to-be-checked data is corrected, and the to-be-checked data after the error bit correction is taken as the original data;

[0030] If the error check result of the to-be-checked data is a multi-bit error, an unrecoverable alarm is sent out;

[0031] set the storage data read according to the storage address to a preset security value.

[0032] Further, the split storage data also obtains a first parity check code, and the method further comprises:

[0033] calculating a second parity check code corresponding to the storage address;

[0034] comparing the first parity check code and the second parity check code;

[0035] in response to the first parity check code and the second parity check code not matching, determining that the storage address is incorrect.

[0036] issuing an unrecoverable alarm;

[0037] set the storage data read according to the storage address to a preset security value.

[0038] In a third aspect, a data storage circuit is provided for implementing the data storage method of the first aspect, and the data storage circuit comprises a data processing module, an address processing module, a first XOR operation module, a splicing module, and a storage module.

[0039] The storage module comprises at least one storage unit;

[0040] The data processing module is connected to the first XOR operation module, the address processing module is connected to the first XOR operation module, the splicing module, and the storage module, and the splicing module is connected to the storage module.

[0041] The data processing module is configured to obtain original data, determine a second check code corresponding to the original data by using an independent error detection algorithm, and transmit the second check code to the first XOR operation module.

[0042] The address processing module is configured to obtain a storage address, determine a storage unit, determine a first parity check code corresponding to the storage address, transmit the first parity check code to the splicing module, determine a first check code corresponding to the storage address by using an independent error detection algorithm, and transmit the first check code to the first XOR operation module.

[0043] The first XOR operation module is configured to obtain the first check code and the second check code, perform XOR operation on the first check code and the second check code to obtain a third check code, and transmit the third check code to the splicing module.

[0044] The splicing module is configured to obtain the original data, the first parity check code, and the third check code, determine storage data according to the original data, the first parity check code, and the third check code, and save the storage data to the storage unit corresponding to the storage address.

[0045] Further, the address processing module comprises a first encoding circuit, a parity encoding circuit and an address decoding circuit.

[0046] The input end of the first encoding circuit is configured to receive the storage address, and the output end of the first encoding circuit is configured to transmit the first check code to the first XOR operation module.

[0047] The input end of the parity encoding circuit is configured to receive the storage address, and the output end of the parity encoding circuit is configured to transmit the first parity check code to the splicing module.

[0048] The input end of the address decoding circuit is configured to receive the storage address, and the output end of the address decoding circuit is configured to determine the corresponding storage unit according to the storage address.

[0049] Further, the data processing module comprises a second encoding circuit.

[0050] The input end of the second encoding circuit is configured to receive the original data, and the output end of the second encoding circuit is configured to transmit the second check code to the first XOR operation module.

[0051] In a fourth aspect, a data reading circuit is provided for implementing the data reading method according to the second aspect, comprising:

[0052] a storage module, a bit selection circuit, a parity check circuit, a third encoding circuit, a second XOR operation module, a decoding circuit and an error processing unit;

[0053] The storage module is connected with the bit selection circuit, the parity check circuit and the third encoding circuit, the bit selection circuit is connected with the parity check circuit, the second XOR operation module and the decoding circuit, the parity check circuit is connected with the error processing unit, the third encoding circuit is connected with the second XOR operation module, the second XOR operation module is connected with the decoding circuit, and the decoding circuit is connected with the error processing unit.

[0054] The storage module is configured to obtain an input storage address and send a reading address to the bit selection circuit.

[0055] The bit selection circuit is configured to obtain the reading address, read storage data saved at the reading address, and split the storage data to obtain check data, a third check code and a first parity check code.

[0056] The parity check circuit is configured to calculate a second parity check code based on the storage address by using an independent error detection algorithm.

[0057] The third encoding circuit is configured to calculate an address check code based on the storage address by using an independent error detection algorithm.

[0058] The second exclusive OR operation module is configured to perform exclusive OR operation between the address check code and the third check code to obtain a data check code.

[0059] The decoding circuit is configured to decode the data check code to obtain decoded data by using an independent error detection algorithm.

[0060] The error processing unit is configured to issue an unrecoverable alarm according to the error type, and set the storage data read according to the storage address to a preset safety value.

[0061] By using the data storage and reading method and the data storage and reading circuit, the source of the data error can be determined to be the storage address or the storage data, the one-time correction and two-time detection function of the saved original data can be realized, and the additional storage space can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0063] Figure 1 is a data storage method provided by the embodiment of the present application;

[0064] Figure 2 is a data reading method provided by the embodiment of the present application;

[0065] Figure 3 is a data storage circuit provided by the embodiment of the present application;

[0066] Figure 4 is a data reading circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0068] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person having ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity of any number, but denote the existence of at least one. The numbers in the drawings of the specification only represent the distinction of the respective functional components or modules, and do not represent the logical relationship between the components or modules. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like only represent relative positional relationships, which can change when the absolute positions of the described objects change.

[0069] In the following, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference signs are assigned to components having substantially the same or similar structure and function, and repeated descriptions thereof will be omitted.

[0070] To solve the problem that the extra storage space occupied by the error correction code generated by using the independent error detection algorithm is large and not suitable for high-speed scenarios, the present application provides the following embodiments.

[0071] In some embodiments, as shown in FIG. 1, a data storage method includes: Figure 1

[0072] A100: obtaining a storage address and original data corresponding to the storage address;

[0073] A200: determining a first parity check code and a third check code of the storage address;

[0074] A300: determining storage data according to the storage address, the original data, the first parity check code, and the third check code;

[0075] A400: saving the storage data to a storage unit corresponding to the storage address.

[0076] The storage address indicates the address of the storage unit where the storage data is saved, and is usually represented by 32-bit data.

[0077] The original data is the data that needs to be saved, and is usually represented by 64-bit data.

[0078] ​The first parity check code is data obtained by performing parity check on the storage address, and is usually represented by 1 bit of data. The parity check mode is: supplementing "0" or "1" to the storage address, so that the number of "0" or "1" in the storage address is odd or even.

[0079] Specifically, the storage data is determined according to the storage address, the original data, the first parity check code and the third check code, and includes:

[0080] A310: determining the first check code corresponding to the storage address by using an independent error detection algorithm;

[0081] A320: determining the second check code corresponding to the original data by using an independent error detection algorithm;

[0082] A330: performing exclusive or operation on the first check code and the second check code to obtain the third check code;

[0083] A340: determining the storage data according to the original data, the first parity check code and the third check code.

[0084] The independent error detection (ECC) algorithm is a data processing algorithm that can be understood by those skilled in the art, and a commonly used independent error detection algorithm is Hamming code. Since the storage address is 32 bits, its ECC code is usually 6 bits of binary number, in order to enable it to have the function of "correcting one and detecting two", 7 bits of binary number are used as the bit number of the first check code. The original data is 64 bits, and its ECC code is usually 7 bits of binary number, in order to enable it to have the function of "correcting one and detecting two", 8 bits of binary number are used as the bit number of the second check code.

[0085] The storage data is determined according to the original data, the first parity check code and the third check code, and includes:

[0086] The original data, the first parity check code and the third check code are spliced to obtain the storage data. The order of data splicing is not limited in the application.

[0087] In other embodiments, as shown in FIG. 8, a data reading method is applied to read the storage data saved by the data storage method of the first aspect, and includes: Figure 2

[0088] B100: obtaining a reading address and reading the storage data saved at the reading address;

[0089] B200: splitting the storage data to obtain the to-be-verified data, the first parity check code and the third check code;

[0090] B300: verifying the to-be-verified data according to the storage address and the storage data;

[0091] ​B400: in response to the to-be-verified data passing the verification, the to-be-verified data is taken as the original data.

[0092] The read address is an address to be read and verified. The correct read address is the storage address after verification.

[0093] Specifically, splitting the storage data also obtains a third verification code, B300: verifying the to-be-verified data according to the storage address and the storage data, including:

[0094] B310: based on the storage address, an independent error detection algorithm is used to calculate an address verification code;

[0095] B320: the address verification code and the third verification code are subjected to an exclusive or operation to obtain a data verification code;

[0096] B330: the data verification code is subjected to a decoding operation using the independent error detection algorithm to obtain decoded data;

[0097] B340: the decoded data is compared with the to-be-verified data;

[0098] B350a: in response to the decoded data matching the to-be-verified data, it is determined that the to-be-verified data passes the verification;

[0099] Preferably, verifying the to-be-verified data according to the storage address and the storage data further includes:

[0100] B350b: in response to the decoded data not matching the to-be-verified data, an independent error detection algorithm is used to check the to-be-verified data for errors;

[0101] B360ba: in response to the result of checking the to-be-verified data for errors being a single-bit error, the error bit of the to-be-verified data is corrected, and the to-be-verified data after the error bit correction is taken as the original data;

[0102] B360bb: in response to the result of checking the to-be-verified data for errors being a multi-bit error, an unrecoverable alarm is issued;

[0103] B370bb: the storage data read according to the storage address is set to a preset safety value.

[0104] Here, the address check code is XORed with the third check code, which is based on the property of XOR operation, i.e., after data A is XORed with data B to obtain data C, data A can be obtained by XORing data C with data B. In the embodiment of the present application, the address check code is XORed with the third check code to obtain the data check code. The data check code corresponds to the original data. If the data check code and the original data pass the check, it is indicated that the correct original data is stored in the stored data. In this way, the correctness of the stored original data is verified.

[0105] The preset security value is used to indicate invalid data or data error. Illustratively, 0 is used as the preset security value. When the data error triggers the unrecoverable alarm, the stored data is set to 0.

[0106] The split stored data also obtains the first parity check code, and the method further comprises:

[0107] B310: calculating the second parity check code corresponding to the storage address;

[0108] B320: comparing the first parity check code and the second parity check code;

[0109] B330a: in response to the first parity check code matching the second parity check code, it is determined that the storage address is correct;

[0110] B330b: in response to the first parity check code not matching the second parity check code, it is determined that the storage address is incorrect.

[0111] B340b: issuing an unrecoverable alarm;

[0112] B350b: setting the stored data read according to the storage address to the preset security value.

[0113] By comparing the parity check codes, the correctness of the storage address can be determined.

[0114] For the case that one-bit error occurs in the data and no error occurs in the address: one-bit error in the data is detected and corrected, and the correct data is output.

[0115] For the case that one-bit error occurs in the address: whether the data has error or not, one-bit error in the address is detected and reported as an unrecoverable error, and the output data is set to 0 to ensure safety.

[0116] For the case that two-bit error occurs in the data and no error occurs in the address: the error in the output data is detected and reported as an unrecoverable error, and the output data is set to 0 to ensure safety.

[0117] For the case that two-bit error occurs in the address and no error occurs in the data: support to detect that the fetched data has error and report as an unrecoverable error, set the output data to 0 to ensure safety.

[0118] In some other embodiments, as shown in FIG. 1, a data storage circuit for implementing the above data storage method includes a data processing module 110, an address processing module 120, a first XOR operation module 130, a splicing module 140, and a storage module 150. Figure 3

[0119] The storage module 150 includes at least one storage unit 151, and any storage unit 151 has a corresponding storage address for saving storage data.

[0120] The data processing module 110 is connected with the first XOR operation module 130, the address processing module 120 is connected with the first XOR operation module 130, the splicing module 140, and the storage module 150, and the splicing module 140 is connected with the storage module 150.

[0121] The data processing module 110 is a second encoding circuit, used for acquiring original data, determining a second check code corresponding to the original data by using an independent error detection algorithm, and transmitting the second check code to the first XOR operation module 130.

[0122] The address processing module 120 is used for acquiring a storage address, determining a storage unit, determining a first parity check code and a third check code corresponding to the storage address, transmitting the first parity check code to the splicing module 140, and determining a first check code corresponding to the storage address by using an independent error detection algorithm, and transmitting the first check code to the first XOR operation module 130.

[0123] The first XOR operation module 130 is used for acquiring the first check code and the second check code, performing XOR operation on the first check code and the second check code to obtain a third check code, and transmitting the third check code to the splicing module 140.

[0124] The splicing module 140 is used for acquiring the original data, the first parity check code, and the third check code, determining storage data according to the original data, the first parity check code, and the third check code, and saving the storage data to the storage unit 151 corresponding to the storage address.

[0125] Further, the address processing module 120 includes a first encoding circuit 121, a parity encoding circuit 122, and an address decoding circuit 123.

[0126] ​An input terminal of the first encoding circuit 121 is configured to receive the storage address, and an output terminal of the first encoding circuit 121 is configured to transmit the first check code to the first XOR operation module 130.

[0127] An input terminal of the parity encoding circuit 122 is configured to receive the storage address, and an output terminal of the parity encoding circuit 122 is configured to transmit the first parity check code to the splicing module 140.

[0128] An input terminal of the address decoding circuit 123 is configured to receive the storage address, and an output terminal of the address decoding circuit 123 is configured to determine the corresponding storage unit 151 according to the storage address.

[0129] Further, the data processing module 110 comprises a second encoding circuit 111.

[0130] An input terminal of the second encoding circuit 111 is configured to receive the original data, and an output terminal of the second encoding circuit 111 is configured to transmit the second check code to the first XOR operation module 130.

[0131] In some other embodiments, as shown in FIG. 2, a data reading circuit is configured to implement the data reading method, and comprises: Figure 4

[0132] The storage module 150, the bit selection circuit 210, the parity check circuit 220, the third encoding circuit 230, the second XOR operation module 240, the decoding circuit 250, and the error processing unit 260.

[0133] The storage module 150 is connected with the bit selection circuit 210, the parity check circuit 220, and the third encoding circuit 230; the bit selection circuit 210 is connected with the parity check circuit 220, the second XOR operation module 240, and the decoding circuit 250; the parity check circuit 220 is connected with the error processing unit 260; the third encoding circuit 230 is connected with the second XOR operation module 240; the second XOR operation module 240 is connected with the decoding circuit 250; and the decoding circuit 250 is connected with the error processing unit 260.

[0134] The storage module 150 is configured to acquire the input storage address, and send the reading address to the bit selection circuit 210.

[0135] The bit selection circuit 210 is configured to acquire the reading address, read the storage data saved at the reading address, and split the storage data to obtain the to-be-checked data, the third check code, and the first parity check code.

[0136] The parity check circuit 220 is configured to calculate the second parity check code based on the storage address by using an independent error detection algorithm.

[0137] ​The third encoding circuit 230 is configured to calculate an address check code based on the storage address by using an independent error detection algorithm.

[0138] The second XOR operation module 240 is configured to perform XOR operation on the address check code and the third check code to obtain a data check code.

[0139] The decoding circuit 250 is configured to decode the data check code by using the independent error detection algorithm to obtain decoded data.

[0140] The error processing unit 260 is configured to issue an unrecoverable alarm according to the error type, and set the storage data read according to the storage address to a preset safety value.

[0141] By using the data storage and reading method and the data storage and reading circuit, it can be determined whether the data error is caused by the storage address or the storage data. The storage address and the storage data error can be checked, and the single-bit error of the storage data can be corrected. Compared with the traditional similar algorithm, less storage space or shorter time sequence path is used, and the method is more friendly to most systems. For example, when the address is 32 bits and the data is 64 bits, the classic ECC algorithm needs 7 (address ECC code) + 8 (data ECC code) = 15 bits of additional encoding storage space, while the method only needs 8 (data ECC code) + 1 (address parity check code) = 9 bits of additional storage space, which brings 40% of additional storage space saving benefit. Compared with the scheme of splicing the address and the data to calculate the ECC, for example, using the GF40 process, the critical path of the ECC-96 scheme is 8.126 ns, which can only support a main frequency of 123 MHz, while the critical path of the present scheme is only 6.04 ns, which can support a main frequency of 165.56 MHz, which is increased by 34.54% in the supportable core frequency. When the actual use requirement of high functional safety requirement is closer, the data single-bit error is the actual single-bit error, which can be corrected by the ECC algorithm.

[0142] All the optional technical solutions can be combined to form optional embodiments of the present application, which will not be repeated here.

[0143] Note that the above merely describes preferred embodiments of the present application and the applied technical principles. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, reconfigurations and substitutions can be made by those skilled in the art without departing from the scope of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A data reading method characterized by, The method comprises: obtaining a read address and reading storage data stored in the storage address; splitting the storage data to obtain at least to-be-verified data; verifying the to-be-verified data according to the storage address and the storage data; in response to the to-be-verified data passing the verification, taking the to-be-verified data as original data; wherein splitting the storage data further obtains a third check code, and verifying the to-be-verified data according to the storage address and the storage data comprises: based on the storage address, calculating an address check code by using an independent error detection algorithm; performing XOR operation on the address check code and the third check code to obtain a data check code; decoding the data check code by using the independent error detection algorithm to obtain decoded data; comparing the decoded data with the to-be-verified data; in response to the decoded data matching the to-be-verified data, determining that the to-be-verified data passes the verification; in response to the decoded data not matching the to-be-verified data, performing error checking on the to-be-verified data by using the independent error detection algorithm; wherein the data is stored in the following manner: obtaining a storage address and original data corresponding to the storage address; determining a first parity check code and a third check code of the storage address; determining storage data according to the storage address, the original data, the first parity check code and the third check code; storing the storage data in a storage unit corresponding to the storage address; wherein determining the storage data according to the storage address, the original data, the first parity check code and the third check code comprises: determining a first check code corresponding to the storage address by using an independent error detection algorithm; determining a second check code corresponding to the original data by using an independent error detection algorithm; performing XOR operation on the first check code and the second check code to obtain the third check code; determining the storage data according to the original data, the first parity check code and the third check code.

2. The data reading method according to claim 1, characterized by, determining the storage data according to the original data, the first parity check code and the third check code comprises: splicing the original data, the first parity check code and the third check code to obtain the storage data.

3. The data reading method according to claim 1, characterized by, The method further comprises: in response to a result of error checking on the to-be-verified data being single-bit error, correcting an error bit of the to-be-verified data, and taking the to-be-verified data after correction of the error bit as the original data; in response to a result of error checking on the to-be-verified data being multi-bit error, issuing an unrecoverable alarm; setting storage data read according to the storage address to a preset security value, wherein the preset security value is used to indicate invalid data or data error, and in response to triggering of the unrecoverable alarm due to data error, setting the storage data to the preset security value.

4. The data reading method according to claim 1, characterized by, Splitting the storage data further obtains a first parity check code, and the method further comprises: calculating a second parity check code corresponding to the storage address; comparing the first parity check code and the second parity check code; determining that the storage address is incorrect in response to the first parity code not matching the second parity code; issuing a non-recoverable alarm; setting storage data read according to the storage address to a preset safe value.

5. A data storage circuit, characterized by The data storage circuit for implementing the data read method according to any one of claims 1-4 comprises a data processing module, an address processing module, a first exclusive OR operation module, a splicing module and a storage module. The storage module comprises at least one storage unit. The data processing module is connected with the first exclusive OR operation module, the address processing module is connected with the first exclusive OR operation module, the splicing module and the storage module, and the splicing module is connected with the storage module. The data processing module is configured to acquire original data, determine a second check code corresponding to the original data by using an independent error detection algorithm, and transmit the second check code to the first exclusive OR operation module. The address processing module is configured to acquire a storage address, determine a storage unit, determine a first parity code corresponding to the storage address, transmit the first parity code to the splicing module, and determine a first check code corresponding to the storage address by using an independent error detection algorithm, and transmit the first check code to the first exclusive OR operation module. The first exclusive OR operation module is configured to acquire the first check code and the second check code, perform exclusive OR operation on the first check code and the second check code to obtain a third check code, and transmit the third check code to the splicing module. The splicing module is configured to acquire the original data, the first parity code and the third check code, determine storage data according to the original data, the first parity code and the third check code, and save the storage data to the storage unit corresponding to the storage address.

6. The data storage circuit of claim 5, wherein, The address processing module comprises a first encoding circuit, a parity encoding circuit and an address decoding circuit. An input end of the first encoding circuit is configured to receive the storage address, and an output end of the first encoding circuit is configured to transmit the first check code to the first exclusive OR operation module. An input end of the parity encoding circuit is configured to receive the storage address, and an output end of the parity encoding circuit is configured to transmit the first parity code to the splicing module. An input end of the address decoding circuit is configured to receive the storage address, and an output end of the address decoding circuit is configured to determine the corresponding storage unit according to the storage address.

7. The data storage circuit of claim 5, wherein, The data processing module comprises a second encoding circuit. An input end of the second encoding circuit is configured to receive the original data, and an output end of the second encoding circuit is configured to transmit the second check code to the first exclusive OR operation module.

8. A data reading circuit, characterized by comprising: The data read method according to any one of claims 1-4 comprises: a storage module, a bit selection circuit, a parity check circuit, a third encoding circuit, a second exclusive OR operation module, a decoding circuit and an error processing unit. The storage module is connected with the bit selection circuit, the parity check circuit and the third encoding circuit, the bit selection circuit is connected with the parity check circuit, the second exclusive OR operation module and the decoding circuit, the parity check circuit is connected with the error processing unit, the third encoding circuit is connected with the second exclusive OR operation module, the second exclusive OR operation module is connected with the decoding circuit, and the decoding circuit is connected with the error processing unit; The storage module is configured to obtain an input storage address and send a read address to the bit selection circuit; The bit selection circuit is configured to obtain the read address, read storage data stored at the storage address, and split the storage data to obtain to-be-checked data, a third check code and a first parity check code; The parity check circuit is configured to obtain a second parity check code based on the storage address by using an independent error detection algorithm; The third encoding circuit is configured to obtain an address check code based on the storage address by using the independent error detection algorithm; The second exclusive OR operation module is configured to perform exclusive OR operation on the address check code and the third check code to obtain a data check code; The decoding circuit is configured to decode the data check code to obtain decoded data by using the independent error detection algorithm; The error processing unit is configured to issue an unrecoverable alarm according to an error type and set storage data read according to the storage address to a preset safety value.

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