A power consumption area switchable standard cell layout automatic generation method

Abstract

The application discloses a kind of standard cell layout automatic generation method for power consumption area switchable, it is related to LELE (lithography-etching-lithography-etching) technology, and the data preprocessing of circuit netlist is carried out;The NMOS tube and PMOS tube in the circuit netlist after preprocessing are respectively operated with source-drain sharing, and the layout of optimal area is obtained;The NMOS tube and PMOS tube in the circuit netlist after preprocessing are operated with gate pairing operation to form MOS tube pair, and the layout of optimal power consumption is obtained by source-drain sharing operation to the MOS tube pair;Grid modeling is carried out based on the design rule parameter of process library, and grid point canvas is established;The layout of optimal area and optimal power consumption is added to the grid point canvas, and the layout of optimal index is obtained by A star algorithm simulation artificial wiring.The application creates grid layout according to two separate layout strategies, combined with process design rule, uses algorithm to simulate artificial wiring, so as to realize the feasibility of layout and wiring whole process.

Description

TECHNICAL FIELD

[0001] The present application relates to the LELE (lithography-etch-lithography-etch) technology, and more particularly to a power-area switchable standard cell layout automatic generation method. BACKGROUND

[0002] Standard cell layout design is a key link in the design flow of digital integrated circuits, which directly affects the performance, power consumption and area (PPA) of the entire chip. In the current integrated circuit design practice, the layout design in the standard cell library mainly relies on manual operation. With the continuous progress of process technology, the design rules become increasingly complex, while the demand for customized standard cells from downstream applications is also increasing, resulting in the number of cells in the standard cell library approaching thousands of levels, which makes it extremely difficult to completely rely on manual operation to complete the layout design of all standard cells. At the same time, the requirements for standard cell PPA are also increasing.

[0003] With the rapid development of deep reinforcement learning, advanced technologies applied in the field of integrated circuit design emerge in an endless stream. In recent years, automated standard cell generation tools, such as BonnCell designed by J. Schneider [1] of Bonn University based on reinforcement learning and NVCell designed by H. Ren [2] et al. of NVIDIA Corporation, can generate a batch of standard cell layouts without DRC violations under a specific process library. However, a significant challenge still exists: for all standard cells under the process library, especially large-scale sequential logic cells, some standard cell layouts generated by the above tools may have wiring problems, resulting in the layout result being unable to be routed or having DRC errors after routing. In 2016, X. Xu et al. [3] concluded that a more dispersed pin distribution strategy is more beneficial to the overall layout by optimizing pin access and multi-layer distribution, which obtains a larger pin access space. In 2019, Yu, T et al. [4] considered the delay of logic cells and design rules, and stored the source and drain of NFET and PFET as pins by using flow capacity control constraints, thereby improving the layout efficiency. However, the above research works do not consider the index optimization problem in actual engineering applications, and the generated layout cannot be adopted by the industry.

[0004] The above work mainly focuses on optimizing the layout of discrete standard cells, while the overall layout optimization of all macro cells is also developing rapidly. In 2021, Yan Junchi et al. from Shanghai Jiaotong University [5] proposed a graph neural network (GNN) embedding and feature extraction, a convolutional neural network (CNN) for global embedding and netlist dictionary extraction, and a random network distillation (RND) algorithm for specific digital circuit layout applications. In 2024, Mirhoseini A et al. from Google [6] based on the powerful computing power of Google's computing center, realized the application of Google's self-developed TPU in digital circuit layout generation, significantly shortened the chip design time, and reached or even surpassed the level of artificial technology. These algorithms have unique innovation, but the effect of their application in the automatic generation of standard cell layout is unknown, and they are difficult to be used as a reference.

[0005] In general, the existing integrated circuit standard cell layout design tools and design techniques have the defect of high computational complexity. The computational difficulty of existing algorithms increases exponentially with the increase of problem size, especially when dealing with a large number of transistors in standard cells, it is often difficult to obtain effective layout design results within a reasonable time. These problems limit the efficiency and effectiveness of standard cell layout design, and new technologies and methods are needed to optimize the design process and improve the design quality and efficiency.

[0006] References:

[0007] Cremer, P., Hougardy, S., Schneider, J., & Silvanus and J., "Automatic Cell Layout in the 7nm Era," Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017, pp. 99-106.

[0008] [2] H. Ren and M. Fojtik, "Nvcell: Standard cell layout in advanced technology nodes with reinforcement learning," In ACM / IEEE Design Automation Conference (DAC), 2021, pp. 1291-1294.

[0009] [3] X. Xu, B. Yu, J.-R. Gao, C.-L. Hsu and D. Z. Pan, "PARR: Pin access planning and regular routing for self-aligned double patterning," Proceedings of the 25th edition on Great Lakes Symposium on VLSI. July 2016, Syst. 21, 3, Article 42, pp. 1-21.

[0010] [4] Yu, T. C., Fang, S. Y., Chiu, H et al., "Pin accessibility prediction and optimization with deep learning-based pin pattern recognition." In Proceedings of the 56th Annual Design Automation Conference (DAC), 2019, pp. 1-6.

[0011] [5] Cheng R, Yan J. "On Joint Learning for Solving Placement and Routing in Chip Design," Neural Information Processing Systems (2021), Article 1262, pp. 16508-16519.

[0012] [6] Mirhoseini A et al., "A graph placement methodology for fast chip design. Nature," 2024, 594(7862), pp. 207-212. SUMMARY

[0013] The technical problem to be solved by the present application is to provide a standard cell layout automatic generation method for power consumption area switchable, which creates a grid layout according to two separate layout strategies and combines process design rules, and uses an algorithm to simulate manual wiring, thereby realizing the feasibility of the whole process of layout and wiring.

[0014] The standard cell layout automatic generation method for power consumption area switchable provided by the present application is:

[0015] data preprocessing is performed on the circuit netlist;

[0016] source-drain sharing operation is performed on NMOS and PMOS in the preprocessed circuit netlist respectively to obtain an area-optimized layout;

[0017] gate pairing operation is performed on NMOS and PMOS in the preprocessed circuit netlist to form MOS pairs, and source-drain sharing operation is performed on the MOS pairs to obtain a power consumption-optimized layout;

[0018] grid modeling is performed based on design rule parameters of a process library to establish a grid canvas;

[0019] the area-optimized layout and the power consumption-optimized layout are added to the grid canvas, and artificial routing is simulated by A-star algorithm to obtain an index-optimized layout.

[0020] Preferably, the source-drain sharing operation is:

[0021] the longest connection path of S, D and G end connection information of NMOS and PMOS is identified by a depth search priority algorithm, the end points of the longest connection path are extracted and compressed into a new unit, and then the new unit is processed recursively using the depth search priority algorithm until all generated new units are simplified into discrete line segments, and the longest connection path obtained in each iteration is arranged to obtain an area-optimized layout.

[0022] Preferably, the source-drain sharing operation is:

[0023] the MOS pairs are processed by a depth search priority algorithm to obtain a combination order with the most number of source-drain sharing, and all MOS pairs in the combination order are input into a simulated annealing algorithm for optimization to obtain a power consumption-optimized layout.

[0024] Preferably, the step of optimizing the combination order by the simulated annealing algorithm is:

[0025] Step 1, set initial temperature T0 and final temperature T end ;

[0026] Step 2, introduce disturbance at the current temperature T to randomly change the combination order;

[0027] Step 3, if the current temperature T is greater than the final temperature T end , calculate the score of the objective function X, and take the score as a new score, and execute Step 4; otherwise, take the current combination order as the power consumption-optimized layout;

[0028] In the fourth step, it is determined whether the new score is better. If the new score is less than the original score, the introduced disturbance is accepted. Otherwise, it is determined whether the disturbance is accepted using the Metropolis criterion. If accepted, the changed combination order is taken as a new solution, and the second step is performed to start the next iteration. If not accepted, the original combination order is kept, and the second step is performed to start the next iteration.

[0029] Preferably, the score of the objective function X is calculated according to the following formula:

[0030]

[0031] In the formula, ω t is the score of the objective function X; represents calculating the range of all position coordinates of the i-th net in the current combination order and summing the ranges of all nets.

[0032] Preferably, the Metropolis criterion is used to determine whether the disturbance is accepted, specifically:

[0033] It is determined whether the following formula is true:

[0034]

[0035] If true, the disturbance is accepted; otherwise, it is not accepted.

[0036] In the formula, X is the objective function of the depth search priority algorithm corresponding to the current temperature T; X new is the objective function of the depth search priority algorithm corresponding to the temperature after the annealing coefficient a is reduced; and λ is a random number between 0 and 1.

[0037] Preferably, the specific method for establishing the grid canvas is as follows:

[0038] The design rule parameters of the process library are extracted.

[0039] The modeling constraint condition is set as the maximum value among the minimum width of the metal line M1 defined in the design rule, the minimum distance between the same layer metals, the minimum distance between the via / hole and the via / hole, and the minimum distance between the metal and the via / hole, and whether the metal line area meets the minimum area requirement of the metal layer in the design rule.

[0040] The grid canvas with a fixed width that meets the process requirements is constructed.

[0041] Preferably, when the A-star algorithm is used to simulate artificial routing, the grid canvas is set with a constraint that the existing via / hole, same layer power signal line and other line network signal line are classified as obstacles in the line network routing process.

[0042] Preferably, after data preprocessing of the circuit netlist, the S, D and G end connection information of the NMOS and PMOS tubes is stored in the form of a graph in a dictionary.

[0043] Advantages

[0044] The present application has the advantages of:

[0045] 1. The present application obtains two ideas of layout area optimization and power optimization by combining the depth search priority algorithm and the simulated annealing algorithm, wherein the depth search priority algorithm is applied to maximize the number of source-drain sharing of transistors, so as to realize the optimal layout of transistor layout area, and enhance the wireability of the layout, thereby reducing the time cost and improving the design efficiency. The simulated annealing algorithm concentrates the line network distribution of the transistor pairs, which is beneficial to improve the search solution space of the routing algorithm while reducing the signal wire length.

[0046] 2. The grid modeling adopted by the present application can consider the design rules in the wiring step, and can classify the through hole / counter bore, power line and other signal lines as obstacles in the wiring process, thereby improving the wiring efficiency. At the same time, the algorithm constraint conditions are set according to the artificial wiring experience, so that the A-star algorithm can complete the wiring process in a limited time. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 Layout and routing flowchart for the standard cell layout automatic generation method of the present application;

[0048] Figure 2 Power consumption optimization flowchart for the standard cell layout of the present application;

[0049] Figure 3 DFS algorithm framework diagram of the present application;

[0050] Figure 4 Wiring process diagram based on the A-star algorithm of the present application. DETAILED DESCRIPTION

[0051] The present application will be further described below in conjunction with the embodiments, but does not constitute any limitation on the present application, and any limited number of modifications made by anyone within the scope of the claims of the present application is still within the scope of the claims of the present application.

[0052] The application discloses a power consumption-area switchable standard cell layout automatic generation method, which mainly uses a hybrid optimization algorithm. First, an optimal transistor layout is obtained through a depth search priority algorithm and a simulated annealing algorithm, design rule parameters are extracted, corresponding grid modeling is carried out, and a grid drawing canvas is established based on the grid, the obtained layout is added to the grid drawing canvas, artificial wiring is simulated by using an A-star algorithm with constraints, and finally a target optimal layout is obtained.

[0053] The core of the application is that power consumption optimal and area optimal layouts can be automatically generated for a standard cell library under a 28nm process. According to two separate layout strategies, a grid layout is created in combination with process design rules, and artificial wiring is simulated by using an algorithm, so that the feasibility of a whole layout and wiring process is realized.

[0054] In the introduction of the specific method process, first, it needs to be understood that in the layout rules of a digital standard cell, PMOS tubes are generally defined to be on the upper side, NMOS tubes are on the lower side, a power line VDD and a ground line VSS are respectively horizontal wide tracks, and the nets of the MOS tubes are connected by signal lines between the two tracks. The width of each standard cell layout is fixed, which is convenient for modular calling of a digital circuit in a post-simulation process, and the whole layout is built like a block of "bricks". Layout determines wiring, and therefore the optimization of the area and power consumption of the layout corresponds to two different layout strategies.

[0055] The standard cell layout automatic layout and wiring flowchart is as shown in Figure 1 The layout strategy and the wiring strategy of area and power consumption optimization are included.

[0056] The layout strategy includes: after data preprocessing of an input circuit netlist, NMOS tubes and PMOS tubes are separately subjected to a source-drain sharing operation through a depth search priority algorithm, so as to obtain an area optimal layout; NMOS tubes and PMOS tubes are subjected to gate pairing operation to form MOS tube pairs, and the MOS tube pairs are subjected to a source-drain sharing operation through a depth search priority algorithm and a simulated annealing algorithm, so as to obtain a power consumption optimal layout.

[0057] The wiring strategy includes: grid modeling is carried out for process library design rule parameters, a grid drawing canvas is established, the obtained layout is added to the grid drawing canvas, artificial wiring is simulated by using an A-star algorithm, and finally a target optimal layout is obtained.

[0058] The optimization of the area is mainly to reduce the width W of the whole standard cell by increasing the number of transistor source-drain sharing. tAssume that the width of two independent transistors is W0 under the premise of meeting the design rules, the number of NMOS transistors and the number of PMOS transistors are the same, both are n, the number of NMOS transistors and PMOS transistors that can share the source and drain is m N and m P , the width of a single transistor is W, and the width of the entire standard cell is:

[0059]

[0060] For the power consumption of the standard cell, the power consumption of the power supply line is fixed, and the power consumption of the entire layout mainly depends on the influence of the signal line. The power consumption of the signal line is divided into dynamic power consumption and static power consumption. Taking the signal line at the output end of an inverter as an example, as shown in Figure 2 (a), the dynamic power consumption P d is mainly affected by the parasitic capacitance C p , and mainly depends on:

[0061]

[0062] W and L are the width and length of the signal line respectively, and t ox is the fixed value of the metal line thickness. The static power consumption P s is mainly affected by the parasitic resistance R p , and the specific expression is:

[0063]

[0064] Therefore, the total power consumption is defined as:

[0065]

[0066] A and B are coefficients after combining multiple parameters. From the simplified expression of the total power consumption in formula (4), it can be obtained that when W increases from the minimum size to a certain fixed value, the total power consumption decreases with the increase of W; the smaller L is, the smaller the total power consumption is. From the above derivation, it can be proved that reducing the length of the signal line and moderately increasing the width of the signal line can reduce the power consumption. Therefore, the idea of power consumption optimization is to reduce the wiring length of net by gate pairing and increase the wire width, as shown in Figure 2 (b).

[0067] The hybrid algorithm proposed in the application has three kinds, which are combined with each other to achieve the optimal automatic layout generation scheme, and the algorithms are as follows:

[0068] (1) Depth search priority algorithm

[0069] Depth-First Search (DFS) is an algorithm that explores as far as possible along each branch of the tree or graph, traversing the nodes of the tree. When a node X is reached and all of its associated edges have been explored, the search process backtracks to the node from which the edge to X was first discovered. This cycle continues until all reachable nodes have been discovered from the source node. If there are still undiscovered nodes, one is selected as a new source node and the process is repeated until all nodes have been visited. The core of the algorithm involves backtracking and pruning. Backtracking is the strategy of automatically returning to the previous step when the algorithm cannot continue forward. Pruning is the strategy of terminating the search of a path early if it is determined that the path cannot lead to the goal, thereby avoiding unnecessary computation and improving the efficiency of the algorithm.

[0070] After preprocessing, the connections within the standard cell layout are converted into a known MOS transistor SPICE netlist, in which the positions of the drain (D) and source (S) terminals can be interchanged. Since the source and drain of a MOS transistor are fixed, the corresponding network can be represented as a node in the graph, and each MOS transistor is modeled as a line segment. Thus, the entire cell can be represented as a directed graph, thereby converting the problem of finding the optimal layout into the problem of identifying the longest path in graph theory.

[0071] After preprocessing the MOS transistors, the S, D, and G terminal connection information of NMOS and PMOS transistors is stored in a dictionary in the form of a graph. Then, the DFS algorithm is applied to identify the longest connection path, which corresponds to the layout strategy that maximizes source-drain sharing for the current cell. The endpoints of this path are extracted and compressed into a new cell, and then the DFS algorithm is recursively used to process the new cell to generate a layout. This recursive process continues until all generated cells are simplified into discrete line segments. At this point, the longest paths obtained in each iteration are arranged to obtain the area-optimal layout. Figure 3 Taking a 3-input AND cell as an example, a schematic diagram of the algorithm is shown.

[0072] (2) Simulated Annealing Algorithm

[0073] During power consumption optimization, the positions of a net in the grid need to be focused on. Only when these positions are most concentrated, i.e., the farthest and nearest positions are closest to each other, is the difficulty of routing the lowest. After performing the depth search priority algorithm on PMOS and NMOS transistor pairs to obtain the combination order with the most source-drain sharing, when all combinations are input into the simulated annealing algorithm for optimization, the specific steps are as follows:

[0074] First, set initial temperature T0 and final temperature T end , define annealing coefficient a and Markov chain length L N , introduce disturbance at current temperature T, i.e. randomly change the positions of MOS pairs to change the combination order. The cooling process at current temperature T is T = T · a. Then, when the current temperature T is greater than the final temperature T end , calculate the score of the objective function X. The score of the objective function X is defined as: calculate the range of all position coordinates of a net at the current combination order and sum the ranges of all nets, i.e. quantify the distance sum of all nets, the expression is

[0075]

[0076] The smaller the score is, the better. If the new score is better, unconditionally accept the change; otherwise, use the Metropolis criterion to judge whether to accept the disturbance.

[0077] In the Metropolis criterion judgment, generate a random number λ between 0 and 1, if the following inequality is satisfied:

[0078]

[0079] then accept the new solution, otherwise keep the original solution. That is, if the disturbance is not accepted, restore the original position. Then, start the next iteration. Once the iteration meets the cooling stop condition, i.e. the current temperature T is less than or equal to the final temperature T end , output the optimized scheme, and finally get the layout with the minimum network distance, i.e. the power optimal layout.

[0080] For example, input the initial Gate sequence and MOS pair sequence defined as:

[0081] G = [g1, g2, … g n ] SD = [[s1, d1], [s2, d2], … [s n , d n ]] (7)

[0082] The output gets the optimal Gate sequence and MOS pair sequence:

[0083] G best = [g1, g2, … g n ] SD best = [[s1, d1], [s2, d2], … [s n , d n ]] (8)

[0084] (3) A-star algorithm

[0085] A-star algorithm is a heuristic search algorithm, which aims to find the shortest path from the initial node to the target node in the graph structure. The algorithm ingeniously combines the certainty of Dijkstra algorithm in path finding (i.e. can definitely find a shortest path) and the efficiency of greedy algorithm in the search process (can quickly lock the target). A algorithm works with the total evaluation function f(n). f(n) = g(n) + h(n). Where g(n) represents the actual cost of reaching any vertex n from the starting point; h(n) is the estimated minimum cost from vertex n to the target node, which is generally calculated by a pre-designed heuristic function, which needs to fit the characteristics of the actual environment. In this case, A algorithm can ensure to find a path with the lowest cost. The specific definition of heuristic function h(n) is that for the point (x, y) in the grid, if the target point is set as (x goal ,y goal ), the Euclidean distance is:

[0086]

[0087] The specific definition of cost function g(n) is that when moving from the starting point to a new node through the path, g(n) will add the moving cost to reach the node. If the moving cost of each step is set as 1, then:

[0088] g(n new ) = g(n current ) + 1 (10)

[0089] After completing the layout operation of the above depth search priority algorithm and simulated annealing algorithm, the obtained JSON file with position information is input into A-star algorithm for wiring operation. The design rule parameters of the process library are extracted for modeling. Among them, the modeling constraint conditions are set as: the maximum value of the minimum width of the metal line M1 defined in the design rules, the minimum distance between the same layer metals, the minimum distance between the via / hole and the via / hole, and the minimum distance between the metal and the via / hole, whether the metal line area meets the minimum area requirement of the metal layer in the design rules. Based on the above constraints, a fixed-width grid canvas that meets the process requirements is constructed.

[0090] The area optimal layout and power consumption optimal layout information are mapped to the canvas in the form of coordinates. Meanwhile, it is necessary to note that the edge of the grid canvas is the boundary of the metal line, and the boundary cannot be exceeded in the process of routing. The process of routing is not continuous, and first, the position information of all nets is extracted, and then the arrangement is arranged in the order from left to right and is routed in turn. For a net, after the first position to the second position is traced, the path is saved. In the process of tracing from the second position to the third position, when the exploration direction is wrong and cannot be solved, the starting point can be found again at any position in the previous path to find a new path direction. Meanwhile, the upper limit of the training times is set, and if the optimal solution is not obtained after a certain training exceeds the number of times, the path searching process of the current starting point is stopped. The training times are artificial setting of the hyperparameters, and for the specific process library, the optimal training times are analyzed to improve the routing search efficiency as much as possible.

[0091] In the routing operation using the A-star algorithm, first, the above canvas needs to be set with constraints: the existing through hole / counterbore, the same layer power signal line and other line network signal line are classified as obstacles in the line network routing process. For two positions of a net, a shortest path from the starting position to the target position is needed to be found to avoid obstacles. As shown in Figure 4 , the modeling process of the routing canvas and the specific routing process of a net are shown.

[0092] The above only describes the preferred embodiments of the present application, and it should be noted that for those skilled in the art, without departing from the structure of the present application, a number of modifications and improvements can be made, which will not affect the effect of the present application and the practicality of the patent.

Claims

1. A method for automatic generation of power-area oriented switchable standard cell floorplan, comprising: The method comprises: data preprocessing is performed on a circuit netlist; source-drain sharing operations are performed on NMOS tubes and PMOS tubes in the preprocessed circuit netlist to obtain an area-optimal layout; wherein the source-drain sharing operations performed on the NMOS tubes and the PMOS tubes in the preprocessed circuit netlist are as follows: longest connection paths of S, D and G end connection information of the NMOS tubes and the PMOS tubes are identified by using a depth search priority algorithm, end points of the longest connection paths are extracted and compressed into a new unit, the depth search priority algorithm is used recursively to process the new unit until all generated new units are simplified into discrete line segments, the longest connection paths obtained in each iteration are arranged to obtain the area-optimal layout; gate pairing operations are performed on the NMOS tubes and the PMOS tubes in the preprocessed circuit netlist to form MOS tube pairs, source-drain sharing operations are performed on the MOS tube pairs to obtain a power consumption-optimal layout; wherein the source-drain sharing operations performed on the MOS tube pairs are as follows: the MOS tube pairs are processed by using the depth search priority algorithm to obtain a combination order with the maximum number of source-drain sharing; the combination order is input into an analog annealing algorithm to be optimized to obtain the power consumption-optimal layout; grid modeling is performed based on design rule parameters of a process library to establish a grid canvas; wherein the grid canvas is established by: extracting the design rule parameters of the process library; setting modeling constraints as: the maximum value of the minimum width of a metal line M1 defined in the design rules, the minimum distance between same-layer metals, the minimum distance between a via / hole and a via / hole, and the minimum distance between a metal and a via / hole, whether the metal line area meets the requirement of the minimum area of a metal layer in the design rules; and constructing a grid canvas with a fixed width that meets the process requirements; the area-optimal layout and the power consumption-optimal layout are added to the grid canvas, and artificial wiring is simulated by using an A-star algorithm to obtain an index-optimal layout; wherein, when the artificial wiring is simulated by using the A-star algorithm, constraints are set for the grid canvas: existing vias / holes, same-layer power signal lines and other line network signal lines are classified as obstacles in the line network wiring process.

2. The method of claim 1, wherein the method is characterized by: The step of optimizing the combination order by using the analog annealing algorithm comprises: First step, set initial temperature and final temperature ; Second step, at current temperature T The perturbation is introduced below to randomly change the order of combination; Third step, if the current temperature T is greater than the final temperature , then calculate the score of the objective function X and take the score as the new score, and execute the fourth step; otherwise, take the current combination order as the power consumption optimal layout; Step 4: determining whether the new score is better, if the new score is less than the original score, the introduced disturbance is accepted; otherwise, whether the disturbance is accepted is determined by using the Metropolis criterion; if accepted, the changed combination order is used as a new solution, and Step 2 is executed to start the next iteration; if not accepted, the original combination order is kept, and Step 2 is executed to start the next iteration.

3. The method of claim 2, wherein the method is characterized by: The calculation formula of the score of the objective function X is: ； wherein is the score of the objective function X; denotes the calculation of the range of all position coordinates of the i-th net in the current combination order and the sum of the ranges of all nets.

4. The method of claim 3, wherein the method is characterized by: whether the disturbance is accepted by using the Metropolis criterion is determined by: determining whether the following formula is true: ； if true, the disturbance is accepted; otherwise, not accepted; where X is the current temperature T the objective function of the corresponding DFS priority algorithm at the temperature after annealing with the annealing coefficient α; λ is a random number between 0 and 1. new the objective function of the corresponding DFS priority algorithm at the temperature after annealing with the annealing coefficient α; λ is a random number between 0 and 1.

5. The method for automatic generation of standard cell layout switchable for power-area according to claim 1, wherein, After data pre-processing of the circuit netlist, the S, D and G connection information of the NMOS and PMOS transistors is stored in a dictionary in the form of a graph.

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