Hierarchical transistor layout method for multiple rows of standard cells

Abstract

The invention discloses a hierarchical transistor layout method for multi-row standard cells, which comprises the following steps: carrying out transistor row distribution modeling and optimization through transistor netlist division and clustering constraint, then generating a local single-row layout of a transistor, and carrying out transistor multi-row overall layout optimization; in the transistor netlist division process, a standard unit transistor netlist is divided into a plurality of transistor clusters; in the transistor row distribution process, row distribution of SMT modeling transistors is used, the optimization solution variable is the row number of each transistor, constraints are added to limit the transistors in the same cluster to have the same row number, and the optimization target is the standard cell area estimated by using an Euler path and the estimated total vertical interconnection line length. According to the method, a hierarchical transistor layout method is adopted, a large-scale multi-row transistor layout is divided into a plurality of controllable small-scale multi-row transistor layouts, the solving complexity is reduced, and the calculation efficiency of the transistor layout is improved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design automation technology and relates to transistor layout technology for generating standard cell layouts of digital integrated circuits. Specifically, it relates to a hierarchical transistor layout method for multiple rows of standard cells, which is used to accelerate transistor layout and improve the scalability of the standard cell layout generation algorithm. Background Art

[0002] Transistor layout is the first step in generating a standard cell layout. In this step, the layout generator calculates the placement order or specific location for each transistor in the standard cell. Early research on automatic generation of standard cell layouts used methods based on Euler paths to generate minimum-area layouts for combinational logic cells. Recent research has often used Satisfiability Modulo Theories (SMT) to model transistor layout problems. This approach typically assumes that transistors are arranged linearly in a single row. Design rules impose mathematical constraints on the x-coordinate of each transistor, using metrics such as area and estimated line length as optimization targets. This modeling of the transistor layout problem as a planning problem is thus achieved.

[0003] Multi-row standard cell layout is no longer limited to a single-row linear arrangement of transistors, and its design space is further expanded, making it more complex to model it using SMT. In addition, SMT problems are difficult to solve, time-consuming, and have unstable runtimes. Therefore, SMT-based transistor layout methods are generally difficult to handle large-scale standard cell designs, and the scale of multi-row standard cells is often large.

[0004] In summary, existing methods struggle to balance layout quality and solution time when handling multi-row standard cell transistor layouts. With the advancement of integrated circuit technology, advanced processes have reduced transistor row heights, reduced routing tracks, and increased multi-row standard cell designs. Existing transistor layout methods struggle to meet actual design requirements. Summary of the Invention

[0005] The purpose of the present invention is to provide a hierarchical transistor layout method for multi-row standard cells to expand the existing transistor layout method so that it can better balance layout quality and solution time in multi-row design scenarios.

[0006] The present invention adopts a hierarchical layout method to decompose the large-scale multi-row transistor layout problem into multiple controllable small-scale multi-row transistor layout sub-problems, so as to reduce the solution complexity and improve the calculation efficiency.

[0007] The technical solution of the present invention is:

[0008] A hierarchical transistor layout method for multi-row standard cells includes the following steps: transistor netlist partitioning, transistor row allocation, local single-row layout, and multi-row overall layout.

[0009] In the transistor netlist partitioning process, the standard unit transistor netlist is divided into multiple transistor clusters based on the connection relationship of the transistors. In the transistor row allocation process, the satisfiability modulo theory SMT is used to model the transistor row allocation problem. The variable to be solved is the row number of each transistor. Constraints are added to limit the transistors in the same cluster to have the same row number. The optimization goal is to use the standard cell area estimated by the Euler path and the estimated total vertical interconnection line length. In the local single-row layout process, the Euler path search method or the SMT-based method is used to generate a local single-row transistor layout for each transistor cluster. In the multi-row overall layout process, the simulated annealing algorithm is used to simultaneously sort the local single-row layouts of each transistor cluster in each row to obtain the final transistor layout. Specifically, it includes the following steps:

[0010] A. Transistor Netlist Partitioning

[0011] The standard cell transistor netlist is divided into multiple transistor clusters based on the transistor connectivity. For sequential logic cells, any transistor is selected as the starting point for traversal, and a breadth-first search is used to group transistors that can be directly connected to a source or drain other than VDD (Voltage Drain) / VSS (Voltage Source Supply) into the same cluster.

[0012] Combinational logic cells are typically small and do not require partitioning. For larger combinatorial logic cells, partitioning can be performed based on gate inputs, grouping transistors with the same gate input into the same cluster; or based on branches, dividing them into multiple clusters with the same internal topology.

[0013] B. Cluster-constrained transistor row allocation modeling and optimization

[0014] The transistor row assignment problem is modeled using satisfiability modulo theory (SMT). The row number of each transistor is used as an optimization variable, and a constraint is added to ensure that transistors in the same cluster have the same row number. For each row assignment, an Euler path is used to calculate the lower bound of the width of the transistor chain in each row to estimate the overall layout area. The vertical interconnect length is also estimated based on the row assignment of each transistor. The layout area (a) and total vertical interconnect length (b) estimated using the Euler path are used as optimization targets, and lexicographic optimization is employed.

[0015] C. Generate a local single-row layout of transistors

[0016] Generate a local single-row transistor layout for each transistor cluster. This step can use existing SMT-based single-row transistor layout methods to generate the local layout of each cluster. For sequential logic cells, considering that the internal topology of each transistor cluster after transistor netlist partitioning is similar to that of a single combinational logic cell, a large number of transistor chains with minimum area can also be obtained by searching Euler paths and screened based on routability.

[0017] The specific process for searching for an Euler path to obtain the minimum-area transistor chain is as follows: First, construct graphs for both the NMOS and PMOS clusters, where edges represent individual transistors (i.e., transistor gates) and nodes represent the nets connected to the transistor source or drain. A pair of nodes is selected from the two graphs as the starting node pair, and a depth-first search is performed to traverse the Euler path. Each pair corresponds to the transistor layout of a cluster.

[0018] The routability index used to screen the local layout of transistor clusters mainly includes the number of shared gates.

[0019] D. Optimize the overall layout of multiple transistor rows

[0020] A simulated annealing algorithm is used to simultaneously sort the local single-row layouts of each transistor cluster in each row. For each n-row layout, n sequences representing the order of the local layouts of the transistor clusters are maintained. Perturbations include swapping the positions of two local layouts in the same row and flipping a local layout. The optimization objectives are the layout area, the total bus length estimated by the half-perimeter wirelength (HPWL), and the number of vertical gate shares between rows. These three factors are weighted to form the final optimization target.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] Existing multi-row transistor layout methods mostly use mixed integer programming (MIP), which divides rows into individual transistors and then performs independent single-row layouts. In large-scale designs, the branching process takes a long time, and the independent single-row layouts lack global considerations. The present invention adopts a hierarchical multi-row transistor layout method for multi-row standard cells, which is based on "clustering-branching-single-row layout-multi-row layout." By dividing the standard cell transistor netlist into multiple transistor clusters, modeling and optimizing cluster-constrained transistor row allocation, generating local single-row transistor layouts, and optimizing the overall multi-row transistor layout, the present invention decomposes the large-scale multi-row transistor layout problem into multiple controllable small-scale transistor layout sub-problems, reducing the solution complexity and improving the computational efficiency of transistor layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1This is a flowchart of the hierarchical transistor layout method for multi-row standard cells provided by the present invention.

[0024] Figure 2 Schematic diagram of the transistor netlist partitioning rules.

[0025] The left side shows sequential logic cells, and the right side shows combinational logic cells. The rounded rectangles in the background represent the partitioning results. The red lines in the left image represent nets that span multiple partitions due to their connection to transistor gates.

[0026] Figure 3 Diagram of how a graph is constructed when estimating the layout area using an Euler path.

[0027] In the construction graph, the edges are transistors (i.e., the gates of transistors), and the nodes are the wire meshes connected to the source or drain of the transistors. A, B, C, and D represent four nodes, all of which have odd degrees. Inserting an edge between nodes A and B reduces the number of odd-degree nodes to 2, and an Euler path is created in the construction graph. This introduces a DDB into the corresponding layout, which is the length of the dummy tube introduced because adjacent transistors cannot share the source and drain.

[0028] Figure 4 Schematic diagram of the overall layout of multiple rows of transistors using the simulated annealing algorithm. DETAILED DESCRIPTION

[0029] The present invention will be further described below through embodiments in conjunction with the accompanying drawings.

[0030] The present invention provides a hierarchical transistor layout method for multiple rows of standard cells. The method includes the following steps: transistor netlist partitioning, transistor row allocation, local single row layout and multi-row overall layout (such as Figure 1 ). Specifically includes the following steps:

[0031] A. Transistor Netlist Partitioning

[0032] For sequential logic units, any transistor is selected as the starting point for traversal, and a breadth-first search method is used to classify transistors that can be directly connected to non-VDD / VSS sources and drains into the same cluster. Figure 2 As shown in the left figure, the red line crosses multiple divisions due to its connection to the gate. Transistors that can be directly connected through non-VDD / VSS source and drain refer to transistors that can be directly connected through non-VDD / VSS source and drain if they are connected to the same non-VDD / VSS line net, and that line net is connected to the source or drain of both transistors.

[0033] For larger combinational logic units, they are divided according to gate input, dividing transistors with the same gate input into the same cluster; or divided according to branches, dividing them into multiple clusters with the same internal topology. Figure 2 shown.

[0034] B. Transistor row allocation modeling and optimization

[0035] Solving the transistor row assignment problem (i.e., the entire constrained optimization process): Using SMT, the transistor row assignment problem is modeled as a multi-objective lexicographic optimization problem with discrete variables and discrete constraints. The optimization objectives are to minimize: (a) the maximum row width, i.e., the width of the standard cell; and (b) the total vertical interconnect length. The constraint is that transistors in each cluster must be assigned to the same row. The optimization objective function is expressed as follows:

[0036]

[0037] satisfy

[0038] Where t and T represent the transistor and the set of all transistors in a standard cell, respectively; C represents the set of all transistors in a cluster; n and N represent the set of all nets in a standard cell, respectively; p represents the pin of the net; r(t) represents the row number of transistor t, w i represents the width of the i-th row, y(p) represents the y coordinate of a pin. r(C) is the row number representing cluster C;

[0039] The width w of the i-th row i The estimation is performed using the Euler path, which is expressed as:

[0040] w i =max(w i,n ,w i,p )

[0041]

[0042] Where w(t) represents the width of transistor t, odd(G) represents the number of odd-degree nodes in the graph constructed by NMOS or PMOS, and DDB represents the length of the dummy tube introduced by adjacent transistors because the source and drain cannot be shared, that is, double diffusion fracture. The process of estimating the length of a single transistor chain using the Euler path is as follows: Figure 3 As shown, the number of odd-degree nodes in the graph is 4, so a DDB needs to be inserted.

[0043] C. Local single-line layout

[0044] Generate a local single-row transistor layout for each transistor cluster. For sequential logic units, considering that the topological structure of each transistor cluster after the transistor netlist is divided is similar to that of a single combinational logic unit, when the number of transistors in each cluster is small, a large number of transistor chains with minimum area can be obtained by searching Euler paths, and then screened according to routability. The specific process is to first construct the following for NMOS and PMOS in the cluster: Figure 3 The graphs in

[15] (undirected graphs with source / drain as nodes and gate as edges) are constructed. A pair of nodes is selected from the two graphs as the starting node pair. The Euler path is traversed using a depth-first search. Each pair corresponds to a clustered transistor layout. If a node with an odd degree exists in the constructed graph, it is added to the candidate starting node set. If no node with an odd degree exists in the graph, VDD / VSS is added to the candidate starting node set. The starting node pair is formed by combining the candidate starting node sets of the two graphs.

[0045] The routability index used to screen the local layout of transistor clusters mainly includes the number of shared gates, which can be calculated synchronously when performing depth-first search.

[0046] D. Multi-line overall layout

[0047] Use simulated annealing to sort the local single-row layout of each transistor cluster simultaneously. Figure 4 . First, each cluster is placed in the corresponding row according to the result of transistor row allocation. For n-row layout, n sequences representing the local layout order of transistor clusters are maintained at the same time. The perturbation operation includes swapping the positions of two local layouts in the same row and flipping a local layout. It is worth noting that the swap operation can only occur between the layouts of two clusters in the same row. The optimization objectives are the layout area, the total bus length estimated by the Half-Perimeter Wirelength (HPWL), and the number of vertically shared gates between rows. The weighted combination of the three is used as the final optimization goal.

[0048] It should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A hierarchical transistor layout method for multiple rows of standard cells, characterized in that: Modeling and optimizing transistor row allocation based on transistor netlist partitioning and clustering constraints, regenerating local single-row transistor layout, and optimizing the overall layout of multiple transistor rows; In the transistor netlist partitioning process, the standard unit transistor netlist is divided into a plurality of transistor clusters based on the connection relationship of the transistors; During the transistor row allocation process, the satisfiability modulo theory (SMT) is used to model the transistor row allocation. The variable to be optimized is the row number of each transistor. A constraint is added to limit transistors in the same cluster to have the same row number. The optimization target is the standard cell area estimated using the Euler path and the estimated total vertical interconnect length. In a local single-row placement process, a local single-row transistor placement is generated for each transistor cluster; During the multi-row overall layout process, the local single-row layouts of each transistor cluster in each row are sorted at the same time to obtain the final transistor layout.

2. The hierarchical transistor layout method for multiple rows of standard cells according to claim 1, wherein: During the transistor netlist partitioning process, for sequential logic units, any transistor is selected as the traversal starting point, and a breadth-first search is used to group transistors that can be directly connected to a source or drain other than VDD / VSS into the same cluster. For combinational logic units, the division is performed based on gate input, and transistors with the same gate input are grouped into the same cluster. Or it can be divided according to branches into multiple clusters with the same internal topological structure.

3. The hierarchical transistor layout method for multiple rows of standard cells according to claim 1, wherein: During the cluster-constrained transistor row allocation modeling and optimization process, for each set of row allocations, the lower limit of the width of the transistor chain in each row is calculated using the Euler path to estimate the overall layout area. The vertical interconnect length is also estimated based on the row allocation of each transistor. The layout area and total vertical interconnect length estimated using Euler path are used as optimization targets, and lexicographic optimization is adopted.

4. The hierarchical transistor layout method for multiple rows of standard cells according to claim 3, wherein: The objective function of cluster-constrained transistor row allocation optimization is expressed as: satisfy Where t and T represent the transistor and the set of all transistors in a standard cell, respectively; C represents the set of all transistors in a cluster; n and N represent the set of all nets in a standard cell, respectively; p represents the pin of the net; r(t) represents the row number of transistor t, w i represents the width of the i-th row, y(p) represents the y coordinate of a pin; r(C) is the row number representing cluster C.

5. The hierarchical transistor layout method for multiple rows of standard cells according to claim 4, wherein: The width of the i-th row is estimated using the Euler path, expressed as: w i =max(w i,n ,w i,p ) Where w(t) represents the width of transistor t, odd(G) represents the number of odd-degree nodes in the graph constructed by NMOS or PMOS, and DDB represents the length of the dummy tube introduced when adjacent transistors cannot share the source and drain, that is, the double diffusion fracture.

6. The hierarchical transistor layout method for multiple rows of standard cells according to claim 1, wherein: In the local single-row layout process, a local single-row transistor layout is generated for each transistor cluster using a method of searching an Euler path or a method based on SMT.

7. The hierarchical transistor layout method for multiple rows of standard cells according to claim 1, wherein: In the multi-row overall layout process, a simulated annealing algorithm is specifically used to simultaneously sort the local single-row layouts of each transistor cluster in each row.

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