2.5D interposer copper exposed process and packaging structure

Abstract

The present application provides a 2.5D interposer copper exposure process and packaging structure. The 2.5D interposer copper exposure process includes providing an interposer with a conductive column; the interposer includes a first surface and a second surface arranged opposite to each other; the edges of the first surface and the second surface are respectively provided with a first groove and a second groove, the depth of the first groove is H1, the depth of the second groove is H2, and the spacing between the bottoms of the first groove and the second groove is H3. The bottom of the second groove is flush with the second end face. The second surface is ground to expose the second end face; the grinding thickness is H2. The interposer is thinned from the second surface so that the protruding height of the conductive column is H3. Then, an electrical connection portion electrically connected to the conductive column is formed. In this way, the grinding thickness and the thinning thickness can be easily controlled to ensure that the protruding height of all conductive columns is consistent, which is conducive to improving the subsequent wiring accuracy, thereby improving the packaging efficiency and packaging quality.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D interposer copper exposure process and packaging structure. Background Art

[0002] In existing interposer copper exposure processes, the interposer surface is directly ground, with the grinding depth controlled by the machine. This lacks a positioning reference design on the interposer, and the interposer edges are prone to collapse during the grinding process. The smoothness of the entire ground surface is difficult to control, affecting the total thickness variation (TTV) and the consistency of the exposed copper height. Summary of the Invention

[0003] The purpose of the present invention is to provide a 2.5D interposer copper exposure process and packaging structure, which can effectively control the grinding depth and thinning thickness, ensure the consistency of the exposed copper height, and improve the packaging quality and packaging efficiency.

[0004] In a first aspect, the present invention provides a 2.5D interposer copper exposure process, comprising:

[0005] An interposer having a conductive pillar is provided; wherein the height of the conductive pillar is less than the thickness of the interposer; the conductive pillar includes a first end face and a second end face disposed opposite to each other; the first end face is flush with a surface of the interposer, and the second end face is located inside the interposer;

[0006] The interposer includes a first surface and a second surface disposed opposite to each other; a first groove is provided at an edge of the first surface, and a second groove is provided at an edge of the second surface; the first groove has a depth of H1, the second groove has a depth of H2, and the distance between the bottoms of the first groove and the second groove is H3; the bottom of the second groove is flush with the second end surface;

[0007] mounting a first carrier on the first surface;

[0008] Grinding the second surface to expose the second end surface; the grinding thickness is H2;

[0009] Thinning the interposer from the second surface so that the second end surface of the conductive pillar protrudes from the second surface; the protrusion height is H3;

[0010] forming a deposition layer on the second surface;

[0011] An electrical connection portion electrically connected to the conductive pillar is formed on the deposition layer.

[0012] In an optional embodiment, in the step of mounting the first carrier on the first surface:

[0013] A bonding adhesive is formed between the first surface and the first carrier; the bonding adhesive fills the first groove;

[0014] The step of thinning the interposer from the second surface comprises:

[0015] The second surface of the interposer is etched, wherein the bonding adhesive serves as an etching stop layer.

[0016] In an optional embodiment, before the step of mounting the first carrier on the first surface, the method further includes:

[0017] A barrier layer is formed at the bottom of the first groove.

[0018] In an optional embodiment, the step of forming a barrier layer at the bottom of the first groove includes:

[0019] Applying protective glue to the first surface; the protective glue exposes the first groove;

[0020] forming a barrier layer at the bottom of the first groove;

[0021] The protective glue is removed.

[0022] In an optional embodiment, in the step of mounting the first carrier on the first surface, the bonding glue is located on a side of the barrier layer away from the groove bottom;

[0023] The step of thinning the interposer from the second surface comprises:

[0024] The second surface of the interposer is etched, wherein the barrier layer serves as an etching stop layer.

[0025] In an optional embodiment, the step of forming a deposition layer on the second surface includes:

[0026] forming a deposition layer on the second surface, wherein the thickness of the deposition layer is greater than the protruding height of the conductive pillar;

[0027] The deposition layer and the conductive pillar are ground to make the deposition layer flush with the second end surface.

[0028] In an optional embodiment, the protruding height H3 of the conductive pillar is 2 microns to 30 microns.

[0029] In an optional embodiment, the step of forming an electrical connection portion electrically connected to the conductive pillar on the deposition layer includes:

[0030] forming a first wiring layer electrically connected to the conductive pillar;

[0031] forming a first bump electrically connected to the first wiring layer;

[0032] After the step of forming a wiring layer electrically connected to the conductive pillar on the deposition layer, the method further includes:

[0033] Mounting a second carrier or mounting a chip on the side having the first bump;

[0034] removing the first carrier;

[0035] forming a second wiring layer electrically connected to the conductive pillar on one side of the first surface;

[0036] A second bump electrically connected to the second wiring layer is formed.

[0037] In an optional embodiment, before the step of mounting the first carrier on the first surface, the method further includes:

[0038] forming a barrier layer at the bottom of the first groove; wherein the barrier layer is a metal layer;

[0039] After the step of removing the first carrier, the method further includes:

[0040] An electrostatic clamp is mounted on the barrier layer.

[0041] In an optional embodiment, after the step of forming an electrical connection portion electrically connected to the conductive pillar on the deposition layer, the method further includes:

[0042] The intermediary layer is cut to separate into individual products; wherein the first groove on the intermediary layer is removed by cutting.

[0043] In a second aspect, the present invention provides a packaging structure manufactured using the 2.5D interposer copper-exposed process described in any one of the aforementioned embodiments.

[0044] In an optional embodiment, the method includes:

[0045] The substrate includes an interposer having a conductive column disposed therein; a first electrical connection electrically connected to the conductive column is disposed on one side of the interposer, and a second electrical connection electrically connected to the conductive column is disposed on the other side of the interposer; the first electrical connection and the second electrical connection respectively include any one or more of a wiring layer, a connection pad, an under ball pad, and a bump.

[0046] In an optional embodiment, the first surface of the interposer is provided with an insulating layer, and the second surface of the interposer is provided with a deposition layer; the first electrical connection portion includes a connection pad, a wiring layer, a ball pad and a first bump connected in sequence; the second electrical connection portion includes a connection pad, a ball pad and a second bump connected in sequence.

[0047] In an optional embodiment, the method further includes:

[0048] a chip, wherein the chip is electrically connected to the first bump and / or the second bump;

[0049] A plastic package is connected to the substrate and covers the chip.

[0050] In an optional embodiment, the chip is electrically connected to the second bump; and the chip is disposed on a side of the interposer away from the deposition layer.

[0051] In an optional embodiment, the diameter of the first bump is greater than the diameter of the second bump. In an optional embodiment, the height of the conductive pillar protruding from the deposited layer is H, where H=H3-H4; H3 is the height of the second end surface of the conductive pillar protruding from the second surface, and H4 is the grinding height of the conductive pillar during the step of grinding the deposited layer and the conductive pillar.

[0052] In an optional embodiment, the method further includes:

[0053] A substrate, wherein the substrate is provided with a pad; the first bump is mounted on the pad;

[0054] components, the components being electrically connected to the substrate;

[0055] The metal ring is connected to the substrate and is arranged around the outer periphery of the substrate.

[0056] The 2.5D interposer copper exposure process and packaging structure provided by the embodiments of the present invention have the following beneficial effects:

[0057] The 2.5D interposer copper exposure process provided by the present invention creates grooves on both sides of the interposer's edge and uses the depth H2 of the second groove to control the interposer's polishing thickness. The interposer's edge thickness H3 is then used to control the thinning thickness, ensuring consistent exposed heights for all conductive pillars and improving the consistency of exposed copper height. This improves subsequent routing accuracy, packaging efficiency, and packaging quality.

[0058] The packaging structure provided by the embodiment of the present invention adopts the above-mentioned 2.5D interposer copper-exposed process, has high wiring accuracy, high packaging efficiency, and reliable structure, which is conducive to improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 A schematic diagram of a manufacturing process of an interposer provided in a 2.5D interposer copper-exposed process according to an embodiment of the present invention;

[0061] Figure 2 for Figure 1 A partial enlarged schematic diagram of point A in the middle;

[0062] Figure 3 This is a schematic diagram of a 2.5D interposer copper-exposed process according to an embodiment of the present invention;

[0063] Figure 4 The second process diagram of the 2.5D interposer copper exposure process provided by an embodiment of the present invention;

[0064] Figure 5 The third process diagram of the 2.5D interposer copper exposure process provided by an embodiment of the present invention;

[0065] Figure 6 The fourth process diagram of the 2.5D interposer copper exposure process provided by an embodiment of the present invention;

[0066] Figure 7 A schematic diagram of a process for mounting a second carrier in a 2.5D interposer copper exposure process according to an embodiment of the present invention;

[0067] Figure 8 A schematic diagram of a process for forming a barrier layer in a 2.5D interposer copper exposure process provided by an embodiment of the present invention;

[0068] Figure 9 A schematic diagram of a packaging structure provided by an embodiment of the present invention;

[0069] Figure 10 Another structural schematic diagram of the packaging structure provided by an embodiment of the present invention;

[0070] Figure 11 A schematic diagram of a structure in which multiple chips are mounted in a packaging structure provided by an embodiment of the present invention;

[0071] Figure 12 A schematic diagram of the structure of the connection between the packaging structure and the substrate provided by an embodiment of the present invention.

[0072] Icons: 110 - interposer; 111 - first surface; 112 - second surface; 113 - first groove; 114 - second groove; 115 - insulating layer; 120 - conductive pillar; 121 - first end surface; 122 - second end surface; 130 - first carrier; 131 - bonding adhesive; 133 - second carrier; 141 - deposition layer; 142 - first dielectric layer; 143 - first wiring layer; 144 - second dielectric layer; 145 - first bump ;146-first base glue;147-connecting pad;148-under-ball pad;150-plastic package;151-chip;1511-first chip;1512-second chip;1513-third chip;152-second wiring layer;153-second bump;160-barrier layer;161-protective glue;170-substrate;200-baseboard;210-pad;220-component;230-metal ring;240-second base glue. DETAILED DESCRIPTION

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0074] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0075] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0076] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0077] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0078] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0079] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0080] A 2.5D interposer copper exposure process proposed in an embodiment of the present invention can improve the consistency of exposed copper height and reduce the overall thickness deviation (TTV) of the interposer, which is beneficial to improving subsequent wiring accuracy and packaging quality.

[0081] Please combine Figure 1 and Figure 2 The 2.5D interposer copper exposed process includes:

[0082] An interposer 110 is provided having a conductive pillar 120. The height of the conductive pillar 120 is less than the thickness of the interposer 110. The conductive pillar 120 includes a first end surface 121 and a second end surface 122 disposed opposite each other. The interposer 110 includes a first surface 111 and a second surface 112 disposed opposite each other. The first end surface 121 is flush with the first surface 111 of the interposer 110, and the second end surface 122 is located within the interposer 110. A first groove 113 is defined at the edge of the first surface 111, and a second groove 114 is defined at the edge of the second surface 112. The first groove 113 has a depth of H1, and the second groove 114 has a depth of H2. The bottom of the second groove 114 is flush with the second end surface 122. The distance between the bottoms of the first groove 113 and the second groove 114 is H3, meaning that the remaining thickness of the interposer 110 after the grooves are formed is H3.

[0083] Optionally, the material of the interposer 110 can be a silicon-based or germanium-based substrate material, or a substrate made of silicon oxide, phosphosilicate glass, fluorine-containing glass, or glass. The conductive pillars 120 can be formed by electroplating metal after opening holes in the interposer 110. The conductive pillars 120 are mostly made of copper, but can also be made of graphene or other metals. It is understood that the first surface 111 of the interposer 110 is provided with an insulating layer 115, and the insulating layer 115 includes at least one of silicon oxide, silicon dioxide, silicon nitride, and silicon oxynitride. The insulating layer 115 can be prepared in advance on the interposer 110. For example, the insulating layer 115 can be formed after the holes are opened or before electroplating metal copper to form the conductive pillars 120.

[0084] It should be understood that the first groove 113 and the second groove 114 can be formed simultaneously when producing the interposer 110 , or can be formed by performing ring cutting or laser grooving on the interposer 110 .

[0085] Optionally, the thickness of the intermediate layer 110 , ie, the sum of H1 , H2 , and H3 , is less than or equal to 1000 micrometers, such as 400 micrometers to 800 micrometers, and may be 400 micrometers, 600 micrometers, 700 micrometers, or 800 micrometers.

[0086] Please combine Figure 3 and Figure 4 , the first carrier 130 is mounted on the first surface 111. Optionally, a bonding glue 131 is formed between the first surface 111 and the first carrier 130; the intermediary layer 110 and the first carrier 130 are fixed by the bonding glue 131. It can be understood that the bonding glue 131 is first applied to the first carrier 130 or the intermediary layer 110, and then the first carrier 130 and the intermediary layer 110 are pasted together. After the first carrier 130 is mounted, the bonding glue 131 will fill the first groove 113. The provision of the first groove 113 can increase the bonding area between the intermediary layer 110 and the first carrier 130, improve the bonding reliability, and enhance the bonding force between the first carrier 130 and the intermediary layer 110. In addition, the first groove 113 has a greater glue holding capacity, which can prevent the bonding glue 131 from overflowing to the second surface 112 of the intermediary layer 110, thereby avoiding contamination of subsequent processes.

[0087] The second surface 112 is ground to expose the second end surface 122; the grinding thickness is H2. In this embodiment, the bottom of the second groove 114 is flush with the second end surface 122. When the interposer 110 is ground to a thickness equal to the depth H2 of the second groove 114, the second groove 114 is ground away, thereby making the second end surface 122 of the conductive pillar 120 flush with the second surface 112 of the interposer 110, thereby exposing the second end surface 122 of the conductive pillar 120. In this embodiment, the provision of the second groove 114 facilitates control of the grinding depth. Using the bottom of the second groove 114 as a reference plane for the grinding surface improves grinding accuracy and efficiency, and helps reduce the overall TTV of the interposer 110 after grinding.

[0088] Alternatively, the grinding process may be chemical grinding or diamond grinding. If chemical grinding is used, a chemical grinding solution such as ammonia, HF acid, or citric acid may be used to grind the interposer 110 under the pressure of a polishing pad and centrifugal force to expose the second end surface 122 of the conductive pillar 120.

[0089] In this embodiment, H2 is smaller than H1, which can reduce the grinding thickness and thus improve the grinding efficiency and grinding accuracy.

[0090] The interposer 110 is thinned from the second surface 112 so that the second end surface 122 of the conductive pillar 120 protrudes from the second surface 112; the protrusion height is H3. Optionally, an etching process is employed to etch the polished second surface 112 of the interposer 110 to achieve the thinning purpose. During the etching and thinning of the second surface 112 of the interposer 110, the bonding adhesive 131 can serve as an etching stop layer. This allows for better control of the etching depth, namely, the protrusion height (also called the exposed copper height) of the conductive pillar 120 above the interposer 110. Furthermore, the bonding adhesive 131 protects the sidewalls of the interposer 110 (such as the walls of the first groove 113) from being attacked by etching gases.

[0091] Optionally, dry etching, chemical etching, or laser grooving can be used to thin the interposer 110. If dry etching is used, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or hydrogen (H2) can be used to thin the interposer 110. If chemical etching is used, a mixture of hydrofluoric acid (HF), buffered oxide etchant, sulfuric acid (H2SO4), and hydrogen peroxide (H2O2) can be used to thin the interposer 110, thereby causing the second end surface 122 of the conductive pillar 120 to protrude from the second surface 112 of the interposer 110. Optionally, the protruding height H3 of the conductive pillar 120 is 2 to 30 microns.

[0092] A deposition layer 141 is formed on the second surface 112. The deposition layer 141 can be formed by vapor deposition methods such as PVCD, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The deposition layer 141 can be made of at least one of silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, silicon oxynitride, and an organic dielectric material.

[0093] Optionally, a deposition layer 141 is formed on the second surface 112. The thickness of the deposition layer 141 is greater than the protruding height of the conductive pillar 120. This means that the deposition layer 141 will cover the second end surface 122 of the conductive pillar 120. Therefore, the deposition layer 141 needs to be polished to expose the second end surface 122 of the conductive pillar 120. It should be noted that during the actual polishing of the deposition layer 141, only the deposition layer 141 can be polished away, leaving the second end surface 122 of the conductive pillar 120 undamaged, so that the deposition layer 141 and the second end surface 122 are flush. However, this can be more challenging to control. Alternatively, in some embodiments, the deposition layer 141 can be polished away while a portion of the conductive pillar 120 is polished away, so that the deposition layer 141 and the second end surface 122 are flush. Optionally, the polishing thickness of the conductive pillar 120 is smaller, less than 100 angstroms, to reduce the processing complexity. It is understood that polishing can change the roughness of the second end surface 122, which helps improve the bonding between the subsequent wiring layer and the conductive pillar 120. The deposition layer 141 can be a single layer or multiple layers, which is not specifically limited here.

[0094] A wiring layer electrically connected to the conductive pillars 120 is formed on the deposited layer 141. Optionally, a first dielectric layer 142 is first formed on the deposited layer 141. The first dielectric layer 142 is exposed and developed to form a patterned layer opening, exposing the second end surface 122 of the conductive pillars 120. A metal layer is then filled into the patterned layer opening by electroplating or other deposition methods to form a first wiring layer 143. The first wiring layer 143 is electrically connected to the conductive pillars 120. It should be noted that the number of layers in the first wiring layer 143 is not limited and can be one, two, three, or more. For multi-layer wiring, the aforementioned steps of forming the first dielectric layer 142, exposing and developing the opening, and electroplating metal are repeated to electrically connect the multiple wiring layers. Alternatively, in some embodiments, connection pads 147 may be first formed on the conductive pillars 120, and then the wiring layer is formed on the connection pads 147. The width or diameter of the connection pads 147 is greater than the width or diameter of the conductive pillars 120. The connection pads 147 can increase the contact area between the wiring layer and the conductive pillars 120 , thereby improving the conductivity and achieving better electrical transmission performance.

[0095] Optionally, a second dielectric layer 144 is formed on the first dielectric layer 142 , and windows are formed on the second dielectric layer 144 by exposure and development. Metal is electroplated in the windows to form first bumps 145 , and the first bumps 145 are electrically connected to the first wiring layer 143 .

[0096] Of course, in some implementations, the under ball pad 148 may be formed only on the conductive pillar 120 , and a ball may be planted on the under ball pad 148 to form the first bump 145 .

[0097] According to actual product requirements, after the first bumps 145 are prepared, the chip 151 can be mounted on the first bumps 145. Alternatively, the second carrier 133 can be mounted on the side with the first bumps 145, the first carrier 130 can be removed, and the process on the first surface 111 of the interposer 110 can be performed.

[0098] Please combine Figure 5 and Figure 6 , taking the mounted chip 151 as an example. The flip chip 151 is mounted on the first bump 145, and the bumps on the flip chip 151 are welded to the first bump 145 to achieve electrical connection. A first base glue 146 is formed on the bottom of the flip chip 151 using a dispensing process. The first base glue 146 is used to protect the welding structure and play an electrical isolation role. Of course, in some embodiments, the mounted chip 151 can also be a upright chip 151, and the electrical connection between the chip 151 and the first bump 145 can be achieved by wire bonding. This is not specifically limited here.

[0099] The plastic-encapsulated chip 151 forms a plastic encapsulation body 150. Plastic encapsulation body 150 covers chip 151, protecting it and the solder joints. Plastic encapsulation body 150 can also replace second carrier 133 during processing of first surface 111 of interposer 110, providing support and cushioning. Optionally, plastic encapsulation body 150 can be thinned to align its surface with the back of chip 151, improving heat dissipation.

[0100] Remove the first carrier 130. Prepare the second wiring layer 152 and the second bump 153 on the side of the first surface 111 of the interposer 110. The method is the same as the formation of the first wiring layer 143 and the first bump 145 mentioned above, and will not be repeated here. The second wiring layer 152 is electrically connected to the conductive column 120, and the second bump 153 is electrically connected to the second wiring layer 152. It should be noted that when performing the preparation process on the side of the first surface 111, in addition to the above-mentioned process of sequentially forming the second wiring layer 152 and the second bump 153; it is also possible to sequentially form the under-ball pad 148 and the second bump 153 on the conductive column 120; or, it is also possible to sequentially form the connecting pad 147, the wiring layer, the under-ball pad 148 and the second bump 153 on the conductive column 120, which is not specifically limited here.

[0101] After preparing the second bumps 153, the interposer 110 is cut to separate the individual products. The first groove 113 on the interposer 110 is removed by cutting. Alternatively, the edge of the interposer 110 can be circumferentially cut to remove the first groove 113 structure, and then cut along the cutting lines to separate the individual products.

[0102] Please combine Figure 7 , taking the case where the chip 151 is not mounted and the second carrier 133 is mounted as an example.

[0103] After forming the first bump 145, a second carrier 133 is mounted on one side of the first bump 145. The first carrier 130 is removed, exposing the first surface 111 of the interposer 110. The first carrier 130 can be removed by debonding methods such as UV irradiation or heating. A second wiring layer 152 and second bumps 153 are formed on the first surface 111 using the same method as described above for forming the first wiring layer 143 and first bump 145, and will not be further described here. The first groove 113 structure on the interposer 110 is then removed by cutting through the edge ring process.

[0104] Please combine Figure 8 Optionally, in some embodiments, before the step of mounting the first carrier 130 on the first surface 111 , the step further includes: forming a barrier layer 160 at the bottom of the first groove 113 .

[0105] For example, a protective adhesive 161 is applied to the first surface 111; the protective adhesive 161 exposes the first groove 113. A barrier layer 160 is formed at the bottom of the first groove 113; and the protective adhesive 161 is then removed. It is understood that the barrier layer 160 can be a metal material, including but not limited to being formed by any process such as vapor deposition PVCD or PVD, CVD, MOCVD, ALD, LPCVD or PECVD. The barrier layer 160 can be made of titanium dioxide or metal materials such as titanium, tantalum, and tungsten. If the barrier layer 160 is made of a metal material, it can serve as an electrostatic dissipator to dissipate electrostatic ions in the interposer 110 and prevent the electrostatic ions from breaking through the wiring layer.

[0106] Furthermore, after the barrier layer 160 is provided, the first carrier 130 is mounted, and the bonding adhesive 131 contacts the barrier layer 160, that is, the bonding adhesive 131 is located on the side of the barrier layer 160 away from the bottom of the first groove 113. In this way, when the second surface 112 of the intermediary layer 110 is subsequently etched to make the conductive pillar 120 protrude from the intermediary layer 110, the barrier layer 160 can serve as an etching stop layer. The barrier layer 160 can effectively prevent the bonding adhesive 131 from being affected by etching gases or chemicals, and prevent the bonding adhesive 131 from being delaminated. It should be noted that during grinding, the bonding adhesive 131 will be squeezed due to the pressing effect of the polishing pad. If the bonding adhesive 131 is delaminated or affected by etching gases, chemicals, etc., the adhesive layer is likely to collapse or become voided, thereby affecting the overall thickness deviation TTV of the intermediary layer 110, which is not conducive to the subsequent high-precision grinding of the deposited layer 141. Furthermore, after the barrier layer 160 is provided, it can support the edge of the interposer 110 and improve the edge strength. In subsequent grinding processes, it is beneficial to improve grinding accuracy, reduce TTV, and improve the consistency of exposed copper height.

[0107] Optionally, the protective adhesive 161 can cover the area on the first surface 111 except the first groove 113 to prevent the barrier layer 160 from contaminating the surface of the interposer 110 where the first end surface 121 of the conductive pillar 120 is located. The protective adhesive 161 can be formed using a spin coating process and can be a photoresist. After forming the barrier layer 160, the protective adhesive 161 can be removed using a developer or a stripping solution.

[0108] Optionally, if a barrier layer 160 is formed at the bottom of the first groove 113 and the barrier layer 160 is a metal layer, after removing the first carrier 130, the method further includes attaching an electrostatic clamp to the barrier layer 160. This effectively dissipates static ions on the first wiring layer 143 and the interposer 110, achieving static discharge and preventing problems such as electrostatic interference and electrostatic breakdown. It is understood that the electrostatic clamp only needs to be in contact with the barrier layer 160 to dissipate static electricity. After dissipating the static electricity, the clamp can be removed.

[0109] Please combine Figure 9 , an embodiment of the present invention further provides a packaging structure, which is manufactured using a 2.5D interposer copper-exposed process as described in any of the aforementioned embodiments. The packaging structure includes a substrate 170, a first bump 145, and a second bump 153. The substrate 170 includes an interposer 110, a first dielectric layer 142, and a second dielectric layer 144. A conductive pillar 120 is provided in the interposer 110; a first wiring layer 143 electrically connected to the conductive pillar 120 is provided on one side of the interposer 110, and a second wiring layer 152 electrically connected to the conductive pillar 120 is provided on the other side of the interposer 110. The first bump 145 is electrically connected to the first wiring layer 143; the second bump 153 is electrically connected to the second wiring layer 152.

[0110] The first dielectric layers 142 on either side of the interposer 110 are used to insulate and protect the first wiring layer 143 and the second wiring layer 152, respectively. The second dielectric layers 144 on either side of the interposer 110 are used to insulate and protect the first bumps 145 and the second bumps 153, respectively. The materials of the first and second dielectric layers 142 and 144 can be the same as those of the interposer 110, or can be any one or more of polyimide and benzocyclobutene.

[0111] Combine Figure 10 Optionally, an insulating layer 115 is provided on the first surface 111 of the interposer 110 to improve insulation between the plurality of conductive pillars 120. A deposition layer 141 is provided on the second surface 112 of the interposer 110 to improve insulation performance. The deposition layer 141 can be a single layer or multiple layers, and is not specifically limited here.

[0112] One side of the second end face 122 of the conductive pillar 120 is connected to a first electrical connection portion, and a dielectric layer is used to isolate and protect the multiple first electrical connections. The first electrical connection portion includes any one or more of a wiring layer, a connecting pad 147, an under-ball pad 148, and a bump. Optionally, the first electrical connection portion includes an electrically connected first wiring layer 143 and a first bump 145, and the first wiring layer 143 is electrically connected to the conductive pillar 120. Alternatively, the first electrical connection portion includes an electrically connected under-ball pad 148 and a first bump 145, and the under-ball pad 148 is electrically connected to the conductive pillar 120. Alternatively, the first electrical connection portion includes a connecting pad 147, a first wiring layer 143, an under-ball pad 148, and a first bump 145, which are electrically connected in sequence, and the connecting pad 147 is electrically connected to the conductive pillar 120. Optionally, the width or diameter D2 of the connecting pad 147 is greater than the width or diameter D1 of the conductive pillar 120. The connection pads 147 may increase the contact area between the first wiring layer 143 and the conductive pillars 120 , thereby improving the conductivity and achieving better electrical transmission performance.

[0113] One side of the first end surface 121 of the conductive pillar 120 is connected to the second electrical connection portion, and the structure of the second electrical connection portion is similar to that of the first electrical connection portion. Various structures of the first electrical connection portion and the second electrical connection portion can be arbitrarily combined.

[0114] Optionally, in this package structure, the thickness D0 of the interposer 110 is less than or equal to 150 microns, such as 120 microns, 100 microns, 90 microns, or 80 microns, preferably 100 microns. The ratio of the diameter D1 of the conductive pillar 120 to the thickness D0 of the interposer 110 is 1:5 to 1:20.

[0115] Optionally, the diameter D2 of the connection pad 147 is greater than D1. It should be noted that if D1 is less than 50 microns, when preparing the first wiring layer 143 or the second wiring layer 152, it is necessary to first form the connection pad 147 on the end surface of the conductive column 120, and then prepare the wiring layer to improve the connection reliability of the wiring layer. If D1 is greater than or equal to 50 microns, the preparation of the connection pad 147 can be omitted, and the wiring layer can be formed directly on the end surface of the conductive column 120. Optionally, the chip 151 is mounted on one side or both sides of the substrate 170, and the chip 151 is electrically connected to the first bump 145 and / or the second bump 153.

[0116] The package structure also includes a plastic encapsulation body 150, which is connected to the substrate 170 and covers the chip 151. The plastic encapsulation body 150 protects the chip 151. The plastic encapsulation body 150 can be flush with the back of the chip 151 to improve heat dissipation. Of course, the plastic encapsulation body 150 can also completely cover the back of the chip 151, which is not specifically limited here.

[0117] Optionally, the height of the conductive pillar 120 protruding from the deposited layer 141 is H, where H=H3-H4; H3 is the height of the second end surface 122 of the conductive pillar 120 protruding from the second surface 112, and H4 is the polished height of the conductive pillar 120 during the polishing step of the deposited layer 141 and the conductive pillar 120. H4 is less than 100 angstroms.

[0118] Please combine Figure 11 It should be understood that multiple chips 151 can be mounted on the substrate 170 to improve integration. The multiple chips 151 can be chips 151 of the same type or chips 151 of different types.

[0119] Optionally, chip 151 includes a first chip 1511, a second chip 1512, and a third chip 1513. The third chip 1513 is disposed between the first chip 1511 and the second chip 1512, or between multiple first chips 1511, or between multiple second chips 1512. The third chip 1513 is a dummy chip. The material of the third chip 1513 can be any one or more of silicon, germanium, ceramic, glass, aluminum, and gallium nitride. The third chip 1513 is not electrically connected to the substrate 170. When the signal lines between chips 151 are close, parasitic capacitance, power supply noise, and capacitive coupling may exist between the signal lines. The provision of the third chip 1513 can increase the distance between the signal lines between the chips, reducing problems such as parasitic capacitance, power supply noise, and capacitive coupling. The first chip 1511 and the second chip 1512 can be different types of chips, such as a SOC chip, an HBM chip, and an RF chip. In this embodiment, the first chip 1511 is a SOC chip, the second chip 1512 is an HBM chip, the first chip 1511 is located in the middle, the second chip 1512 is located on the periphery of the first chip 1511, and the third chip 1513 is provided between adjacent second chips 1512. Of course, the type, quantity, and distribution of the chips 151 can be flexibly adjusted according to actual product requirements.

[0120] Please combine Figure 12 Optionally, the packaging structure further includes a substrate 200, a component 220, and a metal ring 230. The substrate 200 is provided with a soldering pad 210; the side of the substrate 170 away from the plastic package body 150 is mounted on the soldering pad 210. It can be understood that if the first bump 145 is mounted with a chip 151, the second bump 153 is soldered to the soldering pad 210. If the second bump 153 is mounted with a chip 151, the first bump 145 is soldered to the soldering pad 210. The component 220 is electrically connected to the substrate 200. The metal ring 230 is connected to the substrate 200 and is arranged around the outer periphery of the substrate 170. It should be noted that if the metal ring 230 is electrically connected to the substrate 200, a shielding barrier can be formed, and heat dissipation performance and warping prevention can be improved. Alternatively, if the metal ring 230 is adhesively fixed to the substrate 200, there is no electrical connection between the two, and the metal ring 230 plays a role in heat dissipation and warping prevention.

[0121] Optionally, a second underfill 240 is provided between the bottom of the substrate 170 and the base plate 200. The second underfill 240 is used to protect the soldering structure of the second bump 153 and the pad 210. The second underfill 240 can selectively climb to the sidewall of the substrate 170 or the sidewall of the plastic package 150.

[0122] Optionally, in some embodiments, the first bump 145 is soldered to the substrate 200, and the second bump 153 is soldered to the chip 151. In other words, the chip 151 is mounted on the side of the interposer 110 away from the deposition layer 141. This arrangement can increase the distance between the chip 151 and the first wiring layer 143, reduce capacitance effects or parasitic effects, and reduce electron migration.

[0123] The diameter D3 of the first bump 145 is greater than the diameter D4 of the second bump 153. D3 is greater than 50 microns, such as 65 microns, 80 microns or 110 microns. D4 is less than 40 microns, such as 30 microns, 25 microns or 15 microns. The design of the first bump 145 is conducive to meeting the advanced C4 interconnection technology. C4 refers to Controlled Collapse Chip Connection, which means controlled collapse chip connection. Preferably, no wiring layer is provided on one side of the first bump 145, and a connecting pad 147 and an under-ball pad 148 can be directly formed on the second end surface 122 of the conductive column 120, and the first bump 145 is formed on the under-ball pad 148. This can improve the electrical transmission performance and reduce the parasitic effects and capacitance effects caused by the wiring layer. The under-ball pad 148 uses a UBM metal layer, and the UBM metal layer can be any one or more of titanium, copper, nickel and tungsten. It is understandable that a connecting pad 147 may also be provided between the under ball pad 148 and the conductive pillar 120 to increase the contact area between the under ball pad 148 and the conductive pillar 120 and make the electrical connection more reliable.

[0124] In summary, the 2.5D interposer copper-exposed process and packaging structure provided by the embodiments of the present invention have the following beneficial effects, including:

[0125] The 2.5D interposer copper exposure process provided in an embodiment of the present invention controls the grinding thickness of the interposer 110 by grooves on both sides of the edge of the interposer 110 and using the depth H2 of the second groove 114. The thickness H3 of the edge interposer 110 is used to control the thinning thickness to ensure that the exposed height of all conductive pillars 120 is consistent, thereby improving the consistency of the exposed copper height, which is conducive to improving the subsequent wiring accuracy, packaging efficiency and packaging quality. The provision of the first groove 113 and the second groove 114 is conducive to improving the bonding between the carrier and the interposer 110. By providing the barrier layer 160, it can play a role in static dissipation and edge support, which is conducive to improving the grinding accuracy and ensuring the consistency of the exposed copper height.

[0126] The packaging structure provided by the embodiment of the present invention adopts the above-mentioned 2.5D interposer copper-exposed process, has high wiring accuracy, high packaging efficiency, and reliable structure, which is conducive to improving product performance.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the scope of protection of the present invention.

Claims

1. A 2.5D interposer copper exposure process, characterized in that: include: An interposer having a conductive pillar is provided; wherein the height of the conductive pillar is less than the thickness of the interposer; the conductive pillar includes a first end surface and a second end surface disposed opposite to each other; the interposer includes a first surface and a second surface disposed opposite to each other; the first end surface is flush with the first surface of the interposer, and the second end surface is located inside the interposer; A first groove is provided at the edge of the first surface, and a second groove is provided at the edge of the second surface. The depth of the first groove is H1, the depth of the second groove is H2, and the distance between the bottoms of the first groove and the second groove is H3; the bottom of the second groove is flush with the second end surface; mounting a first carrier on the first surface; Grinding the second surface to expose the second end surface; the grinding thickness is H2; Thinning the interposer from the second surface so that the second end surface of the conductive pillar protrudes from the second surface; the protrusion height is H3; forming a deposition layer on the second surface; An electrical connection portion electrically connected to the conductive pillar is formed on the deposition layer.

2. The 2.5D interposer copper exposure process according to claim 1, wherein: In the step of mounting the first carrier on the first surface: A bonding adhesive is formed between the first surface and the first carrier; the bonding adhesive fills the first groove; The step of thinning the interposer from the second surface comprises: The second surface of the interposer is etched, wherein the bonding adhesive serves as an etching stop layer.

3. The 2.5D interposer copper exposure process according to claim 2, characterized in that: Before the step of mounting the first carrier on the first surface, the method further includes: A barrier layer is formed at the bottom of the first groove.

4. The 2.5D interposer copper exposure process according to claim 3, characterized in that: The step of forming a barrier layer at the bottom of the first groove comprises: Applying protective glue to the first surface; the protective glue exposes the first groove; forming a barrier layer at the bottom of the first groove; The protective glue is removed.

5. The 2.5D interposer copper exposure process according to claim 3, characterized in that: In the step of mounting the first carrier on the first surface, the bonding glue is located on a side of the barrier layer away from the groove bottom; The step of thinning the interposer from the second surface comprises: The second surface of the interposer is etched, wherein the barrier layer serves as an etching stop layer.

6. The 2.5D interposer copper exposure process according to claim 1, wherein: The step of forming a deposition layer on the second surface comprises: forming a deposition layer on the second surface, wherein the thickness of the deposition layer is greater than the protruding height of the conductive pillar; The deposition layer and the conductive pillar are ground to make the deposition layer flush with the second end surface.

7. The 2.5D interposer copper exposure process according to claim 1, wherein: The protruding height H3 of the conductive pillar is 2 micrometers to 30 micrometers; and / or H1 is greater than H2.

8. The 2.5D interposer copper exposure process according to claim 1, wherein: The step of forming an electrical connection portion electrically connected to the conductive pillar on the deposition layer includes: forming a first wiring layer electrically connected to the conductive pillar; forming a first bump electrically connected to the first wiring layer; After the step of forming a wiring layer electrically connected to the conductive pillar on the deposition layer, the method further includes: Mounting a second carrier or mounting a chip on the side having the first bump; removing the first carrier; forming a second wiring layer electrically connected to the conductive pillar on one side of the first surface; A second bump electrically connected to the second wiring layer is formed.

9. The 2.5D interposer copper exposure process according to claim 8, characterized in that: Before the step of mounting the first carrier on the first surface, the method further includes: forming a barrier layer at the bottom of the first groove; wherein the barrier layer is a metal layer; After the step of removing the first carrier, the method further includes: An electrostatic clamp is mounted on the barrier layer.

10. The 2.5D interposer copper exposure process according to any one of claims 1 to 9, characterized in that: After the step of forming an electrical connection portion electrically connected to the conductive pillar on the deposition layer, the method further includes: The intermediary layer is cut to separate into individual products; wherein the first groove on the intermediary layer is removed by cutting.

11. A packaging structure, characterized in that: The method is manufactured by adopting the 2.5D interposer copper exposure process according to any one of claims 1 to 10.

12. The packaging structure according to claim 11, wherein: include: The substrate comprises an interposer, wherein the interposer is provided with a conductive column; a first electrical connection portion electrically connected to the conductive column is provided on one side of the interposer, and a second electrical connection portion electrically connected to the conductive column is provided on the other side of the interposer; The first electrical connection portion and the second electrical connection portion respectively include any one or more of a wiring layer, a connection pad, an under ball pad, and a bump.

13. The packaging structure according to claim 12, wherein: The first surface of the interposer is provided with an insulating layer, and the second surface of the interposer is provided with a deposition layer; the first electrical connection portion includes a connection pad, an under-ball pad and a first bump connected in sequence; the second electrical connection portion includes a connection pad, a wiring layer, an under-ball pad and a second bump connected in sequence.

14. The packaging structure according to claim 13, wherein: Also includes: a chip, wherein the chip is electrically connected to the first bump and / or the second bump; A plastic package is connected to the substrate and covers the chip.

15. The packaging structure according to claim 14, wherein: The chip is electrically connected to the second bump; the chip is arranged on a side of the intermediary layer away from the deposition layer.

16. The packaging structure according to claim 15, wherein: The diameter of the first bump is greater than the diameter of the second bump.

17. The packaging structure according to claim 15, wherein: The chip includes a first chip, a second chip and a third chip. The third chip is arranged between the first chip and the second chip, or between multiple first chips, or between multiple second chips; the third chip is a dummy chip.

18. The packaging structure according to claim 12, wherein: The height of the conductive column protruding from the deposited layer is H, H=H3-H4; H3 is the protruding height of the second end face of the conductive column protruding from the second surface, and H4 is the grinding height of the conductive column in the step of grinding the deposited layer and the conductive column.

19. The packaging structure according to claim 16, wherein: Also includes: A substrate, wherein the substrate is provided with a pad; the first bump is mounted on the pad; components, the components being electrically connected to the substrate; The metal ring is connected to the substrate and is arranged around the outer periphery of the substrate.

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