Semiconductor structure, forming method thereof and electronic equipment

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and electronic equipment. The semiconductor structure comprises a substrate; an isolation groove is formed in the substrate; the oxide layer is positioned in the isolation groove; the oxide layer is attached to the bottom of the isolation groove, and an edge opening is formed between the oxide layer and the side wall of the isolation groove; the nitride layer is positioned on the oxide layer; and the nitride layer coats the outer surface of the oxide layer and fills the edge opening. Therefore, the edge opening between the oxide layer and the side wall of the isolation groove can be filled, and the problems of polycrystalline silicon bridging defects or GOX breakdown and the like caused by residues formed in the edge opening in the subsequent deposition process are avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a forming method thereof, and electronic equipment. Background Art

[0002] In the general transistor process flow, functional failures caused by device leakage current are common. Failure analysis (FA) is a post-mortem inspection of failed devices. FA inspections have revealed that during the Shallow Trench Isolation (STI) process, residues are easily formed on the sidewalls, inducing polysilicon bridging defects. If the sidewall dimensions are large, the junction between the STI and AA (active areas) is prone to GOX (gate oxide) breakdown or VT (threshold voltage) variation due to poor electric field uniformity at the edge. Summary of the Invention

[0003] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, as well as an electronic device, which can avoid problems such as polysilicon bridging defects or GOX breakdown.

[0004] In order to solve the above technical problems, the technical solutions of this application are as follows:

[0005] According to a first aspect of an embodiment of the present application, there is provided a semiconductor structure, including:

[0006] A substrate having an isolation trench provided therein;

[0007] an oxide layer located in the isolation trench; the oxide layer adheres to the bottom of the isolation trench, and an edge opening is formed between the oxide layer and the sidewall of the isolation trench;

[0008] A nitride layer is located on the oxide layer; the nitride layer covers the outer surface of the oxide layer and fills the edge opening.

[0009] Optionally, the thickness of the oxide layer is greater than the depth of the isolation trench, and the shape of the nitride layer is arc-shaped or trapezoidal.

[0010] Optionally, also include:

[0011] A passivation layer is located on the active area of ​​the substrate; the material of the passivation layer includes a silicon-deuterium chemical bond; the active area is the area on the substrate except the nitride layer.

[0012] Optionally, the nitride layer fills the edge opening, so that a seamless structure is formed between the oxide layer and the sidewall of the isolation trench.

[0013] Optionally, the material of the nitride layer is silicon nitride or a material doped with silicon nitride.

[0014] Optionally, the tensile stress of the active area is greater than a preset stress threshold.

[0015] Optionally, the thickness of the nitride layer is determined based on the size of the transistor formed on the substrate.

[0016] According to a second aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, the method comprising:

[0017] Providing a substrate; an isolation trench is formed in the substrate;

[0018] forming an oxide layer in the isolation trench; the oxide layer adheres to the bottom of the isolation trench, and an edge opening is formed between the oxide layer and the sidewall of the isolation trench;

[0019] A nitride layer is formed on the oxide layer; the nitride layer covers the outer surface of the oxide layer and fills the edge opening.

[0020] Optionally, the thickness of the oxide layer is greater than the depth of the isolation trench, and the shape of the nitride layer is arc-shaped or trapezoidal.

[0021] Optionally, after forming the nitride layer on the oxide layer, the method further includes:

[0022] Deuterium gas is used to passivate the active area of ​​the substrate to form a passivation layer on the active area; the material of the passivation layer includes silicon-deuterium chemical bonds; the active area is the area on the substrate excluding the nitride layer.

[0023] Optionally, forming a nitride layer on the oxide layer includes:

[0024] depositing nitride on the oxide layer, the edge opening, and the active area of ​​the substrate to form an initial nitride layer;

[0025] The initial nitride layer is subjected to a light-free etching process to remove the nitride on the active area, and the nitride layer is formed on the oxide layer.

[0026] Optionally, depositing nitride on the oxide layer, the edge opening, and the active area of ​​the substrate to form an initial nitride layer includes:

[0027] forming a first nitride layer on the oxide layer;

[0028] Filling the edge opening with nitride to form a second nitride layer, so as to form a seamless structure between the oxide layer and the sidewall of the isolation trench;

[0029] depositing nitride on the active area of ​​the substrate to form a third nitride layer;

[0030] The first nitride layer, the second nitride layer and the third nitride layer form an initial nitride layer.

[0031] Optionally, the material of the nitride layer is silicon nitride or a material doped with silicon nitride.

[0032] Optionally, after removing the nitride on the active area, the method further includes:

[0033] Ultraviolet light is used to irradiate the active area to enhance the tensile strain capability of the active area.

[0034] Optionally, before forming the oxide layer in the isolation trench, the method further includes:

[0035] The isolation trench is cleaned with a cleaning liquid to remove residues in the process of forming the isolation trench.

[0036] Optionally, the cleaning solution includes at least one or a combination of at least two of the following: hydrochloric acid, phosphoric acid, ammonium fluoride, and hydrofluoric acid.

[0037] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising the semiconductor structure as described above.

[0038] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0039] The present invention provides a semiconductor structure comprising: a substrate; an isolation trench disposed in the substrate; an oxide layer located in the isolation trench; the oxide layer adheres to the bottom of the isolation trench, forming an edge opening between the oxide layer and the sidewalls of the isolation trench; and a nitride layer located on the oxide layer; the nitride layer covers the outer surface of the oxide layer and fills the edge opening. This allows the edge opening between the oxide layer and the sidewalls of the isolation trench to be filled, preventing the formation of residue in the edge opening during subsequent deposition processes, which could lead to problems such as polysilicon bridging defects or GOX breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 This is an example 1 of a top view of a semiconductor structure in the prior art;

[0042] Figure 2 This is a second example of a top view of a semiconductor structure in the prior art;

[0043] Figure 3 is a cross-sectional view of a semiconductor structure in the prior art;

[0044] Figure 4 is a schematic flow chart of a method for forming a semiconductor structure provided by an embodiment of the present invention;

[0045] Figures 5 to 9 is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure provided by an embodiment of the present invention;

[0046] The corresponding reference numerals in the figure are: 1-substrate, 2-active area, 3-connection, 31-first connection, 32-second connection, 4-oxide layer, 5-initial nitride layer, 6-nitride layer. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] "One embodiment" or "embodiment" as referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that spatially relative terms, such as "below", "below", "lower", "on", "upper", "front", "back", "above" and the like may be used herein for ease of description to describe the relationship between one element or feature and another element or feature as illustrated in the figures. This is for ease of description only and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as a limitation on the present application. Spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figures. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted similarly.

[0049] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Moreover, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0051] In the prior art, metal-oxide-semiconductor field-effect transistors (MOSFETs) often have leakage problems. The problems of the prior art metal-oxide-semiconductor field-effect transistors (MOSs) are now described in detail with reference to the accompanying drawings.

[0052] First, let’s introduce MOS:

[0053] MOS transistors are classified as PMOS (P-channel) and NMOS (N-channel), and are insulated gate field-effect transistors. MOS transistors are available in a variety of sizes, including 28nm, 40nm, 65nm, 90nm, 130nm, and 180nm.

[0054] During the manufacturing process of the MOS transistor, a shallow trench isolation (STI) process is generally used to prepare a semiconductor structure, and the MOS transistor is further formed based on the semiconductor structure.

[0055] Figure 1 This is an example of a top view of a semiconductor structure in the prior art, including a substrate 1, an active area (AA) 2, and a first connection 31 between the substrate 1 and the active area 2; through failure analysis (FA) of the gate oxide layer, it was found that the first connection 31 is prone to polysilicon bridging defects.

[0056] Figure 2 This is a second example of a top view of a semiconductor structure in the prior art, including a substrate 1, an active area 2, and a second connection 32 between the substrate 1 and the active area 2. Failure analysis of the gate oxide layer revealed that the second connection 32 is prone to gate oxide (GOX) breakdown or threshold voltage (VT) changes. During application, when voltage is applied to the gate, the electric field coupling effect of the gate oxide layer induces doping inversely to the substrate on the underlying channel surface, enabling the Source / Drain to connect, which is called inversion. The gate voltage at this time is called VT. The thinner the GOX, the easier it is to sense, so the lower the VT. The lower the substrate concentration, the easier it is for the surface to be inverted, so the lower the VT. VT is also related to the quality of the GOX.

[0057] Figure 3 This is a cross-sectional view of a semiconductor structure in the prior art, including a substrate 1 having an isolation trench therein, an oxide layer 4 formed in the isolation trench, and a connection 3 formed between an active area 2 between the oxide layer 4 and the substrate 1 and the substrate 1; this structure is prone to polysilicon bridging defects, GOX breakdown, or VT changes.

[0058] In order to solve the problems of polysilicon bridging defects, GOX breakdown or VT change in the prior art, the embodiments of the present application provide a semiconductor structure and a method for forming the same, and an electronic device to solve the above problems in the prior art.

[0059] For the purpose of the following detailed description, it should be understood that the present invention may adopt various alternative variations and step sequences, unless expressly provided otherwise. In addition, except in any operating examples, or when otherwise indicated, all numerals of the amount of the ingredients used in the specification and claims should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise indicated, the numerical parameters set forth in the following specification and the appended claims are approximate values ​​that vary according to the desired performance to be obtained by the present invention. At least, it is not intended to limit the application of the doctrine of equivalents to the scope of the claims, and each numerical parameter should at least be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques.

[0060] The environment in which the methods described in the present embodiments are implemented may include a plurality of semiconductor processing tools and wafer / die handling equipment. The plurality of semiconductor processing tools may include deposition tools, exposure tools, developer tools, etching tools, planarization tools, implantation tools, and / or another type of semiconductor processing tool. Tools included in the example environment may include a semiconductor clean room, a semiconductor fab, a semiconductor processing facility and / or manufacturing facility, and / or the like.

[0061] A deposition tool is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials on a substrate. In some embodiments, the deposition tool includes a spin coating tool capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, the deposition tool can deposit metallic materials to form one or more conductors or conductive layers, and can deposit insulating materials to form dielectric or insulating layers. In some embodiments, the deposition tool includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment includes multiple types of deposition tools.

[0062] An exposure tool is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light source, and / or the like), an X-ray source, and / or the like. The exposure tool can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some implementations, the exposure tool includes a scanner, a stepper, or a similar type of exposure tool.

[0063] A developer tool is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from an exposure tool. In some implementations, the developer tool develops the pattern by removing unexposed portions of the photoresist layer. In some implementations, the developer tool develops the pattern by removing exposed portions of the photoresist layer. In some implementations, the developer tool develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0064] A planarization tool is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the polishing device may include a chemical mechanical polishing (CMP) device and / or another type of polishing device. In some implementations, the polishing device may polish or planarize a deposited or plated material layer. The CMP process may include depositing a polishing slurry or polishing compound onto a polishing pad. The wafer may be mounted on a carrier that rotates the wafer as it is pressed against the polishing pad. The polishing slurry and polishing pad act as an abrasive that polishes or planarizes one or more layers of the wafer as it rotates. The polishing pad may also be rotated to ensure a continuous supply of polishing slurry is applied to the polishing pad.

[0065] An implantation tool is a semiconductor processing tool used to implant ions into a substrate of a semiconductor wafer. In some implementations, the implantation tool generates ions from a source material, such as a gas or solid, in an arc chamber. The source material is provided to the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes are used to extract the ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. In some implementations, the implantation tool can be used to form a photodiode, as in this example, in the substrate.

[0066] Wafer / die handling devices include mobile robots, robotic arms, trams or rail cars, and / or another type of device that handles and / or transports wafers and / or dies between semiconductor processing tools and / or to and from other locations such as wafer racks, storage rooms, and / or the like. In some implementations, the wafer / die handling devices may be programmed to follow a specific path and / or may operate quasi-autonomously or autonomously.

[0067] The number and configuration of each device in this embodiment can be one or more examples. In fact, compared to the devices described in this embodiment, there may be additional devices, fewer devices, different devices, or devices with different configurations. In addition, two or more devices may be implemented in a single device, or a single device may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of an environment (e.g., one or more devices) may perform one or more functions described as being performed by another set of devices in the environment.

[0068] like Figure 4 As shown, Figure 4 is a flow chart showing a method for forming a semiconductor structure according to an exemplary embodiment. Figures 5 to 9 1 is a schematic cross-sectional view of a process for forming a semiconductor structure provided by an embodiment of the present invention; the method includes:

[0069] S401: providing a substrate 1; forming an isolation trench in the substrate 1;

[0070] like Figure 5 As shown, a substrate 1 is provided, and an isolation trench is formed on the substrate 1 using an etching process to obtain a substrate 1 with an isolation trench. The substrate 1 may include a semiconductor crystal substrate, a semiconductor wafer, or another type of substrate formed by semiconductor pixels. In some embodiments, the substrate 1 may be formed of the following materials: silicon, a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or another type of semiconductor material capable of generating charges from photons of incident light. The etching tool is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer or semiconductor device. For example, the etching tool may include a wet etching tool, a dry etching tool and / or the like. In some embodiments, the etching tool includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some implementations, the etching tool can etch one or more portions of the substrate using plasma etching or plasma-assisted etching, which can involve using an ionized gas to etch the one or more portions in a co-regional or directionally manner.

[0071] S402: forming an oxide layer 4 in the isolation trench; the oxide layer 4 adheres to the bottom of the isolation trench, and an edge opening is formed between the oxide layer 4 and the sidewall of the isolation trench;

[0072] like Figure 5 As shown, an oxide layer 4 is formed in the isolation trench, the oxide layer 4 adheres to the bottom of the isolation trench, and an edge opening is formed between the oxide layer 4 and the sidewall of the isolation trench; the material of the oxide layer 4 may include but is not limited to silicon dioxide. In the embodiment of this specification, the STI isolation process refers to filling the trench with silicon oxide and embedding a very thick oxide between the device active areas 2 to form isolation between the devices. The STI isolation process can improve parasitic field effect transistors and latch-up effects. The STI process can be used to form an oxide layer 4 in the isolation trench. The STI process may include the following steps:

[0073] 1) Cleaning: The wafer substrate 1 is placed in a cleaning tank for cleaning to obtain a clean surface.

[0074] 2) STI thermal oxidation. A furnace-based thermal oxidation process grows a silicon dioxide film approximately 100 angstroms thick. This process repairs damage to the trench edge surface caused by the AA etch and rounds the corners of the STI bottom trench to reduce the contact surface. The silicon dioxide film serves as a buffer for the subsequent HDPCVD process, as the HDPCVD process performs sputter etching simultaneously with deposition. This silicon dioxide film protects the substrate silicon.

[0075] 3) Deposit a thick SiO2 layer. Use HDPCVD to deposit a very thick SiO2 layer, approximately 4500-5500 angstroms thick. Because HDPCVD uses high-density ion plasma bombardment and sputtering etching to prevent premature closure of the holes and the formation of voids during CVD filling, HDPCVD has excellent step coverage and can effectively fill STI voids.

[0076] 4) RTA rapid thermal annealing: RTA rapid thermal annealing repairs the damage to the substrate caused by HDPCVD, because the sputtering etching in the HDPCVD process will damage the substrate silicon.

[0077] 5) AR (Active Area Reverse) lithography: The pattern on the AR mask is transferred to the wafer through lithography technology to form the AR photoresist pattern, while the photoresist remains on the non-AR area.

[0078] 6) Measure AR overlay and collect overlay data after exposure.

[0079] 7) Check the exposed pattern after development.

[0080] 8) AR Etch. Dry etching removes silicon oxide from the large AA areas, ultimately stopping at Si3N4. The AR etch removes the large silicon oxide from the AA areas through dry etching, leaving behind smaller silicon oxide patches. This helps the subsequent STI CMP process completely remove the surface oxide irregularities, resulting in a smoother and more uniform surface. It also prevents damage to the AA during the STI CMP process due to excessive stress on the silicon oxide.

[0081] 9) Remove the photoresist. Use dry etching and wet etching to remove the photoresist.

[0082] 10) STI CMP. Global STI planarization is performed through CMP. Si3N4 serves as the stop layer for STI CMP. Considering process margins, the oxide on the Si3N4 must be completely removed to prevent it from covering the Si3N4 and affecting subsequent Si3N4 etching steps. When the endpoint detector detects a Si3N4 signal, further polishing is required. However, the greater hardness of Si3N4 results in a faster silicon oxide polishing rate, resulting in a slightly lower silicon oxide layer in the STI region than in the Si3N4 region.

[0083] 11) Cleaning. The wafer is cleaned in an acid bath to obtain a clean surface. Because STI CMP uses a chemical mechanical method, it produces a large number of particles, so cleaning is required.

[0084] 12) Wet etching to remove Si3N4. Alternatively, 91.5% H3PO4 at 180°C can be used to react with Si3N4 to remove the Si3N4 on the wafer, stopping the etching on the silicon oxide. Because the etching rate of hot H3PO4 and Si3N4 for oxide is very low, and if STI CMP does not completely remove the oxide on the Si3N4, residual oxide will cover the Si3N4, ultimately resulting in incomplete Si3N4 removal in this step.

[0085] 13) Wet etching removes the pre-oxide layer. Wet etching uses a certain ratio of HF, NH4F, and H2O to remove the pre-oxide layer. Because the silicon substrate surface is severely damaged after the above series of processes, the pre-oxide layer is also severely damaged. Therefore, after removing the pre-oxide layer, a layer of silicon oxide is grown to improve these damages.

[0086] For example, STI usually uses a high aspect ratio process HARP (High Aspect Ratio Process) to fill silicon dioxide in shallow trenches. The high aspect ratio process refers to the formation of a microstructure with a height to width ratio greater than 10:1 on the surface of a silicon wafer at the micron level through methods such as chemical etching or physical etching. HARP technology is widely used in fields such as MEMS (Micro-Electro-Mechanica Systems) and 3D packaging. The oxide layer 4 is attached to the bottom of the isolation trench, and the oxide layer 4 can be a trapezoidal structure. The sidewalls of the oxide layer 4 can be partially attached to the sidewalls of the isolation trench; an edge opening can be formed between the oxide layer 4 and the sidewalls of the isolation trench, and the cross-sectional view of the edge opening can be a triangle.

[0087] In an exemplary embodiment, the substrate 1 is a silicon wafer, and the HARP process includes:

[0088] 1. Pre-treatment: cleaning the silicon wafer, removing the oxide layer, etc.

[0089] 2. Photolithography: Coating photoresist on the surface of the silicon wafer and exposing it using a mask;

[0090] 3. Etching: Use chemical etching or physical etching to remove the parts not protected by the photoresist;

[0091] 4. Cleaning: clean the photoresist and waste liquid generated by etching;

[0092] 5. Repeat the above steps until the desired microstructure is formed.

[0093] The thickness of the oxide layer 4 is different for transistors of different sizes.

[0094] S403 : forming a nitride layer 6 on the oxide layer 4 ; the nitride layer 6 covers the outer surface of the oxide layer 4 and fills the edge opening.

[0095] In the embodiment of this specification, a nitride layer 6 can be formed on the oxide layer 4 so that the nitride layer 6 covers the outer surface of the oxide layer 4 and fills the edge opening; this can avoid the formation of residues on the side walls of the edge opening during the subsequent deposition process, thereby causing problems such as polysilicon bridging defects, GOX breakdown or threshold voltage changes.

[0096] In some embodiments, the thickness of the nitride layer 6 can be determined according to the size of the transistor formed by the semiconductor structure; for example, for a 28nm transistor, the thickness of the thickest area in the nitride layer 6 is 1-3nm; for a 40nm transistor, the thickness of the thickest area in the nitride layer 6 is 2-5nm.

[0097] In the embodiment of this specification, the thickness of the oxide layer 4 is greater than the depth of the isolation trench, and the shape of the nitride layer 6 is arc-shaped or trapezoidal.

[0098] In an embodiment of the present specification, the thickness of the oxide layer 4 may be greater than the depth of the isolation trench, the top of the oxide layer 4 is higher than the upper surface of the substrate 1, the oxide layer 4 may be a trapezoid or a pattern formed by splicing multiple trapezoids, the side length corresponding to the top of the oxide layer 4 is smaller than the bottom side length of the oxide layer 4, the shape of the nitride may be determined according to the shape of the oxide layer 4, the nitride layer 6 may completely fill the edge opening and cover the outer surface of the oxide layer 4; illustratively, the oxide layer 4 is a trapezoidal structure, and the shape of the nitride layer 6 may be arc-shaped or trapezoidal.

[0099] In the embodiment of this specification, when the thickness of the oxide layer 4 is greater than the depth of the isolation trench, the nitride layer 6 can be arc-shaped or trapezoidal, so as to completely cover the oxide layer 4, forming a protective layer on the oxide layer 4 and improving the stability of the oxide layer 4.

[0100] In an exemplary embodiment, before forming the oxide layer 4 in the isolation trench, the method further includes:

[0101] The isolation trench is cleaned with a cleaning liquid to remove residues in the process of forming the isolation trench.

[0102] In the embodiment of this specification, after the oxide layer 4 is formed, the isolation trench can be cleaned with a cleaning liquid to remove the residues from the isolation trench formation process. After removing the residues in the isolation trench, the oxide layer 4 is deposited in the isolation trench; in an exemplary embodiment, the cleaning liquid includes at least one of the following or a combination of at least two: hydrochloric acid, phosphoric acid, ammonium fluoride, and hydrofluoric acid. Exemplarily, the cleaning liquid can be obtained by mixing hydrofluoric acid, additives, surfactants, and ultrapure water in a preset proportion; the additives can be at least one of glycoside long carbon chain additives and organic amine additives containing carbon branches; the mass fraction of hydrofluoric acid is 2-8%, the mass fraction of the additive is 0.05-0.2%, the mass fraction of the surfactant is 0.002-0.05%, and the remainder is ultrapure water.

[0103] In the embodiment of this specification, before forming the oxide layer 4 , the isolation trench may be cleaned to remove residues formed during the isolation trench etching process, thereby ensuring the cleanliness of the isolation trench.

[0104] In the embodiments of this specification, ultrasonic cleaning can also be used for cleaning. Ultrasonic waves exert high-frequency vibrations on the solution, creating strong flow and shear forces that can effectively remove contaminants from the chip surface. Jet cleaning can also be used for cleaning, using a jet of compressed air and tiny particles to rinse and clean the chip surface.

[0105] In an exemplary embodiment, forming the nitride layer 6 on the oxide layer 4 includes:

[0106] like Figure 6 As shown, nitride is deposited on the oxide layer 4, the edge opening and the active area 2 of the substrate 1 to form an initial nitride layer 5;

[0107] like Figure 7-8 As shown, the initial nitride layer 5 is subjected to a light-free etching process to remove the nitride on the active area 2 and form the nitride layer 6 on the oxide layer 4; the nitride layer 6 may be trapezoidal or arc-shaped; as shown Figure 7 As shown, the nitride layer 6 is trapezoidal. Figure 8 As shown, the nitride layer 6 is arc-shaped.

[0108] In the embodiment of this specification, the substrate 1 includes an active area 2. Nitride can be deposited on the oxide layer 4, the edge opening, and the active area 2 of the substrate 1 to form an initial nitride layer 5. The initial nitride layer 5 completely covers the surface of the substrate 1 and the outer surface of the oxide layer 4. When the height of the oxide layer 4 is higher than the depth of the isolation trench, the initial nitride layer 5 can be trapezoidal or approximately trapezoidal. The initial nitride layer 5 is then subjected to a blind etch process, that is, etching in the absence of light to remove the nitride on the active area 2 and form an insulating nitride layer 6 on the oxide layer 4.

[0109] In the embodiment of this specification, the nitride on the active area 2 of the substrate 1 can be removed by etching without light, thereby avoiding affecting the size of the active area 2 on the substrate 1 .

[0110] In the embodiment of this specification, the step of depositing nitride on the oxide layer 4, the edge opening, and the active area 2 of the substrate 1 to form the initial nitride layer 5 includes:

[0111] forming a first nitride layer 6 on the oxide layer 4;

[0112] Filling the edge opening with nitride to form a second nitride layer 6, so as to form a seamless structure between the oxide layer 4 and the sidewall of the isolation trench;

[0113] Depositing nitride on the active area 2 of the substrate 1 to form a third nitride layer 6;

[0114] The first nitride layer 6 , the second nitride layer 6 , and the third nitride layer 6 form an initial nitride layer 5 .

[0115] In the embodiment of the present specification, the initial nitride layer 5 may include three parts: a first nitride layer 6, a second nitride layer 6 and a third nitride layer 6, wherein the first nitride layer 6 is a nitride layer 6 formed on the outer surface of silicon dioxide, the second nitride layer 6 is a nitride layer 6 formed by filling in the edge opening, thereby forming a seamless structure between the oxide layer 4 and the side wall of the isolation trench; the third nitride layer 6 is a nitride layer 6 formed on the active area 2 of the substrate 1.

[0116] In the embodiments of this specification, during the formation of the initial nitride layer 5, the edge opening can be filled with nitride, thereby avoiding the formation of residues on the side walls of the edge opening during the subsequent deposition process; thereby further avoiding problems such as polysilicon bridging defects or GOX breakdown caused by the residues.

[0117] In the embodiment of this specification, after removing the nitride on the active area 2, the method further includes:

[0118] The active area 2 is irradiated with ultraviolet light to enhance the tensile strain capability of the active area 2 .

[0119] In the embodiments of this specification, Figure 9As shown, after removing the nitride from the active area 2, the material is exposed to ultraviolet light in a CVD (Chemical Vapor Deposition) processing chamber. The ultraviolet light can be generated by a lamp that emits a gas of a specific wavelength when electrically excited. For example, a UV lamp containing xenon gas can produce ultraviolet light with a wavelength of 150nm. The lamp can also contain other gases with different corresponding wavelengths. For example, a mercury lamp can emit a wavelength of 243nm, deuterium can emit a wavelength of 140nm, and krypton dichloride can emit a wavelength of 222nm. This can also be achieved by injecting a mixed gas into the lamp, where each gas can emit radiation of a characteristic wavelength when excited. By varying the relative concentrations of the gases, the output wavelength from the radiation source can be selected to simultaneously expose all desired wavelengths, thereby minimizing the required exposure time. For example, the duration of the UV light exposure can be set according to actual conditions, for example, from 10 minutes to 24 hours. The active area 2 can be irradiated with a single-wavelength ultraviolet light source, which can be 100-150nm or 200nm-300nm. A broadband ultraviolet light source can also be used. Compared to a single-wavelength ultraviolet light source, the broadband ultraviolet light source provided can increase the tensile stress of the deposited material. In addition, the active area 2 can be irradiated with at least two ultraviolet light sources of different wavelengths. For example, ultraviolet light sources with wavelengths of 70-100nm and 150-240nm can be used to simultaneously irradiate the active area 2. After ultraviolet treatment, the silicon nitride material in the active area 2 contains fewer nitrogen-hydrogen bonds and silicon-hydrogen bonds, increasing the amount of silicon-nitrogen bonds, thereby increasing the tensile stress of the material. The tensile strain capacity of the active area 2 is enhanced, so that the tensile stress of the active area 2 is greater than a preset stress threshold; the preset stress threshold can be 1.8-2.0GPa.

[0120] In the embodiments of this specification, the active region 2 in the substrate 1 can be irradiated with ultraviolet light, thereby increasing the tensile stress of the material in the active region 2 and improving the performance of the semiconductor structure.

[0121] In the embodiment of this specification, the material of the nitride layer 6 is silicon nitride or a material doped with silicon nitride.

[0122] In the embodiments of this specification, the material of the nitride layer 6 may include materials such as Si3N4, Si2N2, and SiN; the insulating properties of silicon nitride are very good, and the resistivity can be as high as 10^14Ω·cm, which far exceeds some common insulating materials, such as silicon oxide (SiO2). Its low dielectric constant makes it an ideal isolation layer in microwave and radio frequency applications. The silicon nitride layer also plays a role in blocking the diffusion of impurities in the chip. It can prevent dopants such as boron and phosphorus from changing the device characteristics through diffusion. In addition, it can also prevent the diffusion of metal ions, etc. to prevent faults such as short circuits. Silicon nitride can also be doped with other elements such as oxygen, calcium, aluminum, magnesium, etc. Doping can change the properties of silicon nitride, such as increasing its conductivity, optical transparency, etc. In addition, silicon nitride can also form composite materials with other materials such as silicon carbide and aluminum nitride to improve its stress and other properties.

[0123] In the embodiment of this specification, the material of the nitride layer 6 is silicon nitride or a material doped with titanium nitride, thereby increasing the stress of the nitride layer 6 .

[0124] In some embodiments, the stress of silicon nitride has a significant impact on its electrical, thermal, and mechanical properties. First, stress can change the band structure and electron transport properties of silicon nitride. Stress will change the band structure of silicon nitride, resulting in changes in its electron transport properties. Second, stress will also affect the thermal properties of silicon nitride. Stress will change the thermal conductivity and thermal expansion coefficient of silicon nitride, thereby affecting its thermal conductivity and thermal stability. Finally, stress will also affect the mechanical properties of silicon nitride. Stress will attack the mechanical strength and fracture toughness of silicon nitride, affecting its mechanical properties and reliability. The stress of silicon nitride can be regulated and controlled by various methods. A common method is to introduce or release stress through crystal growth and heat treatment. For example, the lattice matching degree can be controlled by changing the silicon nitride growth conditions and substrate material, thereby regulating stress. In addition, the thermal stress of silicon hydride can also be regulated by heat treatment. For example, stress can be released by high-temperature annealing, thereby improving the stability and reliability of silicon nitride.

[0125] In the embodiment of this specification, after forming the nitride layer 6 on the oxide layer 4, the method further includes:

[0126] The active area 2 of the substrate 1 is passivated using deuterium gas to form a passivation layer on the active area 2; the material of the passivation layer includes silicon-deuterium chemical bonds; the active area 2 is the area on the substrate 1 excluding the nitride layer 6.

[0127] In the embodiments of the present specification, after forming the substrate 1, the active area 2 of the substrate 1 can be subjected to rapid thermal annealing treatment in deuterium gas to form a passivation layer; the passivation layer can reduce the roughness of the surface of the substrate 1, and during the subsequent formation of the gate oxide layer or the formation of the interface, deuterium can diffuse out and combine with dangling bonds at the interface, and deuterium from the deuterium-containing atmosphere is introduced through the surface of the hydrogenated amorphous silicon-containing material into the lattice of the hydrogenated amorphous silicon-containing material, forming a relatively stable "Si-D" (silicon-deuterium) chemical bond structure.

[0128] In the embodiments of this specification, the passivation layer includes stable "Si-D" (silicon-deuterium) chemical bonds, which prevent carrier penetration and improve device performance. This can particularly improve the NBTi effect in PMOS (positive channel metal oxide semiconductor) transistors. PMOS transistors have an n-type substrate and a p-channel, and rely on the flow of holes to carry current. NBTi is a phenomenon that causes the PMOS threshold voltage to increase (making the device more difficult to turn on).

[0129] The embodiments of this specification provide a method for forming a semiconductor structure, comprising: providing a substrate 1; forming an isolation trench in the substrate 1; forming an oxide layer 4 in the isolation trench; the oxide layer 4 being adhered to the bottom of the isolation trench, with an edge opening formed between the oxide layer 4 and the sidewalls of the isolation trench; forming a nitride layer 6 on the oxide layer 4; the nitride layer 6 covering the outer surface of the oxide layer 4 and filling the edge opening. This method can fill the edge opening between the oxide layer 4 and the sidewalls of the isolation trench, preventing the formation of residue in the edge opening during subsequent deposition processes, which could lead to problems such as polysilicon bridging defects or GOX breakdown.

[0130] like Figure 7-8 As shown, an embodiment of the present invention further provides a semiconductor structure, including:

[0131] A substrate 1 having an isolation trench provided therein;

[0132] an oxide layer 4 located in the isolation trench; the oxide layer 4 adheres to the bottom of the isolation trench, and an edge opening is formed between the oxide layer 4 and the sidewall of the isolation trench;

[0133] A nitride layer 6 is located on the oxide layer 4 ; the nitride layer 6 covers the outer surface of the oxide layer 4 and fills the edge opening.

[0134] Exemplarily, substrate 1 may include a semiconductor die substrate, a semiconductor wafer, or another type of substrate formed of semiconductor pixels. In some implementations, substrate 1 may be formed of silicon, a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or another type of semiconductor material capable of generating charge from incident light photons.

[0135] In the embodiment of this specification, the thickness of the oxide layer 4 is greater than the depth of the isolation trench, and the shape of the nitride layer 6 is arc-shaped or trapezoidal. The nitride layer 6 completely covers the outer surface of the oxide layer 4. The top of the oxide layer 4 is higher than the upper surface of the substrate 1. The oxide layer 4 can be a trapezoid or a pattern formed by splicing multiple trapezoids. The side length corresponding to the top of the oxide layer 4 is smaller than the side length of the bottom of the oxide layer 4. The shape of the nitride can be determined according to the shape of the oxide layer 4. The nitride layer 6 can completely fill the edge opening and cover the outer surface of the oxide layer 4. Exemplarily, the oxide layer 4 has a trapezoidal structure, and the shape of the nitride layer 6 can be arc-shaped or trapezoidal. When the thickness of the oxide layer 4 is greater than the depth of the isolation trench, the nitride layer 6 can be arc-shaped or trapezoidal, so that it can completely cover the oxide layer 4, form a protective layer on the oxide layer 4, and improve the stability of the oxide layer 4.

[0136] In the embodiments of this specification, the semiconductor structure may further include:

[0137] A passivation layer is located on the active area 2 of the substrate 1; the material of the passivation layer includes silicon-deuterium chemical bonds; the active area 2 is the area on the substrate 1 except the nitride layer 6.

[0138] In the embodiments of the present specification, after forming the substrate 1, the active area 2 of the substrate 1 can be subjected to rapid thermal annealing treatment under deuterium gas to form a passivation layer; the passivation layer can reduce the roughness of the surface of the substrate 1, and during the subsequent formation of the gate oxide layer or the formation of the interface, deuterium can diffuse out and combine with dangling bonds at the interface, and deuterium from the deuterium-containing atmosphere is introduced into the lattice of the hydrogenated amorphous silicon-containing material through the surface of the hydrogenated amorphous silicon-containing material, forming a relatively stable "Si-D" (silicon-deuterium) chemical bond structure. The passivation layer includes stable "Si-D" (silicon-deuterium) chemical bonds, thereby avoiding the penetration of carriers and improving the performance of the device. In particular, it can improve the NBTi effect of PMOS (positive channel Metal Oxide Semiconductor, P-type MOS) tubes.

[0139] In some embodiments, the nitride layer 6 fills the edge opening, so that a seamless structure is formed between the oxide layer 4 and the sidewall of the isolation trench.

[0140] In some embodiments, the material of the nitride layer 6 is silicon nitride or a material doped with silicon nitride.

[0141] In some embodiments, the active region 2 in the substrate 1 can be irradiated with ultraviolet light to increase the tensile stress of the material in the active region 2 and improve the performance of the semiconductor structure. The tensile stress of the active region 2 is greater than a preset stress threshold. The active region 2 can be irradiated with a single-wavelength ultraviolet light source, which can be 100-150nm or 200nm-300nm. Alternatively, a broadband ultraviolet light source can be used. Compared to a single-wavelength ultraviolet light source, a broadband ultraviolet light source can increase the tensile stress of the deposited material. Furthermore, the active region 2 can be irradiated with at least two different ultraviolet light sources; illustratively, ultraviolet light sources with wavelengths of 70-100nm and 150-240nm can be used simultaneously. After ultraviolet treatment, the silicon nitride material in the active region 2 contains fewer nitrogen-hydrogen bonds and silicon-hydrogen bonds, increasing the amount of silicon-nitrogen bonds and thereby increasing the tensile stress of the material. This enhances the tensile strain capacity of the active region 2, causing the tensile stress of the active region 2 to exceed a preset stress threshold. The preset stress threshold can be adjusted based on actual conditions.

[0142] In some embodiments, the thickness of the nitride layer is determined based on the size of the transistor formed on the substrate.

[0143] The semiconductor structure of this embodiment can be used to prepare transistors of 40 nm or less, and can also be used to prepare transistors of other sizes. The thickness of the silicon nitride layer can be determined according to the size of the transistor.

[0144] The present invention further provides an electronic device, which includes the semiconductor structure provided by an embodiment of the present invention.

[0145] The electronic device of this embodiment can be any electronic product or device with photoelectric sensing function, such as a mobile phone, tablet computer, laptop computer, navigator, camera, camcorder, sweeping robot, virtual reality device, augmented reality device, etc., or any intermediate product including the aforementioned semiconductor structure.

[0146] Embodiments of this specification provide a semiconductor structure comprising: a substrate; an isolation trench disposed in the substrate; an oxide layer located in the isolation trench; the oxide layer adheres to the bottom of the isolation trench, forming an edge opening between the oxide layer and the sidewalls of the isolation trench; a nitride layer located on the oxide layer; the nitride layer covers the outer surface of the oxide layer and fills the edge opening. This allows the edge opening between the oxide layer and the sidewalls of the isolation trench to be filled, preventing the formation of residue in the edge opening during subsequent deposition processes, which could lead to problems such as polysilicon bridging defects or GOX breakdown.

[0147] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0148] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; An isolation trench is provided in the substrate; an oxide layer located in the isolation trench; The oxide layer is attached to the bottom of the isolation trench, and an edge opening is formed between the oxide layer and the sidewall of the isolation trench; a nitride layer on the oxide layer; The nitride layer covers the outer surface of the oxide layer and fills the edge opening.

2. The semiconductor structure according to claim 1, wherein: The thickness of the oxide layer is greater than the depth of the isolation trench, and the shape of the nitride layer is arc-shaped or trapezoidal.

3. The semiconductor structure according to claim 1, wherein: Also includes: a passivation layer located on the active area of ​​the substrate; The material of the passivation layer includes silicon-deuterium chemical bonds; The active area is a region on the substrate excluding the nitride layer.

4. The semiconductor structure according to claim 1, wherein: The nitride layer fills the edge opening so as to form a seamless structure between the oxide layer and the sidewall of the isolation trench.

5. The semiconductor structure according to claim 1, wherein: The material of the nitride layer is silicon nitride or a material doped with silicon nitride. The semiconductor structure according to claim 3 , wherein: The tensile stress of the active area is greater than a preset stress threshold.

7. The semiconductor structure according to claim 1, wherein: The thickness of the nitride layer is determined based on the size of the transistor formed on the substrate.

8. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing a substrate; an isolation trench is formed in the substrate; forming an oxide layer in the isolation trench; the oxide layer adheres to the bottom of the isolation trench, and an edge opening is formed between the oxide layer and the sidewall of the isolation trench; A nitride layer is formed on the oxide layer; the nitride layer covers the outer surface of the oxide layer and fills the edge opening.

9. The method according to claim 8, characterized in that The thickness of the oxide layer is greater than the depth of the isolation trench, and the shape of the nitride layer is arc-shaped or trapezoidal.

10. The method according to claim 8, characterized in that After forming a nitride layer on the oxide layer, the method further includes: Deuterium gas is used to passivate the active area of ​​the substrate to form a passivation layer on the active area; the material of the passivation layer includes silicon-deuterium chemical bonds; the active area is the area on the substrate excluding the nitride layer.

11. The method according to claim 8, characterized in that The forming of a nitride layer on the oxide layer comprises: depositing nitride on the oxide layer, the edge opening, and the active area of ​​the substrate to form an initial nitride layer; The initial nitride layer is subjected to a light-free etching process to remove the nitride on the active area, and the nitride layer is formed on the oxide layer.

12. The method according to claim 11, characterized in that The step of depositing nitride on the oxide layer, the edge opening, and the active area of ​​the substrate to form an initial nitride layer comprises: forming a first nitride layer on the oxide layer; Filling the edge opening with nitride to form a second nitride layer, so as to form a seamless structure between the oxide layer and the sidewall of the isolation trench; depositing nitride on the active area of ​​the substrate to form a third nitride layer; The first nitride layer, the second nitride layer and the third nitride layer form an initial nitride layer.

13. The method according to claim 12, characterized in that The material of the nitride layer is silicon nitride or a material doped with silicon nitride.

14. The method according to claim 11, characterized in that After removing the nitride on the active area, the method further includes: Ultraviolet light is used to irradiate the active area to enhance the tensile strain capability of the active area.

15. The method according to claim 8, characterized in that Before forming the oxide layer in the isolation trench, the method further includes: The isolation trench is cleaned with a cleaning liquid to remove residues in the process of forming the isolation trench.

16. The method according to claim 15, characterized in that The cleaning solution includes at least one or a combination of at least two of the following: hydrochloric acid, phosphoric acid, ammonium fluoride, and hydrofluoric acid.

17. An electronic device, characterized in that: The device comprises the semiconductor structure according to any one of claims 1-7.

Images