A switch tube delay method and a wave-by-wave current limiting protection method of an NPC type three-level topology structure

Abstract

The application discloses a switch tube delay method and a wave-by-wave current limiting protection method of an NPC type three-level topology structure, which is used for controlling the switch time sequence of inner tubes and outer tubes of switch tubes in an NPC type three-level inverter, and the digital signal processing (DSP) chip comprises a configurable logic module (CLB). The switch tube delay control of the NPC type three-level topology structure is realized through the wave-on delay logic and the wave-off delay logic of the configurable logic module (CLB), the wave-by-wave current limiting protection logic during the overcurrent of the equipment hardware is realized, and the logical control requirements that the inner tube is switched on before the outer tube and the outer tube is switched off before the inner tube are achieved. The switch tube delay control and the wave-by-wave current limiting protection logic of the NPC type three-level topology structure are realized in a single-chip mode, and the hardware structure and the software complexity of the circuit are simplified.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of power supply equipment, in particular to a switch tube delay method and a wave-by-wave current limiting protection method of an NPC type three-level topology structure. BACKGROUND

[0002] The NPC (Neutral Point Clamped) three-level topology structure is a most widely used multi-level topology structure, as shown in the figure. Figure 1 The NPC three-level topology structure has the following advantages: 1. The voltage borne by a single device is low, and the NPC three-level topology structure can be used in a higher voltage field; 2. Compared with a two-level topology structure, the number of generated levels is larger, and the multi-level superposition is more similar to a sine wave, and the harmonic content is small; 3. The electromagnetic interference problem is reduced, and the dv / dt (switching transient voltage change rate) of a single action of a three-level inverter device is only half of that of a traditional two-level inverter device; 4. The switching loss is significantly reduced, and the efficiency is improved.

[0003] The NPC three-level topology structure has special requirements for opening and closing of a tube, and needs to follow the principle of "opening the inner tube first and then the outer tube, and closing the outer tube first and then the inner tube", otherwise the IGBT module may be damaged. The traditional method uses an ARM or DSP + FPGA or CPLD structure, and uses FPGA or CPLD to capture the edges of PWM to realize the delay of the switch tube, as shown in the figure. Figure 2 The double-chip solution not only has a complex structure, but also has high cost, and the ARM and DSP use C language programming, while the FPGA / CPLD uses Verilog or VHDL hardware description language, which increases the complexity of the software. SUMMARY

[0004] Therefore, it is necessary to provide a switch tube delay method and a wave-by-wave current limiting protection method of an NPC type three-level topology structure realized by using a DSP single chip.

[0005] A switch tube delay method of an NPC type three-level topology structure is used for controlling the switching time sequence of an inner tube and an outer tube of a switch tube in an NPC type three-level inverter, the NPC type three-level inverter comprises a digital signal processing (DSP) chip, the digital signal processing (DSP) chip comprises a configurable logic module (CLB), the switch tube delay method comprises wave sending opening delay logic and wave closing closing delay logic, the wave sending opening delay logic is used for delay control of the outer tube when the tube is opened, and the wave closing closing delay logic is used for delay control of the inner tube when the tube is closed, so as to avoid damage to the switch tube IGBT.

[0006] Preferably, the configurable logic module CLB is used to realize digital logic control function through hardware structure, and the configurable logic module CLB includes a counter Counter, a finite state machine FSM, a lookup table module LUT4, an output lookup table module Output LUT, a high-level controller HLC, a configurable switching block, an input signal selector and a peripheral signal multiplexer.

[0007] Preferably, the specific steps of the wave opening delay logic include:

[0008] Step 1.1, when the tube is opened, the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0 output by the PWM module of the digital signal processing DSP chip;

[0009] Step 1.2, set the wave enable signal PWM_EN to high level, and set the event signal E1 to high level;

[0010] Step 1.3, the inner tube wave enable logic signal S2 is valid, the inner tube wave enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0, and the operation result is sent to the inner tube and drives the inner tube to open;

[0011] Step 1.4, the event signal E1 is inverted, and the inverted signal is input into the first timer Timer0, so that the first timer Timer0 starts timing;

[0012] Step 1.5, the first timer Timer0 reaches a predetermined time length, and generates an event signal E2;

[0013] Step 1.6, the event signal E1 is logically ANDed with the event signal E2, and the operation result is valid when the outer tube wave enable logic signal S1 is generated;

[0014] Step 1.7, the outer tube wave enable logic signal S1 is valid, the outer tube wave enable logic signal S1 is logically ANDed with the outer tube drive signal PWMxA0, and the operation result is sent to the outer tube and drives the outer tube to open.

[0015] Preferably, the calculation formula of the outer tube wave enable logic signal S1 in step 1.6 is as shown in formula (1):

[0016] S1 = (S1&E2) |(~S1&E1) (1).

[0017] Preferably, the specific steps of the wave opening delay logic include:

[0018] Step 2.1, when the tube is closed, the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0 output by the PWM module of the digital signal processing DSP chip;

[0019] Step 2.2, the wave enable signal PWM_EN is set to low level, and the event signal E3 is set to low level;

[0020] Step 2.3, the outer tube wave enable logic signal S1 is disabled, and the outer tube wave enable logic signal S1 is logically ANDed with the outer tube drive signal PWMxA0, and the operation result is sent to the outer tube and drives the outer tube to turn off;

[0021] Step 2.4, the wave enable signal E3 triggers the second timer Timer1, and the second timer Timer1 starts timing;

[0022] Step 2.5, the second timer Timer1 reaches a predetermined time length, and generates an event signal E4;

[0023] Step 2.6, the wave enable signal E3 is logically ANDed with the event signal E4, and the operation result is valid when the inner tube wave enable logic signal S2 is generated;

[0024] Step 2.7, the inner tube wave enable logic signal S2 is valid, and the inner tube wave enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0, and the operation result is sent to the inner tube and drives the outer tube to turn off.

[0025] Preferably, the calculation formula of the inner tube wave enable logic signal S2 in step 2.6 is shown in formula (1):

[0026] S2 = (S2&~E3) |(~S2&E4) (2).

[0027] Preferably, in the wave open delay logic and the wave closing delay logic,

[0028] The outer tube PWM output logic expression is shown in formula (3):

[0029] PWMxA = S1&PWMxA0 (3);

[0030] The inner tube PWM output logic expression is shown in formula (4):

[0031] PWMxB = S1&PWMxB0 (4).

[0032] Preferably, the predetermined time length of the first timer Timer0 and the second timer Timer1 is preferably 5us.

[0033] And a NPC type three-level topology wave-by-wave current limiting protection method, the switching time sequence of the inner tube and the outer tube of the switching tube in the NPC type three-level inverter adopts the NPC type three-level topology switching tube delay method as described above, and the specific steps include:

[0034] Step one, the hardware overcurrent detection signal OC_U / V / W is transmitted to the input port of the hardware fault protection module TZ;

[0035] Step two, when the overcurrent signal is detected, the TZ module sets PWMxA to low and PWMxB to high;

[0036] Step three, the outer tube is turned off and the inner tube is in an open state;

[0037] Step four, when the PWM counter underflow interrupt is generated, it is checked whether the periodic current limiting protection flag is valid; if so, the periodic current limiting protection flag is logically ANDed with the running signal GPIO25; if the result is a low signal, the low signal is input to the CLB wave generation module to turn off the output of PWMB;

[0038] Step five, the inner tube is turned off.

[0039] Preferably, when the hardware overcurrent signal is invalid, the wave generation enable signal PWM_EN is set to high to start the wave generation open delay logic of the fully configurable logic module CLB to open the inner tube and the outer tube of the NPC three-level inverter.

[0040] In the above-mentioned NPC three-level topology switch tube delay method and periodic current limiting protection method, the digital signal processing DSP chip includes a configurable logic module CLB, the wave generation open delay logic and the wave blocking turn-off delay logic of the configurable logic module CLB are used to realize the NPC three-level topology switch tube delay control, realize the periodic current limiting protection logic when the device hardware overcurrent, and achieve the logical control requirements of opening the tube first and then the inner tube, and then the outer tube, and closing the tube first and then the outer tube, and then the inner tube. The present application realizes the NPC three-level topology switch tube delay control and the periodic current limiting protection logic in a single chip mode, simplifies the hardware structure and the software complexity of the circuit. The method is simple, easy to implement, low in cost, and convenient to popularize. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a schematic diagram of the circuit structure of the NPC three-level topology.

[0042] Figure 2 is a schematic diagram of the structure of the dual-chip structure of the prior art ARM or DSP + FPGA or CPLD.

[0043] Figure 3 is a schematic diagram of the single-chip structure of the NPC three-level topology switch tube delay method and the periodic current limiting protection method of the embodiment of the present application.

[0044] Figure 4is a flow chart of the wave opening delay logic of the switch tube delay method of the NPC type three-level topology structure of the embodiment of the application.

[0045] Figure 5 is a flow chart of the wave closing-off delay logic of the switch tube delay method of the NPC type three-level topology structure of the embodiment of the application.

[0046] Figure 6 is a timing diagram of the PWM wave switch tube delay logic of the switch tube delay method of the NPC type three-level topology structure of the embodiment of the application.

[0047] Figure 7 is a structural schematic diagram of the PWM wave protection structure of the wave-by-wave current limiting protection method of the NPC type three-level topology structure of the embodiment of the application.

[0048] Figure 8 is a PWM pulse action timing diagram when starting up of the NPC type three-level topology structure of the embodiment of the application.

[0049] Figure 9 is a PWM pulse action timing diagram when shutting down of the NPC type three-level topology structure of the embodiment of the application.

[0050] Figure 10 is a wave-by-wave current limiting PWM pulse action timing diagram of the NPC type three-level topology structure of the embodiment of the application. DETAILED DESCRIPTION

[0051] The switch tube delay method and the wave-by-wave current limiting protection method of the NPC type three-level topology structure are taken as examples in the embodiment, and the application will be described in detail in combination with specific embodiments and the drawings.

[0052] Please refer to Figures 3 to 6 , which shows a switch tube delay method of an NPC type three-level topology structure provided by the embodiment of the application, which is used for controlling the switch timing sequence of inner tubes and outer tubes of switch tubes in an NPC type three-level inverter, the NPC type three-level inverter comprising a digital signal processing (DSP) chip, the digital signal processing (DSP) chip comprising a configurable logic module (CLB); the switch tube delay method comprising wave opening delay logic and wave closing-off delay logic, the wave opening delay logic being used for delay control of the outer tubes when the tubes are opened, and the wave closing-off delay logic being used for delay control of the inner tubes when the tubes are closed, so as to avoid causing damage to the switch tubes (IGBT).

[0053] Preferably, the configurable logic module CLB is used to realize complex digital logic control functions through flexible hardware structure, and the configurable logic module CLB comprises a counter Counter, a finite state machine FSM, a lookup table module LUT4, an output lookup table module Output LUT, a high-level controller HLC, a configurable switching block, an input signal selector and a peripheral signal multiplexer.

[0054] Specifically, the configurable logic module CLB comprises a plurality of Tiles, that is, independent functional units or core modules on a chip, wherein,

[0055] Counter: There are 3 counters in each sub-module, which can be configured as an adder, a counter or a shifter, and can perform addition and subtraction operations, up and down counting and left and right shifting. The counter event input and reset input can be freely connected to other sub-modules in the same instance.

[0056] Finite state machine (FSM): There are 3 FSMs in each sub-module, which can be configured as a single four-state finite state machine, or as two independent two-state finite state machines, accept two external inputs, generate two state outputs and one combination output, and can also work as a 4-input lookup table LUT when not used as a state machine.

[0057] Lookup table module (LUT4): There are 3 LUT4s in each sub-module, which have a 4-input lookup table function and can implement any Boolean equation with up to 4 inputs.

[0058] Output lookup table module (Output LUT): There are 8 Output LUTs in each sub-module, which are three-input lookup table sub-modules and can implement any combination Boolean equation with up to three inputs, and each block is associated with one of the tile outputs.

[0059] High-level controller (HLC): There is only one HLC in each sub-module, which is an event-driven block that can handle up to four concurrent events, performs predefined operations when events occur, and also provides data exchange and interrupt mechanisms for the CPU subsystem. There are four working registers (R0, R1, R2 and R3) for basic operations and to modify or set the values of the three counter blocks.

[0060] Configurable switching block: provides dynamic connection between all the above blocks, and users can connect sub-modules, but cannot form a loop in the sub-module.

[0061] Peripheral signal multiplexer: allocates 8 outputs of the CLB logic block, and the 8 outputs are copied to create 16 output signals, and each output has a separate output enable bit in the register CLB_OUT_EN.

[0062] Specifically, the CLB module is not included in the traditional DSP chip, in the embodiment, the digital signal processing DSP chip adopts a TMS320F28P650DK chip, and the configurable logic module CLB in the chip can be used to replace the FPGA / CPLD chip to realize the function of the delay of the switch tube.

[0063] Compared with the traditional double-chip scheme, the technical scheme of the application adopts a single chip, uses a unified clock, avoids delay, and the overcurrent protection signal acquisition and the special processing of the PWM signal are provided by a mature scheme of the chip, so that the risk of self-written code is avoided, and the reliability of the protection function is improved.

[0064] Please refer to Figure 4 , which shows the wave opening delay logic, and the specific steps of the wave opening delay logic include:

[0065] Step 1.1, when the tube is opened, the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0 output by the PWM module of the digital signal processing DSP chip;

[0066] Step 1.2, set the wave enable signal PWM_EN to high level, and set the event signal E1 to high level;

[0067] Step 1.3, the inner tube wave enable logic signal S2 is valid, the inner tube wave enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0, and the operation result is sent to the inner tube and drives the inner tube to open;

[0068] Step 1.4, the event signal E1 is inverted, and the inverted signal is input into the first timer Timer0, so that the first timer Timer0 starts timing;

[0069] Step 1.5, the first timer Timer0 reaches a predetermined time length, and generates an event signal E2;

[0070] Step 1.6, the event signal E1 is logically ANDed with the event signal E2, and the operation result is valid to generate the outer tube wave enable logic signal S1;

[0071] Step 1.7, the outer tube wave enable logic signal S1 is valid, the outer tube wave enable logic signal S1 is logically ANDed with the outer tube drive signal PWMxA0, and the operation result is sent to the outer tube and drives the outer tube to open.

[0072] In the step 1.6, the calculation formula of the outer tube wave enable logic signal S1 is shown as formula (1):

[0073] S1 = (S1&E2) |(~S1&E1) (1).

[0074] Please refer to Figure 5 , the specific steps of the envelope turn-off delay logic include:

[0075] Step 2.1, when the gate is closed, the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0 output by the PWM module of the digital signal processing DSP chip;

[0076] Step 2.2, the envelope enable signal PWM_EN is set to low level, and the event signal E3 is set to low level;

[0077] Step 2.3, the outer tube envelope enable logic signal S1 is disabled, and the outer tube envelope enable logic signal S1 is logically ANDed with the outer tube drive signal PWMxA0, and the operation result is sent to the outer tube and drives the outer tube to turn off;

[0078] Step 2.4, the envelope enable signal E3 triggers the second timer Timer1, so that the second timer Timer1 starts timing;

[0079] Step 2.5, the second timer Timer1 reaches a predetermined time length, and generates an event signal E4;

[0080] Step 2.6, the envelope enable signal E3 is logically ANDed with the event signal E4, and the operation result is valid when the inner tube envelope enable logic signal S2 is generated;

[0081] Step 2.7, the inner tube envelope enable logic signal S2 is valid, and the inner tube envelope enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0, and the operation result is sent to the inner tube and drives the outer tube to turn off.

[0082] In the step 2.6, the calculation formula of the inner tube envelope enable logic signal S2 is shown in formula (1):

[0083] S2 = (S2&~E3) |(~S2&E4) (2).

[0084] Please refer to Figure 6 , the timing diagram of the PWM envelope opening and closing tube delay logic of the envelope turn-off delay logic and the envelope turn-off delay logic.

[0085] In the envelope turn-off delay logic and the envelope turn-off delay logic,

[0086] The outer tube PWM output logic expression is shown in formula (3):

[0087] PWMxA = S1&PWMxA0 (3);

[0088] The inner tube PWM output logic expression is shown in formula (4):

[0089] PWMxB = S1&PWMxB0 (4).

[0090] Preferably, the predetermined time length of the first timer Timer0 and the second timer Timer1 is preferably 5us.

[0091] Specifically, in the present embodiment, when the outer tube is opened, the opening delay time length of the outer tube is Δt1 = 5us; when the inner tube is closed, the closing delay time length of the inner tube is Δt2 = 5us.

[0092] Specifically, the specific experimental process of the CLB is as follows:

[0093] 1. After the module receives the wave emission enable signal E1 (high level at this time):

[0094] The wave emission steps of the inner tube are as follows:

[0095] E1 and the signal PWMxB0 output by the PWM module of the DSP are logically processed, that is, if PWMxB0 is low at this time, the result of the logical AND operation of the two is low, and the PWMxB pin of the DSP outputs low level at this time; otherwise, the PWMxB pin outputs high level, so that the inner tube is opened without delay.

[0096] The wave emission steps of the outer tube are as follows:

[0097] When the input signal of Timer0 is high, the timer is in a reset state. Then, the logical 0 is obtained by inverting the logic high E1, which is input to Timer0, and Timer0 starts timing. When the delay of 5us ends, event E2 is generated, which is input to the outer tube enable logic expression (1) to obtain the enable signal S1 of the outer tube. Finally, S1 and the signal PWMxA0 output by the PWM module of the DSP are logically ANDed. If the PWMxA pin is low at this time, the PWMxA pin is high, otherwise it is low. In this way, the timer Timer0 of the CLB realizes the delay opening of the outer tube, and the delay opening time length is Δt1 = 5us.

[0098] 2. The processing logic of the outer tube when the wave is sealed is:

[0099] The outer tube is immediately turned off when the wave is sealed. Therefore, when E3 is low, the PWMxA0 output is low by performing logical AND operation between E3 and the outer tube drive signal PWMxA0, that is, the step of immediately turning off the outer tube is completed.

[0100] The processing logic of the inner tube when the wave is sealed is:

[0101] When E3 is detected as low, the timer Timer1 of the CLB is converted from the reset state to the counting state, and when Timer1 counts to 5us, an event E4 is generated, E3 and E4 are input to expression (2) to obtain the inner tube enable signal S2 at the envelope, and then S2 is logically ANDed with the inner tube PWMxB0, if PWMxB0 is low, the internal drive output is low; otherwise, it is high. The delay shutdown time Δt2 = 5us.

[0102] And please refer to Figure 7 , a wave-by-wave current limiting protection method for an NPC three-level topology is shown, the switch timing sequence of the inner tube and the outer tube of the switch tube in the NPC three-level inverter adopts the switch tube delay method of the NPC three-level topology as described above, and the specific steps include:

[0103] Step one, the hardware overcurrent detection signal OC_U / V / W is transmitted to the input port of the hardware fault protection module TZ;

[0104] Step two, when the overcurrent signal is detected, the TZ module (Trip-Zone Module, fault protection module) sets PWMxA to low and PWMxB to high;

[0105] Among them, PWMxA is used to drive the outer tube, PWMxB is used to drive the inner tube, (x = 1, 2, 3 …… 6).

[0106] Step three, the outer tube is turned off; at this time, the inner tube is still in the open state;

[0107] Step four, when the PWM counter underflows, it is queried whether the wave-by-wave current limiting protection flag is valid; if it is valid, the wave-by-wave current limiting protection flag is logically ANDed with the running signal GPIO25; if the operation result is a low level signal, the low level signal is input to the CLB wave module, and the output of PWMB is turned off;

[0108] Step five, the inner tube is turned off.

[0109] Specifically, when the wave-by-wave current limiting module signal is valid, the corresponding overcurrent signal flag is set to 1, triggering the PWM interrupt, and the DSP actively stops wave generation, and at the same time, the signal is sent to the CLB module to trigger the envelope shutdown delay logic of the CLB.

[0110] Specifically, when hardware overcurrent occurs, the full configurable logic module CLB starts the envelope shutdown delay logic, first turns off the outer tube, and then turns off the inner tube.

[0111] Preferably, when the hardware overcurrent signal is invalid, the wave generation enable signal PWM_EN is set to high level, and the wave generation opening delay logic of the full configurable logic module CLB is started to open the inner tube and the outer tube of the switch tube in the NPC type three-level inverter.

[0112] Specifically, in the embodiment, to realize the wave-by-wave current limiting while considering the switch tube timing of the I type three-level, the wave-by-wave current limiting logic as shown in the figure is realized. Figure 7 OC_U / V / W are three-phase hardware overcurrent signals, when any phase in the three-phase inverter causes the wave-by-wave current limiting value due to overcurrent, the three signals are pulled low, triggering the TZ module to operate the output level of PWM. In the design, when the overcurrent signal appears, PWMA is set to low level and PWMB is set to high level. Because PWMxA (x = 1, 2, 3…6) is used to drive the 1 tube and the 4 tube, that is, when overcurrent appears, the outer tube is judged first; this is consistent with the logic of the I type three-level switch tube “first outer and then inner”. At the same time, in the overflow interrupt of PWM, whether the CBC module bit (wave-by-wave current limiting protection flag bit) is valid is queried, if it is valid, a low signal is obtained by logical AND operation with the running signal GPIO25 and input to the CLB wave generation module to turn off the output of PWMB. Finally, the outputs of PWMA and PWMB are judged.

[0113] When the overcurrent signal is invalid, the “first inner and then outer” opening logic is automatically started.

[0114] Specifically, please refer to the figure Figures 8 to 10 , which shows the actual test effect diagram of the technical solution.

[0115] Among them, PWN_EN represents the power-on enable signal, G1 is the drive signal of the bridge arm 1 tube (outer tube), G2 is the drive signal of the 2 tube (inner tube), G3 is the drive signal of the 3 tube (inner tube), and G4 is the drive signal of the 4 tube (outer tube), wherein G1 and G3 are complementary, and G2 and G4 are complementary.

[0116] Figure 8 It is the power-on PWM pulse action diagram, wherein T1 is the shutdown state, T2 is the outer tube delay opening stage, and T3 is the stable running state. Specifically, when the power-on enable signal PWM_EN is converted from low level to high level, the CLB module detects the rising edge, and the drive signals G2 tube and G3 of the two inner tubes are set to high level at the same time, and the outer tube drive G1 and G4 are delayed to high level. Since the 4 tube (outer tube) drive G4 is at low level at the opening time, the 4 tube delay opening cannot be seen in the figure, but it actually exists. Thus, the requirement of opening the inner tube first and then the outer tube when starting is realized.

[0117] Figure 9The PWM pulse action figure for shutdown is shown, wherein T4 is a stable running stage, T5 is an outer tube shutdown delay stage, and T6 is a state in which all of G1-G4 are turned off. Specifically, when the module receives a shutdown instruction, a falling edge signal of the start-up enable signal PWM_EN appears, and the CLB immediately turns the 1st tube (outer tube) drive signal G1 from high to low, the 3rd tube (inner tube) drive G3, and the 4th tube (outer tube) drive G4 remain unchanged at low level; the 2nd tube (inner tube) drive G2 is high, and after a delay Δt2 of the 1st tube (outer tube) drive G1, the 2nd tube (inner tube) drive G2 is flipped from high to low. Thus, the function of turning off the outer tube first and then turning off the inner tube during start-up and shutdown is realized.

[0118] Figure 10 The PWM pulse action figure for triggering the wave-by-wave current limiting function when the overcurrent signal appears is shown. Specifically, the wave enable signal PWN_EN is turned from high to low when the overcurrent signal appears, and the PWM_EN signal is turned from low to high when the overcurrent signal is reset. As shown in the figure, at the beginning of the T8 stage, when the CLB detects the falling edge of PWN_EN, the drive signal G1 of the 1st tube is immediately turned from high to low, and after a delay Δt1, the drive signal G2 of the 2nd tube is turned from high to low; when the PWM_EN signal is restored to high, the 2nd tube (inner tube) is set to high, and since the 3rd tube (inner tube) is low at this time, the 3rd tube remains unchanged at low, and after a delay Δt2, the 1st tube (outer tube) is turned to high. Thus, the logic of turning off the outer tube first and then turning off the inner tube during wave-by-wave current limiting is realized.

[0119] In the above-mentioned switch tube delay method and wave-by-wave current limiting protection method of the NPC three-level topology structure, the digital signal processing DSP chip includes a configurable logic module CLB, the wave-on delay logic and the wave-off shutdown delay logic of the configurable logic module CLB realize the switch tube delay control of the NPC three-level topology structure, realize the wave-by-wave current limiting protection logic when the device hardware overflows, and achieve the logic control requirements of turning off the inner tube first and then the outer tube during turning on, and turning off the outer tube first and then the inner tube during turning off. The switch tube delay control and the wave-by-wave current limiting protection logic of the NPC three-level topology structure are realized in a single chip manner, and the hardware structure and the software complexity of the circuit are simplified. The method is simple, easy to implement, low in cost, and convenient to popularize.

[0120] It should be noted that the above description is only the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for delaying the switching transistors in an NPC-type three-level topology, used to control the switching sequence of the inner and outer transistors in an NPC-type three-level inverter, characterized in that... The NPC-type three-level inverter includes a digital signal processing (DSP) chip, which includes a configurable logic module (CLB). The switching transistor delay method includes waveform turn-on delay logic and waveform blocking turn-off delay logic. The waveform turn-on delay logic is used for delay control of the outer transistor when it is turned on, and the waveform blocking turn-off delay logic is used for delay control of the inner transistor when it is turned off, so as to avoid damage to the IGBT switching transistor. The specific steps of the waveform activation delay logic include: Step 1.1, when the transistor is turned on, the PWM module of the digital signal processing DSP chip outputs the inner transistor drive signal PWMxB0 and the outer transistor drive signal PWMxA0; Step 1.2: Set the waveform enable signal PWM_EN to high level and the event signal E1 to high level; Step 1.3: The inner tube ripple enable logic signal S2 is valid. The inner tube ripple enable logic signal S2 and the inner tube drive signal PWMxB0 are logically ANDed. The result of the operation is sent to the inner tube and drives the inner tube to turn on. Step 1.4: Invert the event signal E1 and input the inverted signal into the first timer Timer0 to start the first timer Timer0. Step 1.5: After the first timer Timer0 reaches the predetermined duration, it generates an event signal E2; Step 1.6: Perform a logical AND operation between event signal E1 and event signal E2. When the operation result is valid, generate the external tube emitting signal enable logic signal S1. Step 1.7: The external transistor waveform enable logic signal S1 is valid. The external transistor waveform enable logic signal S1 and the external transistor drive signal PWMxA0 are logically ANDed. The result of the operation is sent to the external transistor and drives the external transistor to turn on after a delay. The specific steps of the wave blocking delay logic include: Step 2.1, when the transistor is turned off, the PWM module of the digital signal processing DSP chip outputs the inner transistor drive signal PWMxB0 and the outer transistor drive signal PWMxA0; Step 2.2: Set the waveform enable signal PWM_EN to low level and the event signal E3 to low level; Step 2.3: The external transistor emitting signal enable logic signal S1 is disabled. The external transistor emitting signal enable logic signal S1 and the external transistor drive signal PWMxA0 are logically ANDed. The result of the operation is sent to the external transistor and drives the external transistor to turn off. Step 2.4: The blocking enable signal E3 triggers the second timer Timer1, causing the second timer Timer1 to start counting. Step 2.5: After the second timer 1 reaches the predetermined duration, it generates an event signal E4; Step 2.6: Perform a logical AND operation between the blocking enable signal E3 and the event signal E4. When the operation result is valid, generate the inner tube blocking enable logic signal S2. Step 2.7: The inner tube ripple enable logic signal S2 is enabled. The inner tube ripple enable logic signal S2 and the inner tube drive signal PWMxB0 are logically ANDed. The result of the operation is sent to the inner tube and drives the outer tube to turn off after a delay.

2. The switching transistor delay method for an NPC-type three-level topology as described in claim 1, characterized in that, The configurable logic module (CLB) is used to implement digital logic control functions through hardware structure. The CLB includes a counter, a finite state machine (FSM), a lookup table module (LUT4), an output lookup table module (Output LUT), an advanced controller (HLC), a configurable switching block, an input signal selector, and a peripheral signal multiplexer.

3. The switching transistor delay method for an NPC-type three-level topology as described in claim 1, characterized in that, The calculation formula for the external tube wave emission enable logic signal S1 in step 1.6 is shown in equation (1): S1 = (S1 & E2) |(~S1 & E1) (1).

4. The switching transistor delay method for an NPC-type three-level topology as described in claim 1, characterized in that, The calculation formula for the inner tube blocking enable logic signal S2 in step 2.6 is shown in equation (1): S2 = (S2 & ~E3) |(~S2 & E4) (2).

5. The switching transistor delay method for an NPC-type three-level topology as described in claim 1, characterized in that, In the aforementioned waveform activation delay logic and waveform deactivation delay logic The logic expression for the external PWM output is shown in equation (3): PWMxA = S1 & PWMxA0 (3); The logic expression for the PWM output of the inner tube is shown in equation (4): PWMxB = S1 & PWMxB0 (4).

6. The switching transistor delay method for an NPC-type three-level topology as described in claim 1, characterized in that, The predetermined duration of the first timer Timer0 and the second timer Timer1 is 5µs.

7. A wave-by-wave current limiting protection method for an NPC-type three-level topology, characterized in that, The switching timing of the inner and outer transistors in an NPC-type three-level inverter adopts the switching transistor delay method for the NPC-type three-level topology as described in any one of claims 1-6, and the specific steps include: Step 1: The hardware overcurrent detection signal OC_U / V / W is transmitted to the input port of the hardware fault protection module TZ; Step 2: When an overcurrent signal is detected, the TZ module sets PWMxA to low level and PWMxB to high level. Step 3: Turn off the outer pipe and keep the inner pipe open; Step 4: When the PWM counter underflows and is interrupted, check if the cycle-by-cycle current limiting protection flag is valid. If valid, perform a logical AND operation between the cycle-by-cycle current limiting protection flag and the running signal GPIO25. If the result of the operation is a low-level signal, input the low-level signal to the CLB waveform generation module and turn off the output of PWMB. Step 5: Shut down the inner tube.

8. The wave-by-wave current limiting protection method for NPC-type three-level topology as described in claim 7, characterized in that, When the hardware overcurrent signal is invalid, the waveform enable signal PWM_EN is set to high level, and the waveform turn-on delay logic of the fully configurable logic module CLB is started to turn on the inner and outer transistors of the switching transistors in the NPC type three-level inverter.

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