Interleaving parallel control method, interleaving parallel control circuit and electronic equipment

Abstract

The invention discloses an interleaving parallel control method, an interleaving parallel control circuit and electronic equipment. The interleaving parallel control method comprises the following steps: acquiring a resonant current signal and a power supply output signal in a first resonant conversion circuit; generating a first control signal by using the resonance current signal and the power supply output signal; acquiring a first pulse width of each beat of the first control signal; performing phase shift adjustment on the first control signal by using the first pulse width of each beat to obtain a second control signal; and the first control signal and the second control signal are respectively sent to the first resonant conversion circuit and the second resonant conversion circuit to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, so that the power supply output signal is adjusted. According to the interleaving parallel control method, on the premise that the power density is improved, output current ripples can be effectively reduced through phase shift adjustment, the control mode is simple, and response is fast.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to an interleaved parallel control method, an interleaved parallel control circuit, and an electronic device. Background Art

[0002] Today, the continuous miniaturization and informatization of electronic devices are placing higher demands on high-efficiency, high-power-density, and low-noise power supply systems. The LLC resonant converter (which includes an additional inductor (L) in series with two other components, the inductor L and the capacitor (C), hence the name) has become the preferred topology for high-frequency, high-efficiency power supply designs due to its soft switching (zero-voltage / zero-current switching) characteristics across the full load range.

[0003] However, a single-channel LLC resonant converter has the problem of limited power density. To improve the power density, it is necessary to connect multiple LLC resonant conversion circuits in parallel to supply power. However, connecting multiple LLC resonant converters in parallel also has the problem of large output current ripple, complex control methods of each LLC resonant converter, and slow response. Summary of the Invention

[0004] The main technical problem solved by the present application is to provide an interleaved parallel control method, an interleaved parallel control circuit and an electronic device, which can solve the problem of limited power density of a single-channel LLC resonant converter in the related art, and the problem of large output current ripple when multiple LLC resonant converters are connected in parallel, and the control method of each LLC resonant converter is complex and the response is slow.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide an interleaved parallel control method, which is applied to the interleaved parallel control of a resonant conversion circuit, the resonant conversion circuit includes a first resonant conversion circuit and a second resonant conversion circuit connected in parallel with each other, wherein the interleaved parallel control method includes: obtaining a resonant current signal and a power supply output signal in the first resonant conversion circuit; using the resonant current signal and the power supply output signal to generate a first control signal; obtaining a first pulse width of each beat of the first control signal; using the first pulse width of each beat to phase-shift the first control signal to obtain a second control signal; sending the first control signal and the second control signal to the first resonant conversion circuit and the second resonant conversion circuit respectively, so as to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power supply output signal.

[0006] The step of obtaining the first pulse width of each beat of the first control signal includes: obtaining each rising edge and falling edge of the first control signal; and obtaining the first pulse width of each beat using each rising edge and falling edge.

[0007] Among them, the step of using the first pulse width of each beat to phase-shift the first control signal to obtain the second control signal includes: obtaining each rising edge of the first control signal; taking each rising edge as the starting moment, delaying for half the duration of the first pulse width of the previous beat, and using the first pulse width of the previous beat to obtain the second pulse width of each beat of the second control signal to generate the second control signal.

[0008] Among them, the number of second resonant conversion circuits is at least two, and the step of using the first pulse width of each beat to phase-shift the first control signal to obtain the second control signal includes: using the first pulse width to divide the sum of the number of first resonant conversion circuits and second resonant conversion circuits to obtain the pulse adjustment width; obtaining each rising edge of the first control signal; taking each rising edge as the starting moment, the corresponding duration of the delayed pulse adjustment width adopts the first pulse width of the previous beat to obtain the second pulse width of each beat of the first second control signal to generate the first second control signal; the corresponding duration of the delayed pulse adjustment width again adopts the first pulse width of the previous beat to obtain the second pulse width of each beat of the second second control signal to generate the second second control signal, until the cumulative number of delays is equal to the number of second resonant conversion circuits, thereby obtaining at least two second control signals.

[0009] Among them, the step of generating the first control signal using the resonant current signal and the power supply output signal includes: obtaining an adjustment output signal using the difference between the power supply output signal and the target reference voltage; performing slope compensation on the adjustment output signal to obtain a feedback adjustment signal; and generating the first control signal using the feedback adjustment signal and the resonant current signal.

[0010] Among them, the first control signal includes a first drive signal and a second drive signal, and the step of performing slope compensation on the regulated output signal to obtain a feedback regulation signal includes: in the first half cycle of each signal cycle of the first drive signal, in response to the second drive signal being adjusted from a high level to a low level, delaying for a set period of time or simultaneously using a set slope compensation slope to perform slope compensation on the regulated output signal to obtain the feedback regulation signal; the step of using the feedback regulation signal and the resonant current signal to generate the first control signal includes: delaying for a set period of time or simultaneously adjusting the first drive signal from a low level to a high level; when the resonant current signal is greater than or equal to the feedback regulation signal, adjusting the first drive signal from a high level to a low level; in the second half cycle of each signal cycle, copying the first drive signal of each first half cycle to obtain the second drive signal.

[0011] The second control signal includes a third drive signal and a fourth drive signal, and the step of obtaining the first pulse width of each beat of the first control signal includes: obtaining the first pulse width of each beat of the first drive signal; the step of using the first pulse width of each beat to phase-shift the first control signal to obtain the second control signal includes: using the first pulse width of each beat to phase-shift the first drive signal to obtain a third drive signal; and using the third drive signal to obtain the fourth drive signal; wherein the third drive signal and the fourth drive signal are complementary and symmetrical in phase; the step of sending the first control signal and the second control signal to the first resonant conversion circuit and the second resonant conversion circuit respectively to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power supply output signal includes: using the first drive signal and the second drive signal to adjust the switching state of the first resonant conversion circuit, and using the third drive signal and the fourth drive signal to adjust the switching state of the second resonant conversion circuit, thereby adjusting the power supply output signal.

[0012] Among them, the step of using the first pulse width of each beat to phase-shift the first drive signal to obtain the third drive signal includes: obtaining each rising edge and falling edge of the first drive signal; taking each rising edge as the starting moment, delaying for half the first pulse width of the previous beat to adjust the third drive signal from a low level to a high level; taking each falling edge as the starting moment, delaying for half the first pulse width of the previous beat to adjust the third drive signal from a high level to a low level.

[0013] In order to solve the above technical problems, another technical solution adopted in the present application is: providing an interleaved parallel control circuit, wherein the interleaved parallel control couples the first resonant conversion circuit and the second resonant conversion circuit, and the first resonant conversion circuit and the second resonant conversion circuit are connected in parallel with each other; wherein the interleaved parallel control circuit adopts the interleaved parallel control method described in any of the above items to realize interleaved parallel control of the first resonant conversion circuit and the second resonant conversion circuit.

[0014] To solve the above technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a shell and an interleaved parallel control circuit connected to the shell; wherein the interleaved parallel control circuit is the interleaved parallel control circuit as described above.

[0015] The beneficial effects of the present application are as follows: Different from the prior art, the staggered parallel control method provided by the present application obtains the resonant current signal and the power supply output signal in the first resonant conversion circuit, generates a first control signal by using the resonant current signal and the power supply output signal, and obtains the first pulse width of each beat of the first control signal, and uses the first pulse width of each beat to perform phase shift adjustment on the first control signal to obtain a second control signal, thereby using the first control signal and the second control signal to staggeredly control the first resonant conversion circuit and the second resonant conversion circuit in parallel, and adjust the power supply output signal, so that while improving the power density by using the first resonant conversion circuit and the second resonant conversion circuit in parallel, the output current ripple can also be effectively reduced by corresponding phase shift adjustment; and the phase shift adjustment of the digital control method realized by the first pulse width is simpler than the control method relying on the hardware phase modulator, and the signal response is also faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which: Figure 1 This is a flow chart of the first embodiment of the staggered parallel control method of the present application; Figure 2 This is a structural diagram of the first embodiment of the staggered parallel control circuit of the present application; Figure 3 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S12; Figure 4 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S13; Figure 5 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S14; Figure 6 yes Figure 1 A schematic diagram of a flow chart of another embodiment of S14; Figure 7 This is a flow chart of the second embodiment of the staggered parallel control method of the present application; Figure 8 is a schematic structural diagram of a second embodiment of an interleaved parallel control circuit; Figure 9 yes Figure 8 A schematic diagram of waveforms of various related signals of the first control signal generated by the staggered parallel control circuit; Figure 10 yes Figure 7A schematic diagram of a flow chart of an embodiment of S48; Figure 11 yes Figure 8 Schematic diagram of wave generation logic of the staggered parallel control circuit; Figure 12 It is a structural diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0018] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features identified. Therefore, features specified as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional designations (such as up, down, left, right, front, back, etc.) in the embodiments of this application are intended only to illustrate the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional designations will also change accordingly. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to such process, method, product, or apparatus.

[0019] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0020] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0021] Please refer to Figure 1 and Figure 2 ,in, Figure 1 This is a flow chart of the first embodiment of the staggered parallel control method of the present application. Figure 2 This is a schematic diagram of the structure of the first embodiment of the staggered parallel control circuit of the present application. Specifically, it can include the following steps: S11: Acquire a resonant current signal and a power supply output signal in the first resonant conversion circuit.

[0022] It is understandable that the staggered parallel control method in this embodiment is specifically applied to Figure 2 The interleaved parallel control of the resonant conversion circuit 20 shown in FIG. 2 includes a first resonant conversion circuit 21 and a second resonant conversion circuit 22 connected in parallel with each other, and a first interleaved parallel control circuit 30 is coupled to the first resonant conversion circuit 21 and the second resonant conversion circuit 22. The first interleaved parallel control circuit 30 implements interleaved parallel control of the first resonant conversion circuit 21 and the second resonant conversion circuit 22 using any of the interleaved parallel control methods described herein.

[0023] It is worth noting that the first resonant conversion circuit 21 and the second resonant conversion circuit 22 can be the same and both are half-bridge LLC converters, full-bridge LLC converters or other forms of LLC circuit topologies, which is not limited in this embodiment.

[0024] In some embodiments, the number of the first resonant conversion circuit 21 is one, and the number of the second resonant conversion circuit 22 is one or more, such as the second resonant conversion circuit 1, the second resonant conversion circuit 2,..., the second resonant conversion circuit n (n is 1 or an integer greater than 1); or it can be understood that the number of the resonant conversion circuits 20 is at least two, and any one of the resonant conversion circuits 20 is the first resonant conversion circuit 21, serving as the main phase resonant converter, and the other resonant conversion circuits 20 are the second resonant conversion circuit 22, serving as the slave phase resonant converter. This application does not limit this.

[0025] In some embodiments, the first interleaved parallel control circuit 30 may specifically include a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, a discrete gate or transistor logic device, discrete hardware, and any other reasonable circuit unit with signal processing function, and this application does not limit this.

[0026] Furthermore, the term "coupled" as used herein encompasses both direct and indirect connection methods. Therefore, if a first circuit is described as being coupled to a second circuit, this means that the first circuit may be directly connected to the second circuit via electrical connection, wireless transmission, optical transmission, or other signal connection methods, or may be indirectly connected to the second circuit via other circuits or connection methods.

[0027] Specifically, the first staggered parallel control circuit 30 obtains the resonant current signal and the power supply output signal from the first resonant conversion circuit 21 in real time. For example, the resonant current can be obtained from the primary side of the first resonant conversion circuit 21 through a current transformer, a voltage divider, a sampling resistor or other types of circuit units, and the output voltage can be obtained from its secondary side to obtain the resonant current signal and the power supply output signal.

[0028] S12: Generate a first control signal using the resonant current signal and the power supply output signal.

[0029] Furthermore, the first staggered parallel control circuit 30 calculates the necessary adjustment amount to generate a first control signal based on the currently obtained resonant current signal and power supply output signal, such as using proportional integral differential control or other advanced control strategies to ensure that the system can be accurately adjusted according to the current working state.

[0030] S13: Obtain a first pulse width of each beat of the first control signal.

[0031] The first interleaved parallel control circuit 30 measures and obtains the first pulse width of each beat of the currently generated first control signal in real time.

[0032] It's worth noting that the pulse width per beat refers to the duration of a single pulse from the start to the end of a pulse sequence. Pulse width refers to the duration of time it takes for a pulse signal to transition from a high level to a low level, typically expressed in seconds (s). For example, a signal with a pulse width of 100 nanoseconds (ns) means the signal remains high for 100 nanoseconds. The first pulse width can be understood as the duration of time it takes for the first control signal to transition from a high level to a low level within a single signal cycle; each beat refers to each signal cycle of the first control signal.

[0033] S14: performing phase shift adjustment on the first control signal using the first pulse width of each beat to obtain a second control signal.

[0034] Furthermore, to achieve the interleaved parallel effect, the first interleaved parallel control circuit 30 needs to perform phase shifting on the first control signal. Specifically, a fixed phase shift is applied to the first control signal based on the first pulse width of each beat, thereby generating a second control signal. This ensures that the two parallel resonant converter circuits 20 operate at different times, but instead start in an interleaved manner, which helps to disperse peak currents and reduce electromagnetic interference.

[0035] In some embodiments, the first control signal and the second control signal may be one or more of any reasonable control signals such as a PWM (Pulse Width Modulation) signal or a PFM (Pulse Frequency Modulation) signal, and this application does not limit this.

[0036] S15: Sending the first control signal and the second control signal to the first resonant conversion circuit and the second resonant conversion circuit respectively to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switch state, thereby adjusting the power supply output signal.

[0037] The first staggered parallel control circuit 30 sends the first control signal and the second control signal to the first resonant conversion circuit 21 and the second resonant conversion circuit 22, respectively, to trigger the corresponding switching elements in the first resonant conversion circuit 21 and the second resonant conversion circuit 22 to change state, and enables the first resonant conversion circuit 21 and the second resonant conversion circuit 22 to operate in a staggered manner, jointly adjusting the power supply output signal of the entire system, and ensuring stable and efficient energy conversion.

[0038] The above solution, by enabling the first resonant conversion circuit 21 and the second resonant conversion circuit 22 to operate in an interleaved parallel mode, can effectively reduce output voltage and current ripple, providing a more stable power supply. By optimizing the energy transmission path within each cycle, the entire system can operate at a higher efficiency level. This disperses the current stress on individual components, extending the service life of key components. While increasing power density by utilizing the first resonant conversion circuit 21 and the second resonant conversion circuit 22 in parallel, output current ripple can also be effectively reduced through corresponding phase shift adjustment. Furthermore, the phase shift adjustment implemented using a digital control method using the first pulse width is simpler and has a faster signal response than a control method relying on a hardware phase modulator.

[0039] Please continue reading Figure 3 , Figure 3 yes Figure 1Flowchart of S12 in an embodiment. In one embodiment, the staggered parallel control method of the present application includes, in addition to the above S11-S15, further includes some more specific steps. Specifically, the above S12 may further include the following steps: S121: Obtaining an adjusted output signal using the difference between the power supply output signal and the target reference voltage.

[0040] Specifically, the first interleaved parallel control circuit 30 compares the power supply output signal with a preset target reference voltage to obtain the difference between the two (i.e., an error signal). Based on the error signal, the circuit generates an adjusted output signal using a proportional-integral-derivative controller or other control algorithm. The adjusted output signal reflects the energy level or direction that needs to be adjusted to bring the power supply output signal closer to the target reference voltage.

[0041] S122: Perform slope compensation on the regulated output signal to obtain a feedback regulated signal.

[0042] In order to prevent subharmonic oscillation and improve system stability, the first interleaved parallel control circuit 30 performs slope compensation on the regulated output signal to obtain a feedback regulated signal.

[0043] It's worth noting that slope compensation is a common technique used in pulse-width modulation controllers to increase the linear ramp rate, thereby preventing unstable switching behavior under certain conditions. The slope-compensated regulated output signal becomes the feedback regulation signal, which contains precise feedback information about the system state and has been optimized for subsequent control decisions.

[0044] S123: Generate a first control signal using the feedback adjustment signal and the resonant current signal.

[0045] It is understandable that the feedback regulation signal and the resonant current signal are combined to generate the final first control signal. This process may involve complex logical judgments or mathematical operations to ensure that the generated control signal reflects both the current error condition and the instantaneous current conditions. The feedback regulation signal provides information about the output voltage deviation, while the resonant current signal reflects the transient behavior within the circuit. Combining the two can provide a more comprehensive understanding of the system's operating status and make optimal control decisions accordingly. For example, the level adjustment moment of the first control signal can be determined based on the comparison of the voltage amplitude between the feedback regulation signal and the resonant current signal to adjust the duty cycle of the first control signal.

[0046] Based on this integrated information, the control system generates a corresponding first control signal, which is sent to relevant components (such as switching elements) in the resonant converter circuit 20 to trigger a state change, thereby adjusting the power output signal until the target reference voltage is reached. This closed-loop control strategy not only improves the stability and response speed of the resonant converter circuit 20, but also enhances its ability to adapt to varying load conditions. By precisely monitoring and adjusting the output voltage, the system can maintain efficient and stable performance under various operating conditions.

[0047] See also Figure 4 , Figure 4 yes Figure 1 In one embodiment, the staggered parallel control method of the present application includes, in addition to the above steps S11-S15, further including some more specific steps. Specifically, the above step S13 may further include the following steps: S131: Acquire each rising edge and falling edge of the first control signal.

[0048] Specifically, the first interleaved parallel control circuit 30 identifies each rising edge (transition from a low level to a high level) and falling edge (transition from a high level to a low level) in the first control signal. For example, this goal can be achieved through any reasonable means such as hardware circuits (such as edge triggers) or software algorithms (for example, writing corresponding codes in an embedded system) or controller counters, and this application does not limit this.

[0049] S132: Obtain a first pulse width of each beat using each rising edge and falling edge.

[0050] For each detected rising and falling edge, record the exact time at which it occurred. This can be achieved by using a timer or counter to provide a high-precision timestamp.

[0051] The width of a pulse can be determined by calculating the time difference between a rising edge and a corresponding falling edge. This time difference is the width of the pulse.

[0052] Therefore, by measuring the time difference between each rising edge and the next adjacent falling edge in the first control signal, the first pulse width of each beat can be obtained.

[0053] See also Figure 5 , Figure 5 yes Figure 1 Flowchart of S14 in an embodiment. In one embodiment, the staggered parallel control method of the present application includes, in addition to the above S11-S15, further some more specific steps. Specifically, the above S14 may further include the following steps: S1411: Acquire each rising edge of the first control signal.

[0054] Specifically, the first interleaved parallel control circuit 30 identifies each rising edge (transition from a low level to a high level) in the first control signal, and can be implemented in any reasonable manner, such as through a hardware circuit (such as an edge trigger) or a software algorithm (such as writing corresponding code in an embedded system) or a controller counter, to capture the starting moment of each pulse. This application does not limit this.

[0055] S1412: Taking each rising edge as the starting moment, delay for half the duration of the first pulse width of the previous beat, and use the first pulse width of the previous beat to obtain the second pulse width of each beat of the second control signal to generate the second control signal.

[0056] It is understandable that for each rising edge, the system calculates a delay time based on the first pulse width of the previous pulse. When there is only one second resonant conversion circuit 22, that is, when there is only one second resonant conversion circuit 22 connected in parallel with the first resonant conversion circuit 21 to supply power, this delay time can be specifically half of the pulse width of the previous pulse.

[0057] For ease of understanding, assuming that the first pulse width of the previous beat is PWf, the delay time is PWf / 2.

[0058] After detecting a new rising edge, the system will wait for the delay time PWf / 2 calculated above before proceeding to the next step. This is done to ensure that the generated second control signal has a phase offset relative to the first control signal to achieve the effect of staggered parallel connection.

[0059] The first pulse width PWf of the previous pulse is used to determine the corresponding second pulse width PWs in the second control signal. In the simplest case, the second pulse width PWs may be directly equal to the first pulse width PWf, but it may be adjusted appropriately according to specific needs.

[0060] After the delay time PWf / 2 has elapsed, this means that each pulse of the second control signal starts at the middle position of the corresponding pulse of the first control signal and has the same or adjusted pulse width.

[0061] It can be seen that by delaying the start of the second control signal by half the pulse width after each rising edge, the phase interleaving between the two resonant conversion circuits 20 operating in parallel can be ensured. This staggered operating mode helps to disperse the peak current and reduce electromagnetic interference. This method uses the pulse width information of the previous beat to generate the control signal for the next beat, simplifies the synchronous control logic, and makes it easier for the system to achieve precise phase control. Staggered parallel control can effectively reduce the ripple of the output voltage and current, improve the stability and efficiency of the system, and is particularly suitable for applications with high requirements for power quality and efficiency, such as uninterruptible power supplies, renewable energy inverters, etc.

[0062] See also Figure 6 , Figure 6 yes Figure 1 Flowchart of another embodiment of S14 in FIG. In one embodiment, the staggered parallel control method of the present application includes, in addition to the above S11-S15, further some more specific steps. Specifically, the above S14 may further include the following steps: S1421: Divide the first pulse width by the sum of the number of the first resonant conversion circuit and the number of the second resonant conversion circuit to obtain a pulse adjustment width.

[0063] It is understandable that when the number of the second resonant conversion circuits 22 is at least two, that is, when the system is powered by multiple parallel resonant conversion circuits 20, it is necessary to ensure that each resonant conversion circuit 20 operates with an appropriate phase difference to optimize the performance of the entire system.

[0064] For ease of understanding, assume that the first pulse width is PWf, the number of first resonant conversion circuits 21 is one, and the number of second resonant conversion circuits 22 is n, such as second resonant conversion circuit 1, second resonant conversion circuit 2, ..., second resonant conversion circuit n, respectively. In this embodiment, n is greater than or equal to 2. The pulse adjustment width PWr can be calculated using the following formula: PWr = PWf / (n + 1). This value is used to determine the delay between each control signal.

[0065] S1422: Acquire each rising edge of the first control signal.

[0066] Specifically, the first interleaved parallel control circuit 30 identifies each rising edge (transition from a low level to a high level) in the first control signal, and can be implemented in any reasonable manner, such as through a hardware circuit (such as an edge trigger) or a software algorithm (such as writing corresponding code in an embedded system) or a controller counter, to capture the starting moment of each pulse. This application does not limit this.

[0067] S1423: Taking each rising edge as the starting moment, the corresponding duration of the delay pulse adjustment width adopts the first pulse width of the previous beat to obtain the second pulse width of each beat of the first second control signal to generate the first second control signal.

[0068] After detecting a new rising edge, the system begins timing and waits for a pulse width PWr. That is, after a delay of PWr, the first interleaved parallel control circuit 30 uses the previous pulse width PWf to generate the second pulse width PWS1 of the first second control signal. The second pulse width PWS1 can be equal to the first pulse width PWf or adjusted according to specific needs.

[0069] The first interleaved parallel control circuit 30 is further configured to utilize the generated first second control signal to trigger the second resonant conversion circuit 1 to change its switching state.

[0070] S1424: The corresponding duration of the delayed pulse adjustment width is obtained again by using the first pulse width of the previous beat to obtain the second pulse width of each beat of the second second control signal to generate a second second control signal until the cumulative number of delays is equal to the number of second resonant conversion circuits, thereby obtaining at least two second control signals.

[0071] Furthermore, after a further delay of 2*PWr, the first interleaved parallel control circuit 30 generates a second second control signal using the first pulse width PWf of the previous pulse to generate a second pulse width PWS2 of the first second control signal. The second pulse width PWS2 can be equal to the first pulse width PWf or adjusted according to specific needs.

[0072] The first interleaved parallel control circuit 30 is further configured to utilize the generated second control signal to trigger the second resonant conversion circuit 2 to change its switching state.

[0073] The above process is repeated, generating a new second control signal after each delay PWr. Specifically, after the first delay PWr, the first second control signal is generated; after another delay PWr, the second second control signal is generated; this process continues until the cumulative number of delays equals the number n of second resonant conversion circuits 22. Each generated second control signal uses the same first pulse width PWf, or an appropriately adjusted pulse width calculated based on the first pulse width PWf.

[0074] The first staggered parallel control circuit 30 utilizes the first to nth second control signals to respectively trigger the second resonant conversion circuit 1 , the second resonant conversion circuit 2 , . . . , the second resonant conversion circuit n to change their switching states.

[0075] By properly allocating phase differences, the operation of multiple resonant converter circuits 20 can be more balanced, preventing situations where one circuit is overloaded while others are idle. Interleaved parallel operation helps disperse peak currents, reducing output voltage and current ripple, while also minimizing electromagnetic interference. By optimizing energy transmission paths and reducing unnecessary losses, the overall system efficiency can be significantly improved.

[0076] See also Figure 7 and Figure 8 ,in, Figure 7 This is a flow chart of the second embodiment of the staggered parallel control method of the present application. Figure 8 : is a schematic diagram of the structure of the second embodiment of the staggered parallel control circuit. The staggered parallel control method of this embodiment is Figure 1 A flowchart of a detailed implementation of the staggered parallel control method in FIG. 1 specifically includes the following steps: S41: Acquire a resonant current signal and a power supply output signal in the first resonant conversion circuit.

[0077] Among them, S41 and Figure 1 For details, please refer to S11 and its related text descriptions, which will not be repeated here.

[0078] S42: Obtaining an adjusted output signal using the difference between the power supply output signal and the target reference voltage.

[0079] It is understandable that the staggered parallel control method in this embodiment can be specifically as follows: Figure 8The second interleaved parallel control circuit 50 shown implements interleaved parallel control of the resonant conversion circuit 20. The resonant conversion circuit 20 includes a first resonant conversion circuit 21 and a second resonant conversion circuit 22. The first resonant conversion circuit 21 includes a first power switch circuit 211, a first switch freewheeling circuit 212, a first resonant circuit 213, a first isolation transformer 214, a first rectifier circuit 215, and a voltage-stabilized output circuit 216. The second resonant conversion circuit 22 includes a second power switch circuit 221, a second switch freewheeling circuit 222, a second resonant circuit 223, a second isolation transformer 224, and a second rectifier circuit 225. The first power switch circuit 211 includes a first switch tube Q11 and a second switch tube Q12. The first resonant conversion circuit 21 includes a first power switch circuit 211, a first switch freewheeling circuit 212, a first resonant circuit 213, a first isolation transformer 214, a first rectifier circuit 215, and a voltage-stabilized output circuit 216. The second resonant conversion circuit 22 includes a second power switch circuit 221, a second switch freewheeling circuit 222, a second resonant circuit 223, a second isolation transformer 224, and a second rectifier circuit 225. The switch freewheeling circuit 212 includes a first freewheeling resistor Rc11, a second freewheeling resistor Rc12, a first freewheeling capacitor C11, a second freewheeling capacitor C12, a first diode D11, and a second diode D12; the first resonant circuit 213 includes a first resonant capacitor Cr11, a second resonant capacitor Cr12, and a first resonant inductor Lr1; the first isolation transformer 214 includes a first primary winding Lm1, a first secondary winding Ln11, and a second secondary winding Ln12; the first rectifier circuit 215 includes a third diode D13 and a fourth diode D14; the voltage-stabilized output circuit 216 further includes a voltage-stabilizing resistor Ro and a voltage-stabilizing capacitor Co. The second power switch circuit 221 includes a third switch tube Q21 and a fourth switch tube Q22; the second switch freewheeling circuit 222 includes a third freewheeling resistor Rc21, a fourth freewheeling resistor Rc22, a third freewheeling capacitor C21, a fourth freewheeling capacitor C22, a fifth diode D21, and a sixth diode D22; the second resonant circuit 223 includes a third resonant capacitor Cr21, a fourth resonant capacitor Cr22, and a second resonant inductor Lr2; the second isolation transformer 224 includes a second primary winding Lm2, a third secondary winding Ln21, and a fourth secondary winding Ln22; the second rectifier circuit 225 includes a seventh diode D23 and an eighth diode D24.

[0080] The first end of the first switch tube Q11 is coupled to the first end of the first freewheeling resistor Rc11, the second end of the first diode D11, the first end of the first resonant capacitor Cr11, the first end of the third switch tube Q21, the first end of the third freewheeling resistor Rc21, the second end of the fifth diode D21, and the first end of the third resonant capacitor Cr21, and is used to couple to the first end of the power circuit 501. The second end of the second switch tube Q12 is coupled to the second end of the second freewheeling capacitor C12, the first end of the second diode D12, the second end of the second resonant capacitor Cr12, the second end of the fourth switch tube Q22 is coupled to the second end of the fourth freewheeling capacitor C22, the first end of the sixth diode D22, and the second end of the fourth resonant capacitor Cr22, and is used to couple to the second end of the power circuit 501. The second end of the first freewheeling resistor Rc11 is coupled to the first end of the first freewheeling capacitor C11. The second end of the first freewheeling capacitor C11 is coupled to the first end of the first diode D11, the second end of the first switch tube Q11, the first end of the second switch tube Q12, the first end of the second freewheeling resistor Rc12, The second end of the second diode D12 and the first end of the first resonant inductor Lr1, the second end of the second freewheeling resistor Rc12 are coupled to the first end of the second freewheeling capacitor C12, the second end of the first resonant capacitor Cr11 is coupled to the first end of the second resonant capacitor Cr12 and the second end of the first primary winding Lm1, the second end of the first resonant inductor Lr1 is coupled to the first end of the first primary winding Lm1; the second end of the third freewheeling resistor Rc21 is coupled to the first end of the third freewheeling capacitor C21, and the second end of the third freewheeling capacitor C21 is coupled to the fifth diode. The first end of the transistor D21, the second end of the third switch tube Q21, the first end of the fourth switch tube Q22, the first end of the fourth freewheeling resistor Rc22, the second end of the sixth diode D22 and the first end of the second resonant inductor Lr2, the second end of the fourth freewheeling resistor Rc22 is coupled to the first end of the fourth freewheeling capacitor C22, the second end of the third resonant capacitor Cr21 is coupled to the first end of the fourth resonant capacitor Cr22 and the second end of the second primary winding Lm2, and the second end of the second resonant inductor Lr2 is coupled to the first end of the second primary winding Lm2.

[0081] The first primary winding Lm1 is coupled to the first secondary winding Ln11 and the second secondary winding Ln12, the first end of the third diode D13 is coupled to the first end of the first secondary winding Ln11, the second end of the third diode D13 is coupled to the second end of the fourth diode D14, the first end of the zener resistor Ro, the second end of the seventh diode D23, and the second end of the eighth diode D24, and is used to couple to the load circuit R, that is, the first end of the load circuit 102, the first end of the fourth diode D14 is coupled to the second end of the second secondary winding Ln12, the second end of the zener resistor Ro is coupled to the first end of the zener capacitor Co, the second end of the zener capacitor Co is coupled to the second end of the first secondary winding Ln11, the first end of the second secondary winding Ln12, the second end of the third secondary winding Ln21, and the first end of the fourth secondary winding Ln22, and is used to couple to the second end of the load circuit 102.

[0082] In some embodiments, the first switch tube Q11, the second switch tube Q12, the third switch tube Q21 and the fourth switch tube Q22 can specifically be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a triode, a thin film transistor or a field effect transistor or any other reasonable switch tube, and this application does not limit this.

[0083] It is worth noting that, to distinguish the two ends of each switching transistor other than the control terminal, one of the terminals is referred to as the first terminal and the other as the second terminal. When each switching transistor is a triode, the control terminal, i.e., the third terminal, can be specifically the base, while the first terminal is the collector and the second terminal is the emitter. Alternatively, the third terminal can be specifically the base, while the first terminal is the emitter and the second terminal is the collector.

[0084] When the above switching tubes are MOSFETs, thin film transistors or field effect transistors, the third end can be a gate, the first end can be a drain, and the second end can be a source; or, the third end can be a gate, the first end can be a source, and the second end can be a drain.

[0085] When each switch tube is a MOSFET, a thin film transistor or a field effect transistor, it can also be a composite transistor or a single transistor, which is not limited in this application.

[0086] It is worth noting that, in other embodiments, the first resonant conversion circuit 21 and the second resonant conversion circuit 22 can specifically be a half-bridge LLC converter, a full-bridge LLC converter or any other reasonable form of LLC circuit topology. For example, the first power switching circuit 211 and the second power switching circuit 221 can specifically be a full-bridge switching circuit or an asymmetric half-bridge switching circuit. The first rectifier circuit 215 and the second rectifier circuit 225 can specifically be a full-bridge rectifier circuit or a half-bridge rectifier circuit composed of various switching tubes, and any reasonable circuit form for realizing AC to DC conversion.

[0087] The first control signal includes a first driving signal PWMA and a second driving signal PWMB, and the second control signal includes a third driving signal PWMH and a fourth driving signal PWML.

[0088] Specifically, the first interleaved parallel control circuit 30 compares the power output signal Vo with a preset target reference voltage to obtain the difference between the two (i.e., an error signal). Based on the error signal, the circuit generates an adjusted output signal using a proportional-integral-derivative controller or other control algorithm. The adjusted output signal reflects the energy level or direction that needs to be adjusted to bring the power output signal Vo closer to the target reference voltage.

[0089] S43: In the first half of each signal cycle of the first driving signal, in response to the second driving signal being adjusted from a high level to a low level, a delay of a set duration or a set slope compensation slope is used to perform slope compensation on the regulated output signal to obtain a feedback regulated signal.

[0090] See also Figure 9 , Figure 9 yes Figure 8 Schematic diagram of waveforms of various related signals used by the interleaved parallel control circuit to generate the first control signal.

[0091] It is understood that during the first half of each cycle of the first drive signal PWMA, the first interleaved parallel control circuit 30 monitors the level state changes of the second drive signal PWMB. When the second drive signal PWMB changes from a high level to a low level, the first interleaved parallel control circuit 30 performs slope compensation on the regulated output signal using a set slope compensation slope to obtain a feedback regulated signal. Specifically, a ramp signal with a set slope is added to the regulated output signal to prevent subharmonic oscillation and improve system stability. Slope compensation can be implemented using hardware circuits or software algorithms. Alternatively, when the second drive signal PWMB changes from a high level to a low level, the first interleaved parallel control circuit 30 may delay for a set period of time (e.g., to wait for circuit stabilization or a predetermined time point) before performing slope compensation on the regulated output signal using the set slope compensation slope to obtain the feedback regulated signal.

[0092] In some embodiments, the set duration may specifically be the on-off dead time of each switch tube in the inverter circuit, or may be a specific duration determined according to a specific application scenario, which is not limited in this application.

[0093] S44: Delay for a set time or adjust the first driving signal from a low level to a high level at the same time.

[0094] After the above slope compensation, the first interleaved parallel control circuit 30 may choose to delay the set time again, or directly adjust the first driving signal PWMA from a low level to a high level at the same time.

[0095] S45: When the resonant current signal is greater than or equal to the feedback adjustment signal, adjust the first driving signal from a high level to a low level.

[0096] The first interleaved parallel control circuit 30 continuously monitors the resonant current signal and compares it with the feedback regulation signal. When the resonant current signal is greater than or equal to the feedback regulation signal, it indicates that the current operating conditions have met the preset standard. At this time, the state of the first drive signal PWMA needs to be adjusted from a high level to a low level.

[0097] S46: In the second half of each signal cycle, copy the first driving signal of each first half cycle to obtain a second driving signal.

[0098] In the second half of each second signal cycle, the level state change of the first driving signal PWMA in the first half is copied to generate the second driving signal PWMB.

[0099] S47: Obtain a first pulse width of each beat of the first driving signal.

[0100] Furthermore, the first interleaved parallel control circuit 30 acquires the first drive signal PWMA in real time and identifies each rising edge (transition from a low level to a high level) and falling edge (transition from a high level to a low level). This can be achieved using a hardware logic comparator or a software algorithm. For each detected rising edge and corresponding falling edge, the time difference is calculated to determine the first pulse width of each beat.

[0101] S48: performing phase shift adjustment on the first driving signal using the first pulse width of each beat to obtain a third driving signal.

[0102] The first drive signal PWMA is phase-shifted based on the first pulse width of each beat to generate the third drive signal PWMH. The specific method of phase shifting can be determined based on system requirements, but is typically used to achieve an interleaved parallel effect and reduce ripple and harmonic interference. For example, the first drive signal PWMA can be delayed by a fixed phase angle to generate the third drive signal PWMH, and the third pulse width of each beat of the third drive signal PWMH is equal to the first pulse width of the previous beat.

[0103] S49: Obtain a fourth driving signal using the third driving signal.

[0104] In order to achieve phase complementary symmetry, the third drive signal PWMH can be phase-shifted by 180 degrees to generate the fourth drive signal PWML; or, when the third drive signal PWMH is adjusted from a high level to a low level, the fourth drive signal PWML is delayed for a set period of time or adjusted from a low level to a high level at the same time, and when the third drive signal PWMH is adjusted from a low level to a high level, the fourth drive signal PWML is delayed for a set period of time or adjusted from a high level to a low level at the same time, so that when the third drive signal PWMH is at a high level, the fourth drive signal PWML is at a low level, and vice versa.

[0105] S410: Regulating the switching state of the first resonant conversion circuit using the first drive signal and the second drive signal, and regulating the switching state of the second resonant conversion circuit using the third drive signal and the fourth drive signal, thereby regulating the power supply output signal.

[0106] The first interleaved parallel control circuit 30 uses the first drive signal PWMA and the second drive signal PWMB to trigger the switching element in the first resonant conversion circuit 21 to change state, and uses the third drive signal PWMH and the fourth drive signal PWML to trigger the switching element in the second resonant conversion circuit 22 to change state, so as to adjust the power supply output signal Vo, thereby responding to load changes more flexibly and efficiently, and ensuring that the power supply output signal Vo is stable and efficient.

[0107] The second interleaved parallel control circuit 50 is further coupled to the third terminal of the first switch Q11, the third terminal of the second switch Q12, the third terminal of the third switch Q21, and the third terminal of the fourth switch Q22. The second interleaved parallel control circuit 50 is configured to send a first drive signal PWMA and a second drive signal PWMB to the third terminal of the first switch Q11 and the third terminal of the second switch Q12, respectively, to adjust the switching state of the first power switch circuit 211. The second interleaved parallel control circuit 50 also sends a third drive signal PWMH and a fourth drive signal PWML to the third terminal of the third switch Q21 and the third terminal of the fourth switch Q22, respectively, to adjust the switching state of the second power switch circuit 221. This adjusts the power output signal Vo of the voltage-regulated output circuit 216, thereby more flexibly and efficiently responding to load changes and ensuring that the power output signal Vo is stable and efficient.

[0108] Through interleaved parallel operation and phase-complementary symmetrical design, output voltage and current ripple and harmonics are significantly reduced, improving power quality. Precise phase-shift regulation and pulse-width control enable more efficient energy transmission and reduce unnecessary losses. This approach improves the system's dynamic response speed and stability, enabling it to maintain optimal performance under a wide range of operating conditions.

[0109] Furthermore, in one embodiment, the second interleaved parallel control circuit 50 may further include a sampling integration circuit 51, a first proportional filtering correction processing circuit 52, a second proportional filtering correction processing circuit 53 and a control sub-circuit 54, wherein the sampling integration circuit 51 includes a current transformer CT and an integral sampling capacitor CJ; a first end of the current transformer CT is coupled to the second end of the first resonant capacitor Cr11, the first end of the second resonant capacitor Cr12 and the first end of the integral sampling capacitor CJ, a second end of the current transformer CT is coupled to the second end of the first primary winding Lm1 and the second end of the integral sampling capacitor CJ, and the first proportional filtering correction processing circuit 52 includes a sampling integration circuit 51 and a control sub-circuit 54, wherein the sampling integration circuit 51 includes a current transformer CT and an integral sampling capacitor CJ; The positive processing circuit 52 is coupled to the first end of the voltage-stabilizing resistor Ro, the second end of the voltage-stabilizing capacitor Co and the control sub-circuit 54. The second proportional filtering correction processing circuit 53 is coupled to the integral sampling capacitor CJ and the control sub-circuit 54. The control sub-circuit 54 is coupled to the third end of the first switch tube Q11, the third end of the second switch tube Q12, the third end of the third switch tube Q21 and the third end of the fourth switch tube Q22. The above-mentioned S41 can also specifically include: using the current transformer CT to sample and obtain the resonant current signal in the first resonant conversion circuit 21, and using the integral sampling capacitor CJ to integrate the resonant current signal to obtain the resonant capacitor voltage Vcs.

[0110] Among them, the first proportional filtering and correction processing circuit 52 is used to obtain the power supply output signal Vo output by the voltage stabilizing output circuit 216 to the load circuit 102, and compares the power supply output signal Vo with the reference value, filters, and corrects it in turn to obtain a first filtered signal; the second proportional filtering and correction processing circuit 53 is used to obtain the resonant capacitor voltage Vcs in the sampling integration circuit 51, and compares the resonant capacitor voltage Vcs with the reference value, filters, and corrects it in turn to obtain a second filtered signal, so as to provide a more suitable high-quality input for the control sub-circuit 54, thereby effectively optimizing the overall performance and reliability of the control sub-circuit 54 to achieve efficient control.

[0111] The control subcircuit 54 is further used to receive the first filtered signal and the second filtered signal, and use the first filtered signal and the second filtered signal to correspond to S42-S410 respectively to obtain a first drive signal PWMA, a second drive signal PWMB, a third drive signal PWMH and a fourth drive signal PWML, so as to use the first drive signal PWMA, the second drive signal PWMB, the third drive signal PWMH and the fourth drive signal PWML to respectively control the first switch tube Q11, the second switch tube Q12, the third switch tube Q21 and the fourth switch tube Q22 to adjust the power supply output signal Vo.

[0112] See also Figure 10 , Figure 10 yes Figure 8 Schematic diagram of the wave generation logic of the staggered parallel control circuit.

[0113] The control subcircuit 54 integrates a logic comparator. The high terminal of the logic comparator receives the resonant capacitor voltage Vcs or the second filtered signal, and the low terminal of the logic comparator receives the output signal of the voltage loop controller. After slope compensation, a feedback adjustment signal is obtained. Each time a wave transmission cycle ends and the next cycle count reaches 0, slope compensation is triggered. The voltage loop controller in the control subcircuit 54 adjusts the input voltage amplitude of the logic comparator's low terminal based on the error. When the high terminal of the logic comparator is greater than the low terminal voltage, the output turns off the first drive signal PWMA. When the voltage loop controller's counter counts to 0, the first drive signal PWMA is turned on. After the first drive signal PWMA is turned off, the second drive signal PWMB is turned on, with a pulse width that replicates the width of the first drive signal PWMA. The second drive signal PWMB turns off after the pulse width of the first drive signal PWMA equals the pulse width of the first drive signal PWMA. At this point, the voltage loop controller's counter is reset to zero and starts counting again from 0.

[0114] See also Figure 10 , Figure 10 yes Figure 7In one embodiment, the staggered parallel control method of the present application includes, in addition to the above-mentioned S41-S410, further including some more specific steps. Specifically, the above-mentioned S13 may further include the following steps: S481: Acquire each rising edge and falling edge of the first driving signal.

[0115] Specifically, the first interleaved parallel control circuit 30 accurately identifies each rising edge (transition from a low level to a high level) and falling edge (transition from a high level to a low level) of the first drive signal PWMA.

[0116] S482: Taking each rising edge as the starting moment, the third driving signal PWMH is adjusted from a low level to a high level by delaying for half the duration of the previous first pulse.

[0117] For each rising edge, the first interleaved parallel control circuit 30 may further calculate the delay time PWf / 2 according to the first pulse width PWf of the previous beat.

[0118] After the delay time PWf / 2, the third driving signal PWMH is adjusted from a low level to a high level. This is done to make the third driving signal PWMH have a fixed phase offset relative to the first driving signal PWMA, so as to achieve the effect of staggered parallel connection.

[0119] S483: Taking each falling edge as the starting moment, the third driving signal is adjusted from a high level to a low level by delaying for half the duration of the first pulse of the previous beat.

[0120] Likewise, for each falling edge, the first interleaved parallel control circuit 30 calculates the delay time PWf / 2 according to the first pulse width PWf of the previous pulse.

[0121] After the delay time PWf / 2, the third driving signal PWMH is adjusted from a high level to a low level, thereby ensuring that the third driving signal PWMH maintains a consistent phase relationship with the first driving signal PWMA.

[0122] By delaying the start of the third drive signal PWMH by half a pulse width after each rising and falling edge, the phase relationship between the two drive signals can be ensured to be very precise. This interleaved operating mode helps to disperse peak currents and reduce electromagnetic interference. This method uses the pulse width information of the previous pulse to generate the control signal for the next pulse, simplifying the synchronous control logic and making it easier for the system to achieve precise phase control. Interleaved parallel control can effectively reduce output voltage and current ripple, improving system stability and efficiency. It is particularly suitable for applications with high requirements for power quality and efficiency, such as uninterruptible power supplies and renewable energy inverters.

[0123] For ease of understanding, assume that the first pulse width PWf of the previous beat is 10 microseconds: 1. Rising edge processing: detecting a rising edge of the first driving signal PWMA; Wait for PWf / 2=5 microseconds; After the delay ends, the third driving signal PWMH is adjusted from a low level to a high level.

[0124] 2. Falling edge processing: detecting a falling edge of the first driving signal PWMA; Wait for PWf / 2=5 microseconds; After the delay ends, the third driving signal PWMH is adjusted from a high level to a low level.

[0125] See also Figure 11 , Figure 11 yes Figure 8 Schematic diagram of the wave generation logic of the staggered parallel control circuit.

[0126] It is understood that the control subcircuit 54 internally integrates a logic comparator. The high terminal of the logic comparator receives the resonant capacitor voltage Vcs or the second filtered signal, and the low terminal of the logic comparator receives the output signal of the voltage loop controller, which is slope-compensated to obtain a feedback adjustment signal. Each time a wave cycle ends and the next cycle count reaches 0, slope compensation is triggered. The voltage loop controller in the control subcircuit 54 adjusts the input voltage amplitude of the logic comparator's low terminal based on the error. When the high terminal of the logic comparator is greater than the low terminal potential, the output turns off the first drive signal PWMA. When the voltage loop controller's counter counts to 0, the first drive signal PWMA is turned on. The second drive signal PWMB is turned on after the first drive signal PWMA is turned off, with a pulse width that replicates the width of the first drive signal PWMA. The second drive signal PWMB is turned on after the first drive signal PWMA is turned off, with a pulse width that matches the pulse width of the first drive signal PWMA. The second drive signal PWMB is turned off after the pulse width equals the pulse width of the first drive signal PWMA. At this point, the voltage loop controller's counter is reset to zero and counts again from 0.

[0127] Furthermore, when the voltage loop controller counter is equal to 0, the first drive signal PWMA is set high, the high terminal potential of the logic comparator is higher than the low terminal, the first drive signal PWMA is set low, and the rising edge and falling edge of the first drive signal PWMA are obtained respectively. The first counter counter1 and the second counter counter2 record the pulse width of the first drive signal PWMA. Figure 9 The wave generation logic waits until the next first drive signal PWMA is generated. At the rising edge of the next first drive signal PWMA, the first counter 1 counts to half the pulse width of the previous first drive signal PWMA and generates a pulse, turning on the third drive signal PWMH. At the falling edge of the next first drive signal PWMA, the second counter 2 counts to half the pulse width of the previous first drive signal PWMA and generates a pulse, turning off the third drive signal PWMH. This causes the master phase and the slave phase to be staggered by 90 degrees, and the fourth drive signal PWML and the third drive signal PWMH to have complementary and symmetrical phases. In this way, the master and slave phases are cyclically generated to achieve a regulated voltage output.

[0128] This application also provides an electronic device, see Figure 12 , Figure 12 FIG. 2 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 60 includes a housing 61 and a third interleaved parallel control circuit 62 connected to the housing 61 .

[0129] It should be noted that the third interleaved parallel control circuit 62 described in this embodiment is the first interleaved parallel control circuit 30 or the second interleaved parallel control circuit 50 described in any one of the above embodiments. Figures 1-11 And the related text content will not be repeated here.

[0130] The beneficial effects of the present application are as follows: Different from the prior art, the staggered parallel control method provided by the present application obtains the resonant current signal and the power supply output signal in the first resonant conversion circuit, generates a first control signal by using the resonant current signal and the power supply output signal, and obtains the first pulse width of each beat of the first control signal, and uses the first pulse width of each beat to perform phase shift adjustment on the first control signal to obtain a second control signal, thereby using the first control signal and the second control signal to staggeredly control the first resonant conversion circuit and the second resonant conversion circuit in parallel, and adjust the power supply output signal, so that while improving the power density by using the first resonant conversion circuit and the second resonant conversion circuit in parallel, the output current ripple can also be effectively reduced by corresponding phase shift adjustment; and the phase shift adjustment of the digital control method realized by the first pulse width is simpler than the control method relying on the hardware phase modulator, and the signal response is also faster.

[0131] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A staggered parallel control method, applied to staggered parallel control of a resonant conversion circuit, wherein the resonant conversion circuit comprises a first resonant conversion circuit and a second resonant conversion circuit connected in parallel with each other, characterized in that: The staggered parallel control method includes: Acquiring a resonant current signal and a power supply output signal in the first resonant conversion circuit; generating a first control signal using the resonant current signal and the power supply output signal; Obtaining a first pulse width of each beat of the first control signal; Performing phase shift adjustment on the first control signal using the first pulse width of each beat to obtain a second control signal; The first control signal and the second control signal are sent to the first resonant conversion circuit and the second resonant conversion circuit respectively to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power supply output signal.

2. The staggered parallel control method according to claim 1, characterized in that: The step of obtaining the first pulse width of each beat of the first control signal includes: Obtain each rising edge and falling edge of the first control signal; The first pulse width of each beat is obtained by using each rising edge and each falling edge.

3. The staggered parallel control method according to claim 1, characterized in that: The step of performing phase shift adjustment on the first control signal using the first pulse width of each beat to obtain the second control signal comprises: Obtaining each rising edge of the first control signal; Taking each rising edge as the starting moment, the duration of the delay is half of the first pulse width of the previous beat, and the second pulse width of each beat of the second control signal is obtained by using the first pulse width of the previous beat to generate the second control signal.

4. The staggered parallel control method according to claim 1, characterized in that: The number of the second resonant conversion circuits is at least two, and the step of using the first pulse width of each beat to perform phase shift adjustment on the first control signal to obtain the second control signal includes: The pulse adjustment width is obtained by dividing the first pulse width by the sum of the number of the first resonant conversion circuit and the second resonant conversion circuit; Obtaining each rising edge of the first control signal; Taking each rising edge as a starting moment, delaying the pulse adjustment width for a corresponding duration and using the first pulse width of the previous beat to obtain the second pulse width of each beat of the first second control signal, so as to generate the first second control signal; The corresponding duration of delaying the pulse adjustment width again adopts the first pulse width of the previous beat to obtain the second pulse width of each beat of the second control signal to generate the second second control signal until the cumulative number of delays is equal to the number of the second resonant conversion circuits, thereby obtaining at least two second control signals.

5. The staggered parallel control method according to claim 1, characterized in that: The step of generating a first control signal by using the resonant current signal and the power supply output signal comprises: obtaining a regulated output signal using a difference between the power supply output signal and a target reference voltage; performing slope compensation on the regulated output signal to obtain a feedback regulated signal; The first control signal is generated using the feedback adjustment signal and the resonant current signal.

6. The staggered parallel control method according to claim 5, characterized in that: The first control signal includes a first drive signal and a second drive signal, and the step of performing slope compensation on the regulated output signal to obtain a feedback regulated signal includes: In the first half of each signal cycle of the first drive signal, in response to the second drive signal being adjusted from a high level to a low level, performing slope compensation on the regulated output signal by delaying for a set time or simultaneously using a set slope compensation slope to obtain the feedback regulated signal; The step of generating the first control signal by using the feedback adjustment signal and the resonant current signal includes: Delaying the set time or adjusting the first driving signal from the low level to the high level at the same time; When the resonant current signal is greater than or equal to the feedback adjustment signal, adjusting the first driving signal from the high level to the low level; In the second half of each signal cycle, the first driving signal of each first half cycle is copied to obtain the second driving signal.

7. The staggered parallel control method according to claim 6, characterized in that: The second control signal includes a third drive signal and a fourth drive signal, and the step of obtaining a first pulse width of each beat of the first control signal includes: Obtaining a first pulse width of each beat of the first driving signal; The step of performing phase shift adjustment on the first control signal using the first pulse width of each beat to obtain the second control signal comprises: performing phase shift adjustment on the first driving signal using the first pulse width of each beat to obtain a third driving signal; The fourth driving signal is obtained by using the third driving signal; wherein the third driving signal and the fourth driving signal are complementary and symmetrical in phase; The step of sending the first control signal and the second control signal to the first resonant conversion circuit and the second resonant conversion circuit respectively to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power supply output signal includes: The first drive signal and the second drive signal are used to adjust the switching state of the first resonant conversion circuit, and the third drive signal and the fourth drive signal are used to adjust the switching state of the second resonant conversion circuit, thereby adjusting the power supply output signal.

8. The staggered parallel control method according to claim 7, characterized in that: The step of performing phase shift adjustment on the first driving signal using the first pulse width of each beat to obtain a third driving signal comprises: Obtaining each rising edge and falling edge of the first driving signal; Taking each rising edge as a starting moment, delaying the third driving signal by half the first pulse width of the previous pulse to adjust the third driving signal from the low level to the high level; Taking each falling edge as a starting moment, the third driving signal is adjusted from the high level to the low level by delaying for half the duration of the first pulse width of the previous pulse.

9. A staggered parallel control circuit, characterized in that: The staggered parallel control couples the first resonant conversion circuit and the second resonant conversion circuit, and the first resonant conversion circuit and the second resonant conversion circuit are connected in parallel with each other; The interleaved parallel control circuit implements interleaved parallel control of the first resonant conversion circuit and the second resonant conversion circuit using the interleaved parallel control method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device includes a housing and an interleaved parallel control circuit connected to the housing; Wherein, the interleaved parallel control circuit is the interleaved parallel control circuit according to claim 9.

Images