Interleaved parallel control method, interleaved parallel control circuit, and electronic device

Abstract

The application discloses a staggered parallel control method, a staggered parallel control circuit and electronic equipment. The staggered parallel control method comprises the following steps: obtaining a resonant current signal and a power supply output signal in a first resonant conversion circuit; generating a first control signal by using the resonant current signal and the power supply output signal; obtaining a first pulse width of each beat of the first control signal; performing phase shift adjustment on the first control signal by using the first pulse width of each beat to obtain a second control signal; and sending the first control signal and the second control signal to the first resonant conversion circuit and a second resonant conversion circuit respectively, so as to trigger the first resonant conversion circuit and the second resonant conversion circuit to change a switching state, thereby adjusting the power supply output signal. In the foregoing manner, the staggered parallel control method can effectively reduce the output current ripple by using phase shift adjustment under the premise of improving the power density, and the control method is simple and has a relatively fast response.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit control, in particular to an interleaved parallel control method, an interleaved parallel control circuit and an electronic device. BACKGROUND

[0002] Nowadays, with the continuous miniaturization and informatization of electronic devices, higher requirements are put forward for high-efficiency, high-power density and low-noise power supply systems. LLC resonant converter (containing an additional inductance (L, inductance) in series with two other components, inductance L and capacitor (C, capacitor), hence the name L-L-C converter) has become the first choice of high-frequency and high-efficiency power supply design due to its characteristics of realizing soft switching (zero voltage / zero current switching) in the full load range.

[0003] However, the single-channel LLC resonant converter has the problem of limited power density. In order to improve the power density, multiple LLC resonant conversion circuits are needed to be connected in parallel for power supply, but the parallel connection of multiple LLC resonant converters has the problems of large output current ripple, complex control mode of each LLC resonant converter and slow response. SUMMARY

[0004] The technical problem solved by the present application is to provide an interleaved parallel control method, an interleaved parallel control circuit and an electronic device, which can solve the problem of limited power density of single-channel LLC resonant converter in related technology, and the problem of large output current ripple, complex control mode of each LLC resonant converter and slow response of multiple LLC resonant converters connected in parallel.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide an interleaved parallel control method applied to the interleaved parallel control of a resonant conversion circuit, the resonant conversion circuit comprising a first resonant conversion circuit and a second resonant conversion circuit connected in parallel with each other, wherein the interleaved parallel control method comprises: obtaining a resonant current signal in the first resonant conversion circuit and a power supply output signal; generating a first control signal using the resonant current signal and the power supply output signal; obtaining a first pulse width of each beat of the first control signal; phase-shifting and adjusting the first control signal using the first pulse width of each beat to obtain a second control signal; and sending the first control signal and the second control signal to the first resonant conversion circuit and the second resonant conversion circuit, respectively, to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, so as to adjust the power supply output signal.

[0006] The step of obtaining the first pulse width of each beat of the first control signal comprises: obtaining each rising edge and falling edge of the first control signal; and obtaining the first pulse width of each beat using each rising edge and falling edge.

[0007] The step of phase-shifting the first control signal by the first pulse width of each beat to obtain the second control signal comprises: obtaining each rising edge of the first control signal; taking each rising edge as a starting time, delaying for a duration of one-half of the first pulse width of the previous beat, and obtaining the second pulse width of each beat of the first second control signal by using the first pulse width of the previous beat to generate the first second control signal.

[0008] The step of phase-shifting the first control signal by the first pulse width of each beat to obtain the second control signal comprises: obtaining each rising edge of the first control signal; taking each rising edge as a starting time, delaying for a duration of one-half of the first pulse width of the previous beat, and obtaining the second pulse width of each beat of the first second control signal by using the first pulse width of the previous beat to generate the first second control signal.

[0009] The step of generating the first control signal by using the resonant current signal and the power supply output signal comprises: obtaining an adjusted output signal by using a difference between the power supply output signal and a target reference voltage; obtaining a feedback adjustment signal by performing slope compensation on the adjusted output signal; and generating the first control signal by using the feedback adjustment signal and the resonant current signal.

[0010] The first control signal comprises a first drive signal and a second drive signal, the step of obtaining the feedback adjustment signal by performing slope compensation on the adjusted output signal comprises: in a first half period of each signal period of the first drive signal, in response to the second drive signal being adjusted from high to low, delaying for a set duration or simultaneously performing slope compensation on the adjusted output signal by using a set slope compensation slope to obtain the feedback adjustment signal, and the step of generating the first control signal by using the feedback adjustment signal and the resonant current signal comprises: delaying for a set duration or simultaneously adjusting the first drive signal from low to high, adjusting the first drive signal from high to low when the resonant current signal is greater than or equal to the feedback adjustment signal, and copying the first drive signal of each first half period to obtain the second drive signal in a second half period of each signal period.

[0011] The second control signal comprises a third driving signal and a fourth driving signal, the step of obtaining the first pulse width of each beat of the first control signal comprises: obtaining the first pulse width of each beat of the first driving signal; the step of phase-shifting the first control signal to obtain the second control signal comprises: phase-shifting the first driving signal to obtain the third driving signal by using the first pulse width of each beat; the fourth driving signal is obtained by using the third driving signal; the third driving signal and the fourth driving signal are complementary and symmetrical in phase; the steps of sending the first control signal and the second control signal to the first resonant conversion circuit and the second resonant conversion circuit respectively to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power supply output signal, comprise: adjusting the switching state of the first resonant conversion circuit by using the first driving signal and the second driving signal, and adjusting the switching state of the second resonant conversion circuit by using the third driving signal and the fourth driving signal, thereby adjusting the power supply output signal.

[0012] The step of phase-shifting the first driving signal to obtain the third driving signal by using the first pulse width of each beat comprises: obtaining each rising edge and falling edge of the first driving signal; starting from each rising edge, adjusting the third driving signal from low to high in a time period of one half of the first pulse width of the last beat; starting from each falling edge, adjusting the third driving signal from high to low in a time period of one half of the first pulse width of the last beat.

[0013] To solve the above technical problems, another technical solution adopted by the present application is to provide an interleaved parallel control circuit, wherein the interleaved parallel control circuit is coupled with a first resonant conversion circuit and a second resonant conversion circuit, and the first resonant conversion circuit and the second resonant conversion circuit are parallel to each other; wherein the interleaved parallel control circuit adopts the interleaved parallel control method as described in any one of the above to realize interleaved parallel control of the first resonant conversion circuit and the second resonant conversion circuit.

[0014] To solve the above technical problems, another technical solution adopted by the present application is to provide an electronic device, wherein the electronic device comprises a shell and an interleaved parallel control circuit connected to the shell; wherein the interleaved parallel control circuit is the interleaved parallel control circuit as described above.

[0015] The application has the beneficial effects that: different from the prior art, the interleaved parallel control method provided by the application acquires a resonant current signal in the first resonant conversion circuit and a power supply output signal, generates a first control signal by using the resonant current signal and the power supply output signal, acquires a first pulse width of each beat of the first control signal, adjusts the first control signal by using the first pulse width of each beat to obtain a second control signal, and controls the first resonant conversion circuit and the second resonant conversion circuit in interleaved parallel by using the first control signal and the second control signal, so as to adjust the power supply output signal, thereby effectively reducing the output current ripple under the premise of improving the power density by using the first resonant conversion circuit and the second resonant conversion circuit in phase parallel; and the phase shift adjustment by using the digital control mode of the first pulse width is simpler than the control mode relying on the hardware phase shifter, and the signal response is also faster. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0017] Figure 1 is a flowchart of a first embodiment of the interleaved parallel control method of the application;

[0018] Figure 2 is a structural schematic diagram of a first embodiment of the interleaved parallel control circuit of the application;

[0019] Figure 3 is Figure 1 a flowchart of an embodiment of S12 in the application;

[0020] Figure 4 is Figure 1 a flowchart of an embodiment of S13 in the application;

[0021] Figure 5 is Figure 1 a flowchart of an embodiment of S14 in the application;

[0022] Figure 6 is Figure 1 a flowchart of another embodiment of S14 in the application;

[0023] Figure 7 is a flowchart of a second embodiment of the interleaved parallel control method of the application;

[0024] Figure 8 is a structural schematic diagram of a second embodiment of the interleaved parallel control circuit.

[0025] Figure 9 is Figure 8 Waveform diagram of each relevant signal of the first control signal generated by the interleaved parallel control circuit in the first embodiment;

[0026] Figure 10 is Figure 7 Flowchart of an embodiment of S48 in the first embodiment;

[0027] Figure 11 is Figure 8 Logic diagram of the interleaved parallel control circuit in the first embodiment;

[0028] Figure 12 is a structural diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] The terms “first”, “second”, “third” in the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second”, “third” can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of “multiple” is at least two, such as two, three, etc., unless otherwise specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0031] Reference to“an implementation” in this document means that a particular feature, structure, or characteristic described in connection with the implementation can be included in at least one implementation of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same implementation nor are separate or alternative implementations mutually exclusive of other implementations. One of ordinary skill in the art will readily recognize from the disclosure herein, that the implementations described herein can be incorporated into other implementations.

[0032] The application will be described in detail below with reference to the attached drawings and implementations.

[0033] Reference is made to Figure 1 and Figure 2 wherein, Figure 1 is a flowchart of a first implementation of the interleaved parallel control method of the application, Figure 2 is a structural schematic diagram of a first implementation of the interleaved parallel control circuit of the application. Specifically, it can include the following steps:

[0034] S11: Obtain a resonant current signal in the first resonant conversion circuit and a power supply output signal.

[0035] It can be understood that the interleaved parallel control method in this implementation is specifically applied to the interleaved parallel control of the resonant conversion circuit 20 as shown in Figure 2 The resonant conversion circuit 20 includes a first resonant conversion circuit 21 and a second resonant conversion circuit 22 connected in parallel with each other, and a first interleaved parallel control circuit 30 is coupled to the first resonant conversion circuit 21 and the second resonant conversion circuit 22; wherein the first interleaved parallel control circuit 30 uses any of the interleaved parallel control methods described herein to implement interleaved parallel control on the first resonant conversion circuit 21 and the second resonant conversion circuit 22.

[0036] It is worth noting that the first resonant conversion circuit 21 and the second resonant conversion circuit 22 can be the same and can be a half-bridge LLC converter, a full-bridge LLC converter, or other forms of LLC circuit topology, and the present implementation does not limit this.

[0037] In some embodiments, the number of the first resonant conversion circuit 21 is one, and the number of the second resonant conversion circuit 22 is one or more, such as the second resonant conversion circuit 1, the second resonant conversion circuit 2,..., the second resonant conversion circuit n (n is an integer greater than or equal to 1); or it can be understood that the number of the resonant conversion circuit 20 is at least two, and any one of the resonant conversion circuit 20 is the first resonant conversion circuit 21 as the master phase resonant converter, and the other resonant conversion circuit 20 is the second resonant conversion circuit 22 as the slave phase resonant converter, and the present application does not limit this.

[0038] In some embodiments, the first interleaved parallel control circuit 30 can specifically include one of any reasonable circuit unit with signal processing function, such as a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, a discrete gate or transistor logic device, a discrete hardware, etc., and the present application does not make any limitation in this regard.

[0039] In addition, "coupling" in the present application refers to including any direct and indirect connection means. Therefore, if the first circuit is described as being coupled to the second circuit in the present application, it means that the first circuit can be directly connected to the second circuit through electrical connection or wireless transmission, optical transmission, etc. signal connection method, or indirectly connected to the second circuit through other circuits or connection means.

[0040] Specifically, the first interleaved parallel control circuit 30 obtains the resonant current signal and the power supply output signal from the first resonant conversion circuit 21 in real time, such as obtaining the resonant current from the primary side of the first resonant conversion circuit 21 and obtaining the output voltage from the secondary side thereof through a current transformer, a voltage divider, a sampling resistor or other types of circuit units, to obtain the resonant current signal and the power supply output signal.

[0041] S12: generating a first control signal using the resonant current signal and the power supply output signal.

[0042] Further, the first interleaved parallel control circuit 30 calculates the necessary adjustment amount based on the resonant current signal and the power supply output signal obtained at present to generate the first control signal, such as using proportional integral derivative control or other advanced control strategies, to ensure that the system can be accurately adjusted according to the current working state.

[0043] S13: obtaining the first pulse width of each beat of the first control signal.

[0044] The first interleaved parallel control circuit 30 obtains the first pulse width of each beat of the first control signal generated at present in real time.

[0045] It is worth mentioning that the pulse width of each beat refers to the time length of a single pulse from start to end in a pulse sequence. The pulse width refers to the time length of the pulse signal from high level to low level, usually expressed in seconds (s). For example, a signal with a pulse width of 100 nanoseconds (ns) means that the signal lasts for 100 nanoseconds in the high level state. The first pulse width can be understood as the time length of the first control signal from high level to low level in a signal period; each beat refers to each signal period of the first control signal.

[0046] S14: The first control signal is phase-shifted to obtain a second control signal according to the first pulse width of each beat.

[0047] Further, in order to achieve the effect of interleaved parallel connection, the first interleaved parallel control circuit 30 needs to phase-shift the first control signal. Specifically, a fixed phase offset is applied to the first control signal according to the first pulse width of each beat to generate a second control signal. The purpose of this is to make the two parallel resonant conversion circuits 20 not work at the same time, but staggered on and off, which helps to disperse the peak current and reduce electromagnetic interference.

[0048] In some embodiments, the first control signal and the second control signal can be one or more of PWM (Pulse Width Modulation) signals or PFM (Pulse Frequency Modulation) signals, or any reasonable control signal, which is not limited in the present application.

[0049] S15: The first control signal and the second control signal are sent to the first resonant conversion circuit and the second resonant conversion circuit, respectively, to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power output signal.

[0050] The first interleaved parallel control circuit 30 sends the first control signal and the second control signal to the first resonant conversion circuit 21 and the second resonant conversion circuit 22, respectively, to trigger the corresponding switching elements in the first resonant conversion circuit 21 and the second resonant conversion circuit 22 to change state, and make the first resonant conversion circuit 21 and the second resonant conversion circuit 22 work in an interleaved manner, to jointly adjust the power output signal of the entire system, and ensure stable and efficient energy conversion.

[0051] The above scheme can effectively reduce the output voltage and current ripple by using the interleaved parallel operation mode of the first resonant conversion circuit 21 and the second resonant conversion circuit 22, and provide more stable power supply. By optimizing the energy transmission path in each cycle, the entire system can operate at a higher efficiency level. The current stress on individual components is dispersed, prolonging the service life of key components. Under the premise of improving power density by using the first resonant conversion circuit 21 and the second resonant conversion circuit 22 in parallel, the output current ripple can also be effectively reduced by corresponding phase shift adjustment; and the phase shift adjustment of the digital control mode realized by the first pulse width is simpler and the signal response is faster than the control mode relying on the hardware phase shifter.

[0052] Please continue to refer to Figure 3 , Figure 3 is Figure 1 a flowchart of an embodiment of S12 in S11. In an embodiment, the interleaved parallel control method of the present application further includes some more specific steps in addition to S11-S15. Specifically, S12 can further include the following steps:

[0053] S121: obtaining an adjustment output signal by using the difference between the power supply output signal and the target reference voltage.

[0054] Specifically, the first interleaved parallel control circuit 30 compares the power supply output signal with the preset target reference voltage to obtain the difference (i.e. error signal) between them, and generates an adjustment output signal based on the error signal using a proportional-integral-derivative controller or other control algorithm. The adjustment output signal reflects the energy magnitude or direction that needs to be adjusted in order to make the power supply output signal close to the target reference voltage.

[0055] S122: obtaining a feedback adjustment signal by performing slope compensation on the adjustment output signal.

[0056] In order to prevent sub-harmonic oscillation and improve the stability of the system, the first interleaved parallel control circuit 30 performs slope compensation on the adjustment output signal to obtain a feedback adjustment signal.

[0057] It is worth noting that slope compensation is a common technique used in pulse width modulation controllers to increase the linear rise or fall slope, thereby avoiding unstable switching behavior under certain conditions. The adjustment output signal after slope compensation becomes the feedback adjustment signal, which contains accurate feedback information about the system state and has been optimized for subsequent control decisions.

[0058] S123: generating a first control signal by using the feedback adjustment signal and the resonant current signal.

[0059] It is understood that the feedback regulation signal and the resonant current signal are combined to generate the final first control signal. This process can involve complex logical judgments or mathematical operations, aiming to ensure that the generated control signal can not only reflect the current error condition, but also consider the instantaneous current condition. The feedback regulation signal provides information about the output voltage deviation, while the resonant current signal reflects the transient behavior inside the circuit. Combining the two can provide a more comprehensive understanding of the system's running state, and accordingly make the best control decision, such as determining the level adjustment time of the first control signal according to the voltage amplitude comparison between the feedback regulation signal and the resonant current signal, to adjust the duty cycle of the first control signal.

[0060] Based on the above integrated information, the control system generates a corresponding first control signal, which is sent to the relevant components (such as switching elements) in the resonant conversion circuit 20 to trigger their state change, thereby adjusting the power supply output signal until the target reference voltage is reached. This closed-loop control strategy not only improves the stability and response speed of the resonant conversion circuit 20, but also enhances its ability to adapt to different load conditions. By accurately monitoring and adjusting the output voltage, the system can maintain high efficiency and stable performance in various working environments.

[0061] Please refer to Figure 4 , Figure 4 is Figure 1 a flowchart of an embodiment of S13 in In an embodiment, in addition to S11-S15, the interleaved parallel control method of the present application further includes some more specific steps. Specifically, S13 can further include the following steps:

[0062] S131: Obtain each rising edge and falling edge of the first control signal.

[0063] Specifically, the first interleaved parallel control circuit 30 identifies each rising edge (transition from low to high) and falling edge (transition from high to low) in the first control signal, which can be achieved by any reasonable means such as hardware circuit (e.g. edge trigger), software algorithm (e.g. writing corresponding code in embedded system), or controller counter, etc., which is not limited in the present application.

[0064] S132: Obtain the first pulse width of each beat using each rising edge and falling edge.

[0065] For each detected rising edge and falling edge, record the exact time point of its occurrence. This can be achieved by using a timer or a counter to provide a high-precision timestamp.

[0066] The width of one pulse can be determined by calculating the time difference between the rising edge and the corresponding falling edge, which is the width of the pulse.

[0067] Therefore, the width of the first pulse of each beat can be obtained by calculating the time difference between each rising edge and the next falling edge in the first control signal.

[0068] Referring to Figure 5 , Figure 5 is Figure 1 a flowchart of an embodiment of S14. In an embodiment, the staggered parallel control method of the present application further includes some more specific steps in addition to S11-S15. Specifically, S14 can further include the following steps:

[0069] S1411: obtaining each rising edge of the first control signal.

[0070] Specifically, the first staggered parallel control circuit 30 identifies each rising edge (transition from low to high) in the first control signal, which can be achieved by any reasonable means such as hardware circuit (e.g. edge trigger), software algorithm (e.g. writing corresponding code in embedded system), or controller counter, etc. to capture the starting time of each pulse, which is not limited in the present application.

[0071] S1412: taking each rising edge as the starting time, delaying for a duration of one half of the first pulse width of the previous beat, and using the first pulse width of the previous beat to obtain the second pulse width of each beat of the second control signal to generate the second control signal.

[0072] It can be understood that for each rising edge, the system calculates the delay time according to the first pulse width of the previous beat. When the number of second resonant conversion circuits 22 is one, i.e. there is one second resonant conversion circuit 22 in parallel with the first resonant conversion circuit 21 for power supply, the delay time can be specifically one half of the pulse width of the previous beat.

[0073] For ease of understanding, it is assumed that the first pulse width of the previous beat is PWf, and the delay time is PWf / 2.

[0074] After detecting a new rising edge, the system will wait for the delay time PWf / 2 calculated above before proceeding to the next step. This is done to ensure that the generated second control signal has a phase shift relative to the first control signal, so as to achieve the effect of staggered parallel.

[0075] The first pulse width PWf of the previous cycle is used to determine the corresponding second pulse width Pws in the second control signal. In the simplest case, the second pulse width Pws can be directly equal to the first pulse width PWf, but it can also be adjusted as appropriate according to specific requirements.

[0076] After a delay time of PWf / 2, it means that each pulse of the second control signal starts at the middle position of the corresponding pulse of the first control signal, and has the same or adjusted pulse width.

[0077] Therefore, by delaying half a pulse width of time after each rising edge to start the second control signal, the phase staggering between the two parallel working resonant conversion circuits 20 can be ensured. This staggered working mode helps to disperse the peak current and reduce electromagnetic interference. This method uses the pulse width information of the previous cycle to generate the control signal of the next cycle, simplifies the synchronization control logic, and makes it easier to achieve accurate phase control. The staggered parallel control can effectively reduce the ripple of the output voltage and current, improve the stability and efficiency of the system, and is particularly suitable for applications with high requirements for power quality and efficiency, such as uninterruptible power supplies, renewable energy inverters, etc.

[0078] Please refer to Figure 6 , Figure 6 is Figure 1 the flowchart of another embodiment of S14. In an embodiment, in addition to the above-mentioned S11-S15, the staggered parallel control method of the present application further includes some more specific steps. Specifically, the above-mentioned S14 can further include the following steps:

[0079] S1421: using the first pulse width divided by the sum of the number of the first resonant conversion circuit and the second resonant conversion circuit to obtain the pulse adjustment width.

[0080] It can be understood that when the number of the second resonant conversion circuit 22 is at least two, that is, when the system with multiple parallel resonant conversion circuits 20 is used for power supply, it is necessary to ensure that each resonant conversion circuit 20 operates with an appropriate phase difference, so as to optimize the performance of the entire system.

[0081] For easy understanding, it is assumed that the first pulse width is PWf, the number of the first resonant conversion circuit 21 is 1, and the number of the second resonant conversion circuit 22 is n, such as the second resonant conversion circuit 1, the second resonant conversion circuit 2,..., the second resonant conversion circuit n. In this embodiment, n is greater than or equal to 2. The pulse adjustment width PWr can be calculated by the following formula: PWr=PWf / (n+1), which will be used to determine the delay amount between each control signal.

[0082] S1422: acquiring each rising edge of the first control signal.

[0083] Specifically, the first staggered parallel control circuit 30 identifies each rising edge (transition from low to high) in the first control signal, which can be achieved by any reasonable means such as hardware circuit (e.g. edge trigger), software algorithm (e.g. writing corresponding code in embedded system), controller counter, etc. to capture the starting time of each pulse, which is not limited in the present application.

[0084] S1423: using the first pulse width of the last beat as the corresponding duration of the pulse adjustment width, the first staggered parallel control circuit 30 generates the second pulse width of each beat of the first second control signal to generate the first second control signal.

[0085] After detecting a new rising edge, the system starts timing and waits for a pulse adjustment width PWr, i.e. after a delay of PWr, the first staggered parallel control circuit 30 uses the first pulse width PWf of the last beat to generate the second pulse width PWS1 of the first second control signal. The second pulse width PWS1 can be equal to the first pulse width PWf, or adjusted according to specific requirements.

[0086] The first staggered parallel control circuit 30 is further configured to trigger the second resonant conversion circuit 1 to change its switching state using the generated first second control signal.

[0087] S1424: using the first pulse width of the last beat as the corresponding duration of the pulse adjustment width, the first staggered parallel control circuit 30 generates the second pulse width of each beat of the second second control signal to generate the second second control signal, until the cumulative delay times equal the number of the second resonant conversion circuits, thereby obtaining at least two second control signals.

[0088] Further, the first staggered parallel control circuit 30 generates the second second control signal by delaying PWr again, i.e. after a delay of 2*PWr, the first staggered parallel control circuit 30 uses the first pulse width PWf of the last beat to generate the second pulse width PWS2 of the first second control signal. The second pulse width PWS2 can be equal to the first pulse width PWf, or adjusted according to specific requirements.

[0089] The first staggered parallel control circuit 30 is further configured to trigger the second resonant conversion circuit 2 to change its switching state using the generated second second control signal.

[0090] The above process is repeated to generate a new second control signal each time after delaying PWr. Specifically, the first second control signal is generated after delaying PWr for the first time, the second second control signal is generated after delaying PWr for the second time, and the process continues until the cumulative number of delays is equal to the number n of second resonant conversion circuits 22. The second control signal generated each time uses the same first pulse width PWf or a pulse width adjusted based on the first pulse width PWf.

[0091] The first to nth second control signals are used by the first interleaved parallel control circuit 30 to trigger the second resonant conversion circuit 1, the second resonant conversion circuit 2,..., and the nth resonant conversion circuit n to change their switching states, respectively.

[0092] By reasonably allocating the phase difference, the operation of the plurality of resonant conversion circuits 20 can be more balanced, avoiding the situation that some circuits are overloaded while other circuits are idle. The interleaved parallel operation mode helps to disperse the peak current, reduce the ripple of the output voltage and current, and also reduces electromagnetic interference. By optimizing the energy transmission path and reducing unnecessary loss, the overall efficiency of the system can be significantly improved.

[0093] Please refer to Figure 7 and Figure 8 wherein, Figure 7 is a flowchart of the second embodiment of the interleaved parallel control method of the present application, Figure 8 is a structural schematic diagram of the second embodiment of the interleaved parallel control circuit. The interleaved parallel control method of the present embodiment is a detailed embodiment of the interleaved parallel control method in Figure 1 , and specifically includes the following steps:

[0094] S41: Obtain the resonant current signal in the first resonant conversion circuit and the power supply output signal.

[0095] Wherein, S41 is the same as S11 in Figure 1 , and please refer to S11 and the related textual description for details, which will not be repeated here.

[0096] S42: Obtain the adjustment output signal using the difference between the power supply output signal and the target reference voltage.

[0097] It can be understood that the interleaved parallel control method in the present embodiment can be as follows Figure 8The second interleaved parallel control circuit 50 shown implements interleaved parallel control on the resonant conversion circuit 20. The resonant conversion circuit 20 includes a first resonant conversion circuit 21 and a second resonant conversion circuit 22. The first resonant conversion circuit 21 includes a first power switch circuit 211, a first switch freewheeling circuit 212, a first resonant circuit 213, a first isolation transformer 214, a first rectifier circuit 215, and a voltage stabilizing output circuit 216. The second resonant conversion circuit 22 includes a second power switch circuit 221, a second switch freewheeling circuit 222, a second resonant circuit 223, a second isolation transformer 224, and a second rectifier circuit 225. The first power switch circuit 211 includes a first switch tube Q11 and a second switch tube Q12. The first switch freewheeling circuit 212 includes a first freewheeling resistor Rc11, a second freewheeling resistor Rc12, a first freewheeling capacitor C11, a second freewheeling capacitor C12, a first diode D11, and a second diode D12. The first resonant circuit 213 includes a first resonant capacitor Cr11, a second resonant capacitor Cr12, and a first resonant inductor Lr1. The first isolation transformer 214 includes a first primary winding Lm1, a first secondary winding Ln11, and a second secondary winding Ln12. The first rectifier circuit 215 includes a third diode D13 and a fourth diode D14. The voltage stabilizing output circuit 216 further includes a voltage stabilizing resistor Ro and a voltage stabilizing capacitor Co. The second power switch circuit 221 includes a third switch tube Q21 and a fourth switch tube Q22. The second switch freewheeling circuit 222 includes a third freewheeling resistor Rc21, a fourth freewheeling resistor Rc22, a third freewheeling capacitor C21, a fourth freewheeling capacitor C22, a fifth diode D21, and a sixth diode D22. The second resonant circuit 223 includes a third resonant capacitor Cr21, a fourth resonant capacitor Cr22, and a second resonant inductor Lr2. The second isolation transformer 224 includes a second primary winding Lm2, a third secondary winding Ln21, and a fourth secondary winding Ln22. The second rectifier circuit 225 includes a seventh diode D23 and an eighth diode D24.

[0098] The first end of the first switch tube Q11 is coupled to the first end of the first freewheeling resistor Rc11, the second end of the first diode D11, the first end of the first resonance capacitor Cr11, the first end of the third switch tube Q21, the first end of the third freewheeling resistor Rc21, the second end of the fifth diode D21, and the first end of the third resonance capacitor Cr21, and is used for coupling to the first end of the power supply circuit 501. The second end of the second switch tube Q12 is coupled to the second end of the second freewheeling capacitor C12, the first end of the second diode D12, the second end of the second resonance capacitor Cr12, the second end of the fourth switch tube Q22 is coupled to the second end of the fourth freewheeling capacitor C22, the first end of the sixth diode D22, and the second end of the fourth resonance capacitor Cr22, and is used for coupling to the second end of the power supply circuit 501. The second end of the first freewheeling resistor Rc11 is coupled to the first end of the first freewheeling capacitor C11. The second end of the first freewheeling capacitor C11 is coupled to the first end of the first diode D11, the second end of the first switch tube Q11, the first end of the second switch tube Q12, the first end of the second freewheeling resistor Rc12, the second end of the second diode D12, and the first end of the first resonance inductor Lr1. The second end of the second freewheeling resistor Rc12 is coupled to the first end of the second freewheeling capacitor C12. The second end of the first resonance capacitor Cr11 is coupled to the first end of the second resonance capacitor Cr12 and the second end of the first primary winding Lm1. The second end of the first resonance inductor Lr1 is coupled to the first end of the first primary winding Lm1. The second end of the third freewheeling resistor Rc21 is coupled to the first end of the third freewheeling capacitor C21. The second end of the third freewheeling capacitor C21 is coupled to the first end of the fifth diode D21, the second end of the third switch tube Q21, the first end of the fourth switch tube Q22, the first end of the fourth freewheeling resistor Rc22, the second end of the sixth diode D22, and the first end of the second resonance inductor Lr2. The second end of the fourth freewheeling resistor Rc22 is coupled to the first end of the fourth freewheeling capacitor C22. The second end of the third resonance capacitor Cr21 is coupled to the first end of the fourth resonance capacitor Cr22 and the second end of the second primary winding Lm2. The second end of the second resonance inductor Lr2 is coupled to the first end of the second primary winding Lm2.

[0099] The first primary winding Lm1 is coupled with the first secondary winding Ln11 and the second secondary winding Ln12. The first end of the third diode D13 is coupled with the first end of the first secondary winding Ln11. The second end of the third diode D13 is coupled with the second end of the fourth diode D14, the first end of the voltage stabilizing resistor Ro, the second end of the seventh diode D23, the second end of the eighth diode D24, and is used to be coupled with the first end of the load circuit R, i.e., the first end of the load circuit 102. The first end of the fourth diode D14 is coupled with the second end of the second secondary winding Ln12. The second end of the voltage stabilizing resistor Ro is coupled with the first end of the voltage stabilizing capacitor Co. The second end of the voltage stabilizing capacitor Co is coupled with the second end of the first secondary winding Ln11, the first end of the second secondary winding Ln12, the second end of the third secondary winding Ln21, and the first end of the fourth secondary winding Ln22, and is used to be coupled with the second end of the load circuit 102.

[0100] In some embodiments, the first switch Q11, the second switch Q12, the third switch Q21, and the fourth switch Q22 can be one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a transistor, a thin film transistor, or a field effect transistor, or any other reasonable switch, which is not limited in the present application.

[0101] It is worth noting that, in order to distinguish the two ends of each switch except the control end, one pole is referred to as the first end, and the other pole is referred to as the second end. When each switch is a transistor, the control end, i.e., the third end, can be a base, the first end can be a collector, and the second end can be an emitter; or the third end can also be a base, the first end can be an emitter, and the second end can be a collector.

[0102] When each switch is a MOSFET, a thin film transistor, or a field effect transistor, the third end can be a gate, the first end can be a drain, and the second end can be a source; or the third end can also be a gate, the first end can be a source, and the second end can be a drain.

[0103] When each switch is a MOSFET, a thin film transistor, or a field effect transistor, it can also be a compound transistor or a single transistor, which is not limited in the present application.

[0104] It is worth mentioning that in other embodiments, the first resonant conversion circuit 21 and the second resonant conversion circuit 22 can also be a half-bridge LLC converter, a full-bridge LLC converter or any other reasonable form of LLC circuit topology, for example, the first power switch circuit 211 and the second power switch circuit 221 can also be a full-bridge switch circuit or an asymmetric half-bridge switch circuit, and the first rectifier circuit 215 and the second rectifier circuit 225 can be a full-bridge rectifier circuit or a half-bridge rectifier circuit composed of switch tubes, or any other reasonable circuit form for realizing AC to DC conversion, etc.

[0105] The first control signal includes a first drive signal PWMA and a second drive signal PWMB, and the second control signal includes a third drive signal PWMH and a fourth drive signal PWML.

[0106] Specifically, the first interleaved parallel control circuit 30 compares the power supply output signal Vo with a preset target reference voltage to obtain a difference (i.e. an error signal) between the two, and generates an adjustment output signal based on the error signal using a proportional-integral-derivative controller or other control algorithm. The adjustment output signal reflects the energy magnitude or direction that needs to be adjusted in order to make the power supply output signal Vo close to the target reference voltage.

[0107] S43: In the first half of each signal period of the first drive signal, in response to the second drive signal adjusting from high to low, the adjustment output signal is ramp compensated to obtain a feedback adjustment signal by delaying for a set time length or using a set ramp compensation slope.

[0108] Please refer to Figure 9 , Figure 9 is Figure 8 the waveform diagram of the related signals of the first control signal generated by the interleaved parallel control circuit in the first half of each signal period of the first drive signal.

[0109] It can be understood that in the first half of each signal period of the first drive signal PWMA, the first interleaved parallel control circuit 30 monitors the level state change of the second drive signal PWMB, and when the second drive signal PWMB adjusts from high to low, the adjustment output signal is ramp compensated to obtain a feedback adjustment signal using a set ramp compensation slope, that is, a ramp signal with a set slope is added to the adjustment output signal to prevent subharmonic oscillation and improve the stability of the system. The specific implementation of ramp compensation can be completed by hardware circuit or software algorithm; or, the first interleaved parallel control circuit 30 can also choose to delay for a set time length (for example, to wait for circuit stabilization or to reach a certain predetermined time point) when the second drive signal PWMB adjusts from high to low, and then use a set ramp compensation slope to ramp compensate the adjustment output signal to obtain a feedback adjustment signal.

[0110] In some embodiments, the set time length can be the on-off dead time of each switch tube in the inverter circuit, or a specific time length determined according to specific application scenarios, which is not limited in the present application.

[0111] S44: delaying for a set time length or adjusting the first driving signal from low level to high level at the same time.

[0112] After the above slope compensation, the first interleaved parallel control circuit 30 can select to delay for a set time length again, or directly adjust the first driving signal PWMA from low level to high level at the same time.

[0113] S45: adjusting the first driving signal from high level to low level when the resonant current signal is greater than or equal to the feedback adjustment signal.

[0114] The first interleaved parallel control circuit 30 continuously monitors the resonant current signal and compares it with the feedback adjustment signal. When the resonant current signal is greater than or equal to the feedback adjustment signal, it indicates that the current working condition has reached the preset standard, and at this time, the state of the first driving signal PWMA needs to be adjusted, i.e. from high level to low level.

[0115] S46: copying the first driving signal of each first half period to obtain the second driving signal in each second half period.

[0116] In the second half period of each second signal period, the level state change of the first driving signal PWMA in the first half period is copied to generate the second driving signal PWMB.

[0117] S47: obtaining the first pulse width of each beat of the first driving signal.

[0118] Further, the first interleaved parallel control circuit 30 obtains the first driving signal PWMA in real time, and identifies each rising edge (transition from low level to high level) and falling edge (transition from high level to low level). This can be achieved by hardware logic comparator or software algorithm. For each detected rising edge and corresponding falling edge, the time difference is calculated to determine the first pulse width of each beat.

[0119] S48: phase-shifting the first driving signal using the first pulse width of each beat to obtain the third driving signal.

[0120] The first driving signal PWMA is phase-shifted based on the first pulse width of each beat to generate the third driving signal PWMH. The specific way of phase-shifting can be determined according to system requirements, but generally is to achieve the effect of interleaved parallel connection, reduce ripple and harmonic interference. For example, the first driving signal PWMA can be delayed by a fixed phase angle to generate the third driving signal PWMH, and the third pulse width of each beat of the third driving signal PWMH is equal to the first pulse width of the previous beat.

[0121] S49: obtaining the fourth driving signal by using the third driving signal.

[0122] In order to realize phase complementary symmetry, the third driving signal PWMH can be phase-shifted by 180 degrees to generate the fourth driving signal PWML; or, when the third driving signal PWMH is adjusted from high level to low level, the fourth driving signal PWML is adjusted from low level to high level after a set time delay or at the same time, and when the third driving signal PWMH is adjusted from low level to high level, the fourth driving signal PWML is adjusted from high level to low level after a set time delay or at the same time, so that when the third driving signal PWMH is at high level, the fourth driving signal PWML is at low level, and vice versa.

[0123] S410: adjusting the switching state of the first resonant conversion circuit by using the first driving signal and the second driving signal, and adjusting the switching state of the second resonant conversion circuit by using the third driving signal and the fourth driving signal, thereby adjusting the power supply output signal.

[0124] The first interleaved parallel control circuit 30 uses the first driving signal PWMA and the second driving signal PWMB to trigger the switching elements in the first resonant conversion circuit 21 to change state, and uses the third driving signal PWMH and the fourth driving signal PWML to trigger the switching elements in the second resonant conversion circuit 22 to change state, to adjust the power supply output signal Vo, so as to more flexibly and efficiently respond to load changes, and ensure that the power supply output signal Vo is stable and efficient.

[0125] The second interleaved parallel control circuit 50 is also coupled to the third end of the first switch Q11, the third end of the second switch Q12, the third end of the third switch Q21, and the third end of the fourth switch Q22, for sending the first drive signal PWMA and the second drive signal PWMB to the third end of the first switch Q11 and the third end of the second switch Q12, respectively, to adjust the switching state of the first power switch circuit 211, and sending the third drive signal PWMH and the fourth drive signal PWML to the third end of the third switch Q21 and the third end of the fourth switch Q22, respectively, to adjust the switching state of the second power switch circuit 221, so as to adjust the power supply output signal Vo of the voltage stabilization output circuit 216, to more flexibly and efficiently respond to load changes, and ensure that the power supply output signal Vo is stable and efficient.

[0126] By interleaved parallel operation mode and phase complementary symmetric design, the output voltage and current ripple and harmonic can be significantly reduced, and the power quality can be improved. Precise phase-shift regulation and pulse width control make energy transmission more efficient, reducing unnecessary loss. This method improves the dynamic response speed and stability of the system, enabling it to maintain optimal performance under various operating conditions.

[0127] Further, in an embodiment, the second interleaved parallel control circuit 50 can further include a sampling and integration circuit 51, a first proportional filter correction processing circuit 52, a second proportional filter correction processing circuit 53, and a control sub-circuit 54. The sampling and integration circuit 51 includes a current transformer CT and an integration sampling capacitor CJ. The first end of the current transformer CT is coupled to the second end of the first resonant capacitor Cr11, the first end of the second resonant capacitor Cr12, and the first end of the integration sampling capacitor CJ. The second end of the current transformer CT is coupled to the second end of the first primary winding Lm1 and the second end of the integration sampling capacitor CJ. The first proportional filter correction processing circuit 52 is coupled to the first end of the voltage stabilization resistor Ro, the second end of the voltage stabilization capacitor Co, and the control sub-circuit 54. The second proportional filter correction processing circuit 53 is coupled to the integration sampling capacitor CJ and the control sub-circuit 54. The control sub-circuit 54 is coupled to the third end of the first switch Q11, the third end of the second switch Q12, the third end of the third switch Q21, and the third end of the fourth switch Q22. The above S41 can further include: using the current transformer CT to sample and obtain the resonant current signal in the first resonant conversion circuit 21, and using the integration sampling capacitor CJ to integrate the resonant current signal to obtain the resonant capacitor voltage Vcs.

[0128] The first proportional filter correction processing circuit 52 is configured to obtain the power supply output signal Vo output by the voltage stabilizing output circuit 216 to the load circuit 102, and sequentially perform comparison with a reference value, filtering, and correction processing on the power supply output signal Vo to obtain a first filtered signal; the second proportional filter correction processing circuit 53 is configured to obtain the resonant capacitor voltage Vcs in the sampling and integration circuit 51, and sequentially perform comparison with a reference value, filtering, and correction processing on the resonant capacitor voltage Vcs to obtain a second filtered signal, so as to provide a more suitable high-quality input for the control sub-circuit 54, thereby effectively optimizing the overall performance and reliability of the control sub-circuit 54, and realizing efficient control.

[0129] The control sub-circuit 54 is further configured to receive the first filtered signal and the second filtered signal, so as to obtain the first drive signal PWMA, the second drive signal PWMB, the third drive signal PWMH, and the fourth drive signal PWML by using the first filtered signal and the second filtered signal to correspond to S42-S410, respectively, so as to realize switching control on the first switch Q11, the second switch Q12, the third switch Q21, and the fourth switch Q22 by using the first drive signal PWMA, the second drive signal PWMB, the third drive signal PWMH, and the fourth drive signal PWML, respectively, so as to adjust the power supply output signal Vo.

[0130] Please refer to Figure 10 , Figure 10 is Figure 8 the wave generation logic diagram of the interleaved parallel control circuit.

[0131] The control sub-circuit 54 internally integrates a logic comparator, the high terminal of the logic comparator receives the resonant capacitor voltage Vcs or the second filtered signal, and the low terminal of the logic comparator is the output signal of the voltage loop controller, and a feedback adjustment signal is obtained after slope compensation. Wherein, the slope compensation is triggered when the next cycle count is 0 after one wave generation cycle ends, and the voltage loop controller in the control sub-circuit 54 adjusts the error according to the logic of the input voltage amplitude of the low terminal of the comparator, and when the high terminal of the logic comparator is greater than the low terminal potential, the output is turned off the first drive signal PWMA; when the counter of the voltage loop controller counts to 0, the first drive signal PWMA is turned on; the second drive signal PWMB is turned on after the first drive signal PWMA is turned off, the pulse width is copied from the width of the first drive signal PWMA, and the second drive signal PWMB is turned off when the pulse width is equal to the pulse width of the first drive signal PWMA, at this time the counter of the voltage loop controller is cleared and starts counting from 0 again.

[0132] Please refer to Figure 10 , Figure 10 is Figure 7Flowchart of an embodiment of S48. In an embodiment, the interleaved parallel control method of the present application further comprises some more specific steps in addition to S41-S410. Specifically, S13 can further comprise the following steps:

[0133] S481: Obtain each rising edge and falling edge of the first driving signal.

[0134] Specifically, the first interleaved parallel control circuit 30 accurately identifies each rising edge (transition from low to high) and falling edge (transition from high to low) of the first driving signal PWMA.

[0135] S482: At the starting time of each rising edge, adjust the third driving signal PWMH from low to high for a duration of one-half of the first pulse width of the previous beat.

[0136] For each rising edge, the first interleaved parallel control circuit 30 can further calculate the delay time PWf / 2 according to the first pulse width PWfof the previous beat.

[0137] After the delay time PWf / 2, adjust the third driving signal PWMH from low to high. This is done to have a fixed phase shift of the third driving signal PWMH relative to the first driving signal PWMA for achieving the effect of interleaved parallel.

[0138] S483: At the starting time of each falling edge, adjust the third driving signal from high to low for a duration of one-half of the first pulse width of the previous beat.

[0139] Similarly, for each falling edge, the first interleaved parallel control circuit 30 calculates the delay time PWf / 2 according to the first pulse width PWfof the previous beat.

[0140] After the delay time PWf / 2, adjust the third driving signal PWMH from high to low. This ensures that the third driving signal PWMH maintains a consistent phase relationship with the first driving signal PWMA.

[0141] By delaying the third drive signal PWMH half a pulse width after each rising and falling edge, the phase relationship between the two drive signals can be ensured to be very precise. This interleaved mode of operation helps to spread the peak current and reduce electromagnetic interference. This method uses the pulse width information of the previous beat to generate the control signal of the next beat, simplifying the synchronization control logic and making it easier for the system to achieve precise phase control. Interleaved parallel control can effectively reduce the ripple of output voltage and current, improve the stability and efficiency of the system, and is particularly suitable for applications with high requirements for power quality and efficiency, such as uninterruptible power supplies, renewable energy inverters, etc.

[0142] For ease of understanding, assume the first pulse width PWf of the previous beat is 10 microseconds:

[0143] 1. Rising edge processing:

[0144] Detect the rising edge of the first drive signal PWMA;

[0145] Wait for PWf / 2 = 5 microseconds;

[0146] After the delay is over, adjust the third drive signal PWMH from low to high.

[0147] 2. Falling edge processing:

[0148] Detect the falling edge of the first drive signal PWMA;

[0149] Wait for PWf / 2 = 5 microseconds;

[0150] After the delay is over, adjust the third drive signal PWMH from high to low.

[0151] Please refer to Figure 11 , Figure 11 is Figure 8 the interleaved parallel control circuit wave generation logic diagram.

[0152] It can be understood that the control sub-circuit 54 is internally integrated with a logic comparator, the high terminal of the logic comparator receives the resonant capacitor voltage Vcs or the second filtered signal, and the low terminal of the logic comparator is the output signal of the voltage loop controller, and a feedback adjustment signal is obtained after slope compensation. Wherein, the voltage loop controller in the control sub-circuit 54 adjusts the logic comparator low terminal input voltage amplitude according to the error, and when the high terminal of the logic comparator is greater than the low terminal potential, the first drive signal PWMA is output to be turned off; when the counter of the voltage loop controller counts to 0, the first drive signal PWMA is turned on; the second drive signal PWMB is turned on after the first drive signal PWMA is turned off, the pulse width of the second drive signal PWMB is copied from the first drive signal PWMA, and the second drive signal PWMB is turned off when the pulse width of the second drive signal PWMB is equal to the pulse width of the first drive signal PWMA, at this time the counter of the voltage loop controller is cleared and starts counting from 0 again.

[0153] Further, when the counter of the voltage loop controller is equal to 0, the first drive signal PWMA is set to high, the high terminal potential of the logic comparator is higher than the low terminal, the first drive signal PWMA is set to low, the rising edge and the falling edge of the first drive signal PWMA are obtained respectively, the first counter counter1 and the second counter counter2 record the pulse width of the first drive signal PWMA, and according to the wave emitting logic of Figure 9 the next first drive signal PWMA, at the rising edge of the next first drive signal PWMA, the first counter counter1 counts to half of the pulse width of the previous first drive signal PWMA, generates a pulse to make the third drive signal PWMH conduct; at the falling edge of the next first drive signal PWMA, the second counter counter2 counts to half of the pulse width of the previous first drive signal PWMA, generates a pulse to make the third drive signal PWMH turn off, so that the main phase and the slave phase are out of phase by 90 degrees, and the fourth drive signal PWML is complementary to the third drive signal PWMH in phase. In this way, the main phase and the slave phase emit waves in a cycle, and the stable voltage output is realized.

[0154] The application also provides an electronic device. Please refer to Figure 12 , Figure 12 which is a structural schematic diagram of an embodiment of the electronic device. In the embodiment, the electronic device 60 comprises a shell 61 and a third interleaved parallel control circuit 62 connected to the shell 61.

[0155] It should be noted that the third interleaved parallel control circuit 62 described in the embodiment is the first interleaved parallel control circuit 30 or the second interleaved parallel control circuit 50 described in any of the above embodiments, and details can be referred to Figures 1-11 and related text content, which will not be repeated here.

[0156] The beneficial effects of the present application are: different from the prior art, the interleaved parallel control method provided by the present application acquires the resonant current signal in the first resonant conversion circuit and the power supply output signal, generates the first control signal by using the resonant current signal and the power supply output signal, acquires the first pulse width of each beat of the first control signal, adjusts the first control signal by using the first pulse width of each beat to obtain the second control signal, thereby controlling the first resonant conversion circuit and the second resonant conversion circuit in interleaved parallel by using the first control signal and the second control signal, adjusting the power supply output signal, and effectively reducing the output current ripple by corresponding phase shift adjustment under the premise of improving the power density by using the first resonant conversion circuit and the second resonant conversion circuit in phase parallel; and the phase shift adjustment of the digital control mode realized by using the first pulse width is simpler than the control mode relying on the hardware phase shifter, and the signal response is also faster.

[0157] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation by using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An interleaved parallel control method applied to the interleaved parallel control of a resonant converter circuit, wherein the resonant converter circuit comprises a first resonant converter circuit and a second resonant converter circuit connected in parallel, characterized in that, The interleaved parallel control method includes: Obtain the resonant current signal and power supply output signal in the first resonant conversion circuit; A first control signal is generated using the resonant current signal and the power supply output signal; Obtain the first pulse width of each beat of the first control signal; wherein, each beat is each signal period of the first control signal; The first control signal is phase-shifted using the first pulse width of each beat to obtain a second control signal; wherein, the step of phase-shifting the first control signal using the first pulse width of each beat to obtain a second control signal includes: acquiring each rising edge of the first control signal; taking each rising edge as the starting time, delaying by half the duration of the first pulse width of the previous beat, and using or adjusting the first pulse width of the previous beat to obtain the second pulse width of the second control signal for each beat, so as to generate the second control signal; The first control signal and the second control signal are sent to the first resonant conversion circuit and the second resonant conversion circuit respectively to trigger the first resonant conversion circuit and the second resonant conversion circuit to change the switching state, thereby adjusting the power supply output signal.

2. The interleaved parallel control method according to claim 1, characterized in that, The step of obtaining the first pulse width of each frame of the first control signal includes: Acquire each rising and falling edge of the first control signal; The first pulse width for each beat is obtained using each rising edge and each falling edge.

3. The interleaved parallel control method according to claim 1, characterized in that, The number of the second resonant converter circuits is at least two, and the step of using the first pulse width of each beat to perform phase shift adjustment on the first control signal to obtain the second control signal includes: The pulse adjustment width is obtained by dividing the first pulse width by the sum of the number of the first resonant conversion circuit and the second resonant conversion circuit; Acquire each rising edge of the first control signal; Taking each rising edge as the starting time, the second pulse width of each pulse is obtained by delaying the corresponding duration of the pulse adjustment width and using the first pulse width of the previous pulse to generate the first second control signal; The second pulse width of each pulse is used to generate a second second control signal by delaying the pulse adjustment width again, using the first pulse width of the previous pulse to obtain the second pulse width of each pulse, until the cumulative number of delays equals the number of the second resonant conversion circuits, thereby obtaining at least two second control signals.

4. The interleaved parallel control method according to claim 1, characterized in that, The step of generating the first control signal using the resonant current signal and the power supply output signal includes: The difference between the power supply output signal and the target reference voltage is used to obtain the adjusted output signal; The feedback adjustment signal is obtained by performing slope compensation on the adjusted output signal; The first control signal is generated using the feedback adjustment signal and the resonant current signal.

5. The interleaved parallel control method according to claim 4, characterized in that, The first control signal includes a first drive signal and a second drive signal, and the step of performing slope compensation on the adjusted output signal to obtain a feedback adjustment signal includes: In the first half of each signal cycle of the first driving signal, in response to the second driving signal being adjusted from high level to low level, the adjustment output signal is slope compensated by delaying for a set time or by simultaneously using a set slope compensation slope to obtain the feedback adjustment signal. The step of generating the first control signal using the feedback adjustment signal and the resonant current signal includes: Delay the set duration or simultaneously adjust the first drive signal from the low level to the high level; When the resonant current signal is greater than or equal to the feedback adjustment signal, the first drive signal is adjusted from the high level to the low level; In the second half of each signal cycle, the first drive signal of each first half cycle is copied to obtain the second drive signal.

6. The interleaved parallel control method according to claim 5, characterized in that, The second control signal includes a third drive signal and a fourth drive signal, and the step of obtaining the first pulse width of each beat of the first control signal includes: Obtain the first pulse width of each frame of the first driving signal; The step of using the first pulse width of each beat to perform phase shift adjustment on the first control signal to obtain the second control signal includes: The first driving signal is phase-shifted using the first pulse width of each beat to obtain the third driving signal; The third driving signal is used to obtain the fourth driving signal; wherein the third driving signal and the fourth driving signal are complementary and symmetrical in phase. The step of sending the first control signal and the second control signal to the first resonant converter circuit and the second resonant converter circuit respectively to trigger the first resonant converter circuit and the second resonant converter circuit to change their switching states, thereby adjusting the power supply output signal, includes: The switching state of the first resonant converter circuit is adjusted using the first driving signal and the second driving signal, and the switching state of the second resonant converter circuit is adjusted using the third driving signal and the fourth driving signal, thereby adjusting the power supply output signal.

7. The interleaved parallel control method according to claim 6, characterized in that, The step of using the first pulse width of each beat to perform phase shift adjustment on the first driving signal to obtain the third driving signal includes: Acquire each rising and falling edge of the first driving signal; Starting at each rising edge, the third driving signal is adjusted from the low level to the high level after a delay of half the duration of the first pulse width of the previous pulse. Starting at each falling edge, the third driving signal is adjusted from the high level to the low level after a delay of half the duration of the first pulse width of the previous pulse.

8. An interleaved parallel control circuit, characterized in that, The interleaved parallel control is coupled to the first resonant transformation circuit and the second resonant transformation circuit, and the first resonant transformation circuit and the second resonant transformation circuit are connected in parallel with each other; The interleaved parallel control circuit uses the interleaved parallel control method as described in any one of claims 1-7 to achieve interleaved parallel control of the first resonant transformation circuit and the second resonant transformation circuit.

9. An electronic device, characterized in that, The electronic device includes a housing and an interleaved parallel control circuit connected to the housing; The interleaved parallel control circuit is the interleaved parallel control circuit as described in claim 8.

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