Switching circuit
Through the bootstrap switching circuit structure and clock signal control, the input voltage is fed to the second switching capacitor circuit in advance, solving the problem of signal delay in the prior art and improving the conduction speed of the switching circuit.
Patent Information
- Application Number
- CN202410199004.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-22
- Publication Date
- 2025-08-22
AI Technical Summary
The existing switching circuits include capacitors and switches, resulting in signal delays and reduces the conduction speed.
The bootstrap switching circuit structure is adopted to control the conduction and disconnection of the switching capacitor circuit through a clock signal, and the input voltage is fed to the second switching capacitor circuit in advance to reduce signal delay.
The overall conduction speed of the switching circuit is improved and signal delay is reduced.
Smart Images
Figure CN120528409A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a switching circuit. Background Art
[0002] See also Figure 1 , Figure 1 is a functional block diagram of a conventional switching circuit. Switching circuit 100 includes a switched capacitor circuit 110 and a switched capacitor circuit 120 connected in series. When switched capacitor circuit 110 is on, intermediate voltage Vb is substantially equal to input voltage Vin. When switched capacitor circuit 120 is on, output voltage Vout is substantially equal to intermediate voltage Vb. Advantages of switching circuit 100 include reduced crosstalk (for example, as part of a sampling T-switch) or reduced timing skew (for example, as a sampling switch in a 2-rank time-interleaved analog-to-digital converter (TIADC)).
[0003] However, because both the switched capacitor circuit 110 and the switched capacitor circuit 120 include at least one capacitor and at least one switch, there is an inevitable signal delay between the at least one capacitor and the at least one switch (for example, the time from when the switched capacitor circuit 110 is turned on to when the intermediate voltage Vb is substantially equal to the input voltage Vin), which reduces the overall turn-on speed of the switch circuit 100. Summary of the Invention
[0004] In view of the deficiencies of the prior art, one object of the present invention is to provide a switch circuit to improve the deficiencies of the prior art.
[0005] One embodiment of the present invention provides a switching circuit. The switching circuit receives an input voltage and outputs an output voltage, and includes a first switched capacitor circuit, a second switched capacitor circuit, and a switch. The first switched capacitor circuit is configured to receive the input voltage and generate an intermediate voltage. The second switched capacitor circuit is coupled to the first switched capacitor circuit and is configured to receive the intermediate voltage and generate the output voltage. One terminal of the switch receives the input voltage, and the other terminal of the switch is coupled to the second switched capacitor circuit.
[0006] The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art. Therefore, the present invention can increase the overall conduction speed of the switch circuit compared to the prior art.
[0007] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 It is a functional block diagram of an existing switching circuit;
[0009] Figure 2 is a functional block diagram of one embodiment of a switch circuit of the present invention;
[0010] Figure 3A is a circuit diagram of one embodiment of a switched capacitor circuit 210 of the present invention;
[0011] Figure 3B is a circuit diagram of another embodiment of a switched capacitor circuit 210 of the present invention;
[0012] Figure 4A is a circuit diagram of one embodiment of a switched capacitor circuit 220 of the present invention;
[0013] Figure 4B is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention;
[0014] Figure 5A This is a waveform diagram of one embodiment of the operating clock of the switching circuit of the present invention;
[0015] Figure 5B is a waveform diagram of another embodiment of the operating clock of the switching circuit of the present invention;
[0016] Figure 6 is a waveform diagram of another embodiment of the operating clock of the switching circuit of the present invention;
[0017] Figure 7A is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention;
[0018] Figure 7B is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention;
[0019] Figure 8 is a waveform diagram of another embodiment of the operating clock of the switching circuit of the present invention;
[0020] Figure 9 is a waveform diagram of another embodiment of the operating clock of the switching circuit of the present invention;
[0021] Figure 10 is a functional block diagram of an embodiment of a switching circuit of the present invention used in a two-stage time-interleaved analog-to-digital converter; and
[0022] Figure 11 FIG. 2 is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention. DETAILED DESCRIPTION
[0023] The technical terms used in the following descriptions are based on customary terms in the technical field. If this specification provides explanations or definitions for some terms, the interpretation of those terms shall be based on the explanations or definitions in this specification.
[0024] The disclosure of the present invention includes a switching circuit. Since some components of the switching circuit of the present invention may be known components, the following description will omit details of the known components without affecting the full disclosure and feasibility of the device invention.
[0025] In the following description, each transistor has a first terminal, a second terminal, and a control terminal. When the transistor is used as a switch, the first terminal and the second terminal of the transistor are the two terminals of the switch, and the control terminal controls whether the switch is conductive (transistor is on) or non-conductive (transistor is off). For a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the first terminal can be one of the source and the drain, the second terminal is the other of the source and the drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be one of the collector and the emitter, the second terminal is the other of the collector and the emitter, and the control terminal is the base.
[0026] See also Figure 2 , Figure 2 This is a functional block diagram of an embodiment of a switching circuit according to the present invention. Switching circuit 200 includes a switched capacitor circuit 210, a switched capacitor circuit 220, and a switch 230. Switched capacitor circuits 210, 220, and 230 are coupled to each other. When switched capacitor circuit 210 is on, intermediate voltage Vb is substantially equal to input voltage Vin. When switched capacitor circuit 220 is on, output voltage Vout is substantially equal to intermediate voltage Vb.
[0027] The switched capacitor circuit 220 further receives an input voltage Vin through a switch 230 . More specifically, one terminal of the switch 230 receives the input voltage Vin, and the other terminal of the switch 230 is coupled or electrically connected to the switched capacitor circuit 220 .
[0028] The switched capacitor circuit 210 , the switched capacitor circuit 220 , and the switch 230 operate according to the clock CK1 , the clock CK2 , and the clock CK3 , respectively.
[0029] See also Figure 3A , Figure 3AFIG2 is a circuit diagram of an embodiment of a switched capacitor circuit 210 according to the present invention. Switched capacitor circuit 210 may be a bootstrapped switch and includes capacitor Cb1, switch 310, switch 320, switch 330, switch 340, switch 350, and switch 360. Capacitor Cb1 serves as the bootstrap capacitor for the bootstrap switch, with nodes N1 and N2 connected across capacitor Cb1. Switched capacitor circuit 210 receives an input voltage Vin via input terminal 301 and outputs an intermediate voltage Vb via output terminal 302.
[0030] Switch 310 is implemented using an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS transistor) M1. One terminal (source) of switch 310 is coupled or electrically connected to input terminal 301; the other terminal (drain) of switch 310 is coupled or electrically connected to output terminal 302. The control terminal of switch 310 is the gate of NMOS transistor M1.
[0031] The switch 320 is implemented by an NMOS transistor M2 . One terminal (source) of the switch 320 is coupled or electrically connected to the input terminal 301 ; the other terminal (drain) of the switch 320 is coupled or electrically connected to the node N1 ; and the control terminal (gate) of the switch 320 is coupled or electrically connected to the control terminal of the switch 310 .
[0032] The switch 330 is implemented by an NMOS transistor M3. One terminal (source) of the switch 330 is coupled or electrically connected to a reference voltage GND (e.g., ground level); the other terminal (drain) of the switch 330 is coupled or electrically connected to the node N1; and the control terminal (gate) of the switch 330 receives the clock CK1b.
[0033] Switch 340 is implemented using a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS transistor) M4. One terminal (source) of switch 340 is coupled to or electrically connected to a reference voltage VDD (e.g., a power supply voltage); the other terminal (drain) of switch 340 is coupled to or electrically connected to node N2; and a control terminal (gate) of switch 340 receives clock CK1.
[0034] The switch 350 is implemented by a PMOS transistor M5 . One terminal (source) of the switch 350 is coupled or electrically connected to the node N2 . The other terminal (drain) of the switch 350 is coupled or electrically connected to the control terminal of the switch 310 . The control terminal (gate) of the switch 350 receives the clock CK1 b .
[0035] The switch 360 is implemented by an NMOS transistor M6. One terminal (source) of the switch 360 is coupled or electrically connected to the control terminal of the switch 310. The other terminal (drain) of the switch 360 is coupled or electrically connected to the reference voltage GND. The control terminal (gate) of the switch 360 receives the clock CK1b.
[0036] Switched capacitor circuit 210 operates based on clock signals CK1 and CK1b. Clock signals CK1 and CK1b are inverted versions of each other. More specifically, when clock signal CK1b is at a first level (e.g., a high level), switches 330, 340, and 360 are conductive, while switches 310, 320, and 350 are non-conductive. When clock signal CK1b is at a second level (e.g., a low level), switches 330, 340, and 360 are non-conductive, while switches 310, 320, and 350 are conductive.
[0037] Because the clock CK1 and the clock CK1 b are inverted signals of each other, the switched capacitor circuit 210 is equivalent to operating according to only one of them.
[0038] See also Figure 3B , Figure 3B FIG. 2 is a circuit diagram of another embodiment of the switched capacitor circuit 210 of the present invention. Figure 3B and Figure 3A Similar, but different in Figure 3B In the embodiment of FIG. 5 , the control terminal of the switch 340 is coupled to or electrically connected to the control terminal of the switch 310 instead of receiving the clock CK1 .
[0039] See also Figure 4A , Figure 4A FIG2 is a circuit diagram of an embodiment of a switched capacitor circuit 220 according to the present invention. Switched capacitor circuit 220 includes capacitor Cb2, switches 410, 420, 430, 440, 450, and 460. Capacitor Cb2 is connected to nodes N3 and N4, respectively. Switched capacitor circuit 220 receives intermediate voltage Vb via input terminal 401 and outputs output voltage Vout via output terminal 402. Switch 230 is coupled to or electrically connected to node N3.
[0040] exist Figure 4A In the embodiment of FIG, the switched capacitor circuit 220 is also a bootstrap switch (the capacitor Cb2 is the bootstrap capacitor of the bootstrap switch). The switch 410 (M1'), the switch 420 (M2'), the switch 430 (M3'), the switch 440 (M4'), the switch 450 (M5') and the switch 460 (M6') correspond to Figure 3AThe switch 310 (M1), the switch 320 (M2), the switch 330 (M3), the switch 340 (M4), the switch 350 (M5) and the switch 360 (M6) can be based on the ordinary knowledge of the present technical field. Figure 3A The operating principle of the switched capacitor circuit 220 is understood from the description below.
[0041] The switched capacitor circuit 220 operates according to the clock CK2 and the clock CK2b. Since the clock CK2 and the clock CK2b are inverted signals of each other, the switched capacitor circuit 220 is equivalent to operating according to only one of them.
[0042] See also Figure 4B , Figure 4B FIG. 2 is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention. Figure 4B and Figure 4A Similar, but different in Figure 4B In the embodiment of FIG. 4 , the control terminal of the switch 440 is coupled to or electrically connected to the control terminal of the switch 410 instead of receiving the clock CK2.
[0043] See also Figure 5A , Figure 5A FIG. 2 is a waveform diagram of an embodiment of the operating clock of the switch circuit 200 of the present invention. Figure 5A This corresponds to the switch circuit 200 being applied to a T-type switch (ie, being a part of a T-type switch). The clock CK1 and the clock CK2 are both periodic clocks. The clock CK3 can be a periodic pulse signal.
[0044] During an operation cycle Tp of the switch circuit 200, the switched capacitor circuit 220 is first turned on (corresponding to the transition of the clock CK2 from the second level to the first level, e.g., time t1), and the switched capacitor circuit 210 is then turned on (corresponding to the transition of the clock CK1 from the second level to the first level, e.g., time t2). The switch 230 is turned on for a period of time after the switched capacitor circuit 220 is turned on (e.g., between time t1 and time t2). In other words, the clock CK3 is at the first level during the period of time after the clock CK2 transitions from the second level to the first level.
[0045] In an operation cycle Tp of the switch circuit 200, the switched capacitor circuit 220 is first turned off (corresponding to the clock CK2 switching from the first level to the second level, such as time point t3), and the switched capacitor circuit 210 is no longer turned off (corresponding to the clock CK1 switching from the first level to the second level, such as time point t4).
[0046] See also Figure 5B , Figure 5B FIG. 2 is a waveform diagram of an embodiment of the operating clock of the switch circuit 200 of the present invention. Figure 5BThis corresponds to the switch circuit 200 being applied to a T-type switch (ie, being a part of a T-type switch).
[0047] During an operation cycle Tp of the switch circuit 200, the switched capacitor circuit 220 is first turned on (corresponding to the transition of the clock CK2 from the second level to the first level, e.g., time t1), and the switched capacitor circuit 210 is then turned on (corresponding to the transition of the clock CK1 from the second level to the first level, e.g., between time t1 and time t2). The switch 230 is turned on for a period of time after the switched capacitor circuit 220 is turned on (e.g., between time t1 and time t2). In other words, the clock CK3 is at the first level during the period of time after the clock CK2 transitions from the second level to the first level.
[0048] In an operation cycle Tp of the switch circuit 200, the switched capacitor circuit 210 is first turned off (corresponding to the clock CK1 switching from the first level to the second level, for example, before time point t3), and the switched capacitor circuit 220 is no longer turned on (corresponding to the clock CK2 switching from the first level to the second level, for example, at time point t3).
[0049] See also Figure 6 , Figure 6 FIG. 2 is a waveform diagram of another embodiment of the operating clock of the switch circuit 200 of the present invention. Figure 6 The switch circuit 200 is applied to a two-stage time-interleaved analog-to-digital converter (ie, serving as a sampling switch of the two-stage time-interleaved analog-to-digital converter). Clocks CK1 and CK2 are both periodic clocks. Clock CK3 can be a periodic pulse signal.
[0050] During an operation cycle Tp of the switch circuit 200, the switched capacitor circuit 210 and the switched capacitor circuit 220 change from non-conductive to conductive at substantially the same time (e.g., at time t1), and the switch 230 is turned on for a period of time after the switched capacitor circuit 220 is turned on (e.g., between time t1 and time t2). In other embodiments, the time at which the clock CK2 transitions from the second level to the first level may be slightly earlier or slightly later than the time at which the clock CK1 transitions from the second level to the first level.
[0051] In an operation cycle Tp of the switch circuit 200 , the switched capacitor circuit 210 is first turned off (eg, at time point t3 ), and then the switched capacitor circuit 220 is turned off (eg, at time point t4 ).
[0052] In some embodiments, the switch 230 can be implemented by a single transistor. Compared to the switched capacitor circuit 210, the switch 230 is fully conductive faster (ie, the time required for the switch 230 to be fully conductive from being non-conductive to having its input voltage and output voltage being substantially the same is shorter).
[0053] exist Figure 5A 、 Figure 5B and Figure 6 In the embodiment of the present invention, the clock CK3 switches from the second level to the first level at time t1, and switches from the first level to the second level at time t2. In other embodiments, the time point at which the clock CK3 switches from the second level to the first level may be slightly earlier than time t1, and the time point at which the clock CK3 switches from the first level to the second level may be slightly earlier or later than time t2.
[0054] See also Figure 7A , Figure 7A FIG. 2 is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention. Figure 7A and Figure 4A Similar, but different in that Figure 7A In the embodiment of FIG. 4 , the switched capacitor circuit 220 does not include the switch 420 .
[0055] See also Figure 7B , Figure 7B FIG. 2 is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention. Figure 7B and Figure 4B Similar, but different in that Figure 7B In the embodiment of FIG. 4 , the switched capacitor circuit 220 does not include the switch 420 .
[0056] See also Figure 8 , Figure 8 FIG. 2 is a waveform diagram of another embodiment of the operating clock of the switch circuit 200 of the present invention. Figure 8 The clock is suitable for Figure 7A or Figure 7B The circuit. Figure 8 This corresponds to the switch circuit 200 being applied to a T-type switch. Figure 8 and Figure 5A Similar, but different in that Figure 8 In the example, clock CK2 and clock CK3 are the same clock.
[0057] See also Figure 9 , Figure 9 FIG. 2 is a waveform diagram of another embodiment of the operating clock of the switch circuit 200 of the present invention. Figure 9 The clock is suitable for Figure 7A or Figure 7B The circuit. Figure 9 This corresponds to the switch circuit 200 being applied to a two-stage time-interleaved analog-to-digital converter. Figure 9 and Figure 6 Similar, but different in that Figure 9 In the example, clock CK2 and clock CK3 are the same clock.
[0058] according to Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 8 or Figure 9 With the clock, the switch 230 is turned on before the intermediate voltage Vb is substantially equal to the input voltage Vin (that is, before the switch capacitor circuit 210 is fully turned on), so that the voltage on the node N3 is switched to the input voltage Vin earlier (that is, the switch 230 can enable the capacitor Cb2 of the switch capacitor circuit 220 to receive the input voltage Vin earlier), thereby improving the overall conduction speed of the switch circuit 200.
[0059] In summary, since the switch circuit of the present invention feeds forward the input voltage Vin to the second switched capacitor circuit (ie, the aforementioned switched capacitor circuit 220 ) in advance, signal delay can be reduced and the overall conduction speed of the switch circuit can be improved.
[0060] See also Figure 10 , Figure 10 This is a functional block diagram of an embodiment of a switching circuit of the present invention used for a two-stage time-interleaved analog-to-digital converter. The switching circuit 1000 serves as a sampling switch and includes a switching circuit 200, a switching capacitor circuit 220_1, and a switch 230_1. One end of the switch 230_1 receives an input voltage Vin, and the other end of the switch 230_1 is coupled or electrically connected to the switching capacitor circuit 220_1. The functions of the switching capacitor circuit 220_1 and the functions of the switch 230_1 are substantially the same as the functions of the switching capacitor circuit 220 and the functions of the switch 230, respectively. The switching capacitor circuit 220_1 is substantially the same as the switching capacitor circuit 220, and the connection method of the switching capacitor circuit 220_1 and the switch 230_1 can refer to Figure 4A 、 Figure 4B 、 Figure 7A or Figure 7B The switched capacitor circuit 220 and the switched capacitor circuit 220_1 generate output voltages Vout and Vout_1 at different time points, respectively, and the output voltages Vout and Vout_1 are converted by the first sub-analog analog-to-digital converter and the second sub-analog analog-to-digital converter (not shown) to generate the output of the time-interleaved analog-to-digital converter. The operating principle of the time-interleaved analog-to-digital converter is well known to those skilled in the art, and thus those skilled in the art can understand the time-interleaved analog-to-digital converter based on the principle of operation. Figure 6 or Figure 9 The control timing of the switch circuit 1000 is well known, so it will not be described in detail.
[0061] See also Figure 11 , Figure 11 FIG. 2 is a circuit diagram of another embodiment of the switched capacitor circuit 220 of the present invention. Figure 11 and Figure 4A Similar, but different in Figure 11 In the embodiment of FIG. 4 , the switched capacitor circuit 220 further includes a switch 470 , a switch 480 , a switch 490 , and a switch 495 .
[0062] Switch 470 is implemented by an NMOS transistor M7'. One terminal (source) of switch 470 is coupled or electrically connected to the control terminal of switch 410; the other terminal (drain) of switch 470 is coupled or electrically connected to the source of NMOS transistor M6'; and the control terminal (gate) of switch 470 is coupled or electrically connected to reference voltage VDD.
[0063] The switch 480 is implemented by a PMOS transistor M8 ′. One terminal (source) of the switch 480 is coupled or electrically connected to the reference voltage VDD. The other terminal (drain) of the switch 480 is coupled or electrically connected to the control terminal of the switch 450 . The control terminal (gate) of the switch 480 receives the clock CK2 .
[0064] The switch 490 is implemented by an NMOS transistor M9 ′. One terminal (source) of the switch 490 is coupled or electrically connected to the node N3 . The other terminal (drain) of the switch 490 is coupled or electrically connected to the control terminal of the switch 450 . The control terminal (gate) of the switch 490 receives the clock CK2 .
[0065] Switch 495 is implemented by NMOS transistor M10′. One terminal (source) of switch 495 is coupled or electrically connected to the control terminal of switch 450; the other terminal (drain) of switch 495 is coupled or electrically connected to node N3; and the control terminal (gate) of switch 495 is coupled or electrically connected to the control terminal of switch 410.
[0066] Switches 470 , 480 , 490 and 495 serve as protection elements for the bootstrap switches. The operating principles of these protection elements are well known to those skilled in the art and will not be further described.
[0067] Those skilled in the art can Figure 11 exist Figure 4B 、 Figure 7A and Figure 7B Add protection components.
[0068] In other embodiments, the PMOS transistor and the NMOS transistor in the aforementioned embodiment may be replaced by an NMOS transistor and a PMOS transistor, respectively. A person skilled in the art would know how to adjust the clock and the reference voltage accordingly to implement the aforementioned implementation.
[0069] Please note that the shapes, sizes and proportions of the components in the above-mentioned figures are merely illustrative and are provided to help those skilled in the art understand the present invention, and are not intended to limit the present invention.
[0070] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may modify the technical features of the present invention based on the explicit or implicit content of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application defined in this specification.
[0071]
Explanation of symbols
[0072] 100, 200, 1000: switch circuit
[0073] 110,120,210,220,220_1: Switched capacitor circuit
[0074] Vb: middle voltage
[0075] Vin: input voltage
[0076] Vout, Vout_1: output voltage
[0077] 230,310,320,330,340,350,360,410,420,430,440,450,460,230_1,470,480,490,495: switch
[0078] CK1, CK2, CK3, CK1b, CK2b: clock
[0079] 301,401: Input
[0080] 302,402: output terminal
[0081] Cb1, Cb2: capacitors
[0082] GND, VDD: reference voltage
[0083] M1, M2, M3, M6, M1', M2', M3', M6', M7', M9', M10': NMOS transistors
[0084] M4, M5, M4', M5', M8': PMOS transistors
[0085] N1, N2, N3, N4: nodes
[0086] Tp: Operation period
[0087] t1, t2, t3, t4: time points.
Claims
1. A switching circuit for receiving an input voltage and outputting an output voltage, comprising: a first switched capacitor circuit, configured to receive the input voltage and generate an intermediate voltage; a second switched capacitor circuit, coupled to the first switched capacitor circuit, for receiving the intermediate voltage to generate the output voltage; and A switch, wherein One end of the switch receives the input voltage, and the other end of the switch is coupled to the second switched capacitor circuit.
2. The switching circuit according to claim 1, wherein: The second switched capacitor circuit includes a capacitor, and the switch is electrically connected to the capacitor.
3. The switching circuit according to claim 2, wherein: The second switched capacitor circuit is controlled by a first clock, and the second switched capacitor circuit is turned on when the first clock is at a first level. The switch is controlled by a second clock, and the switch is turned on when the second clock is at the first level. The second clock is at the first level for a period of time after the first clock is converted from a second level to the first level.
4. The switching circuit according to claim 3, wherein: In an operation cycle, the first switched capacitor circuit changes from conducting to non-conducting earlier than the second switched capacitor circuit.
5. The switching circuit according to claim 3, wherein: The second switched capacitor circuit is a bootstrap switch, and the capacitor is a bootstrap capacitor of the second switched capacitor circuit.
6. The switching circuit according to claim 2, wherein: The second switched capacitor circuit and the switch are controlled by a clock. The second switched capacitor circuit and the switch are turned on when the clock is at a first level, and are turned off when the clock is at a second level.
7. The switching circuit according to claim 6, wherein: In an operation cycle, the first switched capacitor circuit changes from conducting to non-conducting earlier than the second switched capacitor circuit.
8. The switching circuit according to claim 6, wherein: The two ends of the capacitor are respectively a first node and a second node, and the second switched capacitor circuit includes: a first switch having a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to an input terminal of the second switched capacitor circuit, and the second terminal is coupled to an output terminal of the second switched capacitor circuit; a second switch having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to a first reference voltage, the fourth terminal is coupled to the first node, and the second control terminal receives an inverted signal of the clock; a third switch having a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to a second reference voltage, the sixth terminal is coupled to the second node, and the third control terminal receives the clock; a fourth switch having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the second node, the eighth terminal is coupled to the first control terminal, and the fourth control terminal receives the inverted signal; and A fifth switch has a ninth terminal, a tenth terminal, and a fifth control terminal, wherein the ninth terminal is coupled to the first control terminal, the tenth terminal is coupled to the first reference voltage, and the fifth control terminal receives the inverted signal.
9. The switching circuit according to claim 6, wherein: The two ends of the capacitor are respectively a first node and a second node, and the second switched capacitor circuit includes: a first switch having a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to an input terminal of the second switched capacitor circuit, and the second terminal is coupled to an output terminal of the second switched capacitor circuit; a second switch having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to a first reference voltage, the fourth terminal is coupled to the first node, and the second control terminal receives an inverted signal of the clock; a third switch having a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is coupled to a second reference voltage, the sixth terminal is coupled to the second node, and the third control terminal is coupled to the first control terminal; a fourth switch having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the second node, the eighth terminal is coupled to the first control terminal, and the fourth control terminal receives the inverted signal; and A fifth switch has a ninth terminal, a tenth terminal, and a fifth control terminal, wherein the ninth terminal is coupled to the first control terminal, the tenth terminal is coupled to the first reference voltage, and the fifth control terminal receives the inverted signal.
10. The switching circuit according to claim 2, wherein: The output voltage is a first output voltage, the switch is a first switch, and the switch circuit further includes: a third switched capacitor circuit, coupled to the first switched capacitor circuit, for receiving the intermediate voltage to generate a second output voltage; as well as a second switch, wherein one terminal of the second switch receives the input voltage, and the other terminal of the second switch is coupled to the third switched capacitor circuit.