LDPC decoder and decoding method thereof for ccsds standard

Abstract

The application relates to a CCSDS standard-oriented LDPC decoder and a decoding method thereof, and relates to the fields of satellite communication and channel coding technology, and aims to solve the technical problems of insufficient parallelism and low resource utilization of a satellite communication LDPC decoder in the prior art. The CCSDS standard-oriented LDPC decoder comprises a frame input module, a control module, an initial probability storage module, a check node calculation module, a variable node calculation module and a frame output module. The CCSDS standard-oriented LDPC decoder and the decoding method thereof are suitable for efficient decoding of long frame data in satellite communication, and the dynamic block storage architecture, the hybrid iterative decoding algorithm and the configurable control module are designed in cooperation, the decoding algorithm performance and the complexity balance are realized through storage design optimization, the algorithm flexibility is improved through configurable strategies, and the efficiency and resource contradiction of long frame LDPC decoding in satellite communication are systematically solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of satellite communication and channel coding, in particular to an LDPC decoder and decoding method for CCSDS standard. BACKGROUND

[0002] Low-density parity-check code (LDPC code) is a kind of forward error correction code, which was proposed by Robert Gallager of Massachusetts Institute of Technology in his doctoral thesis in 1963. LDPC code has a sparse check matrix, can approach the Shannon limit, and is simple to describe and implement, and is suitable for hardware implementation.

[0003] The existing satellite communication LDPC decoder has the following technical defects:

[0004] Insufficient parallelism: the traditional decoder adopts a single storage structure, which is difficult to meet the high throughput requirement of long frame data (such as 8176bit / frame), resulting in long decoding delay.

[0005] Low resource utilization: when implemented by FPGA, the check node and variable node iteration process needs to frequently read and write the storage unit, resulting in large hardware resource consumption. SUMMARY

[0006] The present application aims to solve the technical problems of insufficient parallelism and low resource utilization of the existing satellite communication LDPC decoder, and provides an LDPC decoder and decoding method for CCSDS standard.

[0007] In order to solve the above technical problems, the technical scheme of the present application is as follows:

[0008] An LDPC decoder for CCSDS standard comprises:

[0009] Frame input module: used to receive initial probability data and store it in multiple RAM modules in blocks;

[0010] Control module: performs corresponding calculation and control operation according to the jump of state machine;

[0011] Initial probability storage module: encapsulates multiple RAM modules to realize storage and reading of initial probability data; reads data through the reading port for calculation of check nodes and variable nodes;

[0012] Check node calculation module: used to realize the update calculation of check nodes; distributes the input data to the corresponding check node calculation unit for processing according to the flag signal, and stores the calculation results back to the original RAM module;

[0013] Variable node calculation module: used to realize the update calculation of variable nodes;

[0014] Frame output module: used for outputting the decision signal; integrating and sorting the input decision information, and outputting continuous decoding data according to the clock beat.

[0015] In the above technical solution, in the frame input module, one data is input in each clock cycle, and the corresponding storage address and enable signal are output.

[0016] In the above technical solution, in the control module, the state machine includes the following corresponding to different decoding stages: standby state, initialization state, check node calculation state, variable node calculation state and decoding completion output state.

[0017] In the above technical solution, in the variable node calculation module, each variable node calculation unit inputs four-way check node data and one-way initial probability data, and outputs four-way updated variable node data and one-way decision data.

[0018] In the above technical solution, the control module calculates the base address offset in real time according to the input code length, and realizes the dynamic allocation of the storage space of the RAM module through the combination of shift operation and modulo operation.

[0019] The control module further includes a preliminary next processing data address buffer, which adopts a dual-port RAM structure, loads the address mapping tables of adjacent two frames in advance, so that the CNU calculation stage and the address prefetch operation are executed in parallel.

[0020] In the above technical solution, in the RAM module, the even period accesses the initialization RAM group, and the odd period accesses the iteration RAM group, and the read-write conflict is eliminated through the time slice rotation mechanism.

[0021] In the above technical solution, the check node calculation module adopts a 14-stage pipeline structure, each stage includes 8 Min-Sum algorithm processing units, and the critical path delay model is: T_cnu = T_mu + log2(N) × T_ad, N = 112.

[0022] Wherein, T_cnu represents the total delay of the critical path of the check node calculation module; T_mu represents the operation delay time of the multiplier; T_ad represents the operation delay time of the adder.

[0023] In the above technical solution, the GF(2^4) multiplier in the variable node calculation module adopts a polynomial base optimization structure, and the operation logic is simplified to a three-stage pipeline: GF_MUL = (a⊗b) ⊕ ((a<<1) & 0x0F) ⊕ ((b<<1) &0x0F).

[0024] In the above technical solution, in the RAM module, the RAM array is divided into 16 independent power domains, and when it is detected that there is no access operation for 5 continuous periods, the clock of the corresponding region is automatically turned off.

[0025] A decoding method suitable for the above CCSDS standard-oriented LDPC decoder, comprising the following steps:

[0026] Step 1: Block storage of the input initial probability data, input a group of channel soft information every clock, and store the information into the RAM module;

[0027] Step 2: After storing the initial probability data, read the initial probability data for processing; the initial probability data is read for the data source of the first update of the check node calculation module, and after the check node calculation module is updated, the initial probability data needs to be read every time the variable node calculation module is iterated to perform accumulation;

[0028] Step 3: Add flag information when reading the initial probability data;

[0029] Step 4: The check node calculation module performs update calculation;

[0030] Step 5: The variable node calculation module performs update calculation;

[0031] Step 6: Output the decision code word after decoding.

[0032] The present application has the following beneficial effects:

[0033] The CCSDS standard-oriented LDPC decoder and the decoding method thereof are suitable for efficient decoding of long frame data in satellite communication, and the dynamic block storage architecture, the hybrid iterative decoding algorithm and the configurable control module are designed in cooperation, the decoding algorithm performance and complexity are balanced through storage design optimization, the algorithm flexibility is improved through configurable strategy, and the efficiency and resource contradiction of long frame LDPC decoding in satellite communication are systematically solved. BRIEF DESCRIPTION OF DRAWINGS

[0034] The present application will be further described in detail below in combination with the drawings and specific embodiments.

[0035] Figure 1 It is a state transition diagram of the decoder.

[0036] Figure 2 It is a functional module diagram of the LDPC decoder of the present application. DETAILED DESCRIPTION

[0037] The present application will be further described in detail below in combination with the drawings and specific embodiments.

[0038] The CCSDS standard-oriented LDPC decoder of the application is suitable for efficient decoding of long frame data in satellite communication, and is characterized by the synergistic design of a dynamic block storage architecture, a hybrid iterative decoding algorithm and a configurable control module.

[0039] The frame input module is responsible for receiving initial probability data and storing the same in multiple RAM modules in blocks. One data is input every clock cycle, and the corresponding storage address and enable signal are output.

[0040] The control module performs corresponding calculation and control operations according to the jump of the state machine. The state machine includes standby state, initialization state, check node calculation state, variable node calculation state and decoding completion output state, which correspond to different decoding stages, respectively.

[0041] The initial probability storage module encapsulates multiple RAM modules to realize the storage and reading of initial probability data. The data read through the reading port is used for the calculation of check nodes and variable nodes.

[0042] The check node calculation module realizes the update calculation of check nodes. Specifically, the input data is distributed to the corresponding check node calculation unit for processing according to the flag signal, and the calculation result is stored back to the original RAM module.

[0043] The variable node calculation module realizes the update calculation of variable nodes. Specifically, each variable node calculation unit inputs five-way signals (four-way check node data and one-way initial probability data) and outputs five-way signals (four-way updated variable node data and one-way decision data).

[0044] The frame output module is responsible for outputting decision signals. Specifically, the input decision information is integrated and sorted, and continuous decoding data is output according to the clock beat.

[0045] The corresponding modules of the CCSDS standard-oriented LDPC decoder of the application will be described in more detail below.

[0046] The control module calculates the base address offset in real time according to the input code length, realizes the dynamic allocation of the storage space of the RAM module through the combination of shift operation and modulo operation, supports the seamless switching of variable code length shortened codes under the CCSDS standard, and loads the address mapping table of the adjacent two frames in advance to make the CNU calculation stage and the address prefetch operation execute in parallel, so that the overall processing delay is reduced by 42%.

[0047] Based on the innovative design of the parity time division multiplexing technology, the even period access initializes the RAM group (address space 0-72), and the odd period access iterates the RAM group (address space 73-146), and the time slice rotation mechanism eliminates the read-write conflict, and the window sliding compression algorithm is used, and the ping-pong operation of the 8*8 data block is completed every 72 clock periods. The actual measurement shows that the bandwidth utilization rate is increased from 42% to 67%, and the access efficiency is increased by 59%.

[0048] The check node calculation module adopts a 14-stage pipeline structure, each stage includes 8 Min-Sum algorithm processing units, the critical path delay model is: T_cnu = T_mu + log2(N) * T_ad, N = 112, and the actual delay is 1.8 ns. The dynamic weight adjustment module includes an iteration number feedback mechanism to update the belief propagation parameter a, the adjustment range is 0.75-0.95, and the step size 0.05 is programmable.

[0049] In the formula, T_cnu represents the total delay of the critical path of the check node calculation module; T_mu represents the operation delay time of the multiplier; and T_ad represents the operation delay time of the adder.

[0050] The GF(2^4) multiplier in the variable node calculation module adopts a polynomial-based optimization structure, and the operation logic is simplified to a three-stage pipeline: GF_MUL = (a⊗b)⊕((a<<1)&0x0F)⊕((b<<1)&0x0F). The design shortens the 4-period operation of the traditional AND-XOR logic to 2 periods, and the operation speed is increased by 30%. Through the asymmetric check matrix mapping technology, the 112 VNU units are divided into 7 processing clusters, each cluster shares a 16KB check factor lookup table, and the hardware resource reuse rate is increased to 87%.

[0051] The RAM array is divided into 16 independent power domains, and when 5 consecutive periods of no access operation are detected, the clock of the corresponding region is automatically turned off, and the actual static power consumption is reduced by 35%. The temperature adaptive adjustment module included triggers the frequency reduction mechanism when the junction temperature Tj is greater than or equal to 85°C, and the working frequency is reduced from 250MHz to 200MHz, which is suitable for on-orbit requirements.

[0052] The decoding method of the CCSDS standard-oriented LDPC decoder is described in detail below.

[0053] The state transition of the decoder is as follows Figure 1As shown, the core states of the decoder include: IDLE (idle), INIT (initialization), CNU (check node update), VNU (variable node update), Iteration (information circulation between VNU and CNU) and OUTPUT (decoding completion, including iteration upper limit or decoding failure). Wherein, Header represents frame header detection information, which is set to 0 when no frame header is detected, and is set to 1 after the frame header is detected. Code_complete is the channel information integrity identifier, which is set to 1 when a frame of information is completely received, and is set to 0 otherwise. Code_state represents the decoding completion state, which is set to 1 if the decoding is successful or the maximum iteration number is reached, and is set to 0 otherwise. Inter_max represents whether the iteration number reaches the maximum, which is set to 1 if the maximum iteration number is reached, and is set to 0 otherwise. Cnu_finish indicates whether the check node calculation is completed in the iteration process, which is set to 1 if completed, and is set to 0 otherwise. Vnu_pass represents whether the variable node update passes the check, which is set to 1 if passed, and is set to 0 otherwise.

[0054] IDLE represents that the decoder is in an idle state, when the frame header detection message from the front-end frame input module is detected, the decoder enters the INIT state, starts to store the initial channel information, and enters the loop after the storage is completed and the parameter configuration is completed, and the decoder enters the working state. After completing the parameter configuration, enter the Iteration state, jump to the VNU state; first, the variable node calculation module performs hard decision, and if the check is successful, directly enters the OUTPUT state. If the check is unsuccessful, the variable node update is performed, and after the update is completed, the message is transmitted to the check node calculation unit, and enters the CNU state, the check node calculation module, and the check node calculation module is completed. After the iteration number is added by 1, until the iteration number reaches the upper limit or the intermediate iteration check is successful, enter the OUTPUT state, and the code word is output. At the same time, the state of the decoder is set to IDLE state.

[0055] The LDPC decoder for the CCSDS standard of the application is suitable for the decoding method as shown in the figure, wherein the three arrow directions of the control module to the check node calculation module, the variable node calculation module and the channel soft information initialization represent the control bus, and the remaining arrow directions represent the information bus. Figure 2 The decoding method comprises the following steps:

[0056] Step 1: block storage of the input initial probability data, input a group of channel soft information every clock, and store the channel soft information into 112 RAM modules to provide parallel information for subsequent calculation.

[0057] Step 2: After storing the initial probability data, the initial probability data is read for the first time to be used as the data source for the first update of the check node calculation module. After the check node calculation module is updated, the variable node calculation module needs to read the initial probability data for each iteration to perform accumulation.

[0058] Step 3: Add flag information when reading the initial probability data. The first reading of 112 initial probability data to the CV_RAM storage of the check node update intermediate information requires that the data has added flag information. The purpose of the flag information is to correspond to the 14 parallel processing check node calculation modules. Each check node calculation module extracts data from the CV_RAM according to the flag information when processing data. Since the CV_RAM is stored by column, the first data in the first CV_RAM is the first variable node, and so on. The 73rd data is the 73rd variable node. When outputting, the first data may not be the data required by the first check node calculation module, so flag information is added. The added flag information is matched with the 448 CV_RAM data.

[0059] Step 4: After transferring the initial probability data to the CV_RAM and adding flag information, the check node calculation module performs check node update calculation. The input of each sub-check matrix corresponding to the 14 RAMs needs to be input to the corresponding 14 check node calculation module calculation units according to the flag signal. The data after calculation still needs to be sent back to the original RAM module for storage according to the flag signal. There are mainly three sub-modules inside, the data reading unit reads the information required by each check node calculation module from the RAM module according to the flag bit; the calculation unit calculates the minimum value and the second minimum value of the 32 input data in the input port of each check node calculation module; the return unit returns the 32 calculated data to the original storage location.

[0060] Step 5: After the check node calculation module is updated, the variable node calculation module is updated. The variable node calculation module has 112 variable node calculation units, each of which inputs five signals, four check node information, and one initial probability data. It outputs five signals, four updated variable node information, and one decision code word, i.e. decision data, which is controlled by the flag signal to output only when the maximum iteration number is reached or the check is passed.

[0061] Step 6: After decoding, the output decision code word, frame output module each clock input 112 road decision information, because the input of 112 road data is not continuous decision data, but according to the degree of each bit represents the first bit in the RAM module, the data needs to be converted, the data is integrated into continuous decoding data, finally in the arrival of the flag signal each clock output 73 decoding data.

[0062] The CCSDS standard-oriented LDPC decoder and the decoding method thereof are suitable for efficient decoding of long frame data in satellite communication, and are characterized in that the dynamic block storage architecture, the hybrid iterative decoding algorithm and the configurable control module are designed in cooperation, the decoding algorithm performance and the complexity balance are realized through storage design optimization, the algorithm flexibility is improved through configurable strategy, and the efficiency and resource contradiction of long frame LDPC decoding in satellite communication are systematically solved.

[0063] Obviously, the above embodiments are only examples for clearly illustrating but not limiting the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted. The changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A CCSDS standard oriented LDPC decoder, characterized in that, The application relates to a CCSDS standard-oriented LDPC decoder, which comprises the following parts: a frame input module for receiving initial probability data and storing the data into multiple RAM modules in blocks; a control module for performing corresponding calculation and control operations according to the jump of a state machine; an initial probability storage module for encapsulating the multiple RAM modules to realize the storage and reading of initial probability data; the data is read through a reading port to be used for the calculation of check nodes and variable nodes; a check node calculation module for realizing the update calculation of check nodes; input data is distributed to corresponding check node calculation units according to a flag signal for processing, and the calculation results are stored back into the original RAM module; a variable node calculation module for realizing the update calculation of variable nodes; a frame output module for outputting decision signals; input decision information is integrated and sorted, and continuous decoding data is output according to clock beats; the control module calculates a base address offset in real time according to an input code length, realizes the dynamic allocation of the storage space of the RAM module through the combination of shift operation and modulus operation, and the control module further comprises a data address buffer for the next processing, which adopts a dual-port RAM structure, loads an address mapping table of adjacent two frames in advance, and makes the CNU calculation stage and the address prefetch operation execute in parallel; in the RAM module, even period access initializes a RAM group, and odd period access iterates a RAM group, and the read-write conflict is eliminated through a time slice rotation mechanism. In the frame input module, one data is input every clock period, and corresponding storage addresses and enable signals are output.

2. The CCSDS standard oriented LDPC decoder according to claim 1, wherein, In the control module, the state machine comprises the following states corresponding to different decoding stages: a standby state, an initialization state, a check node calculation state, a variable node calculation state and a decoding completion output state.

3. The CCSDS standard oriented LDPC decoder according to claim 1, wherein, In the variable node calculation module, each variable node calculation unit inputs four-way check node data and one-way initial probability information, and outputs four-way updated variable node data and one-way decision data.

4. The CCSDS standard oriented LDPC decoder according to claim 1, wherein, The check node calculation module adopts a 14-stage pipeline structure, each stage contains 8 Min-Sum algorithm processing units, and the critical path delay model is T_cnu=T_mu+log2(N)X T_ad, N=112; 5. The CCSDS standard oriented LDPC decoder according to claim 1, wherein, wherein T_cnu represents the total delay of the critical path of the check node calculation module; T_mu represents the operation delay time of a multiplier; and T_ad represents the operation delay time of an adder.

6. The CCSDS standard-oriented LDPC decoder according to claim 1, characterized in that in the RAM module, the RAM array is divided into 16 independent power domains, and when it is detected that there is no access operation for 5 continuous periods, the clock of the corresponding region is automatically turned off. The GF(2^4) multiplier in the variable node calculation module adopts a polynomial basis optimization structure, and the operation logic is simplified to three stages of pipelining:

7. The CCSDS standard oriented LDPC decoder according to claim 1, wherein, The application further discloses a method for realizing the CCSDS standard-oriented LDPC decoder, which comprises the following steps:

8. A decoding method suitable for the CCSDS standard oriented LDPC decoder of claim 1, characterized in that, Step 1: storing the input initial probability data in blocks, inputting a group of channel soft information every clock, and storing the information into the RAM module; Step 2: reading the initial probability data after storing the initial probability data; the initial probability data is read for the data source of the first update of the check node calculation module, and after the update of the check node calculation module, the initial probability data needs to be read for execution of accumulation every iteration of the variable node calculation module; Step 3: adding flag information when reading the initial probability data; ​ Step 4: The check node calculation module performs update calculation; Step 5: The variable node calculation module performs update calculation; Step 6: After decoding, output the decision codeword.

Images