Improved method for manufacturing a composite core substrate with embedded lines

Abstract

This invention relates to the field of composite core substrate technology, and in particular to an improved method for manufacturing a composite core substrate with embedded circuitry. The method includes a substrate composed of a core layer and a dielectric layer, wherein the dielectric layer is located at the top and bottom of the core layer. This invention solves the problem that lasers cannot process copper-plated via land, and that during target fabrication, the lack of etching of the bottom copper results in a small color difference between the target and the substrate, making identification difficult during hot-melt processes, thus reducing stability and accuracy. The invention proposes a via land with a hollow circular structure, allowing the laser beam to more accurately position and penetrate the via land during processing, thereby effectively improving processing precision and efficiency. Simultaneously, by etching the bottom copper, the color difference and contrast between the target and the substrate are improved, significantly enhancing the stability and accuracy of the processing.

Description

Technical Field

[0001] This invention relates to the field of composite core substrate technology, and in particular to an improved manufacturing method for a composite core substrate with embedded circuitry. Background Technology

[0002] As electronic devices evolve towards miniaturization, high density, and high performance, traditional planar substrate designs are no longer adequate for the demands of high-density interconnects and high-frequency, high-speed applications. Embedded substrate technology, by embedding passive components (such as capacitors and resistors) within the substrate's internal structure, effectively reduces reliance on surface-mount components (SMDs), thereby significantly improving package density and optimizing signal transmission performance.

[0003] When processing the via land of the ETS layer, the shape of the via land makes it impossible for the laser to process the copper-plated via land. In the original process of making the target, there is a layer of base copper that is not etched, resulting in a small color difference between the target and the substrate, making it difficult to identify during hot melting, which reduces the stability and accuracy of the processing. Summary of the Invention

[0004] The technical objective of this invention is to address the limitations of laser processing on copper-plated via land, where the lack of etching of the base copper during target fabrication leads to a small color difference between the target and the substrate, making identification difficult during hot-melt processes and reducing stability and accuracy. This invention proposes a via land with a hollow circular structure, allowing the laser beam to more precisely position and penetrate the via land during processing, thereby effectively improving processing accuracy and efficiency. Furthermore, etching the base copper enhances the color difference and contrast between the target and the substrate, significantly improving stability and accuracy during processing.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] An improved method for manufacturing a composite core substrate with embedded circuitry includes: a substrate composed of a core layer and a dielectric layer, wherein the dielectric layer is located at the top and bottom of the core layer; the manufacturing steps are as follows:

[0007] S1: Create the embedded wire layer;

[0008] S2: Create two core layers;

[0009] S3: After the fabrication of one embedded wire layer and two core layers is completed, the dielectric layer is used to heat-melt the combination. After the heat-melt combination, the top and bottom layers of the core layer are laminated with dielectric layer and copper foil to add layers.

[0010] S4: Separate the two core layers after the two laminated layers are added;

[0011] S5: Laser drilling of the removed core layer;

[0012] S6: Deamear the core layer after drilling, and then apply copper.

[0013] S7: Image transfer is performed after copper plating;

[0014] S8: Subsequently electroplated;

[0015] S9: Rapid etching is performed after film removal;

[0016] S10: After etching, the material is cut and a solder mask layer is created.

[0017] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, the embedded circuitry layer consists of a detach core, two carrier Cu layers, and two Cu layers, wherein the two carrier Cu layers are located on the top and bottom layers of the detach core, and the two Cu layers are located on the two carrier Cu layers.

[0018] The process of creating the embedded wire layer in step S1 includes the following steps:

[0019] S11: Feeding materials;

[0020] S12: Image transfer;

[0021] S13: Pattern electroplating and film removal;

[0022] S14: Image transfer, creating targets for thermal fusion alignment;

[0023] S15: Etching, creating hot-melt alignment targets;

[0024] S16: Remove the film and create a target for hot melt alignment.

[0025] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, the core layer consists of a BT core layer and a copper layer, and multiple copper layers are arranged through the BT core layer.

[0026] The process of creating two core layers in step S2 includes the following steps:

[0027] S21: Feeding material;

[0028] S22: Laser drill holes in the BT core layer;

[0029] S23: Deamear the core layer after drilling, and then apply copper plating;

[0030] S24: Image transfer;

[0031] S25: Electroplating copper layer inside the drilled holes of the BT core layer;

[0032] S26: Defilm removal;

[0033] S27: Rapid etching.

[0034] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuits according to the present invention, in step S1, when the embedded circuit layer is fabricated, at least one reserved space is formed at a predetermined position. The shape, size and position of the reserved space are pre-designed according to the requirements of subsequent laser processing.

[0035] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, in step S5, during the laser drilling of the core layer after disassembly, before the embedded circuitry layer is laminated with subsequent layers, the reserved space is laser-processed to form the preliminary outline of the blind hole.

[0036] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, in step S4, when separating the two core layers after two laminated layers, the embedded circuitry layer is laminated with at least one dielectric layer to form a composite substrate; after lamination, part of the dielectric layer is removed by mechanical or chemical methods to expose the reserved space.

[0037] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry according to the present invention, in step S8 electroplating, the exposed reserved space is electroplated to fill the reserved space and form a blind hole with predetermined conductivity.

[0038] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, in step S14 image transfer, a dry film is pressed onto the surface of a substrate with a detachable core structure, and a preset target pattern is transferred through an exposure process to form a mask.

[0039] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, in step S15 etching, a mask is used as an etching barrier layer to perform wet etching on the detach core substrate, and the etching amount is controlled to form a groove structure on the substrate surface corresponding to the target pattern.

[0040] As a preferred embodiment of the improved manufacturing method of a composite core substrate with embedded circuitry described in this invention, in step S13 pattern electroplating and film removal, the via land is set to a hollow shape.

[0041] The beneficial effects of this invention are:

[0042] 1. This invention provides convenience for laser processing by setting the via land of the embedded wire layer to a hollow circular shape. During processing, the laser beam can be more accurately positioned and penetrate the via land, thereby effectively improving the accuracy and efficiency of processing, making the laser aperture more stable, more reliable, and more feasible.

[0043] 2. This invention optimizes the target fabrication method of the ETS layer by etching the target points, thereby improving the color difference and contrast between the target points and the substrate, which greatly enhances the stability and accuracy of the processing. Compared with the typical double-sided 4L ETS fabrication process, it overcomes the problem of severe warpage in existing ETS substrate methods when the number of product layers increases (≥4L). The new method can produce ETS products with any number of layers, taking into account the advantages of high reliability of fine embedded circuit structure and high mechanical strength and low warpage of core layer structure. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of hot-melt assembly and pressure bonding in the embodiments of this disclosure.

[0045] Figure 2 This is a schematic diagram of the substrate in an embodiment of this disclosure.

[0046] Figure 3 This is a schematic diagram of the core layer in an embodiment of this disclosure.

[0047] Figure 4 This is a schematic diagram of the embedded wire layer in an embodiment of this disclosure.

[0048] Figure 5 This is a flowchart illustrating steps S1 to S3 in an embodiment of this disclosure.

[0049] Figure 6 This is a flowchart illustrating steps S4 to S9 in an embodiment of this disclosure.

[0050] Figure 7 This is a flowchart illustrating step 10 in an embodiment of this disclosure.

[0051] Figure 8 This is a flowchart illustrating steps S11 to S16 of the embedded wire layer in an embodiment of this disclosure.

[0052] Figure 9This is a flowchart illustrating steps S21 to S27 of the core layer in an embodiment of this disclosure.

[0053] Figure 10 This is a side view of via land in step S13 of embodiment 2 of this disclosure.

[0054] Figure 11 This is Embodiment 2 of the present disclosure. Figure 10 A bird's-eye view of the via land.

[0055] Reference numerals: 1. Core layer; 11. BT core layer; 12. Copper layer; 2. Embedded wire layer; 21. Detach core; 22. Carrier Cu; 23. Cu layer; 3. Substrate; 4. Dielectric layer; 5. Copper foil; 6. Solder mask layer; 7. Hollow circle. Detailed Implementation

[0056] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0057] Example 1:

[0058] like Figures 1 to 9 As shown, an improved method for manufacturing a composite core substrate with embedded circuitry includes: a substrate 3 consisting of a core layer 1 and a dielectric layer 4, wherein the dielectric layer 4 is located at the top and bottom of the core layer 1.

[0059] The detachable core 21 serves as a temporary carrier, with carrier Cu 22 and functional Cu layers 23 covering both sides.

[0060] The preparation steps are as follows:

[0061] S1: Create the second embedded wire layer;

[0062] S2: Create two core layers 1;

[0063] S3: After the fabrication of one embedded wire layer 2 and two core layers 1, the dielectric layer 4 is used to heat-melt the combination. After the heat-melt combination, the top and bottom layers of the core layer 1 are laminated with the dielectric layer 4 and copper foil 5.

[0064] It should be noted that the alignment hot-melt assembly: one ETS substrate 3 and two Core layer substrates 3 are combined by hot-melt method using PP as dielectric layer 4. Therefore, the difference in expansion and contraction ratio between the Core layer substrate 1 and the ETS layer substrate 3 must be controlled within 50ppm, and the hot-melt accuracy is ±25μm.

[0065] Layering process: laminating PP and copper foil to extend the number of layers by 5. Temperature / pressure needs to be balanced to avoid interlayer slippage.

[0066] Lamination and Addition: PP and copper foil 5 are pressed onto the semi-finished product from the previous step to achieve lamination.

[0067] S4: Separate the two core layers 1 after the two laminated layers are added;

[0068] S5: Laser drilling of the removed core layer 1;

[0069] Separation Mechanism: Mechanical / chemical methods separate part of the dielectric layer, exposing the reserved space of the buried wire layer 2 for subsequent laser processing. Blind Via Forming: Laser processing creates the blind via outline in the reserved space, and electroplating fills the space with copper to achieve high-precision interconnection. Hollow Via Land Design: The ring structure (round / square) optimizes electroplating uniformity, reduces copper usage, and avoids excessive thickness in the center.

[0070] S6: Drill the core layer 1 after drilling, and then apply copper plating;

[0071] S7: Image transfer is performed after copper plating;

[0072] S8: Subsequently electroplated;

[0073] S9: Rapid etching is performed after film removal;

[0074] S10: After etching, the material is cut and a solder mask layer 6 is created.

[0075] like Figure 4 and Figure 8 As shown, the embedded wire layer 2 consists of a detach core 21, two carrier Cu 22, and two Cu layers 23. The two carrier Cu 22 are located on the top and bottom layers of the detach core 21, respectively, and the two Cu layers 23 are located on the two carrier Cu 22, respectively.

[0076] Detachable core 21: Requires high heat resistance and easy separation (e.g., special polymer coating). Commonly used materials are FR4 with a release layer or polyimide. Carrier Cu22: Ultra-thin copper foil 5 (≤3μm), used as a temporary carrier, must be easily peeled off during disassembly without affecting the functional layers. High-precision alignment system: Equipped with a high-resolution CCD and algorithm, adaptable to groove target point recognition, ensuring ±25μm alignment accuracy.

[0077] In step S1, the fabrication of the embedded wire layer 2 includes the following steps:

[0078] S11: Feeding materials;

[0079] S12: Image transfer;

[0080] S13: Pattern electroplating and film removal;

[0081] S14: Image transfer, creating targets for thermal fusion alignment;

[0082] S15: Etching, creating hot-melt alignment targets;

[0083] S16: Remove the film and create a target for hot melt alignment.

[0084] It should be noted that after the TS layer circuitry is fabricated, an image transfer and etching process is added specifically for creating target dots. This innovative step successfully solves the problems of small color difference and difficulty in target dot identification on the board surface in traditional processes. Target dots created through image transfer and etching technology have higher contrast and clarity, making them easier for machine vision systems to capture and identify during subsequent processing, thus ensuring the stability and accuracy of the processing. This improvement not only enhances the automation level of the production line but also provides a solid technical guarantee for the manufacturing of high-quality IC substrate 3.

[0085] Target innovation: Through secondary image transfer and etching, groove-shaped target points are formed in Cu layer 23 to enhance contrast and solve the traditional problem of color difference recognition.

[0086] When the target is made using the original method, a layer of base copper is not etched, resulting in a small color difference between the target and the substrate 3, making it difficult to identify during hot melting. The target made using the improved method will have the base copper etched away, exposing the substrate, resulting in better color difference and contrast.

[0087] Target molding features: Targets are used to provide alignment references during hot melting. Due to differences in etching amount, the grooved portion exposes the substrate, thereby ensuring color difference standards and alignment accuracy higher than traditional targets.

[0088] like Figure 3 and Figure 9 As shown, core layer 1 consists of a BT core layer 11 and a copper layer 12, with multiple copper layers 12 arranged through the BT core layer 11.

[0089] BT Core1 processing: After laser drilling, the hole walls are cleaned and copper plating is applied to activate them. The image is transferred to form a circuit pattern. Electroplating fills the holes and etching completes the conductive structure.

[0090] Penetrating copper layer 12: To ensure electrical connection between layers, it is necessary to control the uniformity of copper thickness on the hole wall.

[0091] In step S2, the creation of two core layers 1 includes the following steps:

[0092] S21: Feeding material;

[0093] S22: Laser drill holes in BT core layer 11;

[0094] S23: Deamear the core layer 1 after drilling, and then apply copper plating;

[0095] S24: Image transfer;

[0096] S25: Electroplating copper layer 12 inside the drilled hole of BT core layer 11;

[0097] S26: Defilm removal;

[0098] S27: Rapid etching.

[0099] In step S1, when fabricating the embedded wire layer 2, at least one reserved space is formed at a predetermined position. The shape, size and position of the reserved space are pre-designed according to the requirements of subsequent laser processing.

[0100] In the fabrication stage of the buried wire layer 2, through a precision patterning process, reserved spaces are pre-planned and formed on the composite structure of the detachable core material (detach Core21) and the carrier copper layer (carrier Cu22):

[0101] The shape (e.g., circular, rectangular, or irregular), size (depth 5-20μm, width 50-200μm), and distribution location of the reserved space must match the target aperture (e.g., φ30-100μm), interconnection density (e.g., ≥500 holes / cm²), and interlayer alignment tolerance (±15μm) of the subsequent blind vias.

[0102] In step S5, during the laser drilling of the removed core layer 1, before the embedded wire layer 2 is laminated, the reserved space is laser-processed to form the preliminary outline of the blind hole. A graded energy control method is used: initial high energy (e.g., 3 J / cm²) removes the surface medium, followed by low energy (0.5 J / cm²) to refine the hole wall and reduce carbon residue. A beam shaper converts the Gaussian beam into a flat-top beam to ensure the flatness of the hole bottom (Ra≤1μm). A stepped blind hole is machined within the reserved space: the upper section has a slightly larger diameter than the lower section (e.g., φ80μm→φ60μm), forming a taper angle (5-10°) to enhance the subsequent electroplating filling capability.

[0103] In step S4, the two core layers 1 after the two laminated layers are separated, and the buried wire layer 2 is laminated with at least one dielectric layer to form a composite substrate 3. After lamination, part of the dielectric layer is removed by mechanical or chemical methods to expose the reserved space.

[0104] Using low-flow PP (prepreg material, resin content 65%), a bubble-free bonding between the embedded wire layer 2 and the dielectric layer is achieved in a vacuum hot press using a segmented heating strategy (80℃→120℃→180℃, pressure 15-20kg / cm²).

[0105] In step S8, the exposed reserved space is electroplated to fill the reserved space and form a blind hole with predetermined conductivity.

[0106] Pulse reverse plating (PRP) technology is used: forward current density 2ASD, reverse current density 0.5ASD, duty cycle 4:1, which promotes preferential deposition at the bottom of blind holes and avoids the "dog bone effect".

[0107] Electroplating solution formula: copper sulfate (Cu²⁺ 60g / L) + organic additives (accelerator, inhibitor, leveling agent), pH value controlled at 1.8-2.2.

[0108] In step S14, image transfer, a dry film is pressed onto the surface of a substrate with a separable structure detach core 21, and a preset target pattern is transferred through an exposure process to form a mask.

[0109] High-resolution dry film (15μm thickness, ≤5μm resolution) was vacuum-attached to the surface of Detach Core21 and exposed with i-line ultraviolet light (wavelength 365nm) at an energy controlled between 80-100mJ / cm².

[0110] In step S15 etching, a mask is used as an etching barrier layer to perform wet etching on the detach core21 substrate, and the etching amount is controlled to form a groove structure on the substrate surface corresponding to the target pattern.

[0111] In step S13, pattern electroplating and film removal, the via land is set to a hollow shape.

[0112] It should be noted that the via land is designed to be hollow, and the specific shape of the via land is not limited to circles, squares, or other shapes.

[0113] The reserved space and laser pre-processing ensure that the blind hole position error is ≤±10μm, which is 65% higher than the traditional process (±35μm).

[0114] This invention significantly improves the color difference and contrast between the target and the substrate 3 by making a series of innovative optimizations to the target fabrication method of the ETS layer, thereby improving stability and accuracy during processing. Compared with the traditional typical double-sided 4L (four-layer) ETS fabrication process, it overcomes the serious warpage problem commonly faced by existing ETS substrate processing methods when the number of product layers increases (i.e., when the number of layers is greater than or equal to 4L).

[0115] Specifically, this invention not only effectively suppresses warpage caused by increasing the number of layers, but also enables the manufacture of ETS products with any number of layers. This greatly enhances the design freedom of ETS products. Furthermore, the new construction method cleverly combines the high reliability of the fine lines in the embedded wiring structure with the advantages of high mechanical strength and low warpage in the Core Layer 1 structure, ensuring stable and reliable product performance.

[0116] Example 2:

[0117] In step S13, pattern electroplating and film removal, the via land is set to a hollow shape.

[0118] like Figure 10 and Figure 11 As shown, the difference between Embodiment 2 and Embodiment 1 is that in step S13, the via land is set as a hollow circle 7. Embodiment 2 cleverly adjusts the shape of the via land in the ETS layer, modifying it into a hollow circle 7. This design change not only optimizes the structure of the via land but also greatly facilitates subsequent laser processing. During processing, the laser beam can more accurately position and penetrate the via land, thereby effectively improving the accuracy and efficiency of processing, resulting in a more stable laser aperture, higher reliability, and greater feasibility.

[0119] This invention cleverly shapes the via land (i.e., the landing area of ​​the through-hole) in the embedded wire layer 2 into a hollow circle 7. This unique design significantly facilitates the subsequent laser processing. Specifically, the hollow circle 7 of the via land makes it easier to accurately position the laser beam during processing and ensures that the beam penetrates the via land area smoothly and accurately. This design not only greatly improves the accuracy of processing, allowing each processing step to be executed more rigorously, but also significantly improves overall production efficiency.

[0120] More importantly, the laser aperture produced by Via Land using this hollow circle 7 design exhibits greater stability, with significantly improved consistency in both size and position. This further enhances product reliability.

[0121] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An improved manufacturing method for a composite cored substrate with embedded circuitry, characterized in that, include: A substrate (3) is composed of a core layer (1) and a dielectric layer (4), wherein the dielectric layer (4) is located at the top and bottom of the core layer (1); the manufacturing steps are as follows: S1: Create the embedded wire layer (2); S2: Create two core layers (1); S3: After the fabrication of one embedded wire layer (2) and two core layers (1), the dielectric layer (4) is hot-melted together. After hot-melting, the top and bottom layers of the core layer (1) are laminated together with the dielectric layer (4) and copper foil (5). S4: Separate the two core layers (1) after the two laminations are added; S5: Laser drilling of the core layer (1) after removal; S6: Deamear the core layer (1) after drilling, and then copper plating; S7: Image transfer is performed after copper plating; S8: Subsequently electroplated; S9: Rapid etching is performed after film removal; S10: After etching, cut the material and make a solder mask layer (6). The embedded wire layer (2) consists of a detach core, two carrier Cu, and two Cu layers (23), with the two carrier Cu located on the top and bottom layers of the detach core, and the two Cu layers (23) located on the two carrier Cu. In step S1, the fabrication of the embedded wire layer (2) includes the following steps: S11: Feeding materials; S12: Image transfer; S13: Pattern electroplating and film removal; S14: Image transfer, creating targets for thermal fusion alignment; S15: Etching, creating hot-melt alignment targets; S16: Remove the film and create a target for hot melt alignment; In step S15 etching, a mask is used as an etching barrier layer to perform wet etching on the detach core substrate and control the amount of etching to form a groove structure on the substrate surface that corresponds to the target pattern. The groove part will expose the substrate. In step S13, pattern electroplating and film removal, the via land is set to a hollow shape.

2. The improved manufacturing method of a composite core substrate with embedded circuitry as described in claim 1, characterized in that: The core layer (1) consists of a BT core layer and a copper layer (12), and multiple copper layers (12) are arranged through the BT core layer. In step S2, the creation of two core layers (1) includes the following steps: S21: Feeding material; S22: Laser drill holes in the BT core layer; S23: Deamear the core layer (1) after drilling, and then copper plating; S24: Image transfer; S25: Electroplating copper layer inside the drilled hole of BT core layer (12). S26: Defilm removal; S27: Rapid etching.

3. The improved manufacturing method of a composite core substrate with embedded circuits as described in claim 1, characterized in that: in step S1, when the embedded circuit layer (2) is manufactured, at least one reserved space is formed at a predetermined position, and the shape, size and position of the reserved space are pre-designed according to the subsequent laser processing requirements.

4. The improved manufacturing method of a composite core substrate with embedded circuitry as described in claim 1, characterized in that: In step S5, the reserved space is laser-processed in the laser-drilled hole of the core layer (1) after the core layer (1) is removed, before the embedded wire layer (2) is laminated with the subsequent layer, so as to form the preliminary outline of the blind hole.

5. The improved manufacturing method of a composite cored substrate with embedded circuitry as described in claim 1, characterized in that: In step S4, the two core layers (1) after the two laminated layers are separated, the buried wire layer (2) is laminated with at least one dielectric layer to form a composite substrate (3); after lamination, part of the dielectric layer is removed by mechanical or chemical methods to expose the reserved space.

6. The improved manufacturing method of a composite cored substrate with embedded circuitry as described in claim 1, characterized in that: In step S8, the exposed reserved space is electroplated to fill the reserved space and form a blind hole with a predetermined conductivity.

7. The improved manufacturing method of a composite cored substrate with embedded circuitry as described in claim 1, characterized in that: In step S14, image transfer, a dry film is pressed onto the surface of a substrate with a detachable core structure, and a preset target pattern is transferred through an exposure process to form a mask.

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