Silicon carbide groove power device and manufacturing method thereof

Abstract

The invention provides a silicon carbide groove power device and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. Aiming at the problems of high specific on resistance, contradiction between gate oxide reliability and a conducting channel and the like of the traditional silicon carbide trench MOSFET, the invention provides a novel structure and a manufacturing process. The device comprises a semiconductor drain region, a drift region and a second conductive type semiconductor well region, a carrier diffusion layer is arranged at the corner of a first groove, the carrier diffusion layer penetrates through the leading-out end of a semiconductor shielding region in the Z direction, meanwhile, the leading-out end of the semiconductor shielding region on the side edge of the first groove is in stage distribution in the Z direction, and the semiconductor shielding region under the first groove is in continuous distribution. And a second groove formed by over-etching silicon carbide is formed in the interlayer dielectric layer. The carrier diffusion layer enables the conducting channel not to be sacrificed by the leading-out end of the shielding region, and the second groove increases the ohmic contact area; by arranging a series of structures in the invention, the specific on-resistance of the device can be obviously optimized.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and more specifically, relates to a silicon carbide trench power device and a manufacturing method thereof. Background Art

[0002] In recent years, silicon carbide trench MOSFET power devices have been vigorously developed by researchers due to their ability to achieve smaller cell sizes and higher channel density. Among them, silicon carbide trench MOSFETs represented by Infineon have been mass-produced. Their structure sacrifices half of the conductive channel to ensure gate oxide reliability, so their specific on-resistance is not significantly reduced compared to silicon carbide planar MOSFETs.

[0003] The present invention forms a carrier diffusion layer in the semiconductor region at the corner of the first trench. When the device is in forward conduction, electrons on the semiconductor shield region lead-out side flow from the Z-direction without the semiconductor shield region lead-out area to the semiconductor drain region, thereby not sacrificing the conductive channel at the semiconductor shield region lead-out area. Furthermore, a second trench is formed based on the first contact hole. As the second trench depth increases and the width decreases, the surface area of ​​the second trench increases, thereby increasing the ohmic contact area of ​​the device. By providing a series of structures in the present invention, the device's specific on-resistance can be significantly optimized. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a silicon carbide trench power device and a manufacturing method thereof to solve the above problems.

[0005] A silicon carbide trench power device, comprising: Semiconductor drain region: heavily doped first conductivity type semiconductor material; Semiconductor buffer region: a first conductivity type semiconductor material having a doping concentration second only to that of the semiconductor drain region; Semiconductor drift region: a lightly doped first conductivity type semiconductor material, located above the semiconductor buffer region; The second conductive type semiconductor well region has a higher doping concentration than the semiconductor drift region and is located at the top of the semiconductor drift region; The first conductive type semiconductor source region is heavily doped and is located in the middle of the top of the semiconductor well region; The second conductive type semiconductor body contact region is located at the top of the semiconductor well region and away from the middle position; The second conductive type semiconductor shielding region lead-out end - is segmented and arranged in the middle position of the upper part of the semiconductor drift region along the Z direction; The first trench is located in the middle of the top of the semiconductor drift region and extends from the semiconductor source region to the interior of the semiconductor drift region; A first conductive type semiconductor carrier diffusion layer: adjacent to a corner of the first trench; A second conductive type semiconductor shielding region −, located directly below the first trench; Gate dielectric layer: covering the inner wall of the first trench; Gate electrode: located on the gate dielectric layer; Interlayer dielectric layer: covers the gate electrode; Contact hole: set in the interlayer dielectric layer, with silicon carbide over-etched at the bottom to form a second trench; The source metal electrode: forms an ohmic contact with the semiconductor source region and the semiconductor body contact region through the second trench; Drain metal electrode: located below the semiconductor drain region and forms an ohmic contact.

[0006] Preferably, the lead end of the second conductive type semiconductor shielding region is distributed in stages in the Z direction, and its thickness is T1, which is at least greater than 5% of the depth of the first trench; its width is W1, which is at least 80% wider than the first trench. The depth of the second conductive type semiconductor shielding region is determined by the energy of high-energy ion implantation, and the depth is T2.

[0007] Preferably, the initial depth T3 of the first trench is less than the depth of the second conductive type semiconductor well region.

[0008] Preferably, the first trench is formed by the following steps: Covering the initial first trench with a hard mask HM2 having a thickness T3; The hard mask HM2 is etched to expose silicon carbide at the bottom of the trench, and then thermally oxidized and wet-etched to remove the oxide layer, ie, the amorphous region at the bottom of the trench, so that the depth of the first trench exceeds the depth of the second conductive type semiconductor well region by more than 0.1 μm.

[0009] Preferably, the first conductive type semiconductor carrier diffusion layer is formed by oblique angle ion implantation into the semiconductor region at the corner of the first trench, and its net impurity doping concentration is 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 .

[0010] Preferably, the second trench may have a depth T4 of 0.15 μm and a width W4 of 0.1 μm, and its surface area increases as T4 increases and W4 decreases, thereby reducing the ohmic contact resistance.

[0011] Another technical problem to be solved by the present invention is to provide a method for manufacturing a silicon carbide trench power device, comprising the following steps: S1 stacked structure preparation: Semiconductor cache region (2): a first conductive type semiconductor layer is epitaxially grown on the heavily doped first conductive type (N type) semiconductor drain region (1), with a doping concentration of 1×10 18 pieces / cm 3 ~5×10 18 pieces / cm 3 , thickness 0.5μm~1.5μm, as a buffer area; Semiconductor drift region (3): A lightly doped first conductivity type semiconductor layer is grown epitaxially above the buffer region, with a doping concentration of 1×10 15 pieces / cm 3 ~1×10 17 pieces / cm 3 , with a thickness of 3μm~100μm, forming a drift region; S2 well region and contact region are formed: The second conductive type semiconductor well region (4): is formed at the top of the drift region by multiple aluminum ion implantations (dose 5×10 11 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type semiconductor well region with a depth of 0.5μm~1.2μm and a doping concentration higher than that of the drift region; The second conductive type semiconductor body contact region (6): at the top of the well region away from the middle position, by high-dose aluminum ion implantation (dose 5×10 14 pieces / cm 2 ~5×10 15 pieces / cm 2 ), forming a heavily doped P-type body contact region; The second conductive type semiconductor shielding region lead-out terminal (7-1): in the middle of the top of the well region, by aluminum ion implantation (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region lead-out terminal distributed in segments along the Z direction, with a thickness T1 = 0.8μm~1.5μm and a width W1 = 0.5μm~3.6μm. The wide W1 can prevent the semiconductor shielding region lead-out terminal from being exhausted during reverse operation, thereby affecting the reliability and short-circuit capability of the device; S3 first trench and shielding area are formed: Initial first trench (8): by photolithography and etching process, an initial trench is etched in the middle of the top of the drift region below the semiconductor source region, with a depth T3 = 0.3 μm ~ 0.6 μm and a width of 0.25 μm ~ 2 μm; Second conductive type semiconductor shielding region (7-2): Then, aluminum ions (dose 1×1012 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region with a depth of T2 = 0.9 μm; S4 trench optimization and carrier diffusion layer formation: Adjusting the trench depth: covering the hard mask HM2, exposing the bottom of the trench after etching, and then thermally oxidizing and wet etching the amorphous region at the bottom of the trench so that the final depth of the first trench (8) exceeds the well region by 0.1 μm, forming a trench with a depth of 0.6 μm to 1.3 μm; The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique nitrogen ion implantation (dose 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 ), forming an N-type carrier diffusion layer at the corner of the trench, and then removing the hard mask HM2; S5 gate and interlayer dielectric preparation: Gate structure: thermally oxidizing the inner wall of the trench to form a gate dielectric layer (10) with a thickness of 0.05 to 0.1 μm, depositing heavily doped polysilicon and etching back to form a gate electrode (11) 0.05 to 0.1 μm below the silicon carbide plane; Interlayer dielectric and contact hole: depositing non-doped silicon oxide and borophosphosilicate glass (total thickness 0.8 μm) as an interlayer dielectric layer (12), etching the contact hole (13-1) and over-etching silicon carbide to form a second trench (13-2), such as a depth T4 = 0.15 μm and a width W4 = 0.1 μm; S6 metal electrode preparation: Source end metal electrode (14): nickel, titanium, titanium nitride, aluminum-copper alloy is sputtered above the interlayer dielectric, and an electrode is formed by etching, and an ohmic contact is formed with the first conductive type semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second trench (13-2); Drain metal electrode (15): Nickel, titanium, nickel, or silver is sputtered below the drain region to form an electrode, forming an ohmic contact with the semiconductor drain region (1).

[0012] Compared with the prior art, the present invention has the following beneficial effects: In the present invention, by introducing a carrier diffusion layer at the corner of the first trench, electrons on the lead-out side of the semiconductor shielding region can flow directly to the semiconductor drain region along the Z direction without the shielding region, thus avoiding the sacrifice of the shielding region to the conductive channel in the traditional structure. The net impurity concentration of the carrier diffusion layer formed by oblique ion implantation reaches 5×10 15 ~5×10 17 pieces / cm 3, ensuring that the channel resistance is reduced during forward conduction. Combined with the surface area optimization of the second trench, the device's specific on-resistance is significantly reduced compared to traditional silicon carbide trench MOSFETs, significantly improving current conduction efficiency.

[0013] In the present invention, the thickness T1 of the semiconductor shielding region's lead-out end is at least 5% greater than the depth of the first trench, and the width W1 is at least 80% greater than the first trench's width. This wide width W1 effectively prevents depletion during reverse operation, improving the device's short-circuit capability and reliability. A second-conductivity semiconductor shielding region directly below the first trench is formed by high-energy ion implantation to a depth T2.

[0014] In the present invention, the manufacturing process uses a hard mask HM2 protection and a thermal oxidation wet etching process to precisely control the depth of the first trench to at least 0.1μm beyond the semiconductor well region, effectively eliminating amorphization defects at the trench bottom caused by high-energy implantation and preventing abnormal increases in leakage current. The segmented semiconductor shielding region lead-out terminals formed by ion implantation are distributed in stages along the Z direction, short-circuiting the second conductivity type semiconductor shielding region directly below the first trench with the source metal electrode, significantly improving device reliability.

[0015] This invention overcomes the conflict between gate oxide reliability and conductive channel performance in traditional silicon carbide trench devices through the collaborative design of a carrier diffusion layer, segmented shielding region lead-out terminals, and a deep, narrow second trench. Compared to planar MOSFETs, this device offers lower specific on-resistance at the same breakdown voltage. Compared to existing trench structures, it also offers improved short-circuit withstand capability and reduced leakage current, providing a high-performance solution for high-voltage, high-frequency applications (such as new energy vehicles and photovoltaic inverters), and promoting the commercialization of silicon carbide power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic structural diagram of Example 1 of the present application; Figure 2 This is a schematic diagram of the initial structure of Example 1 of the present application; Figure 3 This is a schematic structural diagram of the lead-out terminal of the semiconductor shielding region formed in Example 1 of the present application; Figure 4 This is a schematic structural diagram of forming a semiconductor source region in Example 1 of the present application; Figure 5 This is a schematic structural diagram of a semiconductor shielding region according to embodiment 1 of the present application; Figure 6 This is a schematic structural diagram of a carrier diffusion layer formed in Example 1 of the present application; Figure 7 This is a schematic diagram of forming a gate structure according to Example 1 of the present application; Figure 8 This is a schematic diagram of the structure of the second groove formed in Example 1 of the present application Figure 1 ; Figure 9 This is a schematic diagram of the structure of the second groove formed in Example 1 of the present application Figure 2 ; Figure 10 This is a schematic diagram of the structure of the metal electrode formed in Example 1 of the present application; Figure 11 It is a structural diagram of Example 2 of the present application.

[0017] In the figure, the correspondence between the component names and the figure marks is: 1. semiconductor drain region; 2. semiconductor cache region; 3. semiconductor drift region; 4. second conductive type semiconductor well region; 5. first conductive type semiconductor source region; 6. second conductive type semiconductor body contact region; 7-1. second conductive type semiconductor shielding region lead-out terminal; 8. first trench; 9. first conductive type semiconductor carrier diffusion layer; 10. gate dielectric layer; 7-2. second conductive type semiconductor shielding region; 11. gate electrode; 12. interlayer dielectric layer; 13-1. contact hole; 13-2. second trench; 14. source metal electrode; 15. drain metal electrode. DETAILED DESCRIPTION

[0018] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention. Example 1

[0019] Reference Figure 1-10 The specific structure and manufacturing steps of a silicon carbide trench power device are as follows: 1. Preparation of laminated structure: Semiconductor cache region (2): a first conductive type semiconductor layer is epitaxially grown on the heavily doped first conductive type (N type) semiconductor drain region (1), with a doping concentration of 1×10 18 pieces / cm 3 ~5×10 18 pieces / cm 3 , thickness 0.5μm~1.5μm, as a buffer area; Semiconductor drift region (3): A lightly doped first conductivity type semiconductor layer is grown epitaxially above the buffer region, with a doping concentration of 1×10 15 pieces / cm 3 ~1×10 17 pieces / cm 3 , with a thickness of 3μm~100μm, forming a drift region; 2. Formation of well region and contact region: The second conductive type semiconductor well region (4): is formed at the top of the drift region by multiple aluminum ion implantations (dose 5×10 11 pieces / cm2 ~5×10 13 pieces / cm 2 ), forming a P-type semiconductor well region with a depth of 0.5μm~1.2μm and a doping concentration higher than that of the drift region; The second conductive type semiconductor body contact region (6): at the top of the well region away from the middle position, by high-dose aluminum ion implantation (dose 5×10 14 pieces / cm 2 ~5×10 15 pieces / cm 2 ), forming a heavily doped P-type body contact region; The second conductive type semiconductor shielding region lead-out terminal (7-1): in the middle of the top of the well region, by aluminum ion implantation (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region lead-out terminal distributed in segments along the Z direction, with a thickness T1 = 0.8μm~1.5μm and a width W1 = 0.5μm~3.6μm. The wide W1 can prevent the semiconductor shielding region lead-out terminal from being exhausted during reverse operation, thereby affecting the reliability and short-circuit capability of the device; 3. Formation of the first trench and shielding area: Initial first trench (8): by photolithography and etching process, an initial trench is etched in the middle of the top of the drift region below the semiconductor source region, with a depth T3 = 0.3 μm ~ 0.6 μm and a width of 0.25 μm ~ 2 μm; Second conductive type semiconductor shielding region (7-2): Then, aluminum ions (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region with a depth of T2 = 0.9 μm; 4. Trench optimization and carrier diffusion layer formation: Adjusting the trench depth: covering the hard mask HM2, exposing the bottom of the trench after etching, and then thermally oxidizing and wet etching the amorphous region at the bottom of the trench so that the final depth of the first trench (8) exceeds the well region by 0.1 μm, forming a trench with a depth of 0.6 μm to 1.3 μm; The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique nitrogen ion implantation (dose 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 ), forming an N-type carrier diffusion layer at the corner of the trench, and then removing the hard mask HM2; 5. Preparation of gate and interlayer dielectric: Gate structure: thermally oxidizing the inner wall of the trench to form a gate dielectric layer (10) with a thickness of 0.05 to 0.1 μm, depositing heavily doped polysilicon and etching back to form a gate electrode (11) 0.05 to 0.1 μm below the silicon carbide plane; Interlayer dielectric and contact hole: depositing non-doped silicon oxide and borophosphosilicate glass (total thickness 0.8 μm) as an interlayer dielectric layer (12), etching the contact hole (13-1) and over-etching silicon carbide to form a second trench (13-2), such as a depth T4 = 0.15 μm and a width W4 = 0.1 μm; 6. Metal electrode preparation: Source end metal electrode (14): nickel, titanium, titanium nitride, aluminum-copper alloy is sputtered above the interlayer dielectric, and an electrode is formed by etching, and an ohmic contact is formed with the first conductive type semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second trench (13-2); Drain metal electrode (15): Nickel, titanium, nickel, or silver is sputtered below the drain region to form an electrode, forming an ohmic contact with the semiconductor drain region (1). Example 2

[0020] Reference Figure 11 , which is different from Example 1 in that the semiconductor shielding region lead-out terminal 7-1 is prepared at the following time: After the first trench depth exceeds the depth of the semiconductor well region (e.g., 1.2 μm), a Z-direction segmented window is defined by photoresist, and aluminum ions are implanted at an oblique angle (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming segmented distributed shielding area lead-out ends, and the subsequent process is consistent with Example 1.

[0021] The embodiments of the present invention are presented for purposes of illustration and description and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments are chosen and described in order to better illustrate the principles of the invention and its practical application and to enable those skilled in the art to understand the invention and design various embodiments with various modifications as suited for specific applications.

Claims

1. A silicon carbide trench power device, characterized in that: include: Semiconductor drain region (1): heavily doped first conductivity type semiconductor material; Semiconductor buffer region (2): a first conductive type semiconductor material having a doping concentration second only to that of the semiconductor drain region (1); Semiconductor drift region (3): lightly doped first conductivity type semiconductor material, located above the semiconductor buffer region (2); A second conductive type semiconductor well region (4): having a higher doping concentration than the semiconductor drift region (3) and located at the top of the semiconductor drift region (3); The first conductive type semiconductor source region (5) is heavily doped and is located in the middle of the top of the second conductive type semiconductor well region (4); A second conductive type semiconductor body contact region (6): located at the top of the semiconductor well region (4) and away from the middle; A second conductive type semiconductor shielding region lead-out terminal (7-1) is segmented and arranged in the middle of the upper portion of the semiconductor drift region (3) along the Z direction; A first trench (8): located in the middle of the top of the semiconductor drift region (3), extending from the first conductive type semiconductor source region (5) to the interior of the semiconductor drift region (3); A first conductive type semiconductor carrier diffusion layer (9): adjacent to a corner of the first trench (8); A second conductive type semiconductor shielding region (7-2) is located directly below the first trench (8); Gate dielectric layer (10): covering the inner wall of the first trench (8); Gate electrode (11): located on the gate dielectric layer (10); Interlayer dielectric layer (12): covering the gate electrode (11); A contact hole (13-1) is provided in the interlayer dielectric layer (12), and the bottom of the contact hole is over-etched with silicon carbide to form a second trench (13-2); A source metal electrode (14) forms an ohmic contact with the semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second groove (13-2); Drain metal electrode (15): located below the semiconductor drain region (1) and forming an ohmic contact.

2. A silicon carbide trench power device according to claim 1, characterized in that: The thickness of the second conductive type semiconductor shielding region lead-out end (7-1) is T1, which is at least greater than 5% of the depth of the first trench (8); and the width thereof is W1, which is at least wider than 80% of the first trench (8).

3. The silicon carbide trench power device according to claim 1, wherein: The depth of the second conductive type semiconductor shielding region (7-2) continuously distributed below the first trench is determined by the energy of the high energy ion implantation, and the depth is T2.

4. A silicon carbide trench power device according to claim 1, characterized in that: The initial depth T3 of the first trench (8) is less than the depth of the second conductive type semiconductor well region (4).

5. The silicon carbide trench power device according to claim 1, characterized in that: The first trench (8) is formed by the following steps: Covering the initial first trench (8) with a hard mask HM2 having a thickness T3; The hard mask HM2 is etched to expose the silicon carbide at the bottom of the trench, and then a second conductive type semiconductor shielding region (7-2) with a depth of T2 is formed at the bottom of the initial first trench by high-energy ion implantation. Considering that high-energy particles will cause the bottom of the initial first trench to become amorphous, thermal oxidation is performed, and then the oxide layer, i.e., the amorphous region at the bottom of the trench, is removed by wet etching, so that the depth of the first trench (8) is finally made to exceed the depth of the second conductive type semiconductor well region (4) by more than 0.1 μm.

6. The silicon carbide trench power device according to claim 1, characterized in that: The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique angle ion implantation in the semiconductor region at the corner of the first trench (8), and its net impurity doping concentration can be 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 .

7. The silicon carbide trench power device according to claim 1, characterized in that: The depth T4 of the second trench (13-2) may be 0.15 μm, and the width W4 may be 0.1 μm, and the surface area thereof increases as T4 increases and W4 decreases, thereby reducing the ohmic contact resistance.

8. A method for manufacturing a silicon carbide trench power device according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1 stacked structure preparation: Semiconductor cache region (2): a first conductive type semiconductor layer is epitaxially grown on the heavily doped first conductive type (N type) semiconductor drain region (1), with a doping concentration of 1×10 18 pieces / cm 3 ~5×10 18 pieces / cm 3 , thickness 0.5μm~1.5μm, as a buffer area; Semiconductor drift region (3): A lightly doped first conductivity type semiconductor layer is grown epitaxially above the buffer region, with a doping concentration of 1×10 15 pieces / cm 3 ~1×10 17 pieces / cm 3 , with a thickness of 3μm~100μm, forming a drift region; S2 well region and contact region are formed: The second conductive type semiconductor well region (4): is formed at the top of the drift region by multiple aluminum ion implantations (dose 5×10 11 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type semiconductor well region with a depth of 0.5μm~1.2μm and a doping concentration higher than that of the drift region; The second conductive type semiconductor body contact region (6): at the top of the well region away from the middle position, by high-dose aluminum ion implantation (dose 5×10 14 pieces / cm 2 ~5×10 15 pieces / cm 2 ), forming a heavily doped P-type body contact region; The second conductive type semiconductor shielding region lead-out terminal (7-1): in the middle of the top of the well region, by aluminum ion implantation (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region lead-out terminal distributed in segments along the Z direction, with a thickness T1 = 0.8μm~1.5μm and a width W1 = 0.5μm~3.6μm. The wide W1 can prevent the semiconductor shielding region lead-out terminal from being exhausted during reverse operation, thereby affecting the reliability and short-circuit capability of the device; S3 first trench and shielding area are formed: Initial first trench (8): by photolithography and etching process, an initial trench is etched in the middle of the top of the drift region below the semiconductor source region, with a depth T3 = 0.3 μm ~ 0.6 μm and a width of 0.25 μm ~ 2 μm; Second conductive type semiconductor shielding region (7-2): Then, aluminum ions (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region with a depth of T2 = 0.9 μm; S4 trench optimization and carrier diffusion layer formation: Adjusting the trench depth: covering the hard mask HM2, exposing the bottom of the trench after etching, and then thermally oxidizing and wet etching the amorphous region at the bottom of the trench so that the final depth of the first trench (8) exceeds the well region by 0.1 μm, forming a trench with a depth of 0.6 μm to 1.3 μm; The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique nitrogen ion implantation (dose 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 ), forming an N-type carrier diffusion layer at the corner of the trench, and then removing the hard mask HM2; S5 gate and interlayer dielectric preparation: Gate structure: thermally oxidizing the inner wall of the trench to form a gate dielectric layer (10) with a thickness of 0.05 to 0.1 μm, depositing heavily doped polysilicon and etching back to form a gate electrode (11) 0.05 to 0.1 μm below the silicon carbide plane; Interlayer dielectric and contact hole: depositing non-doped silicon oxide and borophosphosilicate glass (total thickness 0.8 μm) as an interlayer dielectric layer (12), etching the contact hole (13-1) and over-etching silicon carbide to form a second trench (13-2), such as a depth T4 = 0.15 μm and a width W4 = 0.1 μm; S6 metal electrode preparation: Source end metal electrode (14): nickel, titanium, titanium nitride, aluminum-copper alloy is sputtered above the interlayer dielectric, and an electrode is formed by etching, and an ohmic contact is formed with the first conductive type semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second trench (13-2); Drain metal electrode (15): Nickel, titanium, nickel, and silver are sputtered below the drain region to form an electrode, forming an ohmic contact with the semiconductor drain region (1).

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