Semiconductor structure and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method can comprise the following steps: providing a substrate, the substrate comprising an SGT device region and a BCD device region arranged transversely, the conductive types of the SGT device region and the BCD device region being different; forming a plurality of deep grooves in the SGT device region and the BCD device region; performing gate material filling on the plurality of deep grooves to form a first voltage-resistant gate structure of the SGT device region and at least one gate filling structure, and a second voltage-resistant gate structure of the BCD device region, the first voltage-resistant gate structure being adjacent to the BCD device region; forming a shielding gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, the shallow trench isolation structures being located between the first voltage-resistant gate structure and the second voltage-resistant gate structure. The application can reduce the process cost of SGT and BCD device integration and simplify device connection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Power transistor devices and BCD (Bipolar CMOS DMOS) devices are two common semiconductor power devices. The former is mainly applied to the field of power electronics for controlling and processing large current, high voltage and other electrical signals. For example, a new type of power semiconductor device SGT MOSFET (Shielded Gate Trench MOSFET) can significantly reduce the chip area by setting a longitudinal structure, and ensure the withstand voltage performance by setting a longitudinal field oxide layer, and at the same time, the concentration of the drift region is improved, thereby reducing the on-resistance of the device. The BCD device is a device that integrates bipolar transistors, CMOS devices and DMOS devices on one chip, which combines the high transconductance, strong load driving capability of bipolar transistors, the high integration, low power consumption characteristics of CMOS devices, and the high voltage and large current driving advantages of DMOS devices, and is widely used in various fields.

[0003] In the related art, power transistor devices and BCD devices are usually integrated on different chips and connected and communicated through pins and the like. Although this method can realize the functions of the two types of devices, it has the disadvantages of a large number of pins, complex connection, large space occupation and the like. In order to reduce the number of pins and simplify the connection, the related art attempts to integrate the power transistor device and the BCD device on the same chip, such as continuing to superimpose the manufacturing process of the power transistor device on the substrate on which the BCD device has been formed, to realize the integration of the two types of power devices, but the manufacturing process of this scheme is complex and the cost is high. SUMMARY

[0004] To solve the above technical problems, in one aspect, the present application discloses a preparation method of a semiconductor structure, comprising:

[0005] providing a substrate, the substrate comprising an SGT device region and a BCD device region arranged transversely, the SGT device region and the BCD device region being different in conductivity type;

[0006] forming a plurality of deep trenches in the SGT device region and the BCD device region;

[0007] filling the plurality of deep trenches with gate material to form a first voltage-resistant gate structure of the SGT device region and at least one gate filling structure, and a second voltage-resistant gate structure of the BCD device region, the first voltage-resistant gate structure being adjacent to the BCD device region.

[0008] forming a shield gate structure based on the at least one gate fill structure;

[0009] forming a plurality of spaced-apart shallow trench isolation structures in the BCD device region, the shallow trench isolation structures being located between the first voltage withstanding gate structure and the second voltage withstanding gate structure.

[0010] In a possible implementation, the filling the plurality of deep trenches with gate material to form the first voltage withstanding gate structure of the SGT device region, the at least one gate fill structure, and the second voltage withstanding gate structure of the BCD device region comprises:

[0011] forming a first oxide layer on the sidewall of the deep trench and the substrate surface;

[0012] depositing a gate material to form a first gate material layer filling the deep trench and covering the first oxide layer;

[0013] thinning the first gate material layer to expose the first oxide layer of the substrate surface, so as to obtain the first voltage withstanding gate structure, the at least one gate fill structure, and the second voltage withstanding gate structure being isolated by the first oxide layer.

[0014] In a possible implementation, the thinning the first gate material layer to expose the first oxide layer of the substrate surface comprises:

[0015] thinning the first gate material layer to expose the first oxide layer of the substrate surface based on a chemical mechanical planarization process, and continuing to thin the first oxide layer of the substrate surface to a first thickness.

[0016] In a possible implementation, the forming a shield gate structure based on the at least one gate fill structure comprises:

[0017] shielding the first voltage withstanding gate structure and the second voltage withstanding gate structure;

[0018] performing etch-back processing on each of the gate fill structures based on an etch-back process to obtain a shield gate electrode, and forming an isolation oxide layer covering at least an exposed surface of the shield gate electrode, the isolation oxide layer being continuous with the first oxide layer;

[0019] forming a control gate above the shield gate electrode based on a gate material backfilling process, the shield gate electrode and the control gate being isolated by the isolation oxide layer and the first oxide layer.

[0020] In a possible implementation, the shield gate structure includes a first shield gate structure and a second shield gate structure; the etching back process is performed on each of the gate filling structures to obtain shield gates, and an isolation oxide layer is formed to cover at least an exposed surface of the shield gate, including:

[0021] The gate filling structures are etched back to form shield gates of the first shield gate structure and initial shield gates corresponding to the second shield gate structure;

[0022] The shield gates of the first shield gate structure are shielded, and the exposed part of the first oxide layer is removed to expose an unshielded substrate surface, a part of the deep trench sidewall corresponding to the second shield gate structure, and a part of the initial shield gate;

[0023] The exposed part of the initial shield gate, the exposed deep trench sidewall, and the exposed substrate surface are subjected to an oxidation process to form the isolation oxide layer and shield gates of the second shield gate structure.

[0024] In a possible implementation, the gate material backfill process includes:

[0025] A gate material is deposited to form a second gate material layer filling the etched back deep trench and covering the substrate surface;

[0026] The second gate material layer is thinned to a second thickness;

[0027] The thinned second gate material layer is etched to expose the first oxide layer and the isolation oxide layer of the substrate surface to obtain a control gate above the shield gate.

[0028] In a possible implementation, the forming of the plurality of spaced shallow trench isolation structures in the BCD device region includes:

[0029] A second oxide layer is formed to cover at least the shield gate structure;

[0030] A plurality of spaced shallow trenches are formed in the BCD region based on a patterning process;

[0031] The shallow trenches are filled with an isolation material to form the plurality of spaced shallow trench isolation structures.

[0032] In a possible implementation, the forming of the second oxide layer to cover at least the shield gate structure includes:

[0033] An oxide layer material is deposited to form a second oxide layer covering the shield gate structure, the first voltage-resistant gate structure, the second voltage-resistant gate structure, and the substrate surface.

[0034] In a possible implementation, the forming the second oxide layer covering at least the shield gate structure comprises:

[0035] The second oxide layer covering at least the control gate of the shield gate structure is formed by a surface oxidation process, and the second oxide layer is continuous with the first oxide layer and the isolation oxide layer respectively.

[0036] In a possible implementation, after the forming the plurality of spaced-apart shallow trench isolation structures in the BCD device region, the preparation method further comprises:

[0037] The doping structures are formed in the SGT device region and the BCD device region based on an ion implantation process, and at least part of the doping structures in the SGT device region and at least part of the doping structures in the BCD device region are formed in a same ion implantation process.

[0038] In a possible implementation, before the filling the plurality of deep trenches with a gate material, the preparation method further comprises:

[0039] The deep trenches are subjected to a thermal oxidation process to form a sacrificial oxide layer on the sidewalls of the deep trenches;

[0040] The sacrificial oxide layer is removed to expose the sidewalls of the deep trenches, and the filling the plurality of deep trenches with a gate material is performed.

[0041] In another aspect, the present application discloses a semiconductor structure, comprising:

[0042] A substrate comprising a SGT device region and a BCD device region arranged laterally, and the SGT device region and the BCD device region are of different conductivity types;

[0043] A plurality of deep trenches distributed in the SGT device region and the BCD device region;

[0044] A first voltage-resisting gate structure in the deep trench of the SGT device region;

[0045] At least one shield gate structure in the deep trench of the SGT device region;

[0046] A second voltage-resisting gate structure in the deep trench of the BCD device region;

[0047] A plurality of shallow trench isolation structures in the BCD device region and arranged spaced-apart, and the shallow trench isolation structures are located between the first voltage-resisting gate structure and the second voltage-resisting gate structure.

[0048] In a possible implementation, the shielding gate structure comprises a control gate and a shielding gate, the control gate and the shielding gate are separated by a continuous first oxide layer and an isolation oxide layer, the first oxide layer is located on a part of the groove wall of the deep trench, the isolation oxide layer is located on a part of the groove wall of the deep trench, and is located between the control gate and the shielding gate.

[0049] In a possible implementation, the semiconductor structure further comprises:

[0050] a second oxide layer covering at least the shielding gate structure; the second oxide layer is a deposition layer or an oxide layer formed by an oxidation process on the shielding gate structure.

[0051] In another aspect, the application discloses an integrated circuit comprising the semiconductor structure.

[0052] In another aspect, the application discloses an electronic device comprising the semiconductor structure.

[0053] Based on the above technical solutions, the application has the following beneficial effects:

[0054] The technical scheme of the application arranges the SGT device area and the BCD device area with different conductive types in the substrate, so as to facilitate the modular integration of the SGT device and the BCD device, and provide a structural basis for internal communication connection between the modules, not only reducing the number of pins and simplifying the connection, but also saving the chip space, improving the integration, reliability and stability of the integrated circuit. In the device integration preparation process, a plurality of deep trenches are formed in the SGT device area and the BCD device area, and the plurality of deep trenches are filled with gate materials to form a first voltage-resistant gate structure of the SGT device area and at least one gate filling structure, and a second voltage-resistant gate structure of the BCD device area, and then a shielding gate structure is formed based on the at least one gate filling structure, which can form the required gate filling structure in the two device areas through one-time trench etching and filling on the basis of the modularization of the SGT device and the BCD device, so as to facilitate the subsequent gate preparation, not only without increasing additional complex processes, but also integrating the common processes of the two devices, further simplifying the process and reducing the preparation cost. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0056] Figure 1A flowchart of a method for manufacturing a semiconductor structure is provided in the embodiments of the present application;

[0057] Figures 2-19 A cross-sectional view of a semiconductor structure during manufacturing is provided in the embodiments of the present application;

[0058] Figure 20 A cross-sectional view of a semiconductor structure is provided in the embodiments of the present application;

[0059] Figure 21 A cross-sectional view of another semiconductor structure is provided in the embodiments of the present application;

[0060] The following is a supplementary description of the drawings:

[0061] 100 - substrate, 101 - SGT device region, 102 - BCD device region, 103 - epitaxial layer, 104 - substrate layer, 201 - first mask layer, 201a - pad oxide layer, 201b - hard mask layer, 202 - deep trench, 203 - sacrificial oxide layer, 204 - first oxide layer, 205 - first gate material layer, 206 - first voltage-resistant gate structure, 207 - gate filling structure, 208 - second voltage-resistant gate structure, 209 - shielding gate structure, 209a - first shielding gate structure, 209b - second shielding gate structure, 210 - shielding gate, 211 - control gate, 212 - isolation oxide layer, 213 - initial shielding gate, 214 - second gate material layer, 215 - second oxide layer, 216 - photoresist layer, 217 - annular interval, 301 - shallow trench, 302 - shallow trench isolation structure, 303 - second mask layer, 401 - doped structure. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0063] The terms "one embodiment" or "an embodiment" as may be used herein as referring to a particular feature, structure, or characteristic, can be understood as referring to an implementation that can include one or more features, structures, or characteristics, but every implementation can not necessarily include the same feature(s), structure(s), or characteristic(s). Additionally, the terms "first," "second," and the like, as can be used herein for purposes of description, can not necessarily have an actual chronological or relative meaning unless specifically stated otherwise. The terms "first," "second," and the like, as can be used herein for purposes of description, can not necessarily have an actual chronological or relative meaning unless specifically stated otherwise. Thus, a feature, structure, or characteristic described herein as being "first" can occur later in time than a feature, structure, or characteristic described herein as being "second," unless specifically stated otherwise. Furthermore, the terms "comprise," "include," "have," and / or "contain" as can be used herein, can be used in reference to a non-exclusive inclusion, meaning that a process, method, article, or apparatus that comprises, includes, has, and / or contains an element or a plurality of elements, can also comprise, include, have, and / or contain other elements, whether related or unrelated, not specifically listed. Thus, these terms, as can be used herein, can be used in their broadest, normal sense, unless specifically stated otherwise.

[0064] When a range of values is disclosed, unless otherwise stated, the endpoints of the ranges are included. Further, the range is inclusive of the minimum and maximum values, unless otherwise stated. Additionally, one or more ranges can be combined, unless otherwise stated. It is also understood that every range and / or value given herein can be extended by "about" the recited value or range, unless otherwise stated. Accordingly, it is understood that the application encompasses one or more ranges of values that are "about" one or more of the recited values or ranges. For example, a range of "1 to 10" is understood to include one or more ranges of values that are "about" one or more of the recited values or ranges, e.g., "about 1 to about 10," unless otherwise stated. An exemplary range of values that is "about" one or more of the recited values or ranges includes values that are within experimental error or within technical precision, of the recited values or ranges. Further, it is understood that every range and / or value given herein can be doubled, tripled, quadrupled, etc., unless otherwise stated. For example, a range of "1 to 10" is understood to include one or more ranges of values that are double, triple, quadruple, etc., of the recited values or ranges, e.g., "2 to 20," "3 to 30," "4 to 40," etc., unless otherwise stated.

[0065] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can extend over only a portion thereof. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between, or between any pair of horizontal planes within, a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a contoured surface. A layer can include multiple layers. For example, a substrate can include multiple sub-layers, etc., and can have the same or different materials.

[0066] It should be understood that the terms "substantially uniform," "substantially vertical," etc., as used herein, are intended to refer to a substantially uniform or substantially vertical, etc., within process error, and are not intended to refer to absolute uniformity or absolute verticality in a physical sense.

[0067] It should be understood that, as used in this application, "surface", such as "first surface", "second surface", etc. refers to the XY plane of a substrate or a base structure, etc. corresponding to the XY plane of a semiconductor structure, "in-plane direction", "lateral direction" refers to a direction parallel to the XY plane, and "thickness direction", "trench depth direction" or "longitudinal direction" refers to the Z direction relative to the XY plane.

[0068] The following description is provided in connection with Figures 1-21 The preparation method of the semiconductor structure provided in the embodiments of the present application is introduced, Figure 1 is a flowchart of the preparation method of the semiconductor structure. The present specification provides method operation steps such as embodiments or flowcharts, but more or fewer operation steps can be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one of the many execution orders of the steps, and does not represent the only execution order. In actual preparation method execution, the method order shown in the embodiments or the drawings can be executed or executed in parallel. The preparation method can include S11-S15:

[0069] S11: providing a substrate 100, the substrate 100 including laterally arranged SGT device regions 101 and BCD device regions 102, the conductive types of the SGT device regions 101 and the BCD device regions 102 being different.

[0070] Specifically, the substrate 100 is a semiconductor base capable of semiconductor device processing. Exemplarily, the constituent material of the substrate 100 can be at least one of silicon, a material containing silicon (such as a III-V compound semiconductor material of gallium arsenide (GaAs)), at least one of silicon on insulator (SOI), or other types of semiconductor materials capable of forming the substrate 100.

[0071] In a possible implementation, the substrate 100 can be a continuous structure, such as a wafer substrate, or can also include a substrate layer 104 and an epitaxial layer 103, which can be formed by an epitaxial growth process, and can be a homo-epitaxial layer 103 that can continue to grow along the lattice direction of the substrate layer 104, or can be a hetero-epitaxial layer 103, and the process conditions such as growth temperature can be the same as the existing process or can be adjusted as appropriate. Alternatively, the epitaxial layer 103 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. For example, the material of the epitaxial layer 103 can include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), or other materials that can be epitaxially grown or deposited on the substrate layer 104 and can be processed in the device region. In a possible implementation, referring to Figure 2 , the SGT device region 101 and the BCD device region 102 can be formed in the epitaxial layer 103.

[0072] Specifically, the SGT device region 101 is a substrate region for forming an SGT device and has a first conductivity type, and the BCD device region 102 is a substrate region for forming a BCD device and has a second conductivity type. In a possible implementation, the SGT device region 101 is adjacent to the BCD device region 102 to facilitate the preparation of a communication structure between the two devices. In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. For example, the SGT device region 101 is an N-type deep well region, and the BCD device region 102 is a P-type deep well region.

[0073] S12: Forming a plurality of deep trenches 202 in the SGT device region 101 and the BCD device region 102.

[0074] Specifically, referring to Figure 5 , the plurality of deep trenches 202 are laterally distributed in the SGT device region 101 and the BCD device region 102 and are formed based on a patterned etching process. In a possible implementation, a first mask layer 201 is formed on the substrate 100 and spans the SGT device region 101 and the BCD device region 102, the first mask layer 201 is patterned to form an etching window to expose the substrate region corresponding to the deep trenches 202 in the SGT device region 101 and the BCD device region 102, and then the deep trenches 202 are etched with the first mask layer 201 as an etching stop layer to form the plurality of deep trenches 202.

[0075] Specifically, the first mask layer 201 covers at least the active area (AA) of the SGT device region 101 and the active area of the BCD device region 102. In a possible implementation, referring to Figure 3 The first mask layer 201 includes a pad oxide layer 201a on the surface of the substrate and a hard mask layer 201b on the pad oxide layer 201a. The pad oxide layer 201a is used to isolate and protect the surface of the substrate, so as to avoid contamination of the surface of the substrate and reduce the stress of the hard mask layer 201b. The pad oxide layer 201a can be formed on the substrate 100 by thermal oxidation or deposition process. Optionally, the material of the pad oxide layer 201a can include, but is not limited to, silicon dioxide and the like. The hard mask layer 201b can be used for pattern transfer and improving the accuracy of the patterning etching, and can be formed by a deposition process. Optionally, the material of the hard mask layer 201b can include at least one of silicon nitride, titanium nitride, silicon dioxide and the like, or can be other materials capable of achieving pattern transfer. In one embodiment, the pad oxide layer 201a is a silicon oxide layer formed by thermal oxidation, and the hard mask layer 201b is a deposited silicon dioxide layer.

[0076] Optionally, the deposition process can be implemented by a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPECVD), subatmospheric chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other types of chemical vapor deposition processes.

[0077] Specifically, the patterning process of the first mask layer 201 can specifically include: coating photoresist on the first mask layer 201, and performing patterned exposure on the photoresist, taking the patterned photoresist as an etching stop layer, and etching the first mask layer 201 to form an etching window. Optionally, the deep trench 202 etching can be implemented by a wet etching process, such as using phosphoric acid as an etching solution for wet etching, or can be implemented by a dry etching process, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, laser ablation, such as plasma etching by a mixed gas of C4F8 and O2.

[0078] It can be understood that the plurality of deep trenches 202 of the SGT device region 101 and the BCD device region 102 can be formed at one time in the same etching process, so as to integrate the trench etching steps of the two devices and reduce the process cost. Alternatively, in the case that the deep trenches 202 corresponding to the shield gate structure 209 and the deep trenches 202 corresponding to the voltage resistance gate structures (the first voltage resistance gate structure 206 and the second voltage resistance gate structure 208) are different in size, the deep trenches 202 of the shield gate structure 209 and the deep trenches 202 of the voltage resistance gate structure can be formed based on different patterned etching processes, such as forming the deep trenches 202 of the shield gate structure 209 first, and then forming the deep trenches 202 of the voltage resistance gate structure.

[0079] In a possible implementation, the width of the deep trench 202 of the shield gate structure 209 is 0.4 μm-0.6 μm, and preferably 0.5 μm.

[0080] S13: performing gate material filling on the plurality of deep trenches 202 to form the first voltage resistance gate structure 206 and at least one gate filling structure 207 of the SGT device region 101, and the second voltage resistance gate structure 208 of the BCD device region 102, the first voltage resistance gate structure 206 being adjacent to the BCD device region 102.

[0081] Specifically, after the plurality of deep trenches 202 are formed, the first mask layer 201 is removed, and gate material filling is performed on each deep trench 202, and the gate materials in each deep trench 202 are isolated from each other. Referring to Figure 8 The first voltage resistance gate structure 206 is located between each gate filling structure 207 and the BCD device region 102, and is arranged adjacent to the BCD device region 102, and the gate filling structure 207 is used to form the shield gate structure 209. The second voltage resistance gate structure 208 is located in the BCD device region 102, and an active region of the BCD device is arranged between the first voltage resistance gate structure 206 and the second voltage resistance gate structure 208.

[0082] In a possible implementation, referring to Figure 4 Before S13, the preparation method further includes S21-S22:

[0083] S21: performing thermal oxidation treatment on the deep trench 202 to form a sacrificial oxide layer 203 located on the sidewall of the deep trench;

[0084] S22: removing the sacrificial oxide layer 203 to expose the sidewall of the deep trench 202, and performing the step of filling gate material on the plurality of deep trenches 202 in S13.

[0085] Specifically, before removing the first mask layer 201, the exposed deep trench walls can be thermally oxidized to oxidize the base material into a sacrificial oxide layer 203 of a certain thickness. The sacrificial oxide layer 203 is then removed by wet or dry etching, allowing subsequent gate structure fabrication to proceed. The process steps of forming and removing the sacrificial oxide layer 203 can remove trench wall defects formed during the etching of the deep trench 202, flattening the trench walls and facilitating subsequent gate structure fabrication.

[0086] In a possible implementation, reference Figures 6-8 , S13 may specifically include S131-S133:

[0087] S131: forming a first oxide layer 204 on the wall of the deep trench 202 and the surface of the substrate;

[0088] S132: depositing a gate material to form a first gate material layer 205 filling the deep trench 202 and covering the first oxide layer 204;

[0089] S133 : thinning the first gate material layer 205 to expose the first oxide layer 204 on the substrate surface, thereby obtaining a first voltage-resistant gate structure 206 , a gate filling structure 207 , and a second voltage-resistant gate structure 208 isolated by the first oxide layer 204 .

[0090] Specifically, the first oxide layer 204 may be formed based on a deposition process, referring to Figure 6 The first oxide layer 204 is a continuous film layer covering the deep trench wall, the substrate surface of the SGT device area 101 and the substrate surface of the BCD device area 102, and part of it can be used as the field oxide layer of the SGT device. The material of the first oxide layer 204 can be, but is not limited to, silicon dioxide. Then, refer to Figure 7 , a gate material is deposited to form a first gate material layer 205 , and the material of the first gate material layer 205 may include but is not limited to polysilicon.

[0091] Specifically, the first gate material layer 205 covering the substrate surface can be chemically mechanically planarized to remove the gate material covering the first oxide layer 204, thereby obtaining a first voltage-resistant gate structure 206, a gate filling structure 207 and a second voltage-resistant gate structure 208 that are isolated from each other and flush with the first oxide layer 204.

[0092] In some embodiments, reference Figure 8 , the first gate material layer 205 is thinned with the first oxide layer 204 as a stop layer, that is, the thinning is stopped after the first oxide layer 204 is exposed. In other embodiments, referring to Figure 9S133 can specifically include S1331: thinning the first gate material layer 205 based on a chemical mechanical planarization process to expose the first oxide layer 204 of the substrate surface, and continue to thin the first oxide layer 204 of the substrate surface to a first thickness, so as to reduce the oxide layer thickness of the substrate surface, thereby reducing the step difference of the first voltage-resistant gate structure 206, the second voltage-resistant gate structure 208 and other device regions in subsequent preparation process, and planarizing the surface of the SGT device region 101 and the BCD device region 102. In one embodiment, the first oxide layer 204 can be thinned to half of the original thickness. In one embodiment, the first thickness can be 900-1200A.

[0093] S14: forming a shield gate structure 209 based on the at least one gate filling structure 207.

[0094] Specifically, referring to Figure 16 , the shield gate structure 209 specifically includes a control gate 211 located at the top of the trench and a shield gate 210 located at the bottom of the trench, the control gate 211 is used to control the on-off of the channel of the SGT device, and the shield gate 210 is used to adjust the electric field distribution in the channel.

[0095] In a possible implementation manner, referring to Figures 10-16 , S14 can include S141-S143:

[0096] S141: shielding the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208;

[0097] S142: performing etch-back processing on each gate filling structure 207 based on an etch-back process to obtain the shield gate 210, and forming an isolation oxide layer 212 covering at least the exposed surface of the shield gate 210, the isolation oxide layer 212 being continuous with the first oxide layer 204;

[0098] S143: forming the control gate 211 above the shield gate 210 based on a gate material backfilling process, and the shield gate 210 and the control gate 211 are isolated by the isolation oxide layer 212 and the first oxide layer 204.

[0099] Specifically, referring to Figure 10The first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208 are shielded by the photoresist layer 216, and the photoresist layer is coated on the substrate surface, and the photoresist layer is exposed except the area of the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208, so as to expose the gate filling structure 207 and the substrate surface. Then, the gate filling structure 207 is etched back to remove part of the gate filling structure 207, and the remaining part of the gate filling structure 207 is used as the shielding gate 210. The etching back depth is determined based on the trench structure and the electric field distribution of the SGT device. Optionally, the etching back process can be implemented by wet etching or dry etching. The wet etching can be acid etching, and the dry etching can be plasma etching.

[0100] Specifically, referring to Figure 16 The isolation oxide layer 212 is formed on the exposed surface of the shielding gate 210, and is used to isolate the shielding gate 210 and the control gate 211. The isolation oxide layer 212 can be formed by oxide deposition or thermal oxidation process. Preferably, referring to Figure 13 The shielding gate 210 is subjected to thermal oxidation process to form the isolation oxide layer 212 in situ and continuously with the first oxide layer 204, without additional patterning and shielding, and the problem of over-thick oxide layer caused by oxide deposition is avoided. The isolation oxide layer 212 and the first oxide layer 204 form a continuous film layer to cover the shielding gate 210, the deep trench wall and the surface of the active region, so as to isolate the shielding gate 210 and avoid the adverse effect of film stress, and protect the active region of the substrate 100.

[0101] In a possible implementation, after the shielding gate 210 is formed, referring to Figure 12 and Figure 13 The photoresist layer 216 shielding the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208 is removed, and then the oxide deposition and / or thermal oxidation process is performed, so that the surface of the shielding gate 210 forms the isolation oxide layer 212, and the surface of the first voltage-resistant gate structure 206 and the surface of the second voltage-resistant gate structure 208 also form an oxide layer covering, so as to simplify the process.

[0102] Then, after the isolation oxide layer 212 is formed, the gate material is backfilled by a deposition process to obtain the control gate 211 filling the deep trench 202 and being electrically isolated from the shielding gate 210. The backfilled gate material can include but is not limited to polysilicon and the like. In a possible implementation, referring to Figures 14-16 S143 can specifically include: depositing a gate material to form a second gate material layer 214 filling the etched-back deep trench 202 and covering the substrate surface; thinning the second gate material layer 214 to a second thickness; etching the thinned second gate material layer 214 to expose the first oxide layer 204 and the isolation oxide layer 212 of the substrate surface, so as to obtain the control gate 211 above the shielding gate 210.

[0103] Specifically, the deposition process of the gate material can include, but is not limited to, plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. The backfilling depth exceeds the depth of the deep trench 202 to form a second gate material layer 214 covering the first oxide layer 204, and the thickness of the second gate material layer 214 is set based on process requirements. Then, the second gate material layer 214 is thinned to a second thickness based on a chemical mechanical polishing process, so as to facilitate the back-etching of the gate material. Then, the thinned second gate material layer 214 is back-etched based on wet etching or dry etching, so as to remove the gate material on the surface of the substrate and expose the oxide layer on the surface of the substrate, and the gate material remaining in the deep trench 202 forms a control gate 211 of the shield gate structure 209. Each control gate 211, the control gate 211 and the shield gate 210, and the control gate 211 and the substrate 100 are isolated by the first oxide layer 204 and the isolation oxide layer 212. In this way, by depositing a second gate material layer 214 of a certain thickness and then thinning, the planarization of the second gate material layer 214 is achieved before etching, so as to facilitate the control of etching precision and ensure the control precision of the control gate 211. In one embodiment, the second thickness can be 800-1100A, and preferably 1000A.

[0104] In some embodiments, the control gate 211 and the shield gate 210 of each shield gate structure 209 are structurally identical to each other (not shown), and the shield gate 210 of each shield gate structure 209 is formed at one time in the back-etching process of the gate filling structure 207, and the isolation oxide layer 212 covers the surface of each shield gate 210. Accordingly, S142 can specifically include: back-etching each gate filling structure 207 to form the shield gate 210 of each shield gate structure 209; removing the shielding layer on the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208, and performing oxidation treatment on the surface of the shield gate 210, the surface of the first voltage-resistant gate structure 206, and the surface of the second voltage-resistant gate structure 208 to form the isolation oxide layer 212. It can be understood that the isolation oxide layer 212 formed in this embodiment serves as a gate oxide layer between the shield gate 210 and the control gate 211, and at least part of the first oxide layer 204 serves as a field oxide layer.

[0105] In other embodiments, referring to Figure 16 , the shield gate structure 209 includes a first shield gate structure 209a and a second shield gate structure 209b, and the control gate 211 and the shield gate 210 of the first shield gate structure 209a are structurally different from the control gate 211 and the shield gate 210 of the second shield gate structure 209b; accordingly, referring to Figures 11-16S142 can specifically include: etching back each gate filling structure 207 to form an initial shielding gate 213 corresponding to the shielding gate 210 of the first shielding gate structure 209a and the second shielding gate structure 209b; referring to Figures 11-12 shielding the shielding gate 210 of the first shielding gate structure 209a and removing the exposed part of the first oxide layer 204 to expose the unshielded substrate surface, the part of the deep trench sidewall corresponding to the second shielding gate structure 209b and the part of the initial shielding gate 213; referring to Figure 13 performing oxidation treatment on the exposed part of the initial shielding gate 213, the exposed deep trench sidewall and the exposed substrate surface to form the isolation oxide layer 212 and the shielding gate 210 of the second shielding gate structure 209b. Understandably, in the embodiment, the area of the isolation oxide layer 212 covering the shielding gate 210 and the deep trench sidewall serves as a gate oxide layer, and the area on the substrate surface serves as a field oxide layer.

[0106] Specifically, the shielding gate 210 of the first shielding gate structure 209a is formed after etching back the gate filling structure 207, and then the photoresist layer 216 formed by photoresist and other materials is used for shielding, so as to remove the first oxide layer 204 exposed on the substrate surface and remove part of the first oxide layer 204 around the initial shielding gate 213 to expose the upper end of the initial shielding gate 213, as shown in Figure 12 Then, the photoresist layer 216 on the surface of the shielding gate of the first shielding gate structure 209a, the first voltage gate structure 206 and the second voltage gate structure 208 is removed, and the exposed initial shielding gate 213, the deep trench sidewall, the substrate surface, the shielding gate 210, the surface of the first voltage gate structure 206 and the surface of the second voltage gate structure 208 are in-situ oxidized by thermal oxidation treatment to form the isolation oxide layer 212 and the shielding gate 210 of the second shielding gate structure 209b formed after surface oxidation. In this way, the shielding gate 210 with different structures is prepared through a simple etching back, shielding and in-situ oxidation process. In combination with the thinning treatment of the first oxide layer 204 in S1331, the thickness of the first oxide layer 204 remaining after shielding and the thickness of the isolation oxide layer 212 formed by in-situ oxidation of the substrate surface are close, which reduces the thickness of the field oxide while avoiding the step difference of the substrate surface, thereby optimizing the device performance.

[0107] Specifically, referring to Figure 13 and Figure 14 , the isolation oxide layer 212 on the shielding gate 210 of the second shielding gate structure 209b and the isolation oxide layer 212 between the deep trench sidewall have a ring-shaped interval 217 and are continuous with the first oxide layer 204 remaining in the deep trench 202, and the control gate 211 fills the top of the shielding gate 210 and the ring-shaped interval 217 to form a plug structure with the shielding gate 210.

[0108] S15: forming a plurality of spaced shallow trench isolation structures 302 in the BCD device region 102, the shallow trench isolation structures 302 being located between the first voltage-resisting gate structure 206 and the second voltage-resisting gate structure 208.

[0109] Specifically, after forming the first voltage-resisting gate structure 206, the second voltage-resisting gate structure 208 and the shielding gate structure 209 based on the deep trench process, the BCD device region 102 is processed based on the shallow trench process to form a plurality of shallow trench isolation structures 302.

[0110] In summary, by arranging the SGT device region 101 and the BCD device region 102 in the substrate 100 in a transverse arrangement and with different conductive types, the modular integration of the SGT device and the BCD device is facilitated, and a structural basis is provided for internal communication connection between the modules, which not only reduces the number of pins and simplifies the connection, but also saves chip space, improves the integration, reliability and stability of the integrated circuit. In the process of device integration and preparation, a plurality of deep trenches 202 are formed in the SGT device region 101 and the BCD device region 102, and the plurality of deep trenches 202 are filled with gate material to form the first voltage-resisting gate structure 206 and at least one gate filling structure 207 of the SGT device region 101, and the second voltage-resisting gate structure 208 of the BCD device region 102, and then the shielding gate structure 209 is formed based on the at least one gate filling structure 207. On the basis of the modularization of the SGT device and the BCD device, the required gate filling structure 207 in the two device regions can be formed by one-time trench etching and filling, so as to facilitate subsequent gate preparation. Not only does it not increase the additional complex process, but also integrates the common process of the two devices, further simplifies the process and reduces the preparation cost.

[0111] In a possible implementation, referring to Figures 17-20 S15 can specifically include S151-S153:

[0112] S151: forming a second oxide layer 215 covering at least the shielding gate structure 209;

[0113] S152: forming a plurality of spaced shallow trenches 301 in the BCD region based on a patterning process;

[0114] S153: filling the shallow trenches 301 with isolation material to form a plurality of spaced shallow trench isolation structures 302.

[0115] Specifically, the second oxide layer 215 covers the control gate 211 to avoid damage to the control gate 211 in subsequent processes. In some embodiments, referring to Figure 17S151 can include S1511: depositing an oxide layer material to form a second oxide layer 215 covering the shield gate structure 209, the first voltage gate structure 206, the second voltage gate structure 208, and the substrate surface. In this way, the second oxide layer 215 is formed by oxide deposition to achieve gate isolation and protection. Optionally, the deposition process includes, but is not limited to, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. Exemplarily, the HDPCVD can be used to form the second oxide layer 215, and the material of the second oxide layer 215 can include, but is not limited to, silicon dioxide.

[0116] In some embodiments, S151 can include S1512: forming the second oxide layer 215 covering at least the control gate 211 of the shield gate structure 209 by a surface oxidation process, and the second oxide layer 215 is continuous with the first oxide layer 204 and the isolation oxide layer 212, respectively.

[0117] Specifically, the exposed surface of the control gate 211 is thermally oxidized to form the second oxide layer 215 with a desired thickness, avoiding thickening of the oxide layer on the substrate surface, ensuring the ion implantation effect of the subsequent active region, and preventing implantation damage to the control gate 211, thereby avoiding the problem of IGSS (Gate Reverse Current) leakage.

[0118] Specifically, due to the difference between the gate material and the substrate material, the thickness of the second oxide layer 215 formed by thermal oxidation is greater than the thickness of the isolation oxide layer 212 on the substrate surface, achieving a better implantation protection effect. The second oxide layer 215 formed by thermal oxidation of the gate material is an ellipsoid with a convex top surface and / or bottom surface.

[0119] In possible implementations, the thickness of the first oxide layer 204 and the isolation oxide layer 212 on the substrate surface 100 is not higher than a preset thickness, and the preset thickness is 70-130 A, so as to provide isolation protection while improving the ion implantation effect. In preferred embodiments, the thickness of the first oxide layer 204 and the isolation oxide layer 212 on the substrate surface is 70-130 A.

[0120] In possible implementations, the thickness of the isolation oxide layer 212 on the shield gate 210 is higher than 100-130 A, and is preferably higher than 130 A, so as to provide effective isolation protection.

[0121] Specifically, the patterning process of the shallow trench 301 is similar to the patterning process of the aforementioned deep trench 202, and reference can be made to the description of the deep trench 202. Figure 18A second mask layer 303 can be formed on the surface of the substrate, photoresist can be coated on the second mask layer 303, and the photoresist can be patterned to expose part of the second mask layer 303. The etching window of the shallow trench 301 can be formed by etching the second mask layer 303 using the patterned photoresist as an etching stop layer, as shown in FIG. 3B. Optionally, the etching of the shallow trench 301 can be performed by a wet etching process or a dry etching process. The material of the second mask layer 303 can include, but is not limited to, at least one of silicon nitride, titanium nitride, silicon dioxide, etc. In an example, the second mask layer 303 is a silicon nitride layer. Figure 19 The material of the second mask layer 303 can include, but is not limited to, at least one of silicon nitride, titanium nitride, silicon dioxide, etc. In an example, the second mask layer 303 is a silicon nitride layer.

[0122] Specifically, the isolation material filling can be achieved by at least a deposition process, which includes but is not limited to plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. The isolation material can include, but is not limited to, silicon oxide.

[0123] In a possible implementation, referring to Figure 21 After S15, the preparation method further includes S16: forming a doped structure 401 in the SGT device region 101 and the BCD device region 102 based on an ion implantation process, at least part of the doped structure 401 in the SGT device region 101 and at least part of the doped structure 401 in the BCD device region 102 are formed in the same ion implantation process.

[0124] Specifically, the same type of doped structure 401 in the SGT device region 101 and the BCD device region 102 can be formed in the same ion implantation process. In this way, not only the modular integration of the SGT device and the BCD device is achieved, but also the similar process steps of the two types of devices are integrated to simplify the device preparation process and reduce the preparation cost while improving the communication performance. The doped structure 401 can include a well region, as well as a source structure or a drain structure. For example, referring to Figure 21 The P well in the active region of the SGT device and the P well in the active region of the BCD device can be formed in the same ion implantation process, and the N+ well in the active region of the SGT device and the N+ well in the active region of the BCD device can be formed in the same ion implantation process. In one embodiment, the ion implantation process includes at least an ion implantation process and an annealing process. The second oxide layer 215 can not only avoid ion implantation into the gate structure, but also reduce the risk of device damage during the annealing process.

[0125] In some embodiments, the SGT device formed in the SGT device region 101 is an SGT MOSFET, which can further improve the performance of the semiconductor device, reduce the on-resistance, and improve the efficiency and reliability of the device circuit.

[0126] In summary, the above technical solution adopts modular design, integrates SGT devices and BCD devices in the same chip, and performs lateral independent design of different module partitions. The modules can communicate with each other through internal connection, which not only reduces the number of pins, simplifies the connection, but also saves space, improves the integration, reliability and stability of the integrated circuit, and is suitable for multiple fields such as power electronics, communication and computer, and has broad application prospects. Moreover, the integrated manufacturing process of the present application is relatively simple, which not only does not need to increase complex manufacturing steps, but also can integrate common processes such as deep trench 202 etching, gate structure filling and ion implantation, thereby reducing the process complexity and reducing the manufacturing cost. In addition, the semiconductor structure provided by the present application has flexible circuit design, which can be designed and adjusted according to the needs, and has good designability and expandability.

[0127] The embodiment of the present application also provides a semiconductor structure, which is prepared based on the above preparation method. Referring to Figure 20 , the semiconductor structure specifically comprises: a substrate 100, a plurality of deep trenches 202, a first voltage-resistant gate structure 206, at least one shielding gate structure 209, a second voltage-resistant gate structure 208 and a plurality of shallow trench isolation structures 302. The substrate 100 comprises a laterally arranged SGT device region 101 and a BCD device region 102, and the conductive types of the SGT device region 101 and the BCD device region 102 are different; the plurality of deep trenches 202 are distributed in the SGT device region 101 and the BCD device region 102; the first voltage-resistant gate structure 206 is located in the deep trench 202 of the SGT device region 101; the at least one shielding gate structure 209 is located in the deep trench 202 of the SGT device region 101; the second voltage-resistant gate structure 208 is located in the deep trench 202 of the BCD device region 102; and the plurality of shallow trench isolation structures 302 are located in the BCD device region 102 and are arranged at intervals, and the shallow trench isolation structure 302 is located between the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208.

[0128] Specifically, the shielding gate structure 209 is formed based on the gate filling structure 207, and the first voltage-resistant gate structure 206, the second voltage-resistant gate structure 208 and the gate filling structure 207 are formed by filling the gate material in the plurality of deep trenches 202.

[0129] In a possible implementation, the shielding gate structure 209 comprises a control gate 211 and a shielding gate 210, and the control gate 211 and the shielding gate 210 are isolated by a continuous first oxide layer 204 and an isolation oxide layer 212. The first oxide layer 204 is located on part of the groove wall of the deep trench 202, the isolation oxide layer 212 is located on part of the groove wall of the deep trench 202, and is located between the control gate 211 and the shielding gate 210.

[0130] In some embodiments, the isolation oxide layer 212 is formed based on a deposition process. In other embodiments, the isolation oxide layer 212 is formed based on a thermal oxidation process.

[0131] In a possible implementation, the shield gate structure 209 includes a first shield gate structure 209a and a second shield gate structure 209b; the peripheral side of the shield gate 210 and the peripheral side of the control gate 211 of the first shield gate structure 209a are covered by the first oxide layer 204, the top surface of the shield gate 210 and the bottom surface of the control gate 211 are separated by the isolation oxide layer 212, the control gate 211 and the shield gate 210 of the first shield gate structure 209a are oppositely arranged columnar structures; the lower part of the deep trench groove wall where the second shield gate structure 209b is located is covered by the first oxide layer 204, and the upper part is covered by the isolation oxide layer 212; the upper end peripheral side of the shield gate 210 is covered by the isolation oxide layer 212, and the isolation oxide layer 212 on the shield gate 210 and the isolation oxide layer 212 of the deep trench groove wall have annular spacing 217 and are both continuous with the first oxide layer 204 remaining in the deep trench 202, the control gate 211 fills the top of the shield gate 210 and the annular spacing 217, and forms a plug structure with the shield gate 210.

[0132] In a possible implementation, the semiconductor structure further includes a second oxide layer 215, and the second oxide layer 215 covers at least the shield gate structure 209; the second oxide layer 215 is a deposition layer or an oxide layer formed by oxidizing the shield gate structure 209.

[0133] Specifically, the thickness of the second oxide layer 215 formed by thermal oxidation is greater than the thickness of the isolation oxide layer 212 on the surface of the substrate. The second oxide layer 215 formed by thermal oxidation of the gate material is an ellipsoidal shape with a convex top surface and / or a convex bottom surface.

[0134] In a possible implementation, the semiconductor structure further includes a doped structure 401, and the doped structure 401 is formed by ion implantation. Figure 21 At least part of the doped structure 401 of the SGT device region 101 and at least part of the doped structure 401 of the BCD device region 102 are formed in the same ion implantation process.

[0135] It should be noted that the semiconductor structure embodiments of the present application are implemented based on the semiconductor structure preparation method embodiments, and both are based on the same inventive concept.

[0136] The electronic device includes the semiconductor structure and an electronic component connected to the semiconductor structure.

[0137] The electronic device of the embodiments of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a pad, a notebook computer, a game machine, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PlayStation Portable (PSP), and the like, and can also be an intermediate product of any electronic device including the semiconductor structure.

[0138] It should be noted that the above-mentioned embodiments of the present application are in the order of description only, and do not represent the advantages and disadvantages of the embodiments. The above-mentioned embodiments of the present application are described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired result. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In some embodiments, multi-task processing and parallel processing are possible or advantageous.

[0139] Each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0140] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0141] The above-mentioned is only the preferred embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, Comprising: providing a substrate, the substrate comprising laterally arranged SGT device regions and BCD device regions, the SGT device regions and the BCD device regions having different conductivity types; forming a plurality of deep trenches in the SGT device regions and the BCD device regions, the deep trenches having sidewalls and the substrate surface having a first oxide layer; gate material filling the plurality of deep trenches to form a first voltage withstanding gate structure of the SGT device regions and at least one gate filling structure, and a second voltage withstanding gate structure of the BCD device regions, the first voltage withstanding gate structure being adjacent to the BCD device regions; masking the first voltage withstanding gate structure and the second voltage withstanding gate structure; etching back each of the gate filling structures to form a shield gate of a first shield gate structure of the shield gate structures and an initial shield gate corresponding to a second shield gate structure; masking the shield gate of the first shield gate structure and removing exposed portions of the first oxide layer to expose unmasked substrate surface, sidewalls of portions of the deep trenches corresponding to the second shield gate structure and portions of the initial shield gate; oxidizing exposed portions of the initial shield gate, exposed sidewalls of the deep trenches and exposed substrate surface to form an isolation oxide layer and a shield gate of the second shield gate structure, the isolation oxide layer being continuous with the first oxide layer; forming a control gate over the shield gate based on a gate material backfilling process, the shield gate and the control gate being separated by the isolation oxide layer and the first oxide layer; forming a plurality of spaced apart shallow trench isolation structures in the BCD device regions, the shallow trench isolation structures being located between the first voltage withstanding gate structure and the second voltage withstanding gate structure.

2. The production method according to claim 1, characterized by, The gate material filling the plurality of deep trenches to form a first voltage withstanding gate structure of the SGT device regions and at least one gate filling structure, and a second voltage withstanding gate structure of the BCD device regions comprises: forming a first oxide layer on sidewalls of the deep trenches and the substrate surface; depositing a gate material to form a first gate material layer filling the deep trenches and covering the first oxide layer; thinning the first gate material layer to expose the first oxide layer of the substrate surface to obtain the first voltage withstanding gate structure, the gate filling structure and the second voltage withstanding gate structure separated by the first oxide layer.

3. The production method according to claim 2, characterized by, The thinning the first gate material layer to expose the first oxide layer of the substrate surface comprises: thinning the first gate material layer to expose the first oxide layer of the substrate surface based on a chemical mechanical planarization process, and continuing to thin the first oxide layer of the substrate surface to a first thickness.

4. The preparation method according to claim 1, characterized in that The forming a control gate over the shield gate based on a gate material backfilling process comprises: depositing a gate material to form a second gate material layer filling the etched back deep trenches and covering the substrate surface; thinning the second gate material layer to a second thickness; etching the thinned second gate material layer to expose the first oxide layer and the isolation oxide layer of the substrate surface to obtain the control gate over the shield gate.

5. The production method according to any one of claims 1 to 4, characterized by, The forming a plurality of spaced apart shallow trench isolation structures in the BCD device regions comprises: forming a second oxide layer at least covering the shield gate structure; forming a plurality of shallow trenches spaced apart from each other in the BCD device region based on a patterning process; The shallow trenches are filled with an isolation material to form the plurality of shallow trench isolation structures arranged at intervals.

6. The production method according to claim 5, wherein The forming of a second oxide layer at least covering the shield gate structure comprises: An oxide layer material is deposited to form a second oxide layer covering the shielding gate structure, the first voltage-resistant gate structure, the second voltage-resistant gate structure and the surface of the substrate.

7. The preparation method according to claim 5, characterized in that The forming of a second oxide layer at least covering the shield gate structure comprises: A second oxide layer at least covering the control gate of the shielding gate structure is formed by surface oxidation treatment, and the second oxide layer is continuous with the first oxide layer and the isolation oxide layer.

8. The production method according to any one of claims 1 to 4, characterized by, After forming a plurality of shallow trench isolation structures spaced apart in the BCD device region, the preparation method further includes: Doping structures are formed in the SGT device region and the BCD device region based on an ion implantation process. At least a portion of the doping structure in the SGT device region and at least a portion of the doping structure in the BCD device region are formed in the same ion implantation process.

9. The production method according to any one of claims 1 to 4, characterized by, Before filling the plurality of deep trenches with gate material, the preparation method further comprises: performing thermal oxidation on the deep trench to form a sacrificial oxide layer on the wall of the deep trench; The sacrificial oxide layer is removed to expose the trench walls of the deep trenches, and the step of filling the multiple deep trenches with gate materials is performed.

10. A semiconductor structure produced on the basis of the production method according to any one of claims 1 to 9, characterized in that include: A substrate comprising a laterally arranged SGT device region and a BCD device region, wherein the SGT device region and the BCD device region have different conductivity types; A plurality of deep trenches are distributed in the SGT device area and the BCD device area; A first voltage-resistant gate structure is located in a deep trench of the SGT device region; at least one shield gate structure located in the deep trench of the SGT device region; A second voltage-resistant gate structure is located in the deep trench of the BCD device region; A plurality of shallow trench isolation structures are located in the BCD device region and arranged at intervals, wherein the shallow trench isolation structure is located between the first voltage-resistant gate structure and the second voltage-resistant gate structure.

11. The semiconductor structure of claim 10, wherein, The shielding gate structure includes a control gate and a shielding gate, wherein the control gate and the shielding gate are isolated by a continuous first oxide layer and an isolation oxide layer, wherein the first oxide layer is located on a portion of the trench wall of the deep trench, and the isolation oxide layer is located on a portion of the trench wall of the deep trench and between the control gate and the shielding gate.

12. The semiconductor structure according to claim 10, wherein: The semiconductor structure further comprises: The second oxide layer at least covers the shielding gate structure; the second oxide layer is a deposition layer or an oxide layer formed by oxidizing the shielding gate structure.

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