Solar cell and preparation method thereof
By forming an alignment identification area during the preparation of solar cells and using it to align it, the problems of insufficient alignment accuracy of the electrode connection layer and substrate damage are solved, and efficient and accurate electrode connection and printing are achieved, improving battery performance and conversion efficiency.
Patent Information
- Application Number
- CN202410190770.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-20
- Publication Date
- 2025-08-22
AI Technical Summary
In the existing solar cells, the patterning process of the electrode connection layer has problems such as poor alignment accuracy and laser hole drilling is prone to damage the substrate, which affects the battery performance and conversion efficiency.
After forming the first doped layer on the silicon wafer, laser and alkali-polishing treatment are performed to form an alignment identification area. By aligning the alignment identification area, a second patterning treatment is performed to form an isolation area with good uniformity, and grid-line printing is used for screen printing to avoid damage to the substrate by direct laser drilling.
It improves the alignment accuracy of the electrode connection layer, reduces the risk of leakage, improves printing accuracy and aesthetics, avoids substrate damage, and simplifies the process flow.
Smart Images
Figure CN120529670A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of photovoltaic technology, in particular to a solar cell and a preparation method thereof. Background Art
[0002] In a solar cell, a positive electrode connection layer and a negative electrode connection layer are formed on the back of the cell (the positive and negative electrode connection layers are usually made of polysilicon with opposite doping types). The positive and negative electrode connection layers are distributed in an interdigitated manner, for example, and the positive electrode grid lines and the negative electrode grid lines are formed on the corresponding electrode connection layers. This can reduce optical loss and improve efficiency, thereby improving cell performance and making the cell more aesthetically pleasing.
[0003] The main patterning methods for the electrode connection layer are mask etching and graphic film opening. In the traditional graphic film opening method, the patterning of the positive and negative connection layers uses a camera to capture the edge of the silicon wafer to determine the center of the pattern, but this method has poor positioning accuracy. Between the two patterning processes, due to differences in recognition accuracy and silicon wafer size, the width uniformity of the isolation area between the electrode connection layers is poor. In this way, it is difficult to make the isolation area narrow, which makes the effective area of the electrode connection layer small, limiting the improvement of the solar cell conversion efficiency. In addition, there is also a method of forming an alignment point by laser drilling on the connection layer in the first patterning process, and aligning the second patterning process with the help of the alignment point. However, the alignment point drilling needs to reach a certain depth for easy identification. This method can easily cause the substrate to be damaged by the laser, affecting the battery performance. Summary of the Invention
[0004] Based on this, it is necessary to provide a solar cell and a preparation method thereof to solve the problems of poor alignment accuracy between two patterning processes and easy damage to the substrate by laser drilling.
[0005] One of the objects of the present invention is to provide a method for preparing a solar cell, which is as follows:
[0006] A method for preparing a solar cell comprises the following steps:
[0007] forming a first doped layer on a silicon wafer, wherein the first doped layer comprises a doped polysilicon layer and a doped oxide layer formed on the doped polysilicon layer;
[0008] performing a first patterning process on the first doped layer, the first patterning process comprising removing the doped oxide layer in a local area by laser processing, then removing the doped polysilicon layer in the area by alkali polishing, and simultaneously forming a plurality of alignment identification areas by the laser processing and the alkali polishing;
[0009] forming a second doping layer on the silicon wafer, wherein the second doping layer has a doping type opposite to that of the first doping layer;
[0010] The plurality of alignment identification regions are identified, and the plurality of alignment identification regions are used for alignment, and the second doping layer is subjected to a second patterning process.
[0011] In one embodiment, the silicon wafer includes a single crystal silicon substrate and a tunneling layer disposed on the single crystal silicon substrate, and the first doped layer and the second doped layer are both formed on the tunneling layer.
[0012] In one embodiment, the plurality of alignment identification areas are distributed in a centrally symmetrical manner, with the central point of the pattern of the first patterning being the center of symmetry.
[0013] In one embodiment, identifying the plurality of alignment identification areas, and using the plurality of alignment identification areas for alignment, and performing a second patterning process on the second doped layer, includes the following steps:
[0014] obtaining positions of the plurality of alignment identification areas by an image acquisition device;
[0015] Determine the symmetry center according to the positions of the plurality of alignment identification areas;
[0016] The second patterning process is performed with the symmetry center as a reference point, so that the center of the pattern of the second patterning process overlaps with the symmetry center.
[0017] In one embodiment, a plurality of the alignment identification areas are distributed near the edge of the silicon wafer.
[0018] In one embodiment, the first patterning process uses an image acquisition device to obtain the edge position of the silicon wafer, determine the center position of the silicon wafer, and align the center of the pattern of the first patterning process with the center position of the silicon wafer.
[0019] In one embodiment, the first doped layer forms a first electrode connection layer after the first patterning process, and the second doped layer forms a second electrode connection layer after the second patterning process. The first electrode connection layer and the second electrode connection layer are spaced apart and distributed in an interdigitated manner.
[0020] In one embodiment, the first electrode connection layer includes a first main gate connection portion and a plurality of first fine gate connection portions extending from the first main gate connection portion, the first main gate connection portion includes a first linear region and a plurality of first welding point connection regions, the plurality of first welding point connection regions are connected in series through the first linear region, and the width of the first welding point connection regions is greater than the width of the first linear region;
[0021] The second electrode connection layer includes a second main gate connection portion and a plurality of second fine gate connection portions extending from the second main gate connection portion. The second main gate connection portion includes a second linear region and a plurality of second welding point connection regions. The plurality of second welding point connection regions are connected in series through the second linear region. The width of the second welding point connection region is greater than the width of the second linear region.
[0022] In one embodiment, the preparation method further comprises the following steps:
[0023] Alignment is performed using the plurality of alignment identification areas, and a first gate line is screen-printed on the first electrode connection layer, and a second gate line is screen-printed on the second electrode connection layer.
[0024] In one embodiment, the step of screen printing the first gate line and the second gate line specifically includes:
[0025] Using a first screen to screen-print the fine grid of the first grid line and the fine grid of the second grid line;
[0026] A second screen is used to screen print the main grid of the first grid line and the first welding point thereon, and the main grid of the second grid line and the second welding point thereon.
[0027] In one embodiment, the first screen is used for screen printing first, and then the second screen is used for screen printing.
[0028] In one embodiment, a first correction hole and / or a second correction hole are provided on the first screen, the first correction hole corresponds to the position of the first welding point connection area, and the second correction hole corresponds to the position of the second welding point connection area.
[0029] In one embodiment, the second screen is provided with a third correction hole and / or a fourth correction hole, the third correction hole is located on the main grid of the first grid line, and the fourth correction hole is located on the main grid of the second grid line.
[0030] In one embodiment, the preparation method further comprises the following steps:
[0031] Alignment is performed using the printing dots of the third correction hole and / or the printing dots of the fourth correction hole, and an insulating layer is screen-printed on the main grid of the first gate line and the main grid of the second gate line, wherein the insulating layer exposes the first welding point and the second welding point.
[0032] In one embodiment, the preparation method further comprises the following steps:
[0033] The printed points of the third calibration hole and / or the printed points of the fourth calibration hole are used for alignment, and the welding ribbon is welded to the first welding point and the second welding point.
[0034] Another object of the present invention is to provide a solar cell, which has the following scheme:
[0035] A solar cell is prepared by the preparation method described in any one of the above embodiments.
[0036] Compared with traditional solutions, the above solar cell and its preparation method have the following beneficial effects:
[0037] The above-mentioned preparation method of the solar cell forms a plurality of alignment identification areas on the silicon wafer when the first doped layer is subjected to the first patterning treatment. When the second doped layer is subjected to the second patterning treatment, the alignment identification areas are identified and aligned using the alignment identification areas. This method has high alignment accuracy, which is beneficial for forming an isolation area with good uniformity and small width between the first doped layer and the second doped layer after the patterning treatment, thereby avoiding leakage caused by overlap between the two after the patterning treatment. In the above-mentioned preparation method, when forming the alignment identification area, laser treatment is first performed to effectively remove the doped oxide layer. After the laser treatment, the depth of the alignment identification area is very shallow and difficult to be recognized by the camera. Subsequently, the alignment identification area is made obvious by alkaline polishing treatment so that it can be recognized by the camera. Compared with direct laser drilling, alkaline polishing treatment is not easy to cause damage to the silicon wafer, thereby avoiding reducing the performance of the battery. In summary, the above-mentioned preparation method forms the alignment identification area during the first patterning treatment by selecting a specific process and correlating the selection of specific steps, thereby improving the alignment accuracy between the two patterning treatments. The formed alignment identification area is easy to identify, the process causes little damage to the solar cell, and the overall process flow is efficient and concise.
[0038] Furthermore, the above-mentioned preparation method can improve the printing accuracy of the grid lines by performing position alignment of the silk screen by obtaining multiple alignment identification areas formed during the first patterning process. Furthermore, when the above-mentioned preparation method uses the first screen to screen-print the fine grid, the correction point is designed in the welding point connection area, and the welding point is hidden under the welding point after printing. Moreover, when the second screen is used to screen-print the main grid and welding point, the correction point is designed on the main grid, which effectively improves the aesthetics, camera recognition and printing accuracy, and can also avoid the fine grid offset causing the correction hole to deviate from the junction area and cause conduction leakage. Furthermore, the correction points of the second screen for screen-printing the main grid and welding point provide alignment points for the printing of the insulation layer before the subsequent assembly production and for the string welding during assembly production, which can improve the accuracy of the insulation layer printing and the welding of the welding strip, and further improve the process flow. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 1 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present invention;
[0040] Figure 2 is a schematic diagram of forming a first doping layer on a silicon wafer;
[0041] Figure 3 is a schematic diagram of performing a first patterning process on the first doped layer;
[0042] Figure 4 A local pattern processed by a first patterning process;
[0043] Figure 5 is a schematic diagram of forming a second doping layer on a silicon wafer;
[0044] Figure 6 is a schematic diagram of performing a second patterning process on the second doped layer;
[0045] Figure 7 A local pattern of the first patterning process and the second patterning process;
[0046] Figure 8 A schematic diagram of screen printing a first gate line on a first electrode connection layer and screen printing a second gate line on a second electrode connection layer;
[0047] Figure 9 A schematic diagram of the positional correspondence between the correction holes and the grid lines on the first and second screens;
[0048] Figure 10 Schematic diagram of the design of correction holes for the printing screen in the empty area of the fine grid;
[0049] Figure 11 Schematic diagram of the correction holes designed for the printing screen on the fine grid.
[0050] Description of reference numerals:
[0051] 210, silicon wafer; 211, first region; 212, second region; 220, first doped layer; 221, doped polysilicon layer; 222, doped oxide layer; 230, first electrode connection layer; 231, first main gate connection portion; 2312, first linear region; 2314, first welding point connection region; 232, first fine gate connection portion; 240, alignment identification region; 250, second doped layer; 260, second electrode connection layer; 262, second fine gate connection portion; 270, isolation region; 280, first gate line; 281, main gate of first gate line; 282, fine gate of first gate line; 283, first welding point; 290, second gate line; 291, main gate of second gate line; 292, fine gate of second gate line; 293, second welding point; 31, printing point of first correction hole; 32, printing point of second correction hole; 33, printing point of third correction hole. DETAILED DESCRIPTION
[0052] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.
[0053] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be an element centered thereon. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an element centered thereon. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementations.
[0054] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number or order of the indicated technical features.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0056] The invention provides a method for preparing a solar cell.
[0057] like Figure 1 As shown, a method 100 for preparing a solar cell according to an embodiment includes the following steps:
[0058] Step S110, as Figure 2 As shown, a first doping layer 220 is formed on a silicon wafer 210 . The first doping layer 220 includes a doped polysilicon layer 221 and a doped oxide layer 222 formed on the doped polysilicon layer 221 .
[0059] The silicon wafer 210 includes a single crystal silicon substrate. Furthermore, the silicon wafer 210 may further include a tunneling layer disposed on the single crystal silicon substrate. The first doped layer 220 is formed on the tunneling layer. The material of the tunneling layer may be, but is not limited to, silicon oxide.
[0060] The first doping layer 220 may be N-type doped, such as phosphorus doped, or may be P-type doped, such as boron doped.
[0061] The doping process of the first doping layer 220 may be, but is not limited to, a thermal diffusion doping process, an ion implantation process, or the like.
[0062] In one example, the steps of preparing the first doping layer 220 include:
[0063] forming a first silicon material layer on the silicon wafer 210;
[0064] The first silicon material layer is subjected to thermal diffusion doping treatment to form a doped polysilicon layer 221 . Simultaneously, a doped oxide layer 222 (such as a BSG layer or a PSG layer) is formed on the doped polysilicon layer 221 due to thermal reaction, thereby obtaining a first doped layer 220 .
[0065] Step S120, as Figure 3 and Figure 4 As shown, a first patterning process is performed on the first doped layer 220. The first patterning process includes removing the doped oxide layer 222 in a localized area via laser treatment, followed by removing the doped polysilicon layer 221 in that area via alkali polishing. Through the first patterning process including the laser treatment and alkali polishing, the remaining portion of the first doped layer 220 forms the first electrode connection layer 230. Simultaneously, the first patterning process including the laser treatment and alkali polishing forms a plurality of alignment identification regions 240.
[0066] After laser treatment opens the doped oxide layer 222, the alignment identification area 240 is very shallow and difficult for the camera to detect. Alkali polishing then removes the doped polysilicon layer 221 in this area, making the alignment identification area 240 more visible and detectable by the camera. Compared to direct laser drilling, alkaline polishing is less likely to damage the silicon wafer 210, thus preventing degradation of battery performance.
[0067] The alignment accuracy requirements for the first patterning process are not high; the pattern only needs to be roughly centered on the silicon wafer 210. In one example, the first patterning process uses an image acquisition device to obtain the edge position of the silicon wafer 210, determine the center position of the silicon wafer 210, and align the center of the pattern in the first patterning process with the center position of the silicon wafer 210.
[0068] like Figure 3 As shown, through the first patterning process, the first doping layer 220 on the first region 211 is removed, and the first doping layer 220 on the second region 212 (ie, the region outside the first region 211 ) is retained to form a first electrode connection layer 230 .
[0069] like Figure 4As shown, in one example, the first electrode connection layer 230 includes a first main grid connection portion 231 and a plurality of first fine grid connection portions 232 extending from the first main grid connection portion 231. The first main grid connection portion 231 is used to connect the main grid of the first gate line, and the first fine grid connection portion 232 is used to connect the fine grid of the first gate line. The first main grid connection portion 231 extends along a first direction, and the first fine grid connection portion 232 extends along a second direction. The first direction and the second direction are arranged at an angle, and the angle can be but is not limited to a right angle. The first electrode connection layer 230 may have a plurality of first main grid connection portions 231 arranged side by side, and each first main grid connection portion 231 is connected to a plurality of first fine grid connection portions 232.
[0070] Furthermore, the first busbar connection portion 231 includes a first linear region 2312 and a plurality of first welding point connection regions 2314. The plurality of first welding point connection regions 2314 are connected in series via the first linear region 2312, and the width of the first welding point connection regions 2314 is greater than that of the first linear region 2312. In other words, the first busbar connection portion 231 is locally widened to form the first welding point connection regions 2314. The first welding point connection regions 2314 are used to connect to the first welding points located on the busbar of the first grid line. During the production of photovoltaic modules, the first welding points are used for welding to the soldering ribbon.
[0071] The alignment recognition area 240 is a preset graphic that can be recognized by the image acquisition device. The shape of the alignment recognition area 240 can be, but is not limited to, a circle, a rectangle, a triangle, etc.
[0072] Optionally, the alignment identification area 240 can be located in the first area 211 or in the second area 212. The alignment identification area 240 can be located near the first main gate connection portion 231 or near the first fine gate connection portion 232, as long as its shape can be recognized by the image acquisition device.
[0073] like Figure 4 As shown, the alignment identification area 240 is located in the first area 211, and the alignment identification area 240 forms a recessed edge of the first electrode connection layer 230, so that the shape of this position is different from other positions, so that it can be recognized by the image acquisition device. Figure 4 In the specific example shown, the alignment recognition region 240 is located between two adjacent first fine gate connection portions 232 , and the alignment recognition region 240 forms a recessed edge of the two first fine gate connection portions 232 .
[0074] In other examples, the alignment identification area 240 may also be located in the second region 212 , and the alignment identification area 240 forms an edge protrusion of the first electrode connection layer 230 , so that the shape of this position is different from other positions, thereby being recognizable by the image acquisition device.
[0075] There are multiple alignment recognition areas 240, for example, 4 to 10. In one example, the multiple alignment recognition areas 240 are centrally symmetrically distributed, with the center point of the pattern processed by the first patterning being the center of symmetry.
[0076] To improve the point-grabbing accuracy of the image acquisition device, the multiple alignment identification areas 240 are preferably distributed near the edge of the silicon wafer 210. For example, in one example, the silicon wafer 210 is rectangular, and the four alignment identification areas 240 thereon are respectively located near the four corners of the rectangle.
[0077] Step S130, as Figure 5 As shown, a second doping layer 250 is formed on the silicon wafer 210 , and the doping type of the second doping layer 250 is opposite to that of the first doping layer 220 .
[0078] The second doped layer 250 overlies the first electrode connection layer 230 and the exposed portion of the silicon wafer 210 after the first patterning process. For example, the second doped layer 250 can be deposited over the entire surface. In other words, the second doped layer 250 overlies the first region 211 and the second region 212. When the silicon wafer 210 includes a single crystal silicon substrate and a tunneling layer disposed on the single crystal silicon substrate, the second doped layer 250 is formed on the tunneling layer.
[0079] The second doping layer 250 has a doping type opposite to that of the first doping layer 220 and is used to connect a first gate line and a second gate line with opposite electrode polarities, respectively.
[0080] In one example, the steps of preparing the second doping layer 250 include:
[0081] forming a second silicon material layer on the silicon wafer 210;
[0082] The second silicon material layer is subjected to thermal diffusion doping to form a second doping layer 250. Similar to the first doping layer 220, the second doping layer 250 also includes a doped polysilicon layer and a doped oxide layer.
[0083] After the first patterning process, the alignment identification area 240 has a height difference with the surrounding area regardless of whether it is located in the first area 211 or the second area 212. After covering the second doping layer 250, the height difference between the alignment identification area 240 and its surrounding area still exists, and the color will also be different, so it can be recognized by the image acquisition device.
[0084] Step S140, as Figure 6 and Figure 7 As shown, a plurality of alignment identification regions 240 are identified, and the plurality of alignment identification regions 240 are used for alignment, and the second doping layer 250 is subjected to a second patterning process.
[0085] By performing a second patterning process on the second doping layer 250 , the remaining portion of the second doping layer 250 forms the second electrode connection layer 260 . Furthermore, the second electrode connection layer 260 is spaced apart from the first electrode connection layer 230 .
[0086] In one example, the plurality of alignment identification regions 240 are distributed in a centrally symmetrical manner, with the central point of the pattern processed by the first patterning being the center of symmetry.
[0087] Furthermore, using the plurality of alignment identification areas 240 to perform alignment includes:
[0088] Obtaining the positions of the plurality of alignment identification areas 240 by an image acquisition device;
[0089] Determine the symmetry center according to the positions of the plurality of alignment identification areas 240;
[0090] The second patterning process is performed with the symmetry center as a reference point, so that the center of the pattern of the second patterning process overlaps with the symmetry center.
[0091] The second patterning process can remove the surface doped oxide layer (such as BSG layer, PSG layer) by laser etching, and then remove the doped polysilicon by alkali polishing to remove the local area of the second doped layer 250. The unremoved area forms the second electrode connection layer 260.
[0092] An isolation region 270 is provided between the second electrode connection layer 260 and the first electrode connection layer 230 to prevent electrical conduction and leakage between the electrode connection layers.
[0093] and Figure 4 The first electrode connection layer 230 is similarly Figure 7 As shown, the second electrode connection layer 260 includes a second main grid connection portion and a plurality of second fine grid connection portions 262 extending from the second main grid connection portion. The second main grid connection portion is used to connect the main grid of the second grid line, and the second fine grid connection portion 262 is used to connect the fine grid of the second grid line. The second main grid connection portion extends along a first direction, and the second fine grid connection portion 262 extends along a second direction. The first direction and the second direction are arranged at an angle, and the angle can be but is not limited to a right angle. The second electrode connection layer 260 may have a plurality of second main grid connection portions arranged side by side, each second main grid connection portion connecting to a plurality of second fine grid connection portions 262.
[0094] Furthermore, the second busbar connection portion includes a second linear region and multiple second welding point connection regions. The multiple second welding point connection regions are connected in series via the second linear region, and the width of the second welding point connection regions is greater than that of the second linear region. In other words, the width of the second busbar connection portion is locally increased to form the second welding point connection region. The second welding point connection region is used to connect to the second welding point, which is located on the busbar of the second busbar line. During the production of photovoltaic modules, the second welding point is used for welding to the solder ribbon.
[0095] like Figure 7 As shown, in one example, the first electrode connection layer 230 and the second electrode connection layer 260 are arranged in an interdigitated pattern. More specifically, in the second direction, a plurality of first busbar connections 231 and a plurality of second busbar connections are alternately arranged. In the first direction, a plurality of first fine gate connections 232 connected to a first busbar connection 231 and a plurality of second fine gate connections 262 connected to an adjacent second busbar connection are alternately arranged.
[0096] In one example, the solar cell manufacturing method 100 further includes the following steps:
[0097] Step S150, as Figure 8 and Figure 9 As shown, alignment is performed using a plurality of alignment identification areas 240 , and a first gate line 280 is screen-printed on the first electrode connection layer 230 , and a second gate line 290 is screen-printed on the second electrode connection layer 260 .
[0098] Similar to step S140 , in the above example, the position alignment of the screen printing plate is performed by obtaining a plurality of alignment identification areas 240 formed by the first patterning process, thereby improving the printing accuracy.
[0099] Similar to step S140, step S150 includes:
[0100] Obtaining the positions of the plurality of alignment identification areas 240 by an image acquisition device;
[0101] Determine the symmetry center based on the positions of the plurality of alignment identification areas 240;
[0102] The screen printing of the grid lines is performed with the center of symmetry as a reference point so that the center of the grid line pattern overlaps with the center of symmetry. It can be understood that the main grid 281 of the first grid line is printed on the first linear area 2312 of the first main grid connection portion 231, the fine grid 282 of the first grid line is printed on the first fine grid connection portion 232, and the first welding point 283 on the first grid line 280 is printed on the first welding point connection area 2314 of the first main grid connection portion 231. The main grid 291 of the second grid line is printed on the second linear area of the second main grid connection portion, the fine grid 292 of the second grid line is printed on the second fine grid connection portion 262, and the second welding point 293 on the second grid line 290 is printed on the second welding point connection area of the second main grid connection portion.
[0103] In one example, the step of screen printing the first gate line 280 and the second gate line 290 (step S150) specifically includes:
[0104] Step S151, using a first screen to screen print the fine grid 282 of the first grid line and the fine grid 292 of the second grid line;
[0105] Step S152 : using a second screen to screen print the busbar 281 of the first grid line and the first welding point 283 thereon, and the busbar 291 of the second grid line and the second welding point 293 thereon.
[0106] Optionally, step S151 may be performed before step S152 or after step S152.
[0107] In one example, the first screen is used for screen printing first, and then the second screen is used for screen printing, that is, step S151 is performed first, and then step S152 is performed.
[0108] For front-junction cells such as PERC cells and TOPcon cells, there is no height difference on the surface. Usually, the main grid and welding points are printed first, and then the fine grid is printed. However, for solar cells with all grid lines located on the back, due to the influence of processes such as alkaline polishing, there is a height difference of about 2-8μm between the first electrode connection layer 230 and the second electrode connection layer 260. If the main grid and welding points are printed first, this height difference will be increased, resulting in uneven fine grid printing, increased wet weight, and difficulty in controlling the printing process. Therefore, printing the fine grid first, and then printing the main grid and welding points, can make the fine grid wet weight lower and the line shape more uniform. It can also improve the thickness uniformity of the main grid and welding points between the poles, and avoid the problem of insufficient welding tension during welding.
[0109] like Figure 9As shown in the example, between two adjacent solder joints, the busbar has a tapered design with a narrow center width and wide ends. This means the busbar width gradually increases as it approaches the solder joint. This structural design takes into account the fact that the convergence of fine grid current gradually increases as it approaches the solder joint. By designing the busbar width to gradually increase as it approaches the solder joint, it not only reduces current losses when converging to the solder joint but also reduces the amount of silver paste used.
[0110] In one example, the first screen used for screen printing fine grids is provided with first and / or second calibration holes. The calibration holes are used to locate the relative position of the screen pattern and the printing table. After the cell is transferred to the printing machine, the camera identifies and captures the alignment identification area on it, obtains the relative position of the cell on the printing table, and then uses these two positions to align the screen and cell through a machine algorithm. This further improves printing accuracy. The first calibration hole corresponds to the first welding point connection area 2314, and the second calibration hole corresponds to the second welding point connection area.
[0111] like Figure 9 As shown, the printing point 31 of the first correction hole is located within the range of the first welding point 283 , and the printing point 32 of the second correction hole is located within the range of the second welding point 293 .
[0112] It is understood that the area of the first calibration hole is no larger than the area of the first welding point connection area 2314, and is preferably significantly smaller than the area of the first welding point connection area 2314. For example, the area of the first calibration hole is 3% to 50% of the area of the first welding point connection area 2314 to avoid exceeding the range of the welding point during silk screen printing. Similarly, the area of the second calibration hole is no larger than the area of the second welding point connection area, and is preferably significantly smaller than the area of the second welding point connection area. For example, the area of the second calibration hole is 3% to 50% of the area of the second welding point connection area.
[0113] When using the first screen to screen-print the fine grid, the first correction hole is placed in the first solder joint connection area 2314, and the second correction hole is placed in the second solder joint connection area. When using the second screen to screen-print the main grid and solder joints, the solder joints cover the paste at the correction hole. This method not only improves the appearance of the screen printing, but also prevents the correction hole from straying outside the junction area due to fine grid offset, which can cause leakage.
[0114] In one example, a third correction hole and / or a fourth correction hole is provided on the second screen for screen printing the main grid and welding points. The third correction hole is located on the main grid 281 of the first grid line, and the fourth correction hole is located on the main grid 291 of the second grid line.
[0115] The correction holes of the second screen are designed on the main grid, which avoids the problem of leakage caused by the deviation of the correction holes between the fine grids and makes the screen more beautiful.
[0116] exist Figure 9 In the specific example shown, the printing point 33 of the third correction hole is located in the middle position of the main grid between two adjacent welding points.
[0117] like Figure 10 As shown, if the correction hole 40 of the printed screen is not designed on the main grid 51, but a certain area of the fine grid 52 is deliberately left empty to correspond to the correction hole of the printed screen, there will be no electroluminescence in this area during the EL test because there is no fine grid 52 to conduct electricity. That is, there is a risk of EL blackening in this area.
[0118] like Figure 11 As shown, if the correction hole 40 of the printed screen is not designed on the main grid 51, but is designed on the fine grid 52, although the EL can be avoided from being blackened, due to the large size of the correction hole, the upper and lower offsets during printing may hit the boundary. In this way, the fine grid 52 connects the two junction areas into a loop, thereby posing a risk of leakage.
[0119] In the above example, the above problem can be avoided by setting the correction holes of the first screen at the positions of the welding points and setting the correction holes of the second screen at the positions of the main grids.
[0120] In one example, the solar cell manufacturing method 100 further includes the following steps:
[0121] Step S160 , aligning the printed dots 33 of the third calibration hole and / or the printed dots of the fourth calibration hole, screen-printing an insulating layer on the first busbar 281 and the second busbar 291 , exposing the first welding point 283 and the second welding point 293 .
[0122] Similar to step S140, in the above example, by using the printing point 33 of the third correction hole and / or the printing point of the fourth correction hole to align the position of the insulation layer silk screen, the printing accuracy of the insulation layer can be improved, and the insulation layer glue can be prevented from offsetting and shielding the welding point, affecting the welding performance.
[0123] In one example, the printing dots 33 of the third calibration holes and / or the fourth calibration holes for alignment are distributed in a centrally symmetrical manner, with the central point of the pattern processed by the first patterning being the center of symmetry.
[0124] Furthermore, the above step S160 includes:
[0125] obtaining positions of a plurality of printing dots by an image acquisition device;
[0126] Determine the symmetry center according to the positions of the multiple printing points;
[0127] The insulating layer is printed with the symmetry center as a reference point so that the center of the pattern of the insulating layer overlaps with the symmetry center.
[0128] In one example, the solar cell manufacturing method 100 further includes the following steps:
[0129] In step S170, the printed dots 33 of the third calibration hole and / or the printed dots of the fourth calibration hole are used for alignment, and the solder ribbon is soldered to the first soldering point 283 and the second soldering point 293. Similar to step S140, in the above example, by using the printed dots 33 of the third calibration hole and / or the printed dots of the fourth calibration hole to align the solder ribbon and the soldering points, the accuracy of the solder ribbon soldering can be improved.
[0130] Furthermore, the above step S160 includes:
[0131] obtaining positions of a plurality of printing dots by an image acquisition device;
[0132] Determine the symmetry center according to the positions of the multiple printing points;
[0133] The welding of the welding strips is performed with the symmetry center as a reference point so that the center of the pattern composed of multiple welding strips overlaps with the symmetry center.
[0134] In the above-mentioned method 100 for preparing a solar cell, when performing the first patterning process to form the first electrode connection layer 230, a plurality of alignment identification areas 240 are simultaneously formed on the silicon wafer 210. When performing the second patterning process, the plurality of alignment identification areas 240 are used for alignment to form a second electrode connection layer 260 spaced apart from the first electrode connection layer 230. This method has high alignment accuracy and is conducive to forming an isolation area 270 with good uniformity, small width and deep depth between the first electrode connection layer 230 and the second electrode connection layer 260, thereby avoiding leakage caused by overlap between the first electrode connection layer 230 and the second electrode connection layer 260.
[0135] In the above-described fabrication method, laser treatment is first performed to form the alignment identification area, effectively removing the doped oxide layer. After laser treatment, the alignment identification area is shallow and difficult to detect by a camera. Subsequently, alkaline polishing is performed to make the alignment identification area 240 more distinct and detectable by the camera. Compared to direct laser drilling, alkaline polishing is less likely to damage the silicon wafer 210, thereby preventing degradation of battery performance.
[0136] Furthermore, by obtaining the plurality of alignment identification areas 240 formed by the first patterning process and performing position alignment on the screen printing screen, the printing accuracy of the gate lines can be improved. Furthermore, by using the printing points 33 of the third correction hole and / or the printing points of the fourth correction hole to perform position alignment on the screen printing screen of the insulating layer and the soldering strip, the printing accuracy of the insulating layer and the soldering strip can be improved.
[0137] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0138] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.
Claims
1. A method for preparing a solar cell, characterized in that: The following steps are involved: forming a first doped layer on a silicon wafer, wherein the first doped layer comprises a doped polysilicon layer and a doped oxide layer formed on the doped polysilicon layer; performing a first patterning process on the first doped layer, the first patterning process comprising removing the doped oxide layer in a local area by laser processing, then removing the doped polysilicon layer in the area by alkali polishing, and simultaneously forming a plurality of alignment identification areas by the laser processing and the alkali polishing; forming a second doping layer on the silicon wafer, wherein the second doping layer has a doping type opposite to that of the first doping layer; The plurality of alignment identification regions are identified, and the plurality of alignment identification regions are used for alignment, and the second doping layer is subjected to a second patterning process.
2. The preparation method according to claim 1, wherein The silicon wafer includes a single crystal silicon substrate and a tunneling layer arranged on the single crystal silicon substrate, and the first doping layer and the second doping layer are both formed on the tunneling layer.
3. The preparation method according to claim 1, wherein The plurality of alignment identification areas are distributed in a centrally symmetrical manner, with the central point of the pattern processed by the first patterning being the center of symmetry.
4. The preparation method according to claim 3, wherein Identifying the plurality of alignment identification areas, utilizing the plurality of alignment identification areas for alignment, and performing a second patterning process on the second doped layer comprises the following steps: obtaining positions of the plurality of alignment identification areas by an image acquisition device; Determine the symmetry center according to the positions of the plurality of alignment identification areas; The second patterning process is performed with the symmetry center as a reference point, so that the center of the pattern of the second patterning process overlaps with the symmetry center.
5. The preparation method according to claim 3, wherein The plurality of alignment identification areas are distributed near the edge of the silicon wafer.
6. The preparation method according to claim 1, wherein The first patterning process uses an image acquisition device to obtain the edge position of the silicon wafer, determine the center position of the silicon wafer, and align the center of the pattern of the first patterning process with the center position of the silicon wafer.
7. The preparation method according to any one of claims 1 to 6, characterized in that The first doping layer forms a first electrode connection layer after the first patterning process, and the second doping layer forms a second electrode connection layer after the second patterning process. The first electrode connection layer and the second electrode connection layer are spaced apart and distributed in an interdigitated manner.
8. The preparation method according to claim 7, wherein The first electrode connection layer includes a first main gate connection portion and a plurality of first fine gate connection portions extending from the first main gate connection portion, the first main gate connection portion includes a first linear region and a plurality of first welding point connection regions, the plurality of first welding point connection regions are connected in series through the first linear region, and the width of the first welding point connection regions is greater than the width of the first linear region; The second electrode connection layer includes a second main gate connection portion and a plurality of second fine gate connection portions extending from the second main gate connection portion. The second main gate connection portion includes a second linear region and a plurality of second welding point connection regions. The plurality of second welding point connection regions are connected in series through the second linear region. The width of the second welding point connection region is greater than the width of the second linear region.
9. The preparation method according to claim 8, wherein The preparation method further comprises the following steps: Alignment is performed using the plurality of alignment identification areas, and a first gate line is screen-printed on the first electrode connection layer, and a second gate line is screen-printed on the second electrode connection layer.
10. The preparation method according to claim 9, characterized in that The step of screen printing the first gate line and the second gate line specifically includes: Using a first screen to screen-print the fine grid of the first grid line and the fine grid of the second grid line; A second screen is used to screen print the main grid of the first grid line and the first welding point thereon, and the main grid of the second grid line and the second welding point thereon.
11. The preparation method according to claim 10, characterized in that The first screen is used for screen printing first, and then the second screen is used for screen printing.
12. The preparation method according to claim 10, wherein The first screen is provided with a first correction hole and / or a second correction hole. The first correction hole corresponds to the position of the first welding point connection area, and the second correction hole corresponds to the position of the second welding point connection area.
13. The preparation method according to claim 10, wherein The second screen is provided with a third correction hole and / or a fourth correction hole. The third correction hole is located on the main grid of the first grid line, and the fourth correction hole is located on the main grid of the second grid line.
14. The preparation method according to claim 13, wherein The preparation method further comprises the following steps: Alignment is performed using the printing dots of the third correction hole and / or the printing dots of the fourth correction hole, and an insulating layer is screen-printed on the main grid of the first gate line and the main grid of the second gate line, wherein the insulating layer exposes the first welding point and the second welding point.
15. The preparation method according to claim 14, wherein The preparation method further comprises the following steps: The printed points of the third calibration hole and / or the printed points of the fourth calibration hole are used for alignment, and the welding ribbon is welded to the first welding point and the second welding point.
16. A solar cell, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 15.