Instruction package, generation method, decompression method, processor and electronic device

Abstract

The application provides an instruction package, a generating method, a decompression method, a processor and an electronic device. The instruction package comprises a header part and an instruction part. The header part is composed of instruction part size and instruction slot state information. The instruction slot state information is used for identifying whether the instruction corresponding to each instruction slot of a functional unit is in the instruction part according to the instruction slot sequence. The instruction part is composed of instructions arranged closely according to the instruction slot sequence. The instruction package provided by the application can quickly obtain the instruction of each functional unit without decoding one by one through the header part, reduces the burden of a decoder, and improves the decoding speed.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to an instruction package, a generation method, a decompression method, a processor, and an electronic device. Background Technology

[0002] Since simultaneous instruction execution can significantly improve computer processing speed, software (the compiler) performs instruction dependency analysis to combine unrelated instructions that can be executed simultaneously into an instruction packet. This instruction packet is called a Very Long Instruction Word (VLIW). During execution, the hardware reads and decodes instructions in packets. Multiple instructions within a packet can be executed simultaneously without requiring further hardware dependency analysis. This simplifies the controller circuitry and allows for the simultaneous execution of even more instructions, further enhancing processor performance.

[0003] Currently, VLIW instruction packets are all fixed-length. For fixed-length instruction packets, it is only necessary to find the end of the instruction packet. However, for variable-length instruction packets, this process of decoding each packet one by one puts a heavy burden on the decoder. Summary of the Invention

[0004] To address one of the aforementioned technical deficiencies, this application provides an instruction package, a generation method, a decompression method, a processor, and an electronic device.

[0005] In a first aspect, this application provides an instruction package, which includes a header portion and an instruction portion;

[0006] The header consists of the size of the instruction section and the status information of the instruction slot;

[0007] Instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction section according to the instruction slot sequence;

[0008] The instruction section consists of instructions arranged closely in the order of instruction slots.

[0009] A second aspect of this application provides a method for generating the instruction package described in the first aspect, the method comprising:

[0010] Traverse each instruction in the instruction section and record the functional unit to which each instruction belongs;

[0011] Based on the recorded functional units, instruction slot status information is generated;

[0012] Generate the packet header based on the instruction portion size and instruction slot status information;

[0013] Generate an instruction packet based on the header and instruction portions.

[0014] A third aspect of this application provides a method for decompressing the instruction package described in the first method, the method comprising:

[0015] Retrieve the header portion of the instruction packet;

[0016] Based on the header, instructions are retrieved sequentially from the instruction portion of the instruction packet and then distributed.

[0017] In a fourth aspect, this application provides a vector processor, comprising: one or more functional units;

[0018] Functional units are located in instruction slots;

[0019] The instructions of a functional unit constitute the instruction portion of an instruction package;

[0020] Wherein, the instruction package is the instruction package described in the first aspect;

[0021] The instruction package is generated by the method described in the second aspect and decompressed by the method described in the third aspect.

[0022] A fifth aspect of this application provides a high-performance processor, comprising: the vector processor and the scalar processor described in the fourth aspect;

[0023] A read-first-in-first-out FIFO unit and a write-first-out FIFO unit are provided between the vector processor and the scalar processor;

[0024] Both the vector program control unit and the scalar processor perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0025] A sixth aspect of this application provides an electronic device comprising: the high-performance processor described in the fifth aspect; or, comprising one or more processor clusters, wherein each processor cluster includes a plurality of the high-performance processors described in the fifth aspect.

[0026] This application provides an instruction packet, a generation method, a decompression method, a processor, and an electronic device. The instruction packet includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet provided by this application, through its header, can quickly obtain the instructions of each functional unit without decoding them one by one, reducing the burden on the decoder and improving the decoding speed. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0028] Figure 1 A schematic diagram of the header portion of an instruction packet provided in an embodiment of this application;

[0029] Figure 2 A schematic diagram of the header portion of another instruction packet provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram of the header portion of another instruction packet provided in an embodiment of this application;

[0031] Figure 4 A flowchart illustrating a method for generating an instruction packet according to an embodiment of this application;

[0032] Figure 5 A schematic diagram of instruction slot status information provided in an embodiment of this application;

[0033] Figure 6 A flowchart illustrating a method for decompressing an instruction packet provided in an embodiment of this application;

[0034] Figure 7 A schematic diagram of the architecture of a vector processor provided in an embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the structure of a vector operation unit provided in an embodiment of this application;

[0036] Figure 9 A schematic diagram of another vector processor architecture provided in an embodiment of this application;

[0037] Figure 10 This is a schematic diagram of the structure of a scalar processor provided in an embodiment of this application;

[0038] Figure 11 A schematic diagram of the structure of a synchronization unit for a scalar processor provided in an embodiment of this application;

[0039] Figure 12 This is a schematic diagram of the structure of a high-performance processor provided in an embodiment of this application. Detailed Implementation

[0040] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0041] In the process of developing this application, the inventors discovered that current VLIW instruction packets are all fixed-length. For fixed-length instruction packets, it is only necessary to find the end of the instruction packet. However, for variable-length instruction packets, this process of decoding each packet one by one places a heavy burden on the decoder.

[0042] To address the aforementioned issues, this application provides an instruction packet, a generation method, a decompression method, a processor, and an electronic device. The instruction packet includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information identifies whether the instructions for the functional units corresponding to each instruction slot are present in the instruction portion, in instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet provided by this application, through its header, allows for rapid acquisition of instructions for each functional unit without requiring individual decoding, reducing the decoder's burden and improving decoding speed.

[0043] This embodiment provides an instruction package, which includes a header and an instruction portion.

[0044] 1. Headband section

[0045] The header portion consists of the instruction size and instruction slot status information, such as... Figure 1 As shown.

[0046] The header portion has a width of n*8 bits, where n is a positive integer.

[0047] 1) The instruction portion size is the size of the instruction block, which is used to determine the end of the instruction packet. The width of the instruction portion size is determined based on the instruction slot status information, but it is not less than the maximum value of the instruction portion size when all instruction slot status information is 1.

[0048] 2) Instruction slot status information, used to identify whether the instructions of the corresponding functional unit of each instruction slot are in the instruction section according to the instruction slot sequence. In this way, based on the instruction slot status information, it can be determined which functional unit instructions are included in the instruction section, and the corresponding instructions can be obtained based on the size of the instructions of each functional unit.

[0049] The width of the command slot status information is determined based on the total number of command slots. The width of the command slot status information is never less than the total number of command slots. The width of the command slot status information = total number of command slots + number of preset information indicator bits. The preset information indicator bits are pre-set according to specific requirements.

[0050] The instruction slot status information consists of multiple status bits, with each status bit having a width of 1 bit.

[0051] The lower m bits of the instruction slot status information correspond one-to-one with the instruction slots in the order of the instruction slots, where m is the total number of instruction slots.

[0052] The value of any status bit corresponding to an instruction slot is either a first value or a second value. The first value indicates an instruction in the instruction packet that contains a functional unit of the instruction slot corresponding to any status bit, and the second value indicates an instruction in the instruction packet that does not contain a functional unit of the instruction slot corresponding to any status bit.

[0053] For example, if the first value is 1 and the second value is 0, then when a certain status bit is 1, it means that the instruction section includes the instruction for its corresponding functional unit. When a certain status bit is 0, it means that the instruction section does not include the instruction for its corresponding functional unit.

[0054] Figure 1 The width of the instruction slot status information is x.

[0055] In other words, the instruction slot status information consists of x status bits, with each of the m consecutive bits starting from bit 0 corresponding to an instruction slot in the order of the instruction slots. For example, bit 0 corresponds to instruction slot 0, bit 1 corresponds to instruction slot 1, bit 2 corresponds to instruction slot 2, ..., bit (m-1) corresponds to instruction slot m-1.

[0056] There are functional units on the instruction slots. Therefore, each of the lower m status bits also uniquely corresponds to a functional unit. The 0th bit corresponds to functional unit 0 located in instruction slot 0, the 1st bit corresponds to functional unit 1 located in instruction slot 1, the 2nd bit corresponds to functional unit 2 located in instruction slot 2, ..., and the (m-1)th bit corresponds to functional unit m-1 located in instruction slot m-1.

[0057] 2. Instruction Section

[0058] The instruction section consists of instructions arranged closely in the order of instruction slots.

[0059] In practice, the instruction set can be a variable-length instruction packet.

[0060] Taking a header width of 32 bits and 27 instruction slots as an example, the header portion of the instruction packet is as follows: Figure 2 As shown, the size of the instruction portion (i.e. Figure 2The width of the size in the code is 32-27=5 bits.

[0061] Although the instructions in the variable-length instruction packet do not come from all functional units, the instruction length of each functional unit is fixed. By using the value of the instruction slot and the size, the instructions of each functional unit can be obtained quickly without decoding them one by one, which reduces the burden on the decoder and improves the decoding speed.

[0062] For example, there are four instruction slots: instruction slot 0, instruction slot 1, instruction slot 2, and instruction slot 3. Each instruction slot has one functional unit: FU0 on instruction slot 0, FU1 on instruction slot 1, FU2 on instruction slot 2, and FU3 on instruction slot 3. Here, FU is an abbreviation for Functional Unit.

[0063] If the instruction length of FU0 is 16 bits, the instruction length of FU1 is 8 bits, the instruction length of FU2 is 128 bits, and the instruction length of FU3 is 32 bits.

[0064] If the current variable-length instruction packet consists of instructions from FU0 (i.e., instruction 0) and FU3 (i.e., instruction 3), then the size of the variable-length instruction packet is 16 + 32 = 48 bits. If the instruction slot status information occupies 5 bits, with the first value being 1 and the second value being 0, and n = 1, then the header portion is 1 * 8 = 8 bits, and the instruction portion occupies 8 - 5 = 3 bits. Therefore, the final instruction packet header portion is as follows: Figure 3 As shown, the instruction portion of the instruction packet is a variable-length instruction packet (such as Package1) consisting of instruction 0 and instruction 3.

[0065] In this way, the instructions with bits 0-15 of Package 1 being FU0 and bits 16-47 of Package 1 being FU3 can be obtained by using the values ​​of each status bit in the instruction slot status information, without the need for individual decoding.

[0066] It should be noted that all values ​​in this embodiment and subsequent embodiments (such as instruction length) are merely examples and do not represent actual values. In practical applications, the methods provided in this embodiment and subsequent embodiments can be adjusted according to the actual values.

[0067] The instruction packet provided in this embodiment adds a header section, which contains the size of the instruction portion and the status information of the instruction slots. The length of the instruction portion can be determined based on the size of the instruction portion recorded in the header section. The corresponding instructions are decoded one by one from the instruction portion based on the status information of the instruction slots.

[0068] In addition, since the header contains information about the instruction portion, there is no need to encode instruction slot information on the instruction itself, thus saving encoding bits.

[0069] Adding a header to the instruction packet eliminates the need to parse the specific length of the instruction packet line by line for instruction alignment, facilitating instruction packet compression and rapid location, and enabling fast decoding.

[0070] In addition, since the header contains the instruction slot information of each instruction, there is no need to encode the instruction slot information on the instruction, thus saving encoding bits.

[0071] This embodiment provides an instruction packet, which includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet provided in this embodiment, through its header, allows for the rapid acquisition of instructions from each functional unit without requiring individual decoding, reducing the decoder's burden and improving decoding speed.

[0072] Based on the same inventive concept of instruction packets, targeting Figures 1 to 3 For any of the instruction packets shown in the figures, this embodiment provides a method for generating instruction packets, see [link to relevant documentation]. Figure 4 The implementation process of this method is as follows:

[0073] 401, Traverse each instruction in the instruction section and record the functional unit to which each instruction belongs.

[0074] Taking Package1 (a variable-length instruction package consisting of instruction 0 and instruction 3) as an example, where instruction 0 is the instruction of FU0 and instruction 3 is the instruction of FU3, in step 401, Package1 will be traversed, first recording the functional unit FU0 to which instruction 0 belongs, and then recording the functional unit FU3 to which instruction 3 belongs.

[0075] FU stands for Functional Unit.

[0076] 402. Based on the recorded functional units, form instruction slot status information.

[0077] For example, the status bits of recorded functional units are assigned the first value, and the status bits of unrecorded functional units are assigned the second value. The status bits of the functional units corresponding to each instruction slot are arranged closely according to the instruction slot order to form the instruction slot status information.

[0078] The first value is used to indicate an instruction in the instruction package that contains a functional unit with an instruction slot corresponding to any status bit; the second value is used to indicate an instruction in the instruction package that does not contain a functional unit with an instruction slot corresponding to any status bit.

[0079] Taking the example from step 401, if there are four instruction slots: instruction slot 0, instruction slot 1, instruction slot 2, and instruction slot 3, and each instruction slot has one functional unit: FU0 on instruction slot 0, FU1 on instruction slot 1, FU2 on instruction slot 2, and FU3 on instruction slot 3. The instruction length for FU0 is 16 bits, for FU1 it is 8 bits, for FU2 it is 128 bits, and for FU3 it is 32 bits. The instruction slot status information occupies 5 bits, with the first value being 1 and the second value being 0, and n=1. Therefore, the header portion is 1*8=8 bits, and the instruction portion occupies 8-5=3 bits. The status bits corresponding to FU0 and FU3 are set to 1, and the status bits corresponding to FU1 and FU2 are set to 0. The status bits of the functional units corresponding to each instruction slot are arranged closely according to the instruction slot order to form the instruction slot status information as follows: Figure 5 As shown.

[0080] It should be noted that for status bits in the instruction slot status information that do not correspond to the instruction slot, you can fill in the corresponding values ​​according to the actual situation. No further explanation is needed here.

[0081] 403. Generate the packet header based on the instruction portion size and instruction slot status information.

[0082] Taking the example from step 402 as an example, the size of the variable-length instruction packet is 16 + 32 = 48 bits, the instruction slot status information occupies 5 bits, the header part is 1 * 8 = 8 bits, and the instruction part occupies 8 - 5 = 3 bits. Therefore, the header part of the final instruction packet is as follows: Figure 3 As shown.

[0083] 404. Generate an instruction packet based on the header and instruction portions.

[0084] For example, Figure 3 The header and Package1 shown are compressed to obtain the instruction packet.

[0085] The instruction package generated in this embodiment does not require the addition of functional unit identifiers to the instructions, thus reducing the size of the instruction package.

[0086] In addition, the instruction packets generated in this embodiment can be obtained by using the values ​​of each status bit in the instruction slot status information to obtain the instruction with bits 0-15 of Package1 being FU0 and bits 16-47 of Package1 being FU3, without the need for individual decoding.

[0087] The instruction packet provided in this embodiment adds a header section, which contains the size of the instruction portion and the status information of the instruction slots. The length of the instruction portion can be determined based on the size of the instruction portion recorded in the header section. The corresponding instructions are decoded one by one from the instruction portion based on the status information of the instruction slots.

[0088] In addition, since the header contains information about the instruction portion, there is no need to encode instruction slot information on the instruction itself, thus saving encoding bits.

[0089] Adding a header to the instruction packet eliminates the need to parse the specific length of the instruction packet line by line for instruction alignment, facilitating instruction packet compression and rapid location, and enabling fast decoding.

[0090] In addition, since the header contains the instruction slot information of each instruction, there is no need to encode the instruction slot information on the instruction, thus saving encoding bits.

[0091] This embodiment provides a method for generating instruction packets. The generated instruction packets include a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet generated by the method provided in this embodiment, through the header, can quickly obtain the instructions of each functional unit without decoding them one by one, reducing the burden on the decoder and improving the decoding speed.

[0092] Based on the same inventive concept of instruction packets, targeting Figures 1 to 3 For any of the instruction packets shown in the figure, this embodiment provides a method for decompressing the instruction packet. See [link to relevant documentation]. Figure 6 The implementation process of this method is as follows:

[0093] 601, retrieve the header portion of the instruction packet.

[0094] 602. Based on the packet header, retrieve instructions sequentially from the instruction portion of the instruction packet and distribute the instructions.

[0095] The process of fetching instructions sequentially from the instruction portion of the instruction packet is as follows: Based on the size of the instruction portion and the instruction slot status information in the packet header, the instruction length corresponding to each instruction slot is determined. Instructions are then fetched sequentially from the instruction portion of the instruction packet according to the instruction slot order and instruction length.

[0096] For example, if there are four instruction slots: instruction slot 0, instruction slot 1, instruction slot 2, and instruction slot 3, and each instruction slot has a functional unit (FU3), namely FU0 on instruction slot 0, FU1 on instruction slot 1, FU2 on instruction slot 2, and FU3 on instruction slot 3. The instruction length of FU0 is 16 bits, that of FU1 is 8 bits, that of FU2 is 128 bits, and that of FU3 is 32 bits. The instruction slot status information occupies 5 bits, with the first value being 1 and the second value being 0, and n=1. Therefore, the header portion occupies 1*8=8 bits, and the instruction portion occupies 8-5=3 bits. Then, through step 601, the instruction slot status information is obtained... Figure 3 The instruction packet shown contains a header portion. In step 602, based on the instruction portion size (i.e., 48 bits) and instruction slot status information (such as...), the header portion is used to determine the instruction size. Figure 5 As shown, the instruction length corresponding to instruction slot 0 is determined to be FU0 (16 bits), and the instruction length corresponding to instruction slot 3 is determined to be FU3 (32 bits). Since the status bits of instruction slots 1 and 2 are both 0, it means that there are no instructions for instruction slots 1 and 2 in the instruction section. Here, the instruction length can be uncertain or it can be determined to be 0. This example does not limit the method for determining the instruction length when the status bit is 0. Instructions are retrieved sequentially from the instruction section of the instruction packet according to the instruction slot order and instruction length. That is, instructions with bits 0-15 of Package 1 being FU0 are retrieved, and instructions with bits 16-47 of Package 1 being FU3 are retrieved. In this way, the instructions can be obtained without decoding them one by one.

[0097] Additionally, when dispatching instructions, if the current instruction fetch length is insufficient for the instructions to be sent in the current instruction part, and there are no instructions in the instruction prefetch queue, the pipeline will block and wait for all instructions in the current instruction part to be fetched before dispatching instructions.

[0098] All instructions in the current instruction block are sent out in the same clock cycle, and the next clock cycle decompresses the next instruction packet, and so on.

[0099] The instruction packet provided in this embodiment adds a header section, which contains the size of the instruction portion and the status information of the instruction slots. The length of the instruction portion can be determined based on the size of the instruction portion recorded in the header section. The corresponding instructions are decoded one by one from the instruction portion based on the status information of the instruction slots.

[0100] In addition, since the header contains information about the instruction portion, there is no need to encode instruction slot information on the instruction itself, thus saving encoding bits.

[0101] Adding a header to the instruction packet eliminates the need to parse the specific length of the instruction packet line by line for instruction alignment, facilitating instruction packet compression and rapid location, and enabling fast decoding.

[0102] In addition, since the header contains the instruction slot information of each instruction, there is no need to encode the instruction slot information on the instruction, thus saving encoding bits.

[0103] This embodiment provides a method for decoding instruction packets. The decoded instruction packet includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The decoding method provided in this embodiment, through the header, can quickly obtain the instructions of each functional unit without decoding them one by one, reducing the burden on the decoder and improving the decoding speed.

[0104] Based on the same inventive concept of instruction packets, this embodiment provides a vector processor, which includes one or more functional units located in instruction slots.

[0105] In practical implementation, a vector processor, in addition to including one or more functional units, may also include, for example: Figure 7 The diagram shows: a vector program control unit, a register file stack, and scalar registers.

[0106] In addition, the vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0107] 1. Vector Program Control Unit

[0108] Vector program control unit, used for instruction fetching and instruction issuing.

[0109] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0110] The vector program control unit is also used to control instruction jumps.

[0111] The vector program control unit has scalar computation capabilities.

[0112] The vector program control unit interacts with the scalar register.

[0113] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0114] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0115] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0116] 2. Functional Units

[0117] Functional units are used to perform functional processing according to instructions.

[0118] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0119] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0120] 1) Vector operation unit

[0121] Any vector operation unit is used to perform vector operations according to instructions.

[0122] like Figure 8 As shown, any vector operation unit includes: a floating-point multiply-add subunit, a floating-point multiply-accumulate subunit, a floating-point arithmetic subunit, a tensor multiplication subunit, and an intermediate result register.

[0123] The floating-point multiply-accumulate subunit and the floating-point arithmetic subunit share one issue slot. Therefore, a maximum of 8 instructions from the vector operation unit can be issued per cycle.

[0124] The floating-point multiplication-accumulation subunit and the tensor multiplication subunit share a single launch slot.

[0125] The floating-point multiply-accumulate subunit is a functional unit that executes instructions related to floating-point multiply-accumulate operations. For example, instructions related to floating-point multiply-accumulate operations include integer and floating-point vector multiplication and accumulation, multiplication, addition, tensor calculation, etc.

[0126] Each vector operation unit has its own intermediate result register.

[0127] One floating-point multiply-accumulate subunit, one floating-point multiply-accumulate subunit, one tensor multiplication subunit, and one floating-point arithmetic subunit share an intermediate result register.

[0128] (1) Floating-point multiply-accumulate and floating-point multiply-accumulate subunits, which can perform integer and floating-point vector multiplication, multiply-accumulate, and other operations. Supported types include, but are not limited to, int32, fp32, and fp64.

[0129] (2) The floating-point arithmetic subunit can perform integer and floating-point vector arithmetic operations, such as comparison, addition, subtraction, bitwise operations, etc. Supported types include, but are not limited to, int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, fp64.

[0130] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate, and other operations. Supported types include, but are not limited to, int8, bf16, fp16, and tf32.

[0131] 2) Vector interleaving unit

[0132] Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0133] The vector interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point and floating-point calculations. It also supports numerous customized instructions, including table lookup, horizontal calculation, sparse matrix calculation, precision conversion, and FIFO (First Input First Output) functions. It executes instructions such as data broadcasting, extraction, and internal interleaving.

[0134] Each vector interleaving unit has a set of private vector registers; therefore, the private vector registers of each vector interleaving unit correspond one-to-one with the vector interleaving units.

[0135] 3) Vector Access Unit

[0136] Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0137] The vector access unit is the memory access unit within the vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0138] The read / write instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and accumulation mode.

[0139] It supports multiple parameter configurations, with a maximum read / write instruction data width of up to 1024 bits. It executes instructions such as address calculation, load / store, etc.

[0140] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0141] In addition, the instructions of a functional unit constitute the instruction portion of an instruction package.

[0142] Among them, the instruction package is Figures 1 to 3 The instruction package shown in any of the figures.

[0143] Instruction packet passed Figure 4 The instruction packet generation method shown is used to generate the instruction packet. Figure 6 The instruction package is decompressed using the method shown.

[0144] Specifically, the instruction packet includes: a header and an instruction portion;

[0145] The header consists of the size of the instruction section and the status information of the instruction slot;

[0146] Instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction section according to the instruction slot sequence;

[0147] The instruction section consists of instructions arranged closely in the order of instruction slots.

[0148] Optionally, the width of the header portion is n*8 bits; where n is a positive integer;

[0149] The width of the instruction slot status information is determined based on the total number of instruction slots.

[0150] Optionally, the instruction slot status information consists of multiple status bits, wherein the width of each status bit is 1 bit;

[0151] The lower m bits of the instruction slot status information correspond one-to-one with the instruction slots in the order of the instruction slots, where m is the total number of instruction slots;

[0152] The value of any status bit corresponding to the instruction slot is either a first value or a second value; the first value is used to indicate an instruction in the instruction package that contains a functional unit of the instruction slot corresponding to any status bit, and the second value is used to indicate an instruction in the instruction package that does not contain a functional unit of the instruction slot corresponding to any status bit.

[0153] Methods for generating instruction packets include:

[0154] Traverse each instruction in the instruction section and record the functional unit to which each instruction belongs;

[0155] Based on the recorded functional units, instruction slot status information is generated;

[0156] Generate the packet header based on the instruction portion size and instruction slot status information;

[0157] Generate an instruction packet based on the header and instruction portions.

[0158] Optionally, instruction slot status information is formed based on the recorded functional units, including:

[0159] The recorded status bit of the functional unit is set to the first value, and the unrecorded status bit of the functional unit is set to the second value; wherein, the first value is used to indicate the instruction of the functional unit that contains the instruction slot corresponding to any status bit in the instruction package, and the second value is used to indicate the instruction of the functional unit that does not contain the instruction slot corresponding to any status bit in the instruction package.

[0160] The status bits of the functional units corresponding to each instruction slot are arranged closely in sequence to form the instruction slot status information.

[0161] Methods for decompressing command packages include:

[0162] Retrieve the header portion of the instruction packet;

[0163] Based on the header, instructions are retrieved sequentially from the instruction portion of the instruction packet and then distributed.

[0164] Optionally, instructions are retrieved sequentially from the instruction portion of the instruction packet based on the packet header, including:

[0165] Based on the size of the instruction portion and the instruction slot status information in the header section, determine the instruction length corresponding to each instruction slot;

[0166] Instructions are fetched sequentially from the instruction portion of the instruction packet according to the instruction slot order and instruction length.

[0167] 3. Register file stack

[0168] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0169] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0170] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data within the register file stack.

[0171] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0172] Taking other processing processors as examples, such as scalar processors, the synchronization unit of a scalar processor can write data to the register file, and the register file can also receive status information from the synchronization unit of the scalar processor to query whether the data has been written.

[0173] The depth of the register file heap is configurable.

[0174] Figure 9 A schematic diagram of a vector processor is shown, comprising four vector operation units, four vector interleaving units, and four vector access units.

[0175] The vector processor provided in this embodiment supports the VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0176] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0177] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0178] Other processing units perform read or write operations on the vector register.

[0179] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0180] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0181] This embodiment provides a vector processor whose instruction packet includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet in the vector processor provided by this embodiment, through the header, can quickly obtain the instructions of each functional unit without decoding them one by one, reducing the burden on the decoder and improving the decoding speed.

[0182] Based on the same inventive concept of instruction packets, this embodiment provides a high-performance processor, which includes a scalar processor and a vector processor.

[0183] In this configuration, scalar processors and vector processors share memory. Furthermore, vector processors can only access memory and are executed solely by scalar processors.

[0184] A connection is established between scalar processors and vector processors. For example, scalar processors and vector processors can be connected via a dedicated instruction channel.

[0185] In addition, a high-performance processor may include two registers: one for the scalar processor and the other for the vector processor. The vector processor can read and write its corresponding register, while the scalar processor can read and write both its corresponding register and the register corresponding to the vector processor.

[0186] Scalar processors can read and write the registers of vector processors.

[0187] The scalar processor establishes a connection with global memory.

[0188] (a) Scalar Processor

[0189] See Figure 10 The scalar processor may include: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0190] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0191] 1. Instruction Fetch Unit

[0192] The instruction fetch unit is used to fetch and dispatch instructions.

[0193] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0194] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetching. It also receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially searches for one or more instructions from the qualified instructions, performs decoding and related checks, and dispatches the qualified instructions in sequence. At most, it dispatches one program control unit instruction and one synchronization unit instruction at a time. In addition, it can dispatch one or more scalar arithmetic unit instructions and one or more memory access unit instructions at a time.

[0195] 2. Register renaming unit

[0196] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0197] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to the arithmetic reserved stack unit, and stores them in one or more of the following: the program control unit, and the synchronization unit.

[0198] For example, the register renaming unit in a scalar processor is used to receive instructions dispatched by the instruction fetch unit and rename registers and special vector registers, decode instruction conditions, generate pipeline congestion signals, and simultaneously receive data from execution units (such as scalar arithmetic units, memory access units, program control units, and synchronization units) to write back registers, special vector registers, condition registers, and status flag registers and write them back to the corresponding registers.

[0199] Scalar processors support out-of-order write-back, resulting in high execution efficiency. They also distribute instructions to the arithmetic stack, storage stack, program control unit, or synchronization unit.

[0200] The register renaming unit bandwidth can be 6 bits, during which multiple (e.g., 4) input instructions can be valid at the same time.

[0201] There can be multiple condition registers, which are located in the register renaming unit.

[0202] The instructions for the scalar arithmetic unit and memory access unit support reading and writing condition registers.

[0203] The instructions for the synchronization unit support reading the condition register.

[0204] The program control unit's jump and function call instructions support reading the condition register.

[0205] When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

[0206] In other words, the condition register is not renamed; when a read / write request occurs, a dispatch blocking mechanism is triggered to wait. The conditions register read / write rules are as follows:

[0207] • Reading rules:

[0208] (1) All instructions in the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0209] (2) The scalar arithmetic unit also supports read condition register instruction operations.

[0210] (3) The jump and function call instructions of the program control unit support reading condition register operations.

[0211] • Write the rules:

[0212] (1) The scalar arithmetic unit supports the write condition register instruction.

[0213] (2) Scalar arithmetic unit logic and comparison instructions support the option to write to the condition register.

[0214] When a previously issued instruction to write to the condition register has not yet finished executing, and another instruction to read or write to the same condition register enters, the pipeline becomes congested, generating a condition execution block signal, and waits for the previous condition register to finish writing.

[0215] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0216] Each of the following physical registers can be one of the following: scalar physical register, vector physical register, condition register, or flag register.

[0217] Any logic register can be one of the following: scalar logic register or vector logic register.

[0218] For example, a register renaming unit contains one or more physical registers, such as multiple 512-bit special vector registers, multiple condition registers, and a status flag register.

[0219] Among them, the special vector register is renamed, while the condition register and status flag register are not renamed.

[0220] There are multiple logic registers, such as scalar logic registers and multiple vector logic registers.

[0221] In addition, the mapping relationship between logical registers and physical registers is maintained by a register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by a special vector register mapping table.

[0222] 1) Register Map Table

[0223] Initially, the mapped physical registers for all entries corresponding to logical register indices in the register map are all 0. When an instruction is executed, or when an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries corresponding to the allocated logical register indices in the register map is updated to the identifier of the relevant physical register.

[0224] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping relationship between all logical registers and all physical registers. Initially, the register map table is invalid, and all entries mapping physical registers are 0. When a physical register is allocated to a logical register, the entry in the register map table corresponding to the logical register index is changed to the ID of that physical register.

[0225] It should be noted that the register map is only updated when an instruction is actually executed. If the conditional execution instruction is not executed, the register map will not be updated. In addition, the register map will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register map to ensure that the interrupt can return normally.

[0226] 2) Special Vector Register Mapping Table

[0227] Initially, the mapped vector physical registers for all entries corresponding to vector logical register indices in the special vector register map are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logical register indices in the special vector register map is updated to the identifier of the relevant vector physical register.

[0228] For example, the special vector register map table, with a depth of 4 bits and a width of 3 bits, stores the mapping relationship between all vector logic registers and all vector physical registers. Initially, the special vector register map table is invalid, and all entries mapping to vector physical registers are 0. When a vector physical register is allocated to a vector logic register, the entry in the special vector register map table corresponding to the vector logic register index is changed to the ID of that vector physical register.

[0229] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0230] 3. Operations retain stack units

[0231] The operation-reserved stack unit is the issue queue of scalar operation units.

[0232] The arithmetic stack is used to receive instructions, dispatch and rename information from the register renaming unit and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution.

[0233] The stack space is reserved for operations and is also used to decode input instructions and store instruction type information.

[0234] In other words, the arithmetic reserve stack is the dispatch queue of the scalar arithmetic unit. The arithmetic reserve stack receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions onto the scalar arithmetic unit for execution. The arithmetic reserve stack decodes the input instructions and stores the instruction type information.

[0235] In practice, the depth of the operation reserve stack can be flexibly adjusted, such as a depth of 8. Multiple scalar operation units share one operation reserve stack unit.

[0236] The rules for issuing and receiving instructions that reserve stack space are as follows:

[0237] (1) The output of the register renaming unit enters the operation retention stack unit.

[0238] (2) When there is any free scalar arithmetic unit, it will fetch instructions and operands from the arithmetic reserve stack and execute them.

[0239] (3) The principle of fetching instructions from the operation reserved stack is to fetch executable instructions that can be sent from the operation reserved stack in the order from front to back.

[0240] (4) Whether it is possible to send a value based on the values ​​of all source registers or special vector registers or condition registers and status flag registers is ready to be determined.

[0241] (5) If there are multiple instructions that can be sent, send the oldest instruction first according to the order of instructions.

[0242] (6) If any scalar arithmetic unit is blocked, it can no longer receive new instructions.

[0243] (7) If the instruction previously sent to any scalar arithmetic unit was a division instruction, a new division instruction can only be sent to it after the division result is calculated and the calculation completion En signal is returned.

[0244] 4. Store and retain stack units

[0245] The storage-reserved stack unit is the issue queue for memory access units.

[0246] The storage reserve stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0247] The storage reserve stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and to save the read address operand.

[0248] The register renaming unit is also used to calculate the address after the instruction has obtained the address, decode the address, and save the decoded information.

[0249] The register renaming unit is also used to detect when the existence source register of any instruction is ready and the address decoding is complete, and then issue it to the memory access unit for execution.

[0250] In practice, the depth of the memory reservation stack unit can be flexibly adjusted, such as 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the issue queue for memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit obtains the address, it can calculate the address and decode the address, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready in the memory reservation stack unit and the address decoding is complete, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checks, address comparison checks, and address forward checks.

[0251] The rules for storing and reserving stack cells for sending and receiving instructions are as follows:

[0252] (1) The output of the register renaming unit enters the memory retention stack unit.

[0253] (2) Once the source operand for the calculated address is ready, calculate the memory access address and store it in the memory reservation stack.

[0254] (3) Address-independent instructions: can be out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions can all be sent out of order. Write instructions after write instructions need to be ordered (cannot be sent to different memory access units at the same time). Even if the address-independent write instructions are written after write instructions, the order still needs to be maintained.

[0255] (4) Address-related instructions: The order of read instruction followed by write instruction, write instruction followed by read instruction, write instruction followed by write instruction, and read instruction followed by read instruction must be guaranteed.

[0256] (5) When addresses are unrelated but are located in the same memory space as all instructions that have not been successfully sent (i.e. instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level), they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0257] (6) Only one memory access instruction located in the same memory space but with unrelated addresses can be sent at the same time. Two or more memory access units cannot be sent at the same time.

[0258] (7) Address correlation judgment principle: whether addresses are related is determined by whether they are located in different storage spaces. If they are located in the same storage space, the address correlation is determined by the data granularity.

[0259] 5. Scalar Operation Unit

[0260] In a practical implementation, there can be one or more scalar operation units.

[0261] For example, a scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0262] The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform operations on the data based on the instructions, and write the operation result back to the register renaming unit.

[0263] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the arithmetic stack, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0264] The following are some example instructions. In actual implementation, the instructions are not limited to these, nor is it limited to including all of them.

[0265] Instructions at execution level 1 include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point max / min instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction instructions, and Rounding instructions.

[0266] Instructions with an execution level of three include: fixed-point multiplication instructions, fixed-to-floating-point conversion instructions, bit filtering instructions, count instructions, and floating-point addition and subtraction instructions.

[0267] Instructions that support bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0268] The execution cycle of a division instruction is indeterminate and depends on the data of the divisor and dividend. Upon completion, the instruction generates a DivEn instruction, indicating its completion and outputting the result to the register file. No new division instructions can be input during the execution of a division instruction, but other scalar computation unit instructions can be input. The output result of the division is multiplexed with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar computation unit instructions, the division outputs its result and simultaneously outputs the DivEn flag. This DivEn flag is output to the arithmetic reserve stack, indicating that Div instructions can continue to be output to the current scalar computation unit.

[0269] 6. Memory access unit

[0270] In a practical implementation, there can be one or more memory access units.

[0271] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0272] The memory access unit is used to receive instructions, data, and register information sent by the memory-reserved stack unit, and to read and write the data based on the instructions and register information.

[0273] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0274] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0275] 7. Program Control Unit

[0276] In practice, there is only one program control unit.

[0277] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0278] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0279] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0280] 8. Synchronization Unit

[0281] In practice, there is only one synchronization unit.

[0282] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0283] like Figure 11 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0284] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0285] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0286] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0287] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Out) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0288] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate the ExeStall signal affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0289] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit):

[0290] The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0291] The query vector processor execution status function supports option B.

[0292] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. The read / write function waits until the read / write operation is successful, or the result of the read / write operation is successfully or unsuccessfully written back to the register.

[0293] Write register file stack functionality, including special vector register write or register write.

[0294] The function allows reading and writing scalar registers, including reading and writing immediate indexes or register indexes.

[0295] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0296] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0297] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0298] 9. Production line control unit

[0299] The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0300] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0301] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0302] In addition, scalar processors can also perform conditional execution decoding in practical applications. For example, when performing conditional execution decoding, a scalar processor checks the preset bits of the instruction to determine the execution condition. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. Here, a null instruction represents an empty instruction or an invalid instruction.

[0303] If a read / write operation is active in the condition register, pipeline blocking is triggered, waiting for the condition register write operation to complete before the read operation can proceed. There is no bypass for condition register reads and writes.

[0304] Taking two condition registers, namely condition register 0 and condition register 1, with the preset bits [29:28] as an example, when the scalar processor performs conditional execution decoding, it judges the execution conditions of the input instruction based on the [29:28] bits of the instruction set encoding. If the conditions are met, a valid instruction is output; otherwise, a null instruction is output.

[0305] In this instruction, bits [29:28] being 00 indicates that condition register 0 is 1 and the instruction is executed; bits [29:28] being 01 indicates that condition register 1 is 1 and the instruction is executed; bits [29:28] being 10 indicates that condition register 0 is executed; and bits [29:28] being 11 indicates that the instruction is executed without conditions. If the conditions are not met, the instruction is invalid and an empty instruction is output.

[0306] If there is a read / write dependency in the condition register, pipeline blocking is triggered, and the read operation is performed only after the condition register has been written. There is no bypass for condition register read / write operations.

[0307] (II) Vector Processor

[0308] In practical implementation, a vector processor can be as follows: Figures 7-8 As shown in any of the figures, the implementation details of the vector processor can also be seen as follows: Figures 7-8 As illustrated in any of the embodiments, further details are omitted here. For example, a vector processor includes one or more functional units.

[0309] The functional unit is located in the instruction slot.

[0310] The instructions of a functional unit constitute the instruction portion of an instruction package.

[0311] Among them, the instruction package is Figures 1 to 3 The instruction package shown in any of the figures.

[0312] Instruction packet passed Figure 4 The instruction packet generation method shown is used to generate the instruction packet. Figure 6 The instruction package is decompressed using the method shown.

[0313] Specifically, the instruction packet includes: a header and an instruction portion;

[0314] The header consists of the size of the instruction section and the status information of the instruction slot;

[0315] Instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction section according to the instruction slot sequence;

[0316] The instruction section consists of instructions arranged closely in the order of instruction slots.

[0317] Optionally, the width of the header portion is n*8 bits; where n is a positive integer;

[0318] The width of the instruction slot status information is determined based on the total number of instruction slots.

[0319] Optionally, the instruction slot status information consists of multiple status bits, wherein the width of each status bit is 1 bit;

[0320] The lower m bits of the instruction slot status information correspond one-to-one with the instruction slots in the order of the instruction slots, where m is the total number of instruction slots;

[0321] The value of any status bit corresponding to the instruction slot is either a first value or a second value; the first value is used to indicate an instruction in the instruction package that contains a functional unit of the instruction slot corresponding to any status bit, and the second value is used to indicate an instruction in the instruction package that does not contain a functional unit of the instruction slot corresponding to any status bit.

[0322] Methods for generating instruction packets include:

[0323] Traverse each instruction in the instruction section and record the functional unit to which each instruction belongs;

[0324] Based on the recorded functional units, instruction slot status information is generated;

[0325] Generate the packet header based on the instruction portion size and instruction slot status information;

[0326] Generate an instruction packet based on the header and instruction portions.

[0327] Optionally, instruction slot status information is formed based on the recorded functional units, including:

[0328] The recorded status bit of the functional unit is set to the first value, and the unrecorded status bit of the functional unit is set to the second value; wherein, the first value is used to indicate the instruction of the functional unit that contains the instruction slot corresponding to any status bit in the instruction package, and the second value is used to indicate the instruction of the functional unit that does not contain the instruction slot corresponding to any status bit in the instruction package.

[0329] The status bits of the functional units corresponding to each instruction slot are arranged closely in sequence to form the instruction slot status information.

[0330] Methods for decompressing command packages include:

[0331] Retrieve the header portion of the instruction packet;

[0332] Based on the header, instructions are retrieved sequentially from the instruction portion of the instruction packet and then distributed.

[0333] Optionally, instructions are retrieved sequentially from the instruction portion of the instruction packet based on the packet header, including:

[0334] Based on the size of the instruction portion and the instruction slot status information in the header section, determine the instruction length corresponding to each instruction slot;

[0335] Instructions are fetched sequentially from the instruction portion of the instruction packet according to the instruction slot order and instruction length.

[0336] In addition, the vector program control unit is also used to receive the start command sent by the scalar processor, start the vector processor, and return an indication signal to the scalar processor indicating whether the vector processor has ended.

[0337] A FIFO (First Input First Output) unit and a write FIFO unit are set between the vector processor and the scalar processor.

[0338] Both the vector program control unit and the scalar processor perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0339] Based on the scalar processors and vector processors described above, high-performance processors can, as... Figure 12 As shown.

[0340] This embodiment provides a high-performance processor. The instruction packet in this high-performance processor includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet in the high-performance processor provided in this embodiment, through the header, allows for the rapid acquisition of instructions for each functional unit without individual decoding, reducing the decoder's burden and improving decoding speed.

[0341] Based on the same inventive concept of instruction packs, this embodiment provides an electronic device that includes a high-performance processor, or the electronic device includes one or more processor clusters, wherein each processor cluster includes multiple high-performance processors.

[0342] Among them, high-performance processors can be such as Figure 12 As shown, the implementation details of high-performance processors can also be seen as follows: Figure 12 The embodiments shown are illustrated and will not be repeated here.

[0343] For example, this high-performance processor includes scalar processors and vector processors.

[0344] The vector processor includes one or more functional units.

[0345] The functional unit is located in the instruction slot.

[0346] The instructions of a functional unit constitute the instruction portion of an instruction package.

[0347] Among them, the instruction package is Figures 1 to 3 The instruction package shown in any of the figures.

[0348] Instruction packet passed Figure 4 The instruction packet generation method shown is used to generate the instruction packet. Figure 6 The instruction package is decompressed using the method shown.

[0349] Specifically, the instruction packet includes: a header and an instruction portion;

[0350] The header consists of the size of the instruction section and the status information of the instruction slot;

[0351] Instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction section according to the instruction slot sequence;

[0352] The instruction section consists of instructions arranged closely in the order of instruction slots.

[0353] Optionally, the width of the header portion is n*8 bits; where n is a positive integer;

[0354] The width of the instruction slot status information is determined based on the total number of instruction slots.

[0355] Optionally, the instruction slot status information consists of multiple status bits, wherein the width of each status bit is 1 bit;

[0356] The lower m bits of the instruction slot status information correspond one-to-one with the instruction slots in the order of the instruction slots, where m is the total number of instruction slots;

[0357] The value of any status bit corresponding to the instruction slot is either a first value or a second value; the first value is used to indicate an instruction in the instruction package that contains a functional unit of the instruction slot corresponding to any status bit, and the second value is used to indicate an instruction in the instruction package that does not contain a functional unit of the instruction slot corresponding to any status bit.

[0358] Methods for generating instruction packets include:

[0359] Traverse each instruction in the instruction section and record the functional unit to which each instruction belongs;

[0360] Based on the recorded functional units, instruction slot status information is generated;

[0361] Generate the packet header based on the instruction portion size and instruction slot status information;

[0362] Generate an instruction packet based on the header and instruction portions.

[0363] Optionally, instruction slot status information is formed based on the recorded functional units, including:

[0364] The recorded status bit of the functional unit is set to the first value, and the unrecorded status bit of the functional unit is set to the second value; wherein, the first value is used to indicate the instruction of the functional unit that contains the instruction slot corresponding to any status bit in the instruction package, and the second value is used to indicate the instruction of the functional unit that does not contain the instruction slot corresponding to any status bit in the instruction package.

[0365] The status bits of the functional units corresponding to each instruction slot are arranged closely in sequence to form the instruction slot status information.

[0366] Methods for decompressing command packages include:

[0367] Retrieve the header portion of the instruction packet;

[0368] Based on the header, instructions are retrieved sequentially from the instruction portion of the instruction packet and then distributed.

[0369] Optionally, instructions are retrieved sequentially from the instruction portion of the instruction packet based on the packet header, including:

[0370] Based on the size of the instruction portion and the instruction slot status information in the header section, determine the instruction length corresponding to each instruction slot;

[0371] Instructions are fetched sequentially from the instruction portion of the instruction packet according to the instruction slot order and instruction length.

[0372] This embodiment provides an electronic device whose instruction packet includes a header and an instruction portion. The header consists of the instruction portion size and instruction slot status information. The instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion, according to the instruction slot order. The instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet in the electronic device provided in this embodiment, through its header, allows for the rapid acquisition of instructions from each functional unit without requiring individual decoding, reducing the decoder's burden and improving decoding speed.

[0373] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0374] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0375] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0376] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0377] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0378] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A vector processor, characterized in that, include: One or more functional units, a vector program control unit for instruction fetching and issuing, a register file and scalar registers for receiving, reading, and writing requests, returning data, rearranging the data, and returning the result. The functional units include: a vector operation unit for performing vector operations according to instructions, a vector interleaving unit for performing data interleaving and logical processing according to instructions, and a vector access unit for performing multi-mode memory access, address calculation, and scalar calculation according to instructions. The functional unit is located in the instruction slot; the instructions of the functional unit constitute the instruction portion of the instruction package; wherein, the instruction package includes: a header portion and an instruction portion; the header portion consists of the instruction portion size and instruction slot status information; the instruction slot status information is used to identify whether the instruction of the functional unit corresponding to each instruction slot is in the instruction portion according to the instruction slot order; the instruction portion consists of instructions arranged closely according to the instruction slot order. The instruction packet is generated by the following method: traversing each instruction in the instruction section and recording the functional unit to which each instruction belongs; forming instruction slot status information based on the recorded functional units; generating a packet header based on the size of the instruction section and the instruction slot status information; and generating an instruction packet based on the packet header and the instruction section. The instruction packet is decompressed by the following method: obtaining the header portion of the instruction packet; according to the header portion, retrieving instructions from the instruction portion of the instruction packet in sequence, and distributing the instructions.

2. The vector processor according to claim 1, characterized in that, The width of the header portion is n*8 bits; where n is a positive integer; The width of the instruction slot status information is determined based on the total number of instruction slots.

3. The vector processor according to claim 1 or 2, characterized in that, The instruction slot status information consists of multiple status bits, wherein the width of each status bit is 1 bit. The lower m bits of the instruction slot status information correspond one-to-one with the instruction slots in the order of the instruction slots, where m is the total number of instruction slots; The value of any status bit corresponding to the instruction slot is a first value or a second value; the first value is used to indicate an instruction in the instruction package that contains a functional unit of the instruction slot corresponding to any status bit, and the second value is used to indicate an instruction in the instruction package that does not contain a functional unit of the instruction slot corresponding to any status bit.

4. The vector processor according to claim 3, characterized in that, The process of forming instruction slot status information based on the recorded functional units includes: The recorded status bit of the functional unit is set to a first value, and the unrecorded status bit of the functional unit is set to a second value; wherein, the first value is used to indicate the instruction of the functional unit that contains the instruction slot corresponding to any status bit in the instruction package, and the second value is used to indicate the instruction of the functional unit that does not contain the instruction slot corresponding to any status bit in the instruction package. The status bits of the functional units corresponding to each instruction slot are arranged closely in sequence to form the instruction slot status information.

5. The vector processor according to claim 4, characterized in that, The step of retrieving instructions sequentially from the instruction portion of the instruction packet based on the packet header includes: Based on the size of the instruction portion and the instruction slot status information in the header section, determine the instruction length corresponding to each instruction slot; Instructions are fetched sequentially from the instruction portion of the instruction packet according to the instruction slot order and instruction length.

6. A high-performance processor, characterized in that, include: The vector processor and scalar processor according to any one of claims 1-5; A read-first-in-first-out FIFO unit and a write-FIFO unit are provided between the vector processor and the scalar processor; Both the vector program control unit and the scalar processor perform read operations on the read FIFO unit and write operations on the write FIFO unit.

7. An electronic device, characterized in that, include: The high-performance processor of claim 6; or, comprising one or more processor clusters, wherein each processor cluster includes a plurality of the high-performance processors of claim 6.

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