Data transmission method, functional unit, cluster of functional units, processor and device

Abstract

This application provides a data transmission method, functional unit, functional unit cluster, processor, and device. The method includes: acquiring data while parsing a target field in an instruction; wherein the target field consists of a target field module index and a register file number; determining a data path based on the target field module index; and sending the data to the register file corresponding to the register number through the data path. The method provided by this application acquires data while parsing a target field in an instruction; wherein the target field consists of a target field module index and a register file number; determining a data path based on the target field module index; and sending the data to the register file corresponding to the register number through the data path. Data transmission can be completed with a single instruction, reducing the execution time of one instruction compared to existing technologies and improving transmission efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data transmission method, functional unit, functional unit cluster, processor, and device. Background Technology

[0002] In complex clustered structures, different functional units (FUs) have their own unique register files.

[0003] Currently, the register file in a functional unit is private. A functional unit can only access its own register file, as well as the register files of other functional units.

[0004] When transmitting data, if a functional unit (such as FU0) wants to transfer the calculation result to another functional unit (FU1), two instructions are required. The first instruction is used to store the calculation result of FU0 into the register file of FU0, and the second instruction is used to instruct FU1 to read the calculation result from the register file of FU0 and store it into the register file of FU1. Summary of the Invention

[0005] To address one of the aforementioned technical deficiencies, this application provides a data transmission method, a functional unit, a cluster of functional units, a processor, and a device.

[0006] A first aspect of this application provides a data transmission method, the method comprising:

[0007] While acquiring data, the target field in the instruction is parsed; the target field consists of the target field module index and the register file number.

[0008] Determine the data path based on the target domain module index;

[0009] Data is sent to the register file corresponding to the register number via the data path.

[0010] Optionally, the target field consists of multiple target field module indexes and register file numbers;

[0011] Based on the target domain module index, determine the data path, including:

[0012] Based on the index of each target domain module, each data path is determined separately;

[0013] Data is sent to the register file corresponding to the register number via the data path, including:

[0014] Data is simultaneously sent to the register file corresponding to each register number through each data path.

[0015] Optionally, data is sent to the register file corresponding to the register number via the data path, including:

[0016] The computational requirements in the parsing instructions;

[0017] After performing calculations on the data based on computational requirements, the calculation results are sent to the register file corresponding to the register number through the data path.

[0018] A second aspect of this application provides a functional unit, which includes a read port, a decoder, and a write port;

[0019] The read port is used to acquire data;

[0020] The decoder is used to parse the target field in the instruction; the target field consists of the target field module index and the register file number.

[0021] The write port is used to determine the data path based on the target domain module index, and then send the data to the register file corresponding to the register number through the data path.

[0022] Optionally, the target field consists of multiple target field module indexes and register file numbers;

[0023] The write port is used to determine each data path according to the index of each target domain module; and to send data to the register file corresponding to each register number through each data path.

[0024] Optionally, the functional unit may also include: an arithmetic unit;

[0025] A decoder is used to parse the computational requirements in instructions;

[0026] The write port is used to perform calculations on data by the arithmetic logic unit (ALU) based on computational needs; and to send the calculation results obtained by the ALU to the register file corresponding to the register number through the data path.

[0027] A third aspect of this application provides a functional unit cluster, which includes: a plurality of functional units as described in the second aspect above;

[0028] There is a data path between any two functional units in the functional unit cluster, or there is no data path.

[0029] In a fourth aspect, this application provides a vector processor, characterized in that it includes: a cluster of functional units as described in the third aspect above.

[0030] A fifth aspect of this application provides a high-performance processor, characterized in that it includes: a vector processor and a scalar processor as described in the fourth aspect above;

[0031] A read-first-in-first-out FIFO unit and a write-first-out FIFO unit are provided between the vector processor and the scalar processor;

[0032] Both the vector program control unit and the scalar processor perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0033] 10. An electronic device, characterized in that it comprises: the high-performance processor of claim 9; or, it comprises one or more processor clusters, wherein each processor cluster comprises a plurality of the high-performance processors of claim 9.

[0034] This application provides a data transmission method, functional unit, functional unit cluster, processor, and device. The method includes: acquiring data while parsing a target field in an instruction; wherein the target field consists of a target field module index and a register file number; determining a data path based on the target field module index; and sending the data to the register file corresponding to the register number through the data path. The method provided by this application acquires data while parsing a target field in an instruction; wherein the target field consists of a target field module index and a register file number; determining a data path based on the target field module index; and sending the data to the register file corresponding to the register number through the data path. Data transmission can be completed with a single instruction, reducing the execution time of one instruction compared to existing technologies and improving transmission efficiency. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0036] Figure 1 A flowchart illustrating a data transmission method provided in an embodiment of this application;

[0037] Figure 2 A schematic diagram of the structure of a functional unit provided in an embodiment of this application;

[0038] Figure 3 A schematic diagram illustrating data transmission between functional units as provided in an embodiment of this application;

[0039] Figure 4 A schematic diagram illustrating another type of data transmission between functional units provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of another functional unit provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the structure of a vector processor provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the structure of a scalar processor provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of the structure of a synchronization unit for a scalar processor provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of the structure of a high-performance processor provided in an embodiment of this application. Detailed Implementation

[0045] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0046] In the process of developing this application, the inventors discovered that currently, the register file in a functional unit (FU) is private; a functional unit can only access its own register file and the register files of other functional units. When transmitting data, if a functional unit (e.g., FU0) wants to transfer a calculation result to another functional unit (FU1), two instructions are required. The first instruction stores the calculation result of FU0 into FU0's register file, and the second instruction instructs FU1 to read the calculation result from FU0's register file and store it into FU1's register file.

[0047] To address the aforementioned problems, this application provides a data transmission method, functional unit, functional unit cluster, processor, and device. The method includes: acquiring data while simultaneously parsing a target field in an instruction; wherein the target field consists of a target field module index and a register file number; determining a data path based on the target field module index; and sending the data to the register file corresponding to the register number through the data path. The method provided in this application acquires data while simultaneously parsing a target field in an instruction; wherein the target field consists of a target field module index and a register file number; determining a data path based on the target field module index; and sending the data to the register file corresponding to the register number through the data path. Data transmission can be completed with a single instruction, reducing the execution time of one instruction compared to existing technologies and improving transmission efficiency.

[0048] See Figure 1 This embodiment provides a data transmission method, the implementation process of which is as follows:

[0049] 101, while obtaining data, parse the target field in the instruction.

[0050] The target field consists of the target field module index and the register file number.

[0051] In practical implementation, the target field can consist of multiple target field module indices and register file numbers. (It should be noted that the target field module index and register file number are corresponding, that is, one target field module index and one register file number, two target field module indices and two register file numbers. Therefore, the multiple target field module indices and register file numbers here are actually multiple target field module indices and multiple register file numbers.)

[0052] In other words, the target domain module index and the register file number will form a correspondence between the target domain module index and the register file number. One correspondence will uniquely identify one register file (that is, the register file corresponding to the register file number in the target module corresponding to the target domain module index). If there are multiple target domain module indices and register file numbers, then multiple target domain module index-register file number correspondences will be formed, which will correspond to multiple register files. At this time, data can be transferred to multiple register files at the same time.

[0053] 102. Determine the data path based on the target domain module index.

[0054] If the target field can be composed of multiple target field module indices and register file numbers, then in step 102, each data path will be determined according to each target field module index.

[0055] Data paths can be determined based on the functional unit interconnection table and the target domain module index.

[0056] The functional unit interconnection table is used to describe whether there is a data path between any two functional units.

[0057] The functional unit interconnection table is a table that represents whether there is a data path between functional units.

[0058] This data path enables a functional unit to write data into the register file of another data unit.

[0059] For example, there are 5 functional units FU0, FU1, FU2, FU3, and FU4. The interconnection table of the functional units is shown in Table 1.

[0060] Table 1

[0061] FU0 FU1 FU2 FU3 FU4 FU0 √ √ √ FU1 √ √ √ FU2 √ √ √ FU3 √ √ FU4 √ √

[0062] The left column of Table 1 represents the source functional unit, and the right column represents the target functional unit. A checkmark indicates that there is a data path between the two functional units, and the source functional unit can write data to the register file of the target functional unit through this data path.

[0063] For example, there is a data path between FU4 and FU1, where FU4 is the target functional unit and FU1 is the target functional unit. FU4 can write data to the register file of FU1 through this data path.

[0064] Functional units can write data to their own register files; therefore, a data path must exist between a functional unit and itself. Whether a data path exists between any two different functional units is predetermined based on the application scenario (e.g., for CNN computation) and requirements. The determination process is as follows:

[0065] 201. It is determined that there is a data path between any two functional units.

[0066] 202. Based on the area of ​​the hardware to which the functional unit belongs and the computational requirements of the functional unit, reduce the data paths to form a functional unit interconnection table.

[0067] For example, based on the area of ​​the hardware to which the functional unit belongs and the computational requirements of the algorithms executed by the functional unit (such as convolution, matrix multiplication, FFT, etc.), a comprehensive consideration should be made (such as analyzing the instructions generated by the algorithm program and the required data transmission requirements, making targeted interconnection support for the requirements of key algorithms, and retaining the corresponding data paths), and reducing the data paths with lower algorithm requirements until the hardware timing and area requirements are met.

[0068] In other words, first establish a fully interconnected data path, then reduce the number of data paths from it, and finally form a functional unit interconnection table.

[0069] The functional unit interconnection table constructed in this embodiment is not fully interconnected. It is determined based on the data transmission relationship between functional units in the application scenario, which can reduce the area increase caused by full interconnection.

[0070] After obtaining the functional unit interconnection table, the functional unit corresponding to the target domain module index is identified as the target functional unit. The system checks if a data path exists between the current functional unit and the functional unit corresponding to the target domain module index in the functional unit interconnection table. If no data path exists, no more data is sent, and an alert is issued. If a data path exists, data is sent to the register file corresponding to the register number through that data path.

[0071] There can be multiple target domain module indices, and the corresponding data paths can also be reused. This allows a functional unit to send data to multiple functional units corresponding to multiple target domain module indices within a cycle through multiple data paths of the functional units corresponding to multiple target domain module indices.

[0072] Within the same cycle, multiple functional units can write data to the register file corresponding to their respective target domain module index numbers, each acting as a source functional unit. For example, within the same cycle, FU0 writes data 1 to the register files of FU0, FU2, and FU3 simultaneously, and FU2 writes data 2 to the register files of FU0, FU1, and FU2 simultaneously. Thus, from the perspective of the functional unit cluster formed by the functional units, a total of 6 data items are written simultaneously within this cycle (3 data items 1 and 3 data items 2).

[0073] 103, send the data to the register file corresponding to the register number through the data path.

[0074] If the target field can be composed of multiple target field module indices and register file numbers, then in step 103, the data will be sent simultaneously to the register file corresponding to each register number through each data path.

[0075] When data is sent to the register file corresponding to the register number through each data path, the computation requirements in the instruction are also parsed. After the data is calculated based on the computation requirements, the calculation results are sent to the register file corresponding to the register number through the data path.

[0076] The target functional unit is a functional unit that has a data path.

[0077] In other words, the data sent can be data that has undergone simple calculations.

[0078] For example, when data is sent to the register file corresponding to the register number through each data path, the computational requirements (such as accumulation) in the instruction are also parsed. After the data is calculated based on the computational requirements, it is sent to the corresponding arithmetic logic unit (ALU). The ALU performs a simple calculation and then sends the calculation result to the register file corresponding to the register number through the data path.

[0079] Whether calculation is required before data is sent depends on the instruction. If the instruction includes a calculation instruction, the calculation is performed before sending; otherwise, the data is sent directly without calculation.

[0080] Furthermore, the data path is established based on the write port, and is the path between the write port of one functional unit and the register file of another functional unit. Each functional unit includes a write port, such as... Figure 2As shown, the write port is the same as the write port described in this embodiment and subsequent embodiments.

[0081] like Figure 3 As shown, the write port of FU0 establishes a data path with the register file of FU2, and the write port of FU0 establishes a data path with the register file of FU3. Data from FU0 is sent simultaneously through the two data paths.

[0082] like Figure 4 As shown, the write port of FU0 establishes a data path with the register file of FU2, and the write port of FU0 establishes a data path with the register file of FU3. The write port of FU0 will call the arithmetic unit in FU0 to perform calculations and send the calculation results simultaneously through the two data paths.

[0083] It should be noted that the establishment of data paths between all functional units corresponds to the functional unit interconnection table.

[0084] The data transmission method provided in this embodiment includes a target domain field in its instructions. This target domain field consists of a target domain module index and a register file number, or multiple target domain fields consisting of target domain module indices and register file numbers. Taking two target domain module indices and register file numbers as an example, when a functional unit (e.g., FU0) obtains the calculation result according to the instruction, it simultaneously parses the target domain field to obtain one target domain module index (e.g., FU2) and a register file number (register file 2), and another target domain module index (e.g., FU3) and a register file number (register file 3). Then, the calculation result is simultaneously transmitted to register file 2 and register file 3 through the data paths between FU0 and FU2 and between FU0 and FU3. The data transmission method provided in this embodiment can directly send data to the target domain, enabling faster register refresh.

[0085] For example, for a common DST (which may include DST1 and DST2), the data transmission method provided in this embodiment can fulfill the requirement of broadcasting the result of the current register file in the current functional unit, and broadcasting it to the registers of multiple other functional units, and can write it to multiple registers at the same time.

[0086] For DST, there are 32 bits in total. DST1 can use 10 to 16 bits to describe the address representation, while DST2 can use 0 to 9 bits. For DST1, jumps can be performed directly based on the corresponding address representation, such as TENSORx.T0~T1. For DST2, parameters can be calculated directly based on the corresponding address representation, such as SHU[{0},{1},{2},{3}].Td; MC.Wx[{S++},{I++},{A++}].

[0087] The data transmission method provided in this embodiment can transmit data to the register files of multiple other functional units simultaneously by adding a target field. This facilitates register file reading operations of other functional units and reduces the time for transmitting calculation results between functional units.

[0088] The data transmission method provided in this embodiment can complete the calculation and write the data into the register file of multiple functional units with a single instruction, so as to directly send the data to the target domain and refresh the registers faster.

[0089] This embodiment provides a data transmission method that obtains data while parsing the target field in the instruction. The target field consists of a target field module index and a register file number. The data path is determined based on the target field module index. The data is then sent to the register file corresponding to the register number through the data path. Thus, the data transmission can be completed with a single instruction, reducing the execution time of one instruction compared to existing technologies and improving transmission efficiency.

[0090] Based on the same inventive concept of data transmission methods, this embodiment provides a functional unit, such as... Figure 2 As shown, this functional unit includes: a read port (i.e., Figure 2 (read port), decoder and write port (i.e.) Figure 2 (The writing in the middle).

[0091] The read port is used to acquire data.

[0092] The decoder is used to parse the target field in the instruction. The target field consists of the target field module index and the register file number.

[0093] The write port is used to determine the data path based on the target domain module index, and then send the data to the register file corresponding to the register number through the data path.

[0094] In addition, the target field consists of multiple target field module indexes and register file numbers.

[0095] The write port is used to determine each data path based on the index of each target domain module. Data is then simultaneously sent to the register file corresponding to each register number through each data path.

[0096] When determining data paths, the write port can use the functional unit interconnection table and the target domain module index to identify the data paths. The functional unit interconnection table describes whether a data path exists between any two functional units within a functional unit cluster.

[0097] The functional unit interconnection table is formed through the following steps:

[0098] It is determined that there is a data path between any two functional units.

[0099] Based on the area of ​​the hardware to which the functional unit belongs and the computational requirements of the functional unit, data paths are reduced to form a functional unit interconnection table.

[0100] like Figure 5 As shown, the functional unit also includes: an arithmetic unit.

[0101] A decoder is used to parse the computational requirements in instructions.

[0102] The write port is used to perform calculations on data by the arithmetic logic unit (ALU) based on computational needs. The calculation results obtained by the ALU are sent to the register file corresponding to the register number through the data path.

[0103] In practical implementation, each functional unit includes a write port, such as Figure 2 As shown, the write port is the same as the write port described in this embodiment and subsequent embodiments.

[0104] The write port is used to receive data and, according to the functional unit interconnection table, send the data through the data path to the register file of one or more target functional units. Alternatively, after receiving data, the arithmetic unit obtains the calculation result of the data and, according to the functional unit interconnection table, sends the calculation result through the data path to the register file of one or more target functional units.

[0105] In other words, the data path is established based on the write port, and it is the path between the write port of one functional unit and the register file of another functional unit.

[0106] like Figure 3 As shown, the write port of FU0 establishes a data path with the calculator of FU2, and the write port of FU0 establishes a data path with the calculator of FU3. Data from FU0 is sent simultaneously through the two data paths.

[0107] like Figure 4As shown, the write port of FU0 establishes a data path with the calculator of FU2, and the write port of FU0 establishes a data path with the calculator of FU3. The write port of FU0 will call the arithmetic unit in FU0 to perform calculations and send the calculation results simultaneously through the two data paths.

[0108] In other words, the computational logic occurs at the write port of each data path. When data passes through the data path and is about to be written into the register file corresponding to the register file number of the functional unit corresponding to the target domain module index, the write port will obtain the encoding of the computation instruction, parse the instruction encoding involved in the data path for computation, and after parsing out the specific computation requirements, the write port will call the arithmetic unit in the functional unit to perform simple data processing (such as horizontal cumulative summation of vector data). After the computation is completed, the data is written into the register file corresponding to the register file number of the functional unit corresponding to the target domain module index.

[0109] It should be noted that the establishment of data paths between all functional units corresponds to the functional unit interconnection table.

[0110] This embodiment provides a functional unit that can simultaneously acquire data through the read port and parse the target field in the instruction using a decoder. The target field consists of a target field module index and a register file number. The write port determines the data path based on the target field module index and sends the data to the register file corresponding to the register number through the data path. Thus, the data transmission can be completed with a single instruction, reducing the execution time of one instruction compared to existing technologies and improving transmission efficiency.

[0111] Based on the same inventive concept of data transmission method, this embodiment provides a functional unit cluster, which includes: multiple functional units.

[0112] There is a data path between any two functional units in the functional unit cluster, or there is no data path.

[0113] This functional unit is as follows Figure 2 As shown in embodiment 3, it includes: a reading port (i.e. Figure 2 (read port), decoder and write port (i.e.) Figure 2 (The writing in the middle).

[0114] The read port is used to acquire data.

[0115] The decoder is used to parse the target field in the instruction. The target field consists of the target field module index and the register file number.

[0116] The write port is used to determine the data path based on the target domain module index, and then send the data to the register file corresponding to the register number through the data path.

[0117] In addition, the target field consists of multiple target field module indexes and register file numbers.

[0118] The write port is used to determine each data path based on the index of each target domain module. Data is then simultaneously sent to the register file corresponding to each register number through each data path.

[0119] like Figure 5 As shown, the functional unit also includes: an arithmetic unit.

[0120] A decoder is used to parse the computational requirements in instructions.

[0121] The write port is used to perform calculations on data by the arithmetic logic unit (ALU) based on computational needs. The calculation results obtained by the ALU are sent to the register file corresponding to the register number through the data path.

[0122] This embodiment provides a functional unit cluster, in which the functional units can obtain data while parsing the target field in the instruction; wherein, the target field consists of a target field module index and a register file number; the data path is determined according to the target field module index; the data is sent to the register file corresponding to the register number through the data path, and thus the data can be sent with a single instruction, which reduces the execution time of one instruction compared with the prior art and improves the transmission efficiency.

[0123] Based on the same inventive concept of data transmission methods, this embodiment provides a vector processor, which includes a cluster of functional units.

[0124] This functional unit cluster includes: multiple functional units.

[0125] There is a data path between any two functional units in the functional unit cluster, or there is no data path.

[0126] This functional unit is as follows Figure 2 As shown in embodiment 3, it includes: a reading port (i.e. Figure 2 (read port), decoder and write port (i.e.) Figure 2 (The writing in the middle).

[0127] The read port is used to acquire data.

[0128] The decoder is used to parse the target field in the instruction. The target field consists of the target field module index and the register file number.

[0129] The write port is used to determine the data path based on the target domain module index, and then send the data to the register file corresponding to the register number through the data path.

[0130] In addition, the target field consists of multiple target field module indexes and register file numbers.

[0131] The write port is used to determine each data path based on the index of each target domain module. Data is then simultaneously sent to the register file corresponding to each register number through each data path.

[0132] like Figure 3 As shown, the functional unit also includes: an arithmetic unit.

[0133] A decoder is used to parse the computational requirements in instructions.

[0134] The write port is used to perform calculations on data by the arithmetic logic unit (ALU) based on computational needs. The calculation results obtained by the ALU are sent to the register file corresponding to the register number through the data path.

[0135] In a practical implementation, a vector processor will also include: a vector program control unit, a register file stack, and scalar registers, such as... Figure 6 As shown.

[0136] In addition, the vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0137] 1. Vector Program Control Unit

[0138] Vector program control unit, used for instruction fetching and instruction issuing.

[0139] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0140] The vector program control unit is also used to control instruction jumps.

[0141] The vector program control unit has scalar computation capabilities.

[0142] The vector program control unit interacts with the scalar register.

[0143] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0144] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0145] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0146] 2. Register file stack

[0147] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0148] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0149] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data in the register file stack.

[0150] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0151] Taking other processing processors as examples, such as scalar processors, the synchronization unit of a scalar processor can write data to the register file, and the register file can also receive status information from the synchronization unit of the scalar processor to query whether the data has been written.

[0152] The depth of the register file heap is configurable.

[0153] Figure 6 A schematic diagram of a vector processor is shown, comprising four vector operation units, four vector interleaving units, and four vector access units.

[0154] The vector processor provided in this embodiment supports the VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0155] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0156] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0157] Other processing units perform read or write operations on the vector register.

[0158] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0159] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0160] This embodiment provides a vector processor. The functional units in the vector processor can obtain data while parsing the target field in the instruction. The target field consists of a target field module index and a register file number. The data path is determined according to the target field module index. The data is sent to the register file corresponding to the register number through the data path. Thus, the data transmission can be completed with a single instruction. Compared with the prior art, this reduces the execution time of one instruction and improves the transmission efficiency.

[0161] Based on the same inventive concept of data transmission methods, this embodiment provides a high-performance processor, which includes a scalar processor and a vector processor.

[0162] In this configuration, scalar processors and vector processors share memory. Furthermore, vector processors can only access memory and are executed solely by scalar processors.

[0163] A connection is established between scalar processors and vector processors. For example, scalar processors and vector processors can be connected via a dedicated instruction channel.

[0164] In addition, a high-performance processor may include two registers: one for the scalar processor and the other for the vector processor. The vector processor can read and write its corresponding register, while the scalar processor can read and write both its corresponding register and the register corresponding to the vector processor.

[0165] Scalar processors can read and write the registers of vector processors.

[0166] The scalar processor establishes a connection with global memory.

[0167] (a) Scalar Processor

[0168] See Figure 7The scalar processor may include: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0169] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0170] 1. Instruction Fetch Unit

[0171] The instruction fetch unit is used to fetch and dispatch instructions.

[0172] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0173] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetching. It also receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially searches for one or more instructions from the qualified instructions, performs decoding and related checks, and dispatches the qualified instructions in sequence. At most, it dispatches one program control unit instruction and one synchronization unit instruction at a time. In addition, it can dispatch one or more scalar arithmetic unit instructions and one or more memory access unit instructions at a time.

[0174] 2. Register renaming unit

[0175] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0176] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to the arithmetic reserved stack unit, and stores them in one or more of the following: the program control unit, and the synchronization unit.

[0177] For example, the register renaming unit in a scalar processor is used to receive instructions dispatched by the instruction fetch unit and rename registers and special vector registers, decode instruction conditions, generate pipeline congestion signals, and simultaneously receive data from execution units (such as scalar arithmetic units, memory access units, program control units, and synchronization units) to write back registers, special vector registers, condition registers, and status flag registers and write them back to the corresponding registers.

[0178] Scalar processors support out-of-order write-back, resulting in high execution efficiency. They also distribute instructions to the arithmetic stack, storage stack, program control unit, or synchronization unit.

[0179] The register renaming unit bandwidth can be 6 bits, during which multiple (e.g., 4) input instructions can be valid at the same time.

[0180] There can be multiple condition registers, which are located in the register renaming unit.

[0181] The instructions for the scalar arithmetic unit and memory access unit support reading and writing condition registers.

[0182] The instructions for the synchronization unit support reading the condition register.

[0183] The program control unit's jump and function call instructions support reading the condition register.

[0184] When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

[0185] In other words, the condition register is not renamed; when a read / write request occurs, a dispatch blocking mechanism is triggered to wait. The conditions register read / write rules are as follows:

[0186] ●Reading rules:

[0187] (1) All instructions in the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0188] (2) The scalar arithmetic unit also supports read condition register instruction operations.

[0189] (3) The jump and function call instructions of the program control unit support reading condition register operations.

[0190] ●Write the rules:

[0191] (1) The scalar arithmetic unit supports the write condition register instruction.

[0192] (2) Scalar arithmetic unit logic and comparison instructions support the option to write to the condition register.

[0193] When a previously issued instruction to write to the condition register has not yet finished executing, and another instruction to read or write to the same condition register enters, the pipeline becomes congested, generating a condition execution block signal, and waits for the previous condition register to finish writing.

[0194] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0195] Each of the following physical registers can be one of the following: scalar physical register, vector physical register, condition register, or flag register.

[0196] Any logic register can be one of the following: scalar logic register or vector logic register.

[0197] For example, a register renaming unit contains one or more physical registers, such as multiple 512-bit special vector registers, multiple condition registers, and a status flag register.

[0198] Among them, the special vector register is renamed, while the condition register and status flag register are not renamed.

[0199] There are multiple logical registers, such as read-only registers and multiple vector logical registers.

[0200] In addition, the mapping relationship between logical registers and physical registers is maintained by a register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by a special vector register mapping table.

[0201] 1) Register Map Table

[0202] Initially, the mapped physical registers for all entries corresponding to logical register indices in the register map are all 0. When an instruction is executed, or when an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries corresponding to the allocated logical register indices in the register map is updated to the identifier of the relevant physical register.

[0203] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping relationship between all logical registers and all physical registers. Initially, the register map table is invalid, and all entries mapping physical registers are 0. When a physical register is allocated to a logical register, the entry in the register map table corresponding to the logical register index is changed to the ID of that physical register.

[0204] It should be noted that the register map is only updated when an instruction is actually executed. If the conditional execution instruction is not executed, the register map will not be updated. In addition, the register map will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register map to ensure that the interrupt can return normally.

[0205] 2) Special Vector Register Mapping Table

[0206] Initially, the mapped vector physical registers for all entries corresponding to vector logical register indices in the special vector register map are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logical register indices in the special vector register map is updated to the identifier of the relevant vector physical register.

[0207] For example, the special vector register map table, with a depth of 4 bits and a width of 3 bits, stores the mapping relationship between all vector logic registers and all vector physical registers. Initially, the special vector register map table is invalid, and all entries mapping to vector physical registers are 0. When a vector physical register is allocated to a vector logic register, the entry in the special vector register map table corresponding to the vector logic register index is changed to the ID of that vector physical register.

[0208] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0209] 3. Operations retain stack units

[0210] The operation-reserved stack unit is the issue queue of scalar operation units.

[0211] The arithmetic stack is used to receive instructions, dispatch and rename information from the register renaming unit and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution.

[0212] The stack space is reserved for operations and is also used to decode input instructions and store instruction type information.

[0213] In other words, the arithmetic reserve stack is the dispatch queue of the scalar arithmetic unit. The arithmetic reserve stack receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions onto the scalar arithmetic unit for execution. The arithmetic reserve stack decodes the input instructions and stores the instruction type information.

[0214] In practice, the depth of the operation reserve stack can be flexibly adjusted, such as a depth of 8. Multiple scalar operation units share one operation reserve stack unit.

[0215] The rules for issuing and receiving instructions that reserve stack space are as follows:

[0216] (1) The output of the register renaming unit enters the operation retention stack unit.

[0217] (2) When there is any free scalar arithmetic unit, it will fetch instructions and operands from the arithmetic reserve stack and execute them.

[0218] (3) The principle of fetching instructions from the operation reserved stack is to fetch executable instructions that can be sent from the operation reserved stack in the order from front to back.

[0219] (4) Whether it is possible to send a value based on the values ​​of all source registers or special vector registers or condition registers and status flag registers is ready to be determined.

[0220] (5) If there are multiple instructions that can be sent, send the oldest instruction first according to the order of instructions.

[0221] (6) If any scalar arithmetic unit is blocked, it can no longer receive new instructions.

[0222] (7) If the instruction previously sent to any scalar arithmetic unit was a division instruction, a new division instruction can only be sent to it after the division result is calculated and the calculation completion En signal is returned.

[0223] 4. Store and retain stack units

[0224] The storage-reserved stack unit is the issue queue for memory access units.

[0225] The storage retains stack units for receiving instructions and register renaming information from the register renaming unit and pushing them into the queue.

[0226] The storage reserve stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and to save the read address operand.

[0227] The register renaming unit is also used to calculate the address after the instruction has fetched the address, decode the address, and save the decoded information.

[0228] The register renaming unit is also used to detect when the existence source register of any instruction is ready and the address decoding is complete, and then issue it to the memory access unit for execution.

[0229] In practice, the depth of the memory reservation stack unit can be flexibly adjusted, such as 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the issue queue for memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit obtains the address, it can calculate the address and decode the address, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready in the memory reservation stack unit and the address decoding is complete, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checks, address comparison checks, and address forward checks.

[0230] The rules for storing and reserving stack cells for sending and receiving instructions are as follows:

[0231] (1) The output of the register renaming unit enters the memory retention stack unit.

[0232] (2) Once the source operand for the calculated address is ready, calculate the memory access address and store it in the memory reservation stack.

[0233] (3) Address-independent instructions: can be out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions can all be sent out of order. Write instructions after write instructions need to be ordered (cannot be sent to different memory access units at the same time). Even if the address-independent write instructions are written after write instructions, the order still needs to be maintained.

[0234] (4) Address-related instructions: The order of read instruction followed by write instruction, write instruction followed by read instruction, write instruction followed by write instruction, and read instruction followed by read instruction must be guaranteed.

[0235] (5) When addresses are unrelated but are located in the same memory space as all instructions that have not been successfully sent (i.e. instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level), they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0236] (6) Only one memory access instruction located in the same memory space but with unrelated addresses can be sent at the same time. Two or more memory access units cannot be sent at the same time.

[0237] (7) Address correlation judgment principle: whether addresses are related is determined by whether they are located in different storage spaces. If they are located in the same storage space, the address correlation is determined by the data granularity.

[0238] 5. Scalar Operation Unit

[0239] In a practical implementation, there can be one or more scalar operation units.

[0240] For example, a scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0241] The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform operations on the data based on the instructions, and write the operation result back to the register renaming unit.

[0242] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the arithmetic stack, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0243] The following are some example instructions. In actual implementation, the instructions are not limited to these, nor is it limited to including all of them.

[0244] Instructions at execution level 1 include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point max / min instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction instructions, and Rounding instructions.

[0245] Instructions with an execution level of three include: fixed-point multiplication instructions, fixed-to-floating-point conversion instructions, bit filtering instructions, count instructions, and floating-point addition and subtraction instructions.

[0246] Instructions that support bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0247] The execution cycle of a division instruction is indeterminate and depends on the data of the divisor and dividend. Upon completion, the instruction generates a DivEn instruction, indicating its completion and outputting the result to the register file. No new division instructions can be input during the execution of a division instruction, but other scalar computation unit instructions can be input. The output result of the division is multiplexed with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar computation unit instructions, the division outputs its result and simultaneously outputs the DivEn flag. This DivEn flag is output to the arithmetic reserve stack, indicating that Div instructions can continue to be output to the current scalar computation unit.

[0248] 6. Memory access unit

[0249] In a practical implementation, there can be one or more memory access units.

[0250] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0251] The memory access unit is used to receive instructions, data, and register information sent by the memory-reserved stack unit, and to read and write the data based on the instructions and register information.

[0252] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0253] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0254] 7. Program Control Unit

[0255] In practice, there is only one program control unit.

[0256] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0257] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing times.

[0258] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0259] 8. Synchronization Unit

[0260] In practice, there is only one synchronization unit.

[0261] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0262] like Figure 8 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0263] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0264] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0265] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0266] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Out) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0267] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate the ExeStall signal affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0268] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit):

[0269] The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0270] The query vector processor execution status function supports option B.

[0271] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. Reading / writing the FIFO will wait until success, or the result of reading / writing the FIFO successfully or unsuccessfully will be written back to the register.

[0272] Write register file stack functionality, including special vector register write or register write.

[0273] The function allows reading and writing scalar registers, including reading and writing immediate indexes or register indexes.

[0274] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0275] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0276] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0277] 9. Production line control unit

[0278] The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0279] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0280] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0281] In addition, scalar processors can also perform conditional execution decoding in practical applications. For example, when performing conditional execution decoding, a scalar processor checks the preset bits of the instruction to determine the execution condition. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. Here, a null instruction represents an empty instruction or an invalid instruction.

[0282] If a read / write operation is active in the condition register, pipeline blocking is triggered, waiting for the condition register write operation to complete before the read operation can proceed. There is no bypass for condition register reads and writes.

[0283] Taking two condition registers, namely condition register 0 and condition register 1, with the preset bits [29:28] as an example, when the scalar processor performs conditional execution decoding, it judges the execution conditions of the input instruction based on the [29:28] bits of the instruction set encoding. If the conditions are met, a valid instruction is output; otherwise, a null instruction is output.

[0284] In this instruction, bits [29:28] being 00 indicates that condition register 0 is 1 and the instruction is executed; bits [29:28] being 01 indicates that condition register 1 is 1 and the instruction is executed; bits [29:28] being 10 indicates that condition register 0 is executed; and bits [29:28] being 11 indicates that the instruction is executed without conditions. If the conditions are not met, the instruction is invalid and an empty instruction is output.

[0285] If there is a read / write dependency in the condition register, pipeline blocking is triggered, and the read operation is performed only after the condition register has been written. There is no bypass for condition register read / write operations.

[0286] (II) Vector Processor

[0287] In practical implementation, a vector processor can be as follows: Figure 6 As shown, the implementation details of the vector processor can also be found in... Figure 6 The embodiments shown are illustrated and will not be repeated here. For example, the vector processor includes a cluster of functional units.

[0288] This functional unit cluster includes: multiple functional units.

[0289] There is a data path between any two functional units in the functional unit cluster, or there is no data path.

[0290] This functional unit is as follows Figure 2 As shown in embodiment 3, it includes: a reading port (i.e. Figure 2 (read port), decoder and write port (i.e.) Figure 2 (The writing in the middle).

[0291] The read port is used to acquire data.

[0292] The decoder is used to parse the target field in the instruction. The target field consists of the target field module index and the register file number.

[0293] The write port is used to determine the data path based on the target domain module index, and then send the data to the register file corresponding to the register number through the data path.

[0294] In addition, the target field consists of multiple target field module indexes and register file numbers.

[0295] The write port is used to determine each data path based on the index of each target domain module. Data is then simultaneously sent to the register file corresponding to each register number through each data path.

[0296] like Figure 3 As shown, the functional unit also includes: an arithmetic unit.

[0297] A decoder is used to parse the computational requirements in instructions.

[0298] The write port is used to perform calculations on data by the arithmetic logic unit (ALU) based on computational needs. The calculation results obtained by the ALU are sent to the register file corresponding to the register number through the data path.

[0299] Based on the scalar processors and vector processors described above, high-performance processors can, as... Figure 9 As shown.

[0300] This embodiment provides a high-performance processor. The functional unit in the high-performance processor can obtain data while parsing the target field in the instruction. The target field consists of a target field module index and a register file number. The data path is determined according to the target field module index. The data is sent to the register file corresponding to the register number through the data path. Thus, the data transmission can be completed with a single instruction. Compared with the prior art, this reduces the execution time of one instruction and improves the transmission efficiency.

[0301] Based on the same inventive concept of data transmission method, this embodiment provides an electronic device that includes a high-performance processor, or the electronic device includes one or more processor clusters, wherein each processor cluster includes multiple high-performance processors.

[0302] Among them, high-performance processors can be such as Figure 9 As shown, the implementation details of high-performance processors can also be seen as follows: Figure 9 The embodiments shown are illustrated and will not be repeated here. For example, the high-performance processor includes a scalar processor and a vector processor.

[0303] The vector processor includes a cluster of functional units.

[0304] This functional unit cluster includes: multiple functional units.

[0305] There is a data path between any two functional units in the functional unit cluster, or there is no data path.

[0306] This functional unit is as follows Figure 2 As shown in embodiment 3, it includes: a reading port (i.e. Figure 2 (read port), decoder and write port (i.e.) Figure 2 (The writing in the middle).

[0307] The read port is used to acquire data.

[0308] The decoder is used to parse the target field in the instruction. The target field consists of the target field module index and the register file number.

[0309] The write port is used to determine the data path based on the target domain module index, and then send the data to the register file corresponding to the register number through the data path.

[0310] In addition, the target field consists of multiple target field module indexes and register file numbers.

[0311] The write port is used to determine each data path based on the index of each target domain module. Data is then simultaneously sent to the register file corresponding to each register number through each data path.

[0312] like Figure 3 As shown, the functional unit also includes: an arithmetic unit.

[0313] A decoder is used to parse the computational requirements in instructions.

[0314] The write port is used to perform calculations on data by the arithmetic logic unit (ALU) based on computational needs. The calculation results obtained by the ALU are sent to the register file corresponding to the register number through the data path.

[0315] This embodiment provides an electronic device in which a functional unit can obtain data while parsing the target field in an instruction. The target field consists of a target field module index and a register file number. A data path is determined based on the target field module index. Data is sent to the register file corresponding to the register number through the data path, and the data transmission can be completed with a single instruction. Compared with the prior art, this reduces the execution time of one instruction and improves transmission efficiency.

[0316] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0317] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0318] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0319] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0320] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0321] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data transmission method, characterized in that, The method includes: While acquiring data, the target field in the instruction is parsed; wherein, the target field consists of the target field module index and the register file number; Based on the target domain module index, the functional unit interconnection table is queried to determine whether a valid data path exists; wherein, the functional unit interconnection table is used to describe whether a data path exists between any two functional units in the functional unit cluster; If a valid data path exists, the data is sent to the register file corresponding to the register file number through the data path and the write port of the target functional unit, including: parsing the calculation requirements in the instruction; calculating the data based on the calculation requirements, and then sending the calculation result of the data to the register file corresponding to the register file number through the data path; Each of the aforementioned functional units includes a write port; the write port is configured to, after receiving data, send the data to the register file of one or more target functional units via a data path according to the functional unit interconnection table; or, after receiving data, obtain the calculation result of the data through an arithmetic unit, and send the calculation result to the register file of one or more target functional units via a data path according to the functional unit interconnection table.

2. The method according to claim 1, characterized in that, The target field consists of multiple target field module indexes and multiple register file numbers; The step of determining the data path based on the target domain module index includes: Based on the index of each target domain module, each data path is determined separately; Sending the data to the register file corresponding to the register file number through the data path includes: The data is simultaneously sent to the register file corresponding to each register file number through each data path.

3. A functional unit, characterized in that, The functional unit includes a read port, a decoder, and a write port; the write port is configured to, after obtaining data, send the data to the register file of one or more target functional units through a data path according to the functional unit interconnection table; or, after obtaining data, obtain the calculation result of the data through the arithmetic unit, and send the calculation result to the register file of one or more target functional units through a data path according to the functional unit interconnection table. The read port is used to acquire data; The decoder is used to parse the target field in the instruction; wherein the target field consists of the target field module index and the register file number; The write port is used to query the functional unit interconnection table according to the target domain module index to determine whether there is a valid data path; wherein, the functional unit interconnection table is used to describe whether there is a data path between any two functional units in the functional unit cluster; If a valid data path exists, the data is sent to the register file corresponding to the register file number through the data path and the write port of the target functional unit, including: parsing the calculation requirements in the instruction; calculating the data based on the calculation requirements, and then sending the calculation result of the data to the register file corresponding to the register file number through the data path.

4. The functional unit according to claim 3, characterized in that, The target field consists of multiple target field module indexes and register file numbers; The write port is used to determine each data path according to the index of each target domain module; and to send the data to the register file corresponding to each register file number through each data path.

5. The functional unit according to claim 3, characterized in that, The functional unit further includes: an arithmetic unit; The decoder is used to parse the computational requirements in the instructions; The write port is used to perform calculations on the data by the arithmetic unit based on the computational requirements; and to send the calculation results obtained by the arithmetic unit to the register file corresponding to the register file number through the data path.

6. A functional unit cluster, characterized in that, The functional unit cluster includes: a plurality of functional units as described in any one of claims 3-5; There may be a data path between any two functional units in the functional unit cluster, or there may be no data path.

7. A vector processor, characterized in that, include: The functional unit cluster as described in claim 6.

8. A high-performance processor, characterized in that, include: The vector processor and scalar processor as described in claim 7; A read-first-in-first-out FIFO unit and a write-FIFO unit are provided between the vector processor and the scalar processor; Both the vector program control unit and the scalar processor perform read operations on the read FIFO unit and write operations on the write FIFO unit.

9. An electronic device, characterized in that, include: The high-performance processor of claim 8; or, comprising one or more processor clusters, wherein each processor cluster includes a plurality of the high-performance processors of claim 8.

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