Testing device, testing method and testing system for integrated circuit communication bus

Abstract

The invention discloses a testing device, a testing method and a testing system for an integrated circuit communication bus, and relates to the technical field of computer communication and electronic testing, the testing device comprises a microcontroller and a bus expansion module which are electrically connected, the microcontroller sends a test control signal to the bus expansion module, the bus expansion module generates a bus abnormal signal, and the bus abnormal signal is sent to the microcontroller. The microcontroller receives a bus abnormal signal and inputs the bus abnormal signal into the to-be-tested device, the to-be-tested device generates test data according to the bus abnormal signal, the bus abnormal signal at least comprises an abnormal interrupt signal, and the microcontroller dynamically adjusts the test control signal according to the test data fed back by the to-be-tested device so as to continue the test. By introducing the multi-channel bus expansion module with special programmable control capability and combining the intelligent interpretation capability of the microcontroller, the multi-channel polling test is realized, and various bus abnormal signals, especially interrupt signals, can be accurately generated and injected in real time, so that the robustness and other characteristics of equipment to be tested are comprehensively evaluated.

Description

Technical Field

[0001] The present application relates to the field of computer communication and electronic testing technology, and in particular to a testing device for an integrated circuit communication bus, a testing method for an integrated circuit communication bus, and a testing system for an integrated circuit communication bus. Background Art

[0002] As modern electronic devices such as servers, intelligent hardware, and industrial control systems increasingly demand greater stability and reliability from the I2C bus, comprehensive and efficient testing of the I2C bus has become crucial. However, existing I2C bus testing methods generally have the following shortcomings:

[0003] 1. Low test efficiency and limited coverage: Traditional I2C bus testing relies heavily on manual intervention or static settings, resulting in lengthy and inefficient testing processes. Especially when simulating abnormal operating conditions, test scenarios are not fully covered, making it difficult to discover potential design flaws and compatibility issues.

[0004] 2. Insufficient anomaly simulation capabilities: Existing methods struggle to accurately simulate complex anomalies that can occur in actual I2C bus operation, such as microsecond-level timing violations, waveform distortion caused by voltage fluctuations, or signal glitches caused by transient interference. In particular, they are often unable to proactively and dynamically generate and inject non-standard I2C communication signals (such as precisely controlled clock stretching timeouts and data setup / hold time violations) or interrupt signals of non-standard durations.

[0005] 3. Difficulty in fault diagnosis and location: After discovering abnormal equipment behavior, traditional methods often find it difficult to quickly and accurately diagnose the cause of the fault and locate the problem point, and largely rely on the engineer's experience and time-consuming manual troubleshooting. Summary of the Invention

[0006] The present application provides a testing device, a testing method and a testing system for an integrated circuit communication bus, so as to at least solve the problem in the related art that the bus test scenarios are not fully covered and abnormal signals cannot be accurately injected, resulting in inaccurate bus robustness evaluation.

[0007] The present application provides a testing device for an integrated circuit communication bus, comprising: a microcontroller, configured to generate a test control signal and dynamically adjust the test control signal according to test data fed back by a device under test, so as to determine a test result of the device under test; a bus extension module, electrically connected to the microcontroller, configured to generate at least one bus abnormality signal according to the test control signal sent by the microcontroller, and input the bus abnormality signal into the device under test, so that the device under test generates the test data according to the bus abnormality signal, wherein the bus abnormality signal is a simulated abnormal signal of the bus of the device under test, and the bus abnormality signal includes at least an abnormal interrupt signal.

[0008] The present application also provides a method for testing an integrated circuit communication bus, which is applied to a microcontroller in any one of the integrated circuit communication bus testing devices. The method includes: determining multiple test scenarios, and determining corresponding test control signals based on the test scenarios; sending the test control signal to a bus extension module, so that the bus extension module generates at least one bus abnormality signal based on the test control signal, and causes the bus extension module to input the bus abnormality signal into the device under test, wherein the bus abnormality signal is an abnormal signal of the bus of the simulated device under test, and the bus abnormality signal at least includes an abnormal interrupt signal; receiving test data fed back by the device under test, and dynamically adjusting the test control signal based on the test data to determine the test result of the device under test.

[0009] The present application also provides a testing system for an integrated circuit communication bus, comprising: a device to be tested; a testing device for an integrated circuit communication bus of any one type, electrically connected to the device to be tested; an oscilloscope, electrically connected to the device to be tested, for detecting the bus waveform of the device to be tested in real time; and a host computer, communicatively connected to the testing device for the integrated circuit communication bus, for displaying the test results of the device to be tested.

[0010] Through this application, the microcontroller sends a test control signal to the bus extension module, the bus extension module generates a bus abnormality signal, and inputs the bus abnormality signal into the device under test. The device under test generates test data based on the bus abnormality signal. The bus abnormality signal at least includes an abnormal interrupt signal. The microcontroller dynamically adjusts the test control signal based on the test data fed back by the device under test to continue testing. By introducing a multi-channel bus extension module with special programmable control capabilities and combining it with the intelligent interpretation capability of the microcontroller, multi-channel polling testing is achieved, and a variety of bus abnormality signals, especially interrupt signals, can be accurately and in real time generated and injected, thereby comprehensively evaluating the robustness and other characteristics of the device under test, thereby solving the problem in the related art that the bus test scenario coverage is not comprehensive and the abnormal signal cannot be accurately injected, resulting in inaccurate bus robustness evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic structural diagram of a test device for an integrated circuit communication bus provided in an embodiment of the present application;

[0013] Figure 2 A schematic diagram of the interface structure of a test device for an integrated circuit communication bus provided in an embodiment of the present application;

[0014] Figure 3 A schematic diagram of the interface structure of another integrated circuit communication bus testing device provided in an embodiment of the present application;

[0015] Figure 4 A schematic structural diagram of a real integrated circuit communication bus testing device provided in an embodiment of the present application;

[0016] Figure 5 A schematic diagram of the structure of a device under test provided in an embodiment of the present application;

[0017] Figure 6 A schematic structural diagram of another integrated circuit communication bus testing device provided in an embodiment of the present application;

[0018] Figure 7 A flowchart of a method for testing an integrated circuit communication bus provided in an embodiment of the present application;

[0019] Figure 8A schematic diagram of an I2C bus communication anomaly detection and processing flow provided in an embodiment of the present application;

[0020] Figure 9 A flowchart of an interrupt handling mechanism in I2C bus communication provided by an embodiment of the present application;

[0021] Figure 10 A schematic structural diagram of a test system for an integrated circuit communication bus provided in an embodiment of the present application.

[0022] The above drawings include the following reference numerals:

[0023] 01. Test device for integrated circuit communication bus; 02. Device under test; 03. Oscilloscope; 04. Host computer; 10. Microcontroller; 11. Main control interface; 12. General-purpose input and output pins; 20. Bus expansion module; 21. Abnormal signal input interface; 22. Interrupt signal input interface; 23. Abnormal signal output interface; 231. Bus output interface; 2311. Clock signal output interface; 2312. Data signal output interface; 232. Interrupt signal output interface. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the integrated circuit communication bus test method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0028] The embodiment of the present application provides a test device 01 for an integrated circuit communication bus, such as Figure 1 As shown, it includes: a microcontroller 10 and a bus extension module 20, wherein the microcontroller 10 is used to generate a test control signal and dynamically adjust the test control signal according to the test data fed back by the device under test 02 to determine the test result of the device under test 02; the bus extension module 20 is electrically connected to the microcontroller 10, and the bus extension module 20 is used to generate at least one bus abnormality signal according to the test control signal sent by the microcontroller 10, and input the bus abnormality signal into the device under test 02, so that the device under test 02 generates test data according to the bus abnormality signal. The bus abnormality signal is an abnormal signal of the bus of the simulated device under test 02, and the bus abnormality signal at least includes an abnormal interrupt signal.

[0029] The microcontroller generates a series of signals to control the test process. These signals direct the bus expansion module to transmit normal and abnormal communication signals. Test control signals contain specific test instructions, such as read and write operations, interrupt signal generation, and abnormal signal type and parameter settings. The microcontroller unit (MCU) dynamically adjusts subsequent test control signals in real time based on feedback from the device under test (DUT) during testing. This means that if the DUT performs poorly under specific abnormal signals, the MCU can adjust the abnormal signal strength, type, or frequency to further test the device's robustness and fault tolerance. The MCU analyzes the received feedback data to determine whether the DUT can correctly respond to various normal and abnormal communication signals. If the DUT maintains communication stability and data accuracy under abnormal signals, it indicates good robustness; otherwise, it may indicate a design flaw or compatibility issue.

[0030] The bus expansion module is an I2C (Inter-Integrated Circuit) bus expansion module. It receives test control signals from the MCU and, according to instructions, generates and injects at least one bus anomaly signal into the DUT. These anomaly signals simulate various non-ideal communication conditions that the DUT may encounter in real-world applications, such as abnormal interruptions, timing errors, and signal glitches, to test the DUT's response and processing capabilities. The bus expansion module inputs the generated anomaly signal into the DUT's communication bus, forcing the DUT to generate feedback data under abnormal conditions. For example, when simulating an abnormal interrupt signal, the DUT may need to reinitialize communications, record error logs, or execute error recovery procedures after receiving the interrupt. The feedback data indicates its response.

[0031] The device / board under test (DUT) is any electronic device with multiple I2C buses and associated interrupt input pins.

[0032] In digital communications, interrupt signals are often used to notify the receiving end of an event, such as data readiness or an abnormal condition. In this test setup, abnormal interrupt signals are those that do not conform to the communication protocol standard. For example, an interrupt may last too long, be triggered at the wrong time, or have a level change that does not meet protocol requirements. By injecting these abnormal interrupt signals, the DUT's ability to respond and handle non-standard interrupt conditions can be tested.

[0033] The MCU automatically interprets feedback data from the DUT, not only to determine whether communication is successful, but more importantly, to analyze the specific behavior patterns of the DUT under abnormal conditions (for example, whether it immediately restarts, hangs, experiences data transmission errors, or is able to self-recover and record error logs).

[0034] The MCU combines its own recorded anomaly injection information (when and what anomaly was injected into which channel) with the DUT's response to perform preliminary fault location and cause analysis. For example, if a specific channel frequently fails under a specific anomaly injection, the MCU can mark the channel as "abnormally sensitive" or indicate a possible hardware or software design flaw.

[0035] In the test device for the integrated circuit communication bus of the present application, the microcontroller sends a test control signal to the bus extension module, the bus extension module generates a bus abnormality signal, and inputs the bus abnormality signal into the device under test. The device under test generates test data based on the bus abnormality signal. The bus abnormality signal includes at least an abnormal interrupt signal. The microcontroller dynamically adjusts the test control signal based on the test data fed back by the device under test to continue the test. By introducing a multi-channel bus extension module with special programmable control capabilities and combining it with the intelligent interpretation capability of the microcontroller, multi-channel polling testing is achieved, and a variety of bus abnormality signals, especially interrupt signals, can be accurately and in real time generated and injected, thereby comprehensively evaluating the robustness and other characteristics of the device under test, thereby solving the problem in the related art that the bus test scenario coverage is not comprehensive and the abnormal signal cannot be accurately injected, resulting in inaccurate bus robustness evaluation.

[0036] Among them, the above-mentioned embodiment can solve the problems of low efficiency, insufficient abnormality simulation capability, and difficulty in fault diagnosis in existing I2C bus testing methods. By introducing a multi-channel I2C bus expansion module with special programmable control capabilities and combining it with the intelligent interpretation capability of a microcontroller, it can realize parallel, independent, or synchronous testing of multiple I2C buses and their accompanying interrupt signals, and can accurately and real-timely generate and inject various I2C bus abnormality signals, thereby comprehensively evaluating the robustness and other characteristics of the device under test.

[0037] In some embodiments, such as Figure 2As shown, the microcontroller 10 further includes: at least one main control interface 11, electrically connected to the bus expansion module 20, for sending control instructions and receiving test data, where the control instructions are signals for controlling the bus expansion module 20 to generate a bus abnormality signal; and at least one general-purpose input / output pin 12, electrically connected to the bus expansion module 20, for sending first abnormality information and second abnormality information, where the first abnormality information includes information about a bus abnormality signal generated by the bus expansion module 20 that is not an abnormal interrupt signal, and the second abnormality information includes information about an abnormal interrupt signal generated by the bus expansion module 20.

[0038] The master control interface 11 is an I2C master control interface, used as an I2C master controller to communicate data and control commands with the I2C bus expansion module. One or more general-purpose input / output (GPIO) pins 12 are used to send (or simulate) reference interrupt signals or other auxiliary test control signals to the I2C bus expansion module. The microcontroller also has an embedded control program for generating I2C test signals according to test requirements, precisely controlling I2C bus timing and interrupt signal output, and automatically interpreting received test data. Alternatively, the microcontroller can be replaced with a central processing unit (CPU). Based on preset or dynamically adjusted test scenarios, the microcontroller can precisely control the bus expansion module to generate and inject various non-standard I2C communication signals and / or interrupt signals of non-standard durations on designated I2C channels in real time. Furthermore, the microcontroller can automatically interpret feedback data from the device under test (DUT) and perform preliminary fault behavior pattern analysis and fault location based on the type and timing of injected anomalies and the DUT's response.

[0039] The microcontroller 10 sends detailed control instructions to the bus extension module 20 through the main control interface 11. These instructions contain specific parameters for generating specific types of bus abnormality signals, such as the size of the timing deviation, the duration of the signal glitch, etc. In this way, the bus extension module 20 can accurately simulate various abnormal working conditions according to the instructions of the microcontroller, increasing the accuracy and complexity of the test. The main control interface 11 is also used to receive test data returned from the device under test 02. These data reflect the processing results of the DUT after experiencing the bus abnormality signal, including but not limited to data integrity, error code, communication status, etc. The microcontroller judges whether the response of the DUT meets expectations based on these data, thereby evaluating its robustness and compatibility. In addition, the MCU has built-in algorithms or logic that can generate specific patterns of composite abnormalities. For example, while injecting clock stretching timeouts, it can also inject instantaneous glitches on the data line to simulate more complex bus failure scenarios.

[0040] In addition to sending control commands via the host control interface 11, the microcontroller can also send first and second anomaly information directly to the bus expansion module 20 via the general-purpose input / output pin 12. These signals contain additional information about the bus anomaly signal, such as the duration of the interrupt signal or the trigger conditions for injecting the anomaly signal at specific timing points. This allows the microcontroller to more precisely control the anomaly simulation process, ensuring the diversity and accuracy of test scenarios. By using the general-purpose input / output pin 12 to send first and second anomaly information, the test system can cover a wider range of more complex abnormal operating conditions. This includes not only anomalies within the protocol's permitted range, but also extreme cases that exceed protocol limits, greatly enriching the test scenarios and improving test comprehensiveness. The injection of first and second anomaly information helps evaluate the robustness of the DUT under non-standard or extreme conditions, namely its ability to maintain stable operation and data integrity in the face of various communication anomalies. This evaluation is crucial for ensuring device reliability in real-world application environments, such as those in the presence of noise or timing deviations.

[0041] Specifically, the microcontroller can actively simulate and inject I2C communication signals exhibiting abnormal timing, including but not limited to clock stretching timeouts, data setup / hold violations, signal glitches, or transient interference. It can also generate interrupt signals whose duration exceeds the threshold specified by the I2C bus protocol (for example, 25ms for a standard 20ms). The microcontroller (MCU) works in conjunction with the I2C bus expansion module to precisely generate and inject these abnormal signals.

[0042] By combining the microcontroller's host control interface 11 and general-purpose input / output pins 12, the entire test system achieves refined simulation and intelligent control of IC communication bus anomalies. This highly integrated and programmable test approach comprehensively and efficiently detects and verifies the DUT's behavior and performance under a variety of non-ideal communication environments. Furthermore, it facilitates automated fault diagnosis, reducing the time and resources required for manual troubleshooting and improving overall test efficiency and quality.

[0043] As the main control unit, the MCU's embedded control program precisely controls I2C bus timing and interrupt signal output, enabling accurate simulation of abnormal signals. The MCU also automatically interprets received test data, improving test efficiency and objectivity. Furthermore, it can generate I2C test signals based on test requirements, including normal read and write operations and abnormal signal injection.

[0044] In some embodiments, such as Figure 2As shown, the test control signal includes first abnormality information and second abnormality information. The first abnormality information includes information about a bus abnormality signal generated by the bus extension module 20 that is not an abnormal interrupt signal. The second abnormality information includes information about an abnormal interrupt signal generated by the bus extension module 20. The bus extension module 20 includes:

[0045] The abnormal signal input interface 21 is electrically connected to the microcontroller 10 and is used to receive the first abnormal information;

[0046] an interrupt signal input interface 22, electrically connected to the microcontroller 10, for receiving second abnormality information;

[0047] Multiple groups of abnormal signal output interfaces 23 are used to electrically connect to the device under test 02. Each group of abnormal signal output interfaces 23 includes multiple bus output interfaces 231 and an interrupt signal output interface 232. The bus output interface 231 is used to output bus abnormality signals that are not abnormal interrupt signals, and the interrupt signal output interface 232 is used to output abnormal interrupt signals.

[0048] The I2C bus expansion module is connected to the I2C master interface of the microcontroller and has an abnormal signal input interface 21 and an interrupt signal input interface 22, as well as several independent bus output interfaces 231 and several independent interrupt signal output interfaces 232. The abnormal signal input interface can be regarded as an I2C input interface, and the bus output interface can be regarded as an I2C output interface.

[0049] The I2C bus expansion module can be programmed and controlled by a microcontroller to independently enable / disable bus output interface 231 and several independent interrupt signal output interfaces 232, perform independent address routing, and independently or synchronously transmit test signals and simulate interrupt signals. More importantly, it works in conjunction with the microcontroller to proactively and precisely generate and inject a variety of I2C bus anomaly signals onto specific channels within the bus output interfaces and the terminal signal output interface.

[0050] The first exception information contains bus exception signal information related to non-abnormal interrupt signals. This information instructs the bus expansion module on how to simulate and generate bus-level exceptions during normal communication, such as data setup time violations, hold time errors, signal glitches, and clock stretch timeouts. In this way, the tester can carefully examine the DUT's response to signals outside the standard communication bus signal range, assessing its stability and data integrity in non-ideal communication environments.

[0051] The second type of abnormal information specifically involves the generation of abnormal interrupt signals. This information includes information such as the interrupt signal's non-standard timing, duration, and level. It is intended to test the device's behavior and robustness when handling abnormal interrupt requests. The injection of abnormal interrupt signals helps evaluate the device's interrupt management mechanisms, including interrupt response efficiency and its ability to handle prolonged interrupts. This is crucial for ensuring the device's stability and security in the face of emergencies.

[0052] Through the abnormal signal input interface 21 and the interrupt signal input interface 22, the bus extension module 20 can independently receive and process two types of abnormal information, which means that it can simultaneously generate and inject two different types of abnormal signals, providing a more complex and realistic test scenario. This separation design improves the flexibility of the test and allows the tester to conduct more in-depth analysis and verification for specific abnormal situations. Each group of abnormal signal output interfaces 23 includes multiple bus output interfaces 231 and an interrupt signal output interface 232. This design allows the bus extension module 20 to poll and output abnormal signals on multiple independent bus channels, thereby testing the anti-interference ability and resource allocation efficiency of the integrated circuit in multi-channel communication. This architecture enables each group of abnormal signal output interfaces to independently control the output of bus abnormal signals and interrupt abnormal signals, allowing the tester to set unique test scenarios and abnormal conditions for each channel. This highly customized testing capability helps to discover the weaknesses of individual devices or specific channels, ensuring the robust operation of the entire system under various abnormal conditions.

[0053] In some embodiments, such as Figure 3 As shown, a group of abnormal signal output interfaces 23 includes multiple bus output interfaces, which are respectively a clock signal output interface 2311 and a data signal output interface 2312 , and the communication addresses of any two groups of abnormal signal output interfaces 23 are different.

[0054] Different abnormal signal output interfaces correspond to different communication channels and are designed to be brought out through a test fixture or connector, allowing for flexible connection to multiple I2C buses and their corresponding interrupt GPIO interfaces on the board under test (DUT).

[0055] The microcontroller can control the selection of different I2C channels (i.e., a group of abnormal signal output interfaces) for testing. Through the programmable multi-channel I2C bus expansion module, efficient and automated polling testing of multiple I2C bus channels can be achieved, eliminating the need for frequent manual switching, significantly shortening the test cycle, and reducing testing costs and manpower requirements.

[0056] Separating the clock signal output interface and data signal output interface into two independent interfaces allows the tester to independently control and simulate anomalies for the clock signal (Clock Synchronization, SCL) and the data signal (Serial Data Line, SDA). This means that anomalies such as clock stretch timeouts and clock signal glitches can be injected independently on the clock line, while anomalies such as data setup time violations and data hold time violations can be injected independently on the data line. Compound anomalies can also be generated collaboratively between the two, providing more refined and customized test scenarios.

[0057] Any two sets of abnormal signal output interfaces have different communication addresses, meaning each set can independently communicate with the specific communication channel of the device under test without interfering with each other. In I2C bus communication, different devices are identified by unique addresses. Therefore, abnormal signal output interfaces with different addresses can accurately locate different devices or channels under test, enabling multi-channel selective polling testing, improving the targetedness and automation of testing.

[0058] Since the communication address of each group of abnormal signal output interfaces is independent, the tester can simulate complex communication sequences and observe the response of the device under test by sending abnormal signals to the abnormal signal output interfaces with different communication addresses one by one or in a specific sequence. This is very important for discovering potential communication sequence dependency issues, timing sensitivity issues, and interactivity issues between devices.

[0059] When a communication problem is discovered on a specific channel during testing, the unique communication address of each group of interfaces allows the specific channel or device to be quickly located, eliminating the need for additional diagnostic steps to identify the affected device, greatly simplifying the troubleshooting process.

[0060] By injecting abnormal signals separately or jointly on channels with different communication addresses, the test device can comprehensively evaluate the robustness and compatibility of the device under normal communication and various abnormal conditions, ensuring that the device can maintain stable operation in complex and changing environments.

[0061] In some embodiments, the bus extension module is used to output an abnormal interrupt signal to the device under test through an interrupt signal output interface. The abnormal interrupt signal is a low-level pulse signal with a first duration, and the first duration is greater than the duration of the interrupt signal that enables the device under test to maintain normal communication.

[0062] The generation of abnormal interrupt signals involves generating interrupt signals with non-standard durations. This involves proactively generating and outputting interrupt signals with durations exceeding the I2C bus protocol threshold (e.g., 25ms). This verifies the response and robustness of the electronic device under test (DUT) when subjected to conditions exceeding the I2C bus standard or encountering abnormal disturbances. The I2C bus expansion module can be programmed through the MCU to output a low-level pulse on the designated INTx pin with a duration (e.g., 25ms) that is longer than the typical I2C device interrupt signal (e.g., 10ms). This tests the DUT's response to abnormal interrupts.

[0063] By outputting low-level pulse signals of unusually long duration as interrupt signals, the bus expansion module can simulate extreme conditions outside the standard or normal operating range. The injection of these abnormal interrupt signals is crucial for testing the DUT's response and recovery capabilities in the face of prolonged interruptions. These prolonged abnormal interrupt signals help verify the DUT's fault tolerance and recovery strategies. Under normal circumstances, a device should exhibit a certain degree of interruption tolerance, meaning it should be able to automatically restore communication after a short interruption. However, when the interrupt signal duration exceeds the normal range, the device's recovery mechanism becomes challenged. The test results can be used to assess the device's fault tolerance performance under extreme conditions.

[0064] Different devices or designs may have different tolerances for interrupt signal durations. By injecting interrupt signals with durations longer than the normal range, the compatibility of the device under test with different standards or devices can be evaluated, especially in multi-device or complex systems.

[0065] By outputting low-level pulses of unusually long duration as interrupt signals, the bus expansion module can deeply test the robustness of the device under test under extreme conditions, including identifying interrupt sensitivity, verifying fault tolerance mechanisms, evaluating compatibility, and promoting robustness improvements. This testing strategy is crucial for ensuring the device's continued operation in a variety of non-ideal communication scenarios, thereby improving overall system stability and reliability.

[0066] In some embodiments, the bus abnormality signal includes a clock timeout signal, an abnormal timing signal, an interference signal, and a circuit fault signal. The clock timeout signal is a signal whose low level duration exceeds the maximum time threshold of the bus protocol. The abnormal timing signal is a data signal or clock signal whose timing causes the device under test to incorrectly identify data. The circuit fault signal is a bus disconnect signal or a bus short circuit signal.

[0067] A clock timeout occurs when the clock signal (SCL) on the bus remains low for a duration exceeding the maximum time threshold specified by the bus protocol. For example, in the I2C bus, if the clock signal remains low for significantly longer than the standard timing, it is considered a clock timeout. By simulating clock timeouts that exceed protocol limits, the responsiveness and robustness of the device under test (DUT) are tested under extreme conditions. This test determines whether the device can maintain normal communication functionality even when the clock signal remains low for an extended period, and whether it can perform appropriate error handling and recovery actions in the event of a timeout.

[0068] Abnormal timing signals occur when data or clock signals do not adhere to fixed or protocol-specified timing rules during transmission, causing the device under test to misread or fail to interpret data. For example, the data line SDA may not stabilize before the rising edge of the clock line, or may change state too quickly after the falling edge, violating setup and hold time requirements. By testing the device under test's performance under abnormal timing signals, we can verify its sensitivity to timing, particularly its behavior at timing edge conditions.

[0069] Interference signals are unexpected, brief voltage fluctuations or pulses injected into data or clock lines. They simulate real-world electromagnetic interference and power supply fluctuations to assess the communication bus's anti-interference capabilities. The test examines the DUT's response to circuit faults (such as open or short circuits) to determine whether it can detect the fault and take appropriate protection or error recovery measures.

[0070] By injecting the above four types of bus abnormality signals, the test device can comprehensively evaluate the robustness, compatibility, anti-interference capability, and fault response mechanism of the integrated circuit communication bus under various abnormal and extreme conditions. The above embodiment can not only verify the normal read and write functions of the I2C bus, but also accurately simulate and inject abnormal timing and status of I2C bus communication or interrupt signals (such as interrupt time limit exceedance, timing distortion, signal interference), thereby systematically evaluating the robustness of the device under test under non-ideal conditions. This makes it possible to discover potential design defects and compatibility issues that are difficult to detect with traditional test methods, and comprehensively improves test coverage. It can flexibly set and test potential interference or competition issues under multi-channel parallel communication, ensuring the stability of I2C communication in complex systems.

[0071] In some embodiments, the bus extension module is used to generate a low-level signal, and the duration of the low-level signal exceeds the maximum time threshold of the bus protocol to generate a clock timeout signal, and the clock signal is a signal of the serial clock signal line; the bus extension module is used to generate a clock signal with a first abnormal timing, and / or generate a data signal with a second abnormal timing to generate an abnormal timing signal, and the data signal is a signal of the serial data signal line; the bus extension module is used to inject a pulse of a preset width and a preset amplitude onto the serial clock signal line and / or the serial data signal line to generate an interference signal.

[0072] Among them, the clock signal line provides a clock signal for synchronizing the data transmission of all devices on the I2C bus. The master device generates this clock signal, and the slave device synchronizes the reception and transmission of data based on this clock signal.

[0073] Therefore, by maintaining a specific low-level state on the clock signal line for a duration exceeding the maximum threshold specified by the I2C protocol (for example, injecting a 25ms clock stretching timeout while the protocol specifies 20ms), the clock stretching timeout condition on the serial clock signal line (SCL) is accurately simulated to obtain a clock timeout signal.

[0074] Test the device's response to prolonged clock stretching timeouts. Ideally, the device should be able to detect this anomaly and take appropriate action, such as error handling, communication retry, or entering safe mode. By observing the device's handling mechanisms, you can assess the design's robustness and fault tolerance and implement optimizations where necessary, such as enhancing timeout detection logic or refining error recovery strategies.

[0075] Specifically, the MCU sends a command to the I2C bus expansion module. The module's internal logic or programmable GPIO takes over control of the SCL line of a specific channel. During data transmission, the module forces the SCL line low for a preset duration (e.g., 25ms), exceeding the maximum clock stretching allowed by the I2C protocol, before releasing the SCL line. The DUT's response to this non-standard clock stretching (e.g., hang-up, timeout error, or communication anomaly) is recorded and analyzed by the MCU.

[0076] Data is transmitted on another line, the Serial Data Line (SDA), but the validity of the data is tied to the state of SCL. Typically, data on SDA can only change when SCL is low, and data on SDA must remain stable when SCL is high. This timing control ensures that data can be read and written normally.

[0077] Therefore, abnormal timing signals are actually violations of data setup or hold time. By precisely adjusting the relative timing of the serial data line and the SCL signal, setup or hold times that do not meet the I2C protocol requirements are intentionally created. Verify the device's data reception capabilities under timing anomalies, including deviations from key timing parameters such as data setup time and hold time. Ensure that the device can communicate correctly with other devices or systems with even slight timing deviations.

[0078] Interference signals inject brief voltage pulses or dips into the SDA or SCL lines, simulating physical noise or interference. This test verifies whether the pulses on the signal lines affect data integrity and whether the device can identify and filter out these interference signals, maintaining communication quality. This test also demonstrates the device's data transmission accuracy and ability to recover from transient interference.

[0079] Specifically, each I2C channel of the I2C bus expansion module can integrate a controllable transient voltage generator or a high-speed switch controlled by the MCU to briefly inject a pulse with a preset width (e.g., tens of nanoseconds to several microseconds) and amplitude on the SDA or SCL line to simulate transient interference.

[0080] For circuit fault signals, the SDA / SCL signal line is forced to be pulled low or left floating to simulate a bus short circuit or open circuit fault, thereby obtaining a circuit fault signal.

[0081] By injecting clock timeouts, abnormal timing, and interference signals, the bus expansion module can comprehensively test the performance of the communication bus in the face of various software anomalies and physical interference. It can achieve in-depth testing of the integrated circuit communication bus under complex and extreme conditions, promote the optimization of equipment design, and improve the communication quality and reliability of the equipment.

[0082] In the event of a violation of the analog data setup time and hold time, the bus extension module 20 is configured to change the state of the data signal within a first preset time period before reaching the rising edge of the clock signal to generate an abnormal timing signal, where the first preset time period is less than the data stabilization time period, which is the time period during which the data signal is stable; and / or, the bus extension module 20 is configured to change the state of the data signal within a second preset time period after reaching the falling edge of the clock signal to generate the abnormal timing signal, where the second preset time period is less than the time period during which data of the data signal is completely acquired.

[0083] Specifically, the MCU uses the I2C bus expansion module to precisely control the switching timing of the SDA and SCL signals on a specific channel. For example, the SDA signal's stabilization time can be advanced or delayed before the rising edge of the SCL signal, causing it to fail the setup time requirement specified by the I2C protocol. Alternatively, the SDA signal's state can be changed too early or too late after the falling edge of the SCL signal, causing it to fail the hold time requirement. The module can incorporate a built-in programmable delay unit or use high-speed GPIOs to precisely control these microsecond-level timings.

[0084] Within a first preset time interval before the rising edge of the clock signal (SCL), the bus expansion module 20 changes the state of the data signal (SDA). This first preset time interval is intentionally set to be shorter than the data settling time (i.e., the minimum time during which data must remain unchanged until the rising edge of the clock signal arrives), resulting in instability in the data signal during the setup period. This tests the device's ability to receive and process data when this setup time is violated. The device should be able to identify this error and take appropriate action, such as retrying communication, logging the error, or implementing other fault tolerance strategies.

[0085] During a second preset duration after the falling edge of the clock signal, bus expansion module 20 changes the state of the data signal. This second preset duration is shorter than the time required for complete data acquisition (i.e., the data must remain constant until a period after the falling edge of the clock signal), resulting in instability in the data signal during the hold period. This test verifies that the device can correctly transmit and interpret data even with the shortened data hold time. This type of test is crucial for ensuring device compatibility and data integrity under timing edge conditions.

[0086] By deliberately introducing anomalies in data setup and hold timing, the tester can deeply assess the timing sensitivity of the device under test, especially under high-speed communication or timing-critical conditions. This type of testing reveals potential design weaknesses, prompting the development team to optimize the device's timing management strategy and improve its robustness to timing variations. Verifying that the device under test can correctly handle data signals at the edge of the I2C protocol standard is crucial for ensuring compatibility with a variety of standard and non-standard devices in real-world applications.

[0087] By intentionally violating standards for data setup and hold timing, the bus expansion module generates abnormal timing signals that enable detailed testing of the integrated circuit communication bus. This helps developers evaluate the device's timing robustness and data transmission quality, while also promoting design improvements and optimizations to ensure stable operation in complex and changing communication environments.

[0088] In some embodiments, the microcontroller is also used to determine the target abnormal signal output interface of the bus extension module, the bus output interface in the target abnormal signal output interface is an interface that actually outputs the bus abnormality signal that is not an abnormal interrupt signal to the device under test, the interrupt signal output interface in the target abnormal signal output interface is an interface that actually outputs the abnormal interrupt signal to the device under test, and the target abnormal signal output interface is one or more.

[0089] The microcontroller intelligently selects and controls the target abnormal signal output interface in the bus expansion module, ensuring that the abnormal signal is accurately injected into the intended communication path of the device under test. Testers precisely send abnormal signals to specific I2C channels or interrupt lines, avoiding the redundancy and unnecessary complexity that would result from indiscriminate testing across the entire range. The microcontroller's intelligent decision-making enables selective abnormal signal injection, significantly accelerating the test process and reducing unnecessary waiting time and wasted resources.

[0090] The microcontroller can dynamically adjust the target abnormal signal output interface according to test needs. This means that not only can testing be performed on a single channel, but it can also seamlessly switch to other channels and even inject abnormal signals on multiple channels simultaneously, enhancing the flexibility and coverage of the test. By leveraging the parallel nature of the target abnormal signal output interface, abnormal signal injection testing can be performed simultaneously on multiple I2C channels, greatly improving the parallel processing capability of the test and shortening the overall test cycle. By synchronously or asynchronously injecting abnormal signals on multiple channels, the test device can evaluate the robustness and anti-interference capabilities of the device under test at the entire system level, ensuring that the device can still operate stably in complex multi-device communication environments.

[0091] During testing, the microcontroller records the anomaly type, injection time, and duration of each target abnormal signal output interface, as well as the device's response, providing detailed data support for subsequent fault analysis and repair. Because the microcontroller clearly records the specific injection path and timing of each abnormal signal, testers can more accurately locate the specific location and moment of the fault, accelerating the diagnosis process.

[0092] In some embodiments, the bus expansion module 20 includes a bus multiplexer and / or an integrated circuit switch.

[0093] The bus expansion module utilizes off-the-shelf I2C bus multiplexers or integrated circuit switches to implement independent control and routing of multi-channel I2C buses. This module not only provides multiple I2C outputs, but more importantly, it can be programmed by the MCU to enable / disable each channel independently, perform independent address routing, and inject abnormal signals on specific channels.

[0094] The bus multiplexer and integrated circuit switch components enable independent control and switching of multiple I2C bus channels, enabling the test system to simultaneously test multiple devices or multiple interfaces on a single device. This significantly improves test efficiency by eliminating the need to manually switch test devices or channels, saving significant test preparation and switching time. The bus multiplexer and integrated circuit switch can be programmably controlled by the microcontroller 10, enabling refined management and routing of I2C bus signals (including the clock signal SCL and data signal SDA). This means the test system can freely choose which signals pass through which channels and when to route signals to specific I2C lines, greatly enhancing test customization and controllability.

[0095] The use of a bus multiplexer and integrated circuit switch makes the hardware design of bus expansion module 20 more compact and efficient. This modular architecture not only facilitates maintenance and upgrades, but also simplifies the overall design of the test setup, reducing the required external wiring and system complexity. The combination of the bus multiplexer and integrated circuit switch enables the test system to dynamically inject abnormal signals into a specific I2C channel at any time without pausing the entire test process.

[0096] Figure 4 The figure is a structural diagram of a real integrated circuit communication bus test device. Figure 4 As shown, the microcontroller is connected to the positive power supply voltage and outputs clock signals, data signals, reset signals, and interrupt signals to the bus expansion module through general pins. The signals output by the microcontroller to the bus expansion module include information about the channel for outputting abnormal signals and the type and parameters of the abnormal signals to be output. Figure 4 The bus expansion module shown in Figure 1 supports four channels and receives clock, data, reset, and interrupt signals from the microcontroller via universal pins. The first clock signal, first data signal, and first interrupt signal are the clock signal, data signal, and interrupt signal output by the first channel, respectively. The second clock signal, second data signal, and second interrupt signal are the clock signal, data signal, and interrupt signal output by the second channel, respectively. The third clock signal, third data signal, and third interrupt signal are the clock signal, data signal, and interrupt signal output by the third channel, respectively. The fourth clock signal, fourth data signal, and fourth interrupt signal are the clock signal, data signal, and interrupt signal output by the fourth channel, respectively. Each channel can be connected to a device under test, and multiple channels can be polled and enabled to perform polling tests on multiple devices under test. The microcontroller can set which channel to enable and the order in which the multiple channels are enabled. Figure 5 A schematic diagram of the structure of a device under test is shown in FIG. Figure 5As shown, the device under test includes a mainboard equipped with an intelligent baseboard management controller (BMC). The BMC has a clock signal input interface, a data signal input interface, and an interrupt signal input interface. The device under test receives abnormal bus signals sent by the bus expansion module through the clock signal input interface, the data signal input interface, and the interrupt signal input interface.

[0097] Figure 6 This is a structural diagram of another real integrated circuit communication bus test device. Figure 6 As shown, the IC communication bus tester features a universal serial port (USB) input that connects to a microcontroller and bus expansion module. The IC communication bus tester also includes a DC converter module, a power connector, a 3.3V regulated power supply, and six 12V power outputs. The number and voltage of the power supplies can be adjusted based on actual needs. The bus expansion module has four channels: the first bus channel, the second bus channel, the third bus channel, and the fourth bus channel. Abnormal bus signals are transmitted to a device under test (DUT) motherboard via one of these four channels. Each channel can be connected to a DUT motherboard for testing.

[0098] The core I2C bus expansion module in the above embodiment can be flexibly replaced based on the actual number of buses to be tested (for example, from a four-channel IC to a higher-channel IC). The microcontroller, serving as the master control unit, can adapt to different test scenarios and I2C bus configuration requirements through firmware programming. Its modular design accommodates different I2C bus expansion module models, and the MCU firmware is flexibly configurable, making it easily expandable to other serial communication protocols. Without adding additional hardware cost or structural complexity, software programming integrates the hardware features of the existing microcontroller and multi-channel I2C bus switch chip, achieving powerful exception simulation and testing capabilities while avoiding large-scale modifications to the existing test architecture or the introduction of expensive dedicated hardware.

[0099] In addition, the above embodiment is not limited to the robustness test of the I2C bus. Its core principles and architecture can be flexibly extended to the following fields to achieve a wider range of feature injection and detection:

[0100] 1. Robustness and compatibility test of other serial communication protocols:

[0101] SPI (Serial Peripheral Interface): simulates clock phase / polarity anomalies, data sampling timing violations, multi-master contention conflicts, etc.

[0102] UART (Universal Asynchronous Receiver / Transmitter): Simulates baud rate deviation, start / stop bit loss or error, parity error, framing error, etc.

[0103] CAN (Controller Area Network): Simulates network layer anomalies such as bit errors, stuff errors, CRC errors, and ACK errors.

[0104] RS-232 / RS-485: Abnormal analog voltage levels, data bit errors, noise interference, etc.

[0105] Low-level Ethernet (physical layer): simulates physical layer anomalies such as signal attenuation, crosstalk, packet loss, and latency to test the robustness of the PHY chip.

[0106] 2. General hardware / firmware robustness and performance testing:

[0107] Power Management IC (PMIC) testing: Simulates abnormalities in the PMIC control bus (such as PMBus and SMBus) to detect its stability and protection mechanisms under non-standard inputs.

[0108] Sensor interface testing: Inject abnormal signals into digital sensor interfaces such as I2C and SPI to evaluate the accuracy and reliability of sensor data in harsh environments.

[0109] Fault injection in safety-critical systems: In fields such as aerospace, medical equipment, and automotive electronics, I2C bus faults are injected to verify the effectiveness of the system's safety mechanisms (such as fault isolation and fault tolerance) under fault conditions.

[0110] Inter-processor communication (IPC) testing: This test simulates I2C or SPI communication anomalies between different processors to evaluate the communication robustness of multi-core or distributed systems.

[0111] Peripheral driver development and verification: When developing new hardware drivers, accelerate the driver's error handling logic and robustness verification by actively injecting I2C exceptions.

[0112] 3. Product manufacturing testing and quality assurance:

[0113] During final inspection or online testing on the product production line, standard, boundary-condition I2C anomalies can be quickly injected to screen out devices with marginal I2C interface performance or potential defects, thereby improving product quality before delivery.

[0114] The embodiment of the present application also provides a test method for an integrated circuit communication bus, which is applied to a microcontroller in any test device for an integrated circuit communication bus, such as Figure 7 As shown, the method includes the following steps:

[0115] Step S101, determining multiple test scenarios, and determining corresponding test control signals according to the test scenarios;

[0116] Step S102: Sending a test control signal to a bus extension module, so that the bus extension module generates at least one bus abnormality signal according to the test control signal, and inputs the bus abnormality signal into the device under test, wherein the bus abnormality signal is a simulated abnormal signal of a bus of the device under test, and the bus abnormality signal includes at least an abnormal interrupt signal;

[0117] Step S103 : receiving test data fed back by the device under test, and dynamically adjusting the test control signal according to the test data to determine a test result of the device under test.

[0118] Before testing, the MCU, I2C bus expansion module, device under test (DUT), and test result display and analysis unit must be electrically connected. The MCU controls the I2C bus expansion module through programming, selecting the I2C channel to be tested and setting communication parameters. The I2C bus module and the DUT's I2C are connected via a cable. The MCU then issues commands through the I2C bus module to select or switch I2C channels for communication with the DUT.

[0119] Before testing, one or more test scenarios must be preset in the microcontroller, including normal communication testing and at least one I2C bus anomaly verification condition. The I2C bus anomaly verification condition is a specific test parameter designed to assess the DUT's robustness to non-ideal I2C bus behavior.

[0120] According to the preset test program, the microcontroller sends test instructions (such as data reading and writing, register configuration) to the target I2C bus of the electronic device under test through the I2C bus expansion module.

[0121] The microcontroller receives feedback data from the electronic device under test and automatically interprets it to determine whether the read data meets expectations and whether the response of the device under test to the injected abnormal signal meets its robustness design goals.

[0122] The test result display and analysis unit (oscilloscope) displays the SDA / SCL waveforms of the I2C bus in real time, allowing testers to conduct intuitive timing verification and signal quality analysis, especially when abnormal simulations occur, to observe waveform changes and device responses.

[0123] The microcontroller also performs comprehensive fault diagnosis and precise positioning based on automated data interpretation results and waveform analysis to determine whether the I2C bus design under test strictly complies with standard specifications, as well as its reliability and robustness under various complex or abnormal conditions.

[0124] In the above-mentioned test method of the present application, the microcontroller sends a test control signal to the bus extension module, the bus extension module generates a bus abnormality signal, and inputs the bus abnormality signal into the device under test. The device under test generates test data based on the bus abnormality signal. The bus abnormality signal at least includes an abnormal interrupt signal. The microcontroller dynamically adjusts the test control signal based on the test data fed back by the device under test to continue the test. By introducing a multi-channel bus extension module with special programmable control capabilities and combining it with the intelligent interpretation capability of the microcontroller, multi-channel polling testing is achieved, and a variety of bus abnormality signals, especially interrupt signals, can be accurately and in real time generated and injected, thereby comprehensively evaluating the robustness and other characteristics of the device under test, thereby solving the problem in the related art that the bus test scenario coverage is not comprehensive and the abnormal signal cannot be accurately injected, resulting in inaccurate bus robustness evaluation.

[0125] In some embodiments, the test control signal includes first exception information and second exception information, the first exception information including information about a bus exception signal generated by the bus extension module that is not an exception interrupt signal, and the second exception information including information about an exception interrupt signal generated by the bus extension module. The corresponding test control signal is determined based on the test scenario, including at least one of the following:

[0126] In the case where the test scenario is a clock timeout scenario, determining a duration of a low level of the clock timeout signal, obtaining first abnormality information, and the duration exceeds a maximum time threshold of a bus protocol of the device under test;

[0127] When the test scenario is an abnormal timing scenario, determining a first abnormal timing of a clock signal and a second abnormal timing of a data signal to obtain first abnormal information, where the clock signal is a signal of a serial clock signal line, and the data signal is a signal of a serial data signal line;

[0128] When the test scenario is an interference scenario, determining a preset width and a preset amplitude of the interference pulse to obtain first abnormality information;

[0129] In the case where the test scenario is a circuit fault scenario, determining a signal type of the circuit fault signal, obtaining first abnormality information, the signal type being a bus disconnection signal or a bus short circuit signal;

[0130] When the test scenario is a signal interruption scenario, the abnormal interruption signal is determined to be a low-level pulse signal with a first duration, and the second abnormal information is obtained. The first duration is greater than the duration of the interruption signal that enables the device under test to maintain normal communication.

[0131] Specifically, when executing test scenarios containing abnormal verification conditions, the MCU precisely controls the I2C bus expansion module to generate and inject simulated I2C bus abnormal signals (such as clock stretch timeout, signal glitches, data setup / hold time violations) or interrupt signals with non-standard durations on specific I2C channels in real time.

[0132] Among them, to simulate complex interrupt timing anomalies, the microcontroller is set to apply non-standard interrupt signal timing to the interrupt input interface of the device under test through the I2C bus expansion module. For example, a simulated interrupt signal with a duration exceeding the I2C bus specification threshold (such as 25ms) is generated.

[0133] Alternatively, simulate fine-grained I2C communication waveform anomalies by precisely injecting brief disturbances on the I2C data or clock lines, forcing the signal low, or fine-tuning the timing to the edge of the protocol (for example, intentionally creating data setup / hold time violations).

[0134] By setting the non-abnormal interrupt signal (i.e., standard interrupt signal) generated by the bus expansion module and the clock timeout signal exceeding the maximum time threshold of the I2C protocol, the DUT's handling mechanism and robustness under conditions of excessively long clock lows (SCL held low for too long) can be tested. This verifies the effectiveness of the DUT's clock timeout protection mechanism and whether it can correctly restore communication under extreme clock timeout conditions, avoiding system deadlock or abnormal suspension.

[0135] Accurately identify abnormal timing for clock and data signals, i.e., deviations from the normal protocol behavior for the serial clock (SCL) and serial data (SDA) lines. This allows for testing the DUT's sensitivity to timing violations, including setup and hold time anomalies, and assessing its stability and compatibility in edge-of-timing situations.

[0136] Generate interference pulses with preset width and amplitude to simulate noise or transient disturbances at the physical layer. Test the DUT's anti-interference capabilities to ensure it maintains communication accuracy even when encountering minimal interference in real-world environments.

[0137] Simulate bus open or short circuit faults to test the DUT's hardware-level fault detection and handling capabilities. Verify the DUT's robustness to circuit faults, such as its ability to identify faults and take appropriate measures to prevent data corruption or system crashes.

[0138] Set interrupt signals with non-standard durations, such as low-level pulse signals that last beyond the threshold that the DUT can normally handle. Evaluate the DUT's response to abnormal interrupt signals, especially its ability to handle extremely long interrupt signals, to ensure that it can maintain communication continuity and system stability under non-standard interrupt conditions.

[0139] Through these tests, we can systematically verify and optimize the performance of the DUT under complex or abnormal operating conditions, ensuring its stable operation in real-world application environments and meeting expected robustness and compatibility requirements. This testing approach not only improves test efficiency but also expands test coverage, enabling the timely detection and correction of design defects, thereby improving the overall quality and reliability of the product.

[0140] In some embodiments, the test control signal includes a control instruction, and the corresponding test control signal is determined according to the test scenario, including: determining at least one test channel of the device to be tested according to the test scenario, obtaining a control instruction, the communication addresses of any two test channels are different, and the control instruction is used to control the bus extension module to output the bus abnormality signal using the target abnormality signal output interface corresponding to the test channel.

[0141] That is, exception injection can be used to perform independent testing on a single channel or to perform polling testing on multiple channels.

[0142] Based on pre-set test scenarios, the microcontroller (MCU) identifies at least one test channel for the device under test and generates corresponding control instructions. This enables precise control of a specific I2C channel, allowing it to inject abnormal signals into that channel without disrupting normal communication on other channels, testing its robustness and exception handling capabilities.

[0143] Multiple test channels are independent of each other, and the microcontroller controls multiple channels for polling testing, thereby improving the level of test automation.

[0144] The MCU uses control instructions to select the target abnormal signal output interface corresponding to the test channel and output the bus abnormal signal. This provides a flexible test strategy that can dynamically adjust the abnormal signal type, intensity, and target channel according to different test scenarios, achieving a more comprehensive and detailed robustness assessment.

[0145] After receiving control commands, the bus expansion module outputs preset bus abnormality signals, such as clock stretching timeouts, data setup / hold time violations, and signal glitches, through the target abnormality signal output interface. This simulates various abnormal conditions that the I2C bus may encounter in actual operation, verifying the performance of the device under test under non-standard communication conditions, and helping to identify potential design flaws or compatibility issues.

[0146] In summary, by using control instructions to dynamically configure and operate the bus expansion module, this embodiment can effectively perform accurate abnormal signal simulation and robustness testing on different I2C channels, thereby significantly improving the efficiency, accuracy, and flexibility of testing. It provides a comprehensive test solution for the I2C bus design of electronic devices, which helps to improve product quality and reliability.

[0147] In some embodiments, dynamically adjusting the test control signal according to the test data includes: adjusting the signal type, signal strength, occurrence time and signal quantity of the bus abnormality signal according to the test data to obtain an updated abnormality signal to dynamically adjust the test control signal.

[0148] The MCU can dynamically adjust the type, intensity, timing, and channel of anomaly injection based on real-time feedback from the device under test (DUT) or pre-set test sequences. For example, if the DUT exhibits instability in response to a specific anomaly, the MCU can automatically adjust the anomaly parameters or switch to other related anomaly types for deeper testing, simulating the complex chain reactions of real-world scenarios.

[0149] Test data collected during the test process (including DUT response, error rate, communication latency, etc.) is used to analyze the current robustness and anomaly sensitivity of the DUT. Based on the test data feedback, the MCU can intelligently adjust the parameters of the abnormal signal, including signal type (such as clock stretching and data glitches), signal strength (such as voltage fluctuation amplitude), occurrence time (when the anomaly is injected), and signal quantity (number of injections within the test cycle), to more accurately evaluate the DUT's performance under various specific abnormal conditions. This adaptive test strategy enables more precise and in-depth testing of DUT weaknesses or specific abnormal scenarios, helping to discover problems that are difficult to expose under fixed test conditions, further optimizing test efficiency and quality.

[0150] By continuously adjusting abnormal signal parameters and gradually approaching the DUT's extreme operating conditions, it's possible to more quickly identify the signal types and intensities that are the key factors causing DUT performance degradation or failure. This accelerates problem location, reduces ineffective testing, and allows engineers to focus on abnormal conditions that truly impact system stability and reliability, thereby speeding up problem analysis and resolution.

[0151] Dynamically adjusting the abnormal signal means that a variety of abnormal types and intensities can be covered in a single test. This is more comprehensive than using only preset fixed abnormal signals and enables a more systematic check of the robustness of the DUT. This significantly enhances the comprehensiveness and depth of testing, avoids test blind spots, ensures that the DUT can be fully verified during the design phase, and reduces potential quality issues in production.

[0152] The method of dynamically adjusting the test control signal not only improves the flexibility and efficiency of the test, but also greatly enriches the test scenarios. It helps to verify the robustness of the I2C bus of electronic devices more comprehensively and in-depth, and provides strong support for product quality control and design optimization.

[0153] In some specific test experiments, the test platform is first built, and the MCU, I2C bus expansion module, and multiple DUTs (such as I2C sensors, EEPROM, and PMIC) are connected and powered on. The PC host software then loads the test firmware into the MCU.

[0154] Next, configure the exception test scenario. On the PC interface, select the I2C channels to be tested (for example, Channel A and Channel C) and configure the exception injection type, for example, "Channel A: Clock stretch timeout (25ms); Channel C: SDA signal glitch (100ns width)." You can also set whether the MCU automatically switches to the next exception scenario or repeatedly injects the current exception after detecting a DUT communication error.

[0155] The automated test process then begins. The MCU begins sending normal I2C read and write commands to the DUT on Channel A. At a specific moment or when a condition triggers, the MCU instructs the I2C bus expansion module to precisely inject a 25ms clock stretch timeout on Channel A. The MCU simultaneously begins sending commands to the DUT on Channel C and, during communication, randomly or periodically injects 100ns glitches into the SDA line. The oscilloscope is triggered to capture the I2C waveform during the injection of the anomaly for manual analysis.

[0156] Finally, the MCU monitors the responses of each DUT in real time. If the DUT of channel A can still respond correctly after the clock stretching timeout, but there is an internal log recording timeout error, it is judged as "robustness is good and anomalies can be recorded." If it cannot respond, it is judged as "poor robustness." If the DUT of channel C has a data error or no response after the glitch injection, the MCU will record the error type and time, display the error information on the PC interface, and mark the DUT of channel C as "sensitive to SDA glitches." The PC host software will summarize all test results and generate a report, including key indicators such as the abnormal injection type, number of injections, DUT response, error rate, etc. of each channel.

[0157] Figure 8 The following is a flow chart of I2C bus communication abnormality detection and processing. Figure 8 As shown, the process first confirms IIC bus master transmission, then prepares the IIC bus for data transmission, sends the slave address, enables and waits for interrupts (enables clock signal low-level timeout), and then checks whether the IIC bus has timed out. If so, it determines that the return value is IIC bus_error_retry, indicating an error return. If not, it checks whether it has woken up from a clock signal low-level timeout. If so, it resets the bus and confirms the return value is IIC bus_error_retry, indicating an error return. If not, it confirms a normal return.

[0158] The above process ensures the security and integrity of communications during I2C data transmission while detecting and responding to Clock Low Timeout.

[0159] Figure 9 It is an interrupt handling mechanism in I2C bus communication, used to monitor and ensure the smooth progress of data transmission, especially when encountering possible communication anomalies. Figure 9 As shown, the IIC bus interrupt handler first checks whether data transmission and reception are normal. If so, it processes the next batch of data or completes the process (waking up the host for transmission). If not, it checks whether the data is erroneous. If so, it wakes up the host for transmission. If not, it checks whether the low level of the clock signal has timed out. If so, it wakes up the host for transmission. If not, the interrupt returns.

[0160] The above process is a key step in ensuring data transmission quality and system stability in I2C bus communication. By monitoring communication status in real time and quickly responding to anomalies, it improves overall communication efficiency and reliability, providing a solid guarantee for high-performance communication in electronic devices.

[0161] The embodiment of the present application also provides a test system for an integrated circuit communication bus, such as Figure 10 As shown, it includes: a device under test 02; a test device 01 of any type of integrated circuit communication bus, electrically connected to the device under test 02; an oscilloscope 03, electrically connected to the device under test 02, for real-time detection of the bus waveform of the device under test 02; and a host computer 04, communicatively connected to the test device 01 of the integrated circuit communication bus, for displaying the test results of the device under test 02.

[0162] The MCU firmware is responsible for generating I2C test logic, controlling the I2C bus expansion module, interpreting test results, and communicating with the user interface. When the MCU precisely injects a specific anomaly, it can trigger an external oscilloscope for synchronized waveform capture, allowing engineers to simultaneously observe the anomaly injection point and the DUT's response waveform details, greatly accelerating fault diagnosis and debugging.

[0163] The electronic device / circuit board under test (DUT) has several I2C bus interfaces and interrupt input interfaces (usually GPIO) associated with the I2C bus functions. The corresponding interfaces of the electronic device under test are connected to the corresponding output interfaces of the I2C bus expansion module.

[0164] The oscilloscope is connected to the I2C bus interface of the DUT to monitor the I2C bus waveform, timing, and signal quality in real time. In particular, when abnormal injection occurs, the waveform details can be captured and displayed synchronously.

[0165] The PC debugging terminal / host computer software communicates with the MCU through interfaces such as UART, USB, or Ethernet. It is used to load test programs, display test results, logs, and error information, and allow users to configure test parameters and exception injection strategies.

[0166] The indicator lights on the I2C bus expansion module provide real-time status information for each communication channel. The system also includes a power supply module and a mechanical structure / housing to provide a stable operating power supply and enclose all components.

[0167] The microcontroller's automated data interpretation capabilities, combined with the test result display unit's real-time waveform monitoring, enable faster and more accurate isolation of issues, such as whether they lie with a specific I2C channel, slave device, or a specific timing anomaly or bus fault, thereby accelerating product debugging and problem resolution. The combination of the MCU's automated data interpretation and real-time waveform monitoring enables faster diagnosis of fault causes and precise location of problem points, reducing the difficulty of troubleshooting.

[0168] The IC communication bus test system integrates multiple components, including the device under test (DUT), an IC communication bus test fixture, an oscilloscope, and a host computer, forming a comprehensive test platform. The system comprehensively evaluates the performance and robustness of the IC communication bus from aspects such as hardware signal waveforms, software data interaction, and protocol compliance. The IC communication bus test fixture enables precise control and injection of various abnormal signals, simulating different failure scenarios and thus providing deeper insights into potential issues with the DUT.

[0169] By using an oscilloscope to monitor and display the bus waveform of the device under test in real time, engineers can visually observe signal quality and timing characteristics, allowing them to quickly diagnose communication issues. The host computer not only displays test results but also performs in-depth data analysis, such as calculating error rates and identifying abnormal patterns, helping engineers quickly understand the behavioral characteristics of the device under test.

[0170] The test system automatically executes pre-defined test sequences, including both normal communication and anomaly injection scenarios, reducing manual operations and improving testing efficiency. The system combines waveform information and test data to analyze fault causes from multiple perspectives, more accurately locating the problem. Based on the results of fault diagnosis, the tester can dynamically adjust its testing strategy, for example, by repeating or enhancing specific anomaly injections until the device's response mechanism is fully understood.

[0171] The above system can be used to inject normal signals that comply with the I2C protocol but are under boundary conditions (for example, the minimum / maximum communication rate allowed by the protocol, the minimum / maximum packet length, or the longest / shortest clock stretch time within the protocol range) to evaluate the compatibility and stability of the DUT under various compliant but extreme I2C communication scenarios.

[0172] Under continuous injection of specific anomalies or high-intensity communication loads, the system can measure key performance indicators such as the DUT's I2C communication throughput, response latency, or error rate. For example, under frequent signal glitch injection, the degree of reduction in I2C communication rate can be used as a quantitative indicator of performance degradation.

[0173] This system can be integrated with or collaborate with an external power measurement module to monitor the DUT's real-time power consumption while injecting anomalies. By analyzing the DUT's power consumption changes under abnormal conditions, its energy efficiency management strategy and energy consumption characteristics under fault conditions can be evaluated.

[0174] For I2C devices involving security-sensitive data, the above system can simulate malicious or unauthorized I2C command injection (for example, injecting incorrect device addresses, forged read / write commands, or illegal data packets) to test the effectiveness of the DUT's I2C communication security protection mechanism, for example, whether it can identify and reject illegal operations or whether it will trigger a security alarm.

[0175] For example, through MCU software programming and combined with the hardware features of the I2C bus expansion module, it is possible to "actively simulate and inject" non-standard / abnormal behaviors into the I2C bus and interrupt signals.

[0176] This combination of hardware and software enables a systematic evaluation of the robustness of the device under test under non-ideal conditions, which is difficult to achieve with traditional testing methods.

[0177] In addition, by utilizing the multi-channel characteristics of the I2C bus expansion module, parallel or efficient automated polling testing of multiple I2C bus channels is achieved, significantly improving test efficiency.

[0178] By collaborating with a programmable MCU and an I2C bus expansion module, various "non-standard" or "abnormal" I2C communication signals and interrupt signals are actively and accurately simulated and injected on a multi-channel I2C bus, thereby systematically evaluating the robustness of the electronic device under test under harsh conditions.

[0179] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0180] An embodiment of the present application also provides a microcontroller, including: a determination unit, a sending unit and a receiving unit, the determination unit is used to determine multiple test scenarios, and determine corresponding test control signals based on the test scenarios; the sending unit is used to send the test control signal to the bus extension module, so that the bus extension module generates at least one bus abnormality signal based on the test control signal, and enables the bus extension module to input the bus abnormality signal into the device under test, the bus abnormality signal is an abnormal signal of the bus of the simulated device under test, and the bus abnormality signal at least includes an abnormal interrupt signal; the receiving unit is used to receive test data fed back by the device under test, and dynamically adjust the test control signal based on the test data to determine the test result of the device under test.

[0181] The above-mentioned microcontroller of the present application sends a test control signal to the bus extension module. The bus extension module generates a bus abnormality signal and inputs the bus abnormality signal into the device under test. The device under test generates test data according to the bus abnormality signal. The bus abnormality signal at least includes an abnormal interrupt signal. The microcontroller dynamically adjusts the test control signal according to the test data fed back by the device under test to continue the test. By introducing a multi-channel bus extension module with special programmable control capabilities and combining it with the intelligent interpretation capability of the microcontroller, multi-channel polling testing is achieved, and a variety of bus abnormality signals, especially interrupt signals, can be accurately and in real time generated and injected, thereby comprehensively evaluating the robustness and other characteristics of the device under test, thereby solving the problem in the related art that the bus test scenario coverage is not comprehensive and the abnormal signal cannot be accurately injected, resulting in inaccurate bus robustness evaluation.

[0182] In some embodiments, the test control signal includes first exception information and second exception information, the first exception information includes information about a bus exception signal that is not an exception interrupt signal generated by the bus extension module, and the second exception information includes information about an exception interrupt signal generated by the bus extension module. The determination unit includes a first determination module, a second determination module, a third determination module, a fourth determination module, and a fifth determination module. The first determination module is used to determine the duration of the low level of the clock timeout signal when the test scenario is a clock timeout scenario, and obtain the first exception information, and the duration exceeds the maximum time threshold of the bus protocol of the device under test; the second determination module is used to determine the first abnormal timing of the clock signal and the second abnormal timing of the data signal when the test scenario is an abnormal timing scenario. The first abnormality information is obtained by the normal timing sequence, where the clock signal is the signal of the serial clock signal line, and the data signal is the signal of the serial data signal line. The third determination module is used to determine the preset width and amplitude of the interference pulse when the test scenario is an interference scenario, thereby obtaining the first abnormality information. The fourth determination module is used to determine the signal type of the circuit fault signal when the test scenario is a circuit fault scenario, thereby obtaining the first abnormality information, where the signal type is a bus disconnect signal or a bus short circuit signal. The fifth determination module is used to determine the abnormal interrupt signal as a low-level pulse signal with a first duration when the test scenario is a signal interruption scenario, thereby obtaining the second abnormality information, where the first duration is greater than the duration of the interrupt signal that enables the device under test to maintain normal communication. By setting the non-abnormal interrupt signal (i.e., standard interrupt signal) generated by the bus expansion module and the clock timeout signal that exceeds the maximum time threshold of the I2C protocol, the DUT's handling mechanism and robustness when encountering excessively long clock lows (SCL low level is held for too long) can be tested.

[0183] In some embodiments, the test control signal includes a control instruction, and the determination unit includes a sixth determination module configured to determine at least one test channel of the device under test based on the test scenario and obtain the control instruction. Any two test channels have different communication addresses, and the control instruction is used to control the bus extension module to output a bus abnormality signal using the target abnormality signal output interface corresponding to the test channel. A microcontroller (MCU) is capable of determining the at least one test channel of the device under test and generating the corresponding control instruction. This enables precise control of a specific I2C channel, allowing the injection of abnormal signals into that channel without interfering with normal communication in other channels, to test its robustness and abnormality handling capabilities.

[0184] In some embodiments, the receiving unit includes an adjustment module for adjusting the signal type, signal strength, occurrence time, and signal quantity of the bus abnormality signal based on test data to obtain an updated abnormality signal for dynamic adjustment of the test control signal. By continuously adjusting the abnormal signal parameters and gradually approaching the extreme operating conditions of the DUT, it is possible to more quickly identify which signal types and strengths are the key factors causing DUT performance degradation or failure.

[0185] For the description of the features in the embodiment corresponding to the microcontroller, reference can be made to the relevant description of the embodiment corresponding to the test method of the integrated circuit communication bus, which will not be repeated here.

[0186] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned integrated circuit communication bus test method embodiments.

[0187] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned integrated circuit communication bus test method embodiments when run.

[0188] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0189] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned integrated circuit communication bus test method embodiments are implemented.

[0190] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned integrated circuit communication bus test method embodiments.

[0191] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] The above is a detailed introduction to a test device for an integrated circuit communication bus, a test method for an integrated circuit communication bus, and a test system for an integrated circuit communication bus provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A test device for an integrated circuit communication bus, characterized in that: include: A microcontroller, configured to generate a test control signal and dynamically adjust the test control signal according to test data fed back by the device under test, so as to determine a test result of the device under test; A bus extension module is electrically connected to the microcontroller, and is used to generate at least one bus abnormality signal according to the test control signal sent by the microcontroller, and input the bus abnormality signal into the device under test, so that the device under test generates the test data according to the bus abnormality signal. The bus abnormality signal is an abnormal signal of the bus of the simulated device under test, and the bus abnormality signal at least includes an abnormal interrupt signal.

2. The test device for an integrated circuit communication bus according to claim 1, wherein: The test control signal includes first abnormality information and second abnormality information, the first abnormality information includes information about the bus abnormality signal generated by the bus extension module, which is not an abnormal interrupt signal, and the second abnormality information includes information about the abnormal interrupt signal generated by the bus extension module, and the bus extension module includes: an abnormal signal input interface, electrically connected to the microcontroller, and configured to receive the first abnormality information; an interrupt signal input interface, electrically connected to the microcontroller, and configured to receive the second abnormality information; Multiple groups of abnormal signal output interfaces are used to electrically connect to the device under test, each group of abnormal signal output interfaces includes multiple bus output interfaces and an interrupt signal output interface, the bus output interface is used to output the bus abnormality signal that is not an abnormal interrupt signal, and the interrupt signal output interface is used to output the abnormal interrupt signal.

3. The test device for an integrated circuit communication bus according to claim 2, wherein: A group of the abnormal signal output interfaces includes a plurality of bus output interfaces, each of which is a clock signal output interface and a data signal output interface. The communication addresses of any two groups of the abnormal signal output interfaces are different.

4. The test device for an integrated circuit communication bus according to claim 2, wherein: The bus extension module is used to output the abnormal interrupt signal to the device under test through the interrupt signal output interface, where the abnormal interrupt signal is a low-level pulse signal with a first duration, and the first duration is greater than the duration of the interrupt signal that enables the device under test to maintain normal communication.

5. The test device for an integrated circuit communication bus according to claim 2, wherein: The bus abnormality signal includes a clock timeout signal, an abnormal timing signal, an interference signal, and a circuit fault signal. The clock timeout signal is a signal whose low level duration exceeds the maximum time threshold of the bus protocol. The abnormal timing signal is a data signal or clock signal whose timing causes the device under test to incorrectly identify data. The circuit fault signal is a bus disconnect signal or a bus short circuit signal.

6. The test device for an integrated circuit communication bus according to claim 5, characterized in that: The bus extension module is used to generate a low-level signal, and the duration of the low-level signal exceeds the maximum time threshold of the bus protocol to generate the clock timeout signal, and the clock signal is a signal of the serial clock signal line; The bus extension module is used to generate a clock signal with a first abnormal timing sequence, and / or generate a data signal with a second abnormal timing sequence, so as to generate the abnormal timing signal, wherein the data signal is a signal of a serial data signal line; The bus extension module is used to inject a pulse of preset width and preset amplitude into the serial clock signal line and / or the serial data signal line to generate the interference signal.

7. The test device for an integrated circuit communication bus according to claim 6, wherein: The bus extension module is configured to change the state of the data signal within a first preset time period before reaching a rising edge of the clock signal to generate the abnormal timing signal, wherein the first preset time period is less than a data stabilization time period, and the data stabilization time period is a time period during which the data signal is stable; and / or, The bus extension module changes the state of the data signal within a second preset time period after reaching the falling edge of the clock signal to generate the abnormal timing signal, and the second preset time period is less than the time period during which data of the data signal is completely collected.

8. The test device for an integrated circuit communication bus according to claim 2, wherein: The microcontroller is also used to determine the target abnormal signal output interface of the bus extension module, the bus output interface in the target abnormal signal output interface is an interface that actually outputs the bus abnormal signal that is not an abnormal interrupt signal to the device under test, the interrupt signal output interface in the target abnormal signal output interface is an interface that actually outputs the abnormal interrupt signal to the device under test, and the target abnormal signal output interface is one or more.

9. The test device for an integrated circuit communication bus according to claim 1, wherein: The bus expansion module includes a bus multiplexer and / or an integrated circuit switch.

10. The test device for an integrated circuit communication bus according to claim 1, wherein: The microcontroller further comprises: at least one main control interface, electrically connected to the bus extension module, and configured to send control instructions and receive the test data, wherein the control instructions are signals for controlling the bus extension module to generate the bus abnormality signal; At least one general-purpose input / output pin is electrically connected to the bus expansion module and is used to send first exception information and second exception information, wherein the first exception information includes information about the bus exception signal generated by the bus expansion module that is not an exception interrupt signal, and the second exception information includes information about the exception interrupt signal generated by the bus expansion module.

11. A method for testing an integrated circuit communication bus, characterized in that: A microcontroller used in the integrated circuit communication bus test device according to any one of claims 1 to 10, wherein the method comprises: Determine a plurality of test scenarios, and determine corresponding test control signals according to the test scenarios; Sending the test control signal to a bus extension module, so that the bus extension module generates at least one bus abnormality signal according to the test control signal, and inputting the bus abnormality signal into the device under test, wherein the bus abnormality signal is a simulated abnormal signal of a bus of the device under test and includes at least an abnormal interrupt signal; Receive test data fed back by the device under test, and dynamically adjust the test control signal according to the test data to determine a test result of the device under test.

12. The method for testing an integrated circuit communication bus according to claim 11, wherein: The test control signal includes first exception information and second exception information, wherein the first exception information includes information about the bus exception signal generated by the bus extension module, which is not an exception interrupt signal, and the second exception information includes information about the exception interrupt signal generated by the bus extension module. The corresponding test control signal is determined according to the test scenario, including at least one of the following: In a case where the test scenario is a clock timeout scenario, determining a duration of a low level of a clock timeout signal to obtain the first abnormality information, wherein the duration exceeds a maximum time threshold of a bus protocol of the device under test; When the test scenario is an abnormal timing scenario, determining a first abnormal timing of a clock signal and a second abnormal timing of a data signal to obtain the first abnormality information, wherein the clock signal is a signal of a serial clock signal line, and the data signal is a signal of a serial data signal line; In a case where the test scenario is an interference scenario, determining a preset width and a preset amplitude of an interference pulse to obtain the first abnormality information; In a case where the test scenario is a circuit fault scenario, determining a signal type of a circuit fault signal to obtain the first abnormality information, the signal type being a bus disconnection signal or a bus short circuit signal; When the test scenario is a signal interruption scenario, the abnormal interruption signal is determined to be a low-level pulse signal with a first duration, and the second abnormal information is obtained. The first duration is greater than the duration of the interruption signal that enables the device under test to maintain normal communication.

13. The method for testing an integrated circuit communication bus according to claim 11, wherein: The test control signal includes a control instruction, and determining a corresponding test control signal according to the test scenario includes: According to the test scenario, at least one test channel of the device under test is determined to obtain the control instruction, wherein the communication addresses of any two of the test channels are different, and the control instruction is used to control the bus extension module to output the bus abnormality signal using the target abnormality signal output interface corresponding to the test channel.

14. The method for testing an integrated circuit communication bus according to claim 11, wherein: Dynamically adjusting the test control signal according to the test data includes: According to the test data, the signal type, signal strength, occurrence time and signal quantity of the bus abnormality signal are adjusted to obtain an updated abnormality signal, so as to dynamically adjust the test control signal.

15. A test system for an integrated circuit communication bus, characterized in that: include: Equipment under test; The integrated circuit communication bus test device according to any one of claims 1 to 10, electrically connected to the device under test; an oscilloscope, electrically connected to the device under test, and configured to detect the bus waveform of the device under test in real time; The host computer is communicatively connected to the test device of the integrated circuit communication bus and is used to display the test results of the device under test.

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