Memory address management method and circuit

Abstract

The embodiment of the invention relates to the technical field of computers, in particular to a memory address management method and circuit. According to the method, the phenomenon of mutual kicking-out possibly generated in a direct mapping mode when the HBM is used as the Cache can be reduced, and particularly, the phenomenon of kicking-out of hotspot data in the cache is reduced. The method comprises the steps of determining that a first memory address meets at least one mapping condition; the at least one mapping condition comprises that the mth cache line needing to be occupied by the first memory address is occupied; obtaining a second memory address based on the first memory address; the second memory address is a memory address needing to occupy the nth cache line; m and n are integers, and m is not equal to n.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory address management method and circuit. Background Art

[0002] Currently, there are three mapping methods between cache and main memory (such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR)): direct mapping (or direct mapped), fully associative mapping, and set associative mapping.

[0003] Among them, in the direct mapping mode, when multiple memory addresses (or memory access addresses) need to be mapped to the same cache line, they will be evicted from each other, resulting in thrashing, which affects system performance. Summary of the Invention

[0004] The embodiments of the present application provide a memory address management method and circuit, which can reduce the occurrence of mutual kicking actions in a direct mapping mode, give full play to the role of cache or HBM working in cache mode, and improve system performance.

[0005] In a first aspect, an embodiment of the present application provides a memory address management method, the method comprising: determining that a first memory address satisfies at least one mapping condition; at least one mapping condition includes that the mth cache line that the first memory address needs to occupy is occupied; based on the first memory address, obtaining a second memory address; the second memory address is a memory address that needs to occupy the nth cache line; m and n are both integers, and m≠n.

[0006] The first memory address is a memory address of the cache or HBM currently being accessed. Based on the first memory address, the second memory address is obtained, which may be obtained by mapping or transforming the first memory address. The mth cache line may represent a cache line in the cache or HBM, where m is determined by the value of the index in the first memory address; the nth cache line represents a cache line in the cache or HBM that is different from the mth cache line, where n is determined by the value of the index in the second memory address.

[0007] If the mth cache line that needs to be occupied by the first memory address currently reached is already occupied, according to the original direct mapping mechanism, the data in the mth cache line will be kicked out to store the data corresponding to the first memory address, so that a kick-out action occurs. The data kicked out may be data that needs to be frequently accessed in the recent period (i.e., hot data). Kicking it out may cause the next request to access the hot data to require a new kick-out action and then write the hot data, and so on, which may cause frequent kick-out actions. The solution proposed in the embodiment of the present application maps the first memory address to the second memory address, and the mapped second memory address is changed to occupy the nth cache line, so that the data in the mth cache line does not need to be kicked out, reducing the occurrence of kick-out actions. In this way, the method can reduce the occurrence of mutual kick-out actions when requesting access to data in the Cache or HBM, especially reduce the frequent kicking out of data in the cacheline under direct mapping, thereby reducing system jitter.

[0008] In one possible implementation, the second memory address includes a first marking bit, and the first marking bit is used to mark that the second memory address is obtained through mapping.

[0009] Optionally, the unmapped memory address may have a second flag bit, and the first flag bit and the second flag bit may be represented by different values.

[0010] In one possible implementation, before determining that the first memory address satisfies at least one mapping condition, the method further includes: recording at least the Nth memory address and the access frequency corresponding to the Nth memory address through a status table; N is an integer.

[0011] The access frequency is used to reflect the popularity of data stored in each memory address recorded in the status table. For example, the status table can record at least one flag bit corresponding to each memory address; the at least one flag bit includes the access frequency.

[0012] In one embodiment, before determining that the first memory address satisfies at least one mapping condition, the method further includes: determining that the first memory address satisfies at least one mapping condition, including: determining that the mth cache line that the first memory address needs to occupy is already occupied by the Nth memory address, and the access frequency corresponding to the Nth memory address is greater than or equal to a preset first threshold.

[0013] The access frequency corresponding to the Nth memory address exceeds a preset threshold, which means that the data corresponding to the Nth memory address is hot data and is currently stored in the mth cache line. The process of performing mapping on the first memory address, that is, the process of changing the storage address of the data corresponding to the first memory address in the cache or HBM, can prevent the hot data stored in the mth cache line from being frequently kicked out. The next time the hot data corresponding to the Nth memory address is requested to be accessed, it can be read from the mth cache line.

[0014] In one embodiment, determining that the first memory address satisfies at least one mapping condition includes determining that an mth cache line to be occupied by the first memory address is already occupied by an Nth memory address, and that a heat level corresponding to the Nth memory address is greater than or equal to a predetermined level. The heat level is determined based on access frequency.

[0015] Access popularity can be represented in a variety of ways. It can be compared with a threshold or classified into different popularity levels. Mapping is performed when the popularity level reaches or exceeds a preset level. For example, the popularity level can occupy a flag bit, and at least one flag bit in the state table can also include the popularity level.

[0016] In one possible implementation, at least the Nth memory address and the access frequency corresponding to the Nth memory address are recorded through a status table, including: when the third memory address currently reached hits the Nth memory address recorded in the status table, the value of the access frequency corresponding to the Nth memory address is increased by 1; or, when the third memory address currently reached does not hit the memory address recorded in the status table, the third memory address is recorded in the status table, and the value of the access frequency corresponding to the third memory address is recorded as 1.

[0017] Access frequency counts the number of times the data stored in the cache line currently occupied by each memory address is accessed within a certain period of time. A hit occurs when both the tag and index of two memory addresses are equal, or when the tags of two memory addresses are equal but the indexes are fuzzy matched.

[0018] By counting the access frequency, hot spot data and cold spot data can be accurately distinguished. When hot spot data is about to be kicked out, mapping is performed on the memory address currently requested for access, while when cold spot data is about to be kicked out, mapping may not be performed, thereby achieving more precise control over the mapped objects.

[0019] In one possible implementation, the first memory address includes an index index; determining that the mth cache line that the first memory address needs to occupy is already occupied by the Nth memory address includes: determining that the index in the first memory address is equal to the index in the Nth memory address recorded in the status table, and determining that the mth cache line that the first memory address needs to occupy is already occupied by the Nth memory address.

[0020] If the index in the first memory address is equal to the index in the Nth memory address recorded in the state table, it can be determined that the first memory address and the Nth memory address recorded in the state table are an exact match.

[0021] In one embodiment, the mask corresponding to the Nth memory address is used to indicate that the Nth memory address represents 2 q memory addresses, 2 q Memory addresses occupy 2 consecutive q cache lines; q is the mask length, q≥0, and q is an integer. For example, the mask may occupy a flag bit, that is, at least one flag bit in the state table may also include a mask.

[0022] In one possible implementation, the mask is a binary code with the lowest q bits being 1; the index in the first memory address is XORed with the index in the Nth memory address, and then XORed with the mask corresponding to the Nth memory address. If the resulting value is 0, it is determined that the mth cache row that the first memory address needs to occupy has been occupied by the Nth memory address.

[0023] When the first memory address matches the memory address in the state table exactly or fuzzily, it can be determined that the mth cache line required by the first memory address is already occupied. The maintenance of the Mask field can support the execution of mapping in the case of fuzzy matching.

[0024] In one possible implementation, before determining that the first memory address satisfies at least one mapping condition, the method further includes: when the currently arrived first memory address does not hit the memory address recorded in the status table, recording the first memory address in the status table, and recording the value of the mask corresponding to the first memory address as a first value; the first value is used to indicate that the mask length q is 0; determining that the mask values ​​corresponding to two memory addresses recorded in the status table are equal, and when the two memory addresses are compared, except for the values ​​of the lowest q bits, the values ​​of other bits are the same, adding a group address to the status table, recording the value of the mask corresponding to the group address as a second value; the second value is used to indicate that the mask length q ≥ 1.

[0025] The memory address in the state table can be a single memory address occupying a single cache line or a group address. The mask field is maintained to record the mask length corresponding to the memory address. The mask and / or mask length are used to implement fuzzy matching and expand the prefetch granularity.

[0026] In one possible implementation, the first memory address includes a tag and an index; the tag is an X-bit binary code, and the index is a Y-bit binary code; obtaining the second memory address based on the first memory address includes: when X<Y, swapping the value of the X bits of the tag in the first memory address with the value of the lowest X bits of the index in the first memory address, keeping the value of the highest YX bits of the index unchanged, adding or setting the first tag bit, to obtain a mapped or transformed second memory address; or, when X=Y, swapping the value of the tag and the value of the index to obtain the mapped or transformed second memory address.

[0027] Through mapping, the first memory address that originally needs to be mapped to the mth cache line (the cache line that currently stores the hot data) is transformed or mapped into the second memory address. The second memory address needs to be mapped to the nth cache line in the cache (the nth cache line, that is, the cache line corresponding to the index in the second memory address). The data originally stored in the nth cache line is kicked out and the data corresponding to the second memory address is stored. It is a low-probability event that the data originally stored in the nth cache line is hot data. The worst result is to kick out the hot data originally stored in the nth cache line, which is similar to the effect of the mechanism before mapping), or the nth cache line is empty and does not need to be kicked out. Therefore, in most cases, through this mapping mechanism, the phenomenon of hot data being kicked out can be reduced.

[0028] In one possible implementation, when it is determined that multiple entries in the state table are full, at least one memory address is removed from the state table based on access frequencies corresponding to the multiple memory addresses.

[0029] In one feasible implementation, when it is determined that the mask length q corresponding to the Nth memory address is ≥1, the average access frequency corresponding to the Nth memory address is determined based on the access frequency corresponding to the Nth memory address and the mask length q; when it is determined that the mask length q corresponding to the fourth memory address recorded in the status table is =0, at least one memory address is removed from the status table by comparing the access frequency corresponding to the fourth memory address with the average access frequency corresponding to the Nth memory address.

[0030] Since the embodiment of the present application proposes a mask mechanism, the access frequency corresponding to the group address is the sum of the access frequencies of all specific addresses in the group address. Therefore, when comparing the access frequencies, the average access frequency corresponding to the group address can be calculated first, and the average access frequency can be compared with the access frequencies corresponding to other specific addresses (not group addresses, but single memory addresses), so as to determine the removal strategy of the status table when it is full based on the access frequency.

[0031] In one embodiment, the method further includes: determining that at least one hit has occurred at the Nth memory address; and sending a message to a prefetch module, the message including the Nth memory address and granularity information corresponding to the Nth memory address; the granularity information being a mask or a mask length q. The mask mechanism proposed in the embodiment of the present application also enables the size of the granularity of prefetches performed by the prefetch module to be adjustable, thereby selecting a more appropriate granularity for prefetching based on bandwidth and program locality, thereby improving prefetch performance.

[0032] In one embodiment, the method further includes: determining that the first memory address does not satisfy at least one mapping condition, obtaining a fifth memory address; the fifth memory address includes a second flag bit, and the second flag bit is used to mark that the fifth memory address has not been mapped.

[0033] In a second aspect, an embodiment of the present application further provides a circuit for implementing the method as described in any one of the above-mentioned first aspects.

[0034] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, wherein the processor is configured to execute a computer program or instruction in a memory to implement any of the methods described above.

[0035] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed by a processor, the method as described in any one of the above items is implemented.

[0036] In a fifth aspect, an embodiment of the present application also provides a chip system, comprising: a communication interface for inputting and / or outputting data; a processor for executing a computer executable program so that a device equipped with the chip system executes any of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1A to 1E An example diagram of the system architecture corresponding to the memory address management method provided in an embodiment of the present application;

[0038] Figure 2 An example of a state table in the memory address management method provided in an embodiment of the present application;

[0039] Figure 3A schematic diagram of different address matching in the memory address management method provided in an embodiment of the present application;

[0040] Figure 4 and Figure 5 A schematic diagram of refreshing the value of the access frequency freq in the memory address management method provided in an embodiment of the present application;

[0041] Figure 6 An example of a state table in the memory address management method provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of an example of a mapping module in the memory address management method provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of the format of the mapped memory address in the memory address management method provided in an embodiment of the present application;

[0044] Figure 9 An example diagram of the address mapping module performing the mapping process provided in an embodiment of the present application;

[0045] Figure 10 Another example diagram of the address mapping module performing the mapping process provided in an embodiment of the present application;

[0046] Figure 11 Another example of a state table in the memory address management method provided in an embodiment of the present application;

[0047] Figure 12 This is an example diagram of updating the mask value in the memory address management method provided in an embodiment of the present application;

[0048] Figure 13 An example diagram of merging addresses based on mask values ​​in the memory address management method provided in an embodiment of the present application;

[0049] Figure 14 A schematic diagram of the system architecture in one embodiment of the memory address management method provided in an embodiment of the present application;

[0050] Figure 15 A flowchart of an embodiment of the memory address management method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to better understand the technical solutions of this specification, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0052] It should be clear that the embodiments described are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this specification.

[0053] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a," "an," "the," and "the" used in the examples of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0054] Computer systems are subject to increasing workloads, including those on the CPU, memory, disk, and network. As workloads continue to increase, users are placing higher demands on hardware, such as increased computing power and higher memory bandwidth. Hardware vendors are responding by introducing new hardware form factors to meet these demands. For example, one new hardware form factor incorporates high-bandwidth memory (HBM) using a 3D stacked process onto high-performance general-purpose processors to provide high memory bandwidth.

[0055] Due to cost issues, HBM's capacity is not very large, generally ranging from a few GB to tens of GB. At this stage, it is difficult to directly replace Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0056] In order to better cooperate with DDR and give full play to its advantages, HBM generally has the following three working modes:

[0057] HBM-only mode: Only HBM is used. The operating mode is similar to that of a DDR-only server, and the HBM capacity cannot be exceeded.

[0058] Flat mode: HBM and DDR are exposed to the user as different Non-Uniform Memory Access (NUMA) nodes. Users can use the numactl command or libnuma to control the location of program memory allocation. HBM can be used first, with overflow stored in DDR.

[0059] In cache mode, HBM is invisible to software and is managed by the memory controller, similar to the L4 cache. In cache mode, HBM can be symmetrically distributed, for example, with one HBM attached to each memory controller, and the HBMs corresponding to different memory controllers are of the same size. In cache mode, HBM operates in direct-mapped mode.

[0060] Of these three modes, Flat mode supports complete user autonomy. Users can leverage HBM's strengths and achieve excellent performance based on their professional experience and deep program customization. However, this requires program intrusion, making existing code difficult to optimize and requiring a high level of professional experience, making it less user-friendly for the average user. HBM-only mode significantly limits program memory requirements. Furthermore, related technologies employ a hybrid mode that manages HBM in a hybrid manner, splitting it into two parts: cache and flat. The cache part is used for caching, while the flat mode is used for display management. In this hybrid mode, Flat mode is intrusive to user code and requires deep customization. The development cost of fully utilizing HBM's performance is high and difficult to implement.

[0061] The cache mode does not require any code modification and can transparently leverage the advantages of HBM. It is a user-friendly working mode, but there are currently some problems.

[0062] For example, one issue is the cache mapping method when HBM is used as a cache. HBM capacity is typically large, potentially several orders of magnitude larger than L1-L3 caches, so fully associative or set associative approaches are generally not used. If fully associative or set associative approaches were used, the logic circuitry for tag storage and parallel lookup would be very large, making implementation difficult and power-intensive. Therefore, HBM in cache mode generally uses direct mapping.

[0063] Direct mapping has a drawback: when multiple memory addresses are mapped to the same cache line in HBM, they can be evicted from each other, a phenomenon known as thrashing. This can hinder the effectiveness of HBM cache mode, leading to inconsistent and fluctuating performance. In particular, the eviction of hotspot memory addresses can lead to a certain degree of performance degradation.

[0064] Furthermore, due to the bandwidth mismatch between HBM and DDR, the granularity of prefetched data from DDR when HBM operates in cache mode is also an issue that needs to be addressed. When prefetching at a fine granularity, such as prefetching at the cacheline granularity (prefetching only one cache line of data at a time), the prefetching algorithm struggles to exploit program locality and cannot achieve good prefetching performance. When prefetching at a coarser granularity, such as prefetching at the page granularity (prefetching an entire page table of data at a time), this places significant pressure on the bandwidth between HBM and DDR. This data may include addresses that are unnecessary to prefetch, resulting in many ineffective prefetches and low bandwidth utilization.

[0065] In order to solve at least one of the above problems, an embodiment of the present application proposes a memory address management method. When the cache line that the memory address (or memory access address) currently requested to access needs to occupy is already occupied, the currently arrived memory address (first memory address) is mapped or transformed (hereinafter referred to as mapping) to obtain a second memory address after mapping. For ease of description, the address before mapping is defined as the first memory address, and the address after mapping is defined as the second memory address. The second memory address can directly access the HBM and / or cache working in cache mode. The role of mapping is to make the second memory address after mapping occupy other cache lines to reduce the occurrence of mutual kicking.

[0066] It should be noted that the mapping operation is performed on the first memory address to obtain the mapped second memory address. The mapping refers to the operation of transforming the first memory address according to certain rules to obtain a second memory address different from the first memory address. This operation is different from the three mapping methods between the cache and the main memory and should not be confused.

[0067] In some embodiments, hotspot detection is performed on the accessed memory addresses, that is, the access frequency of the memory addresses is counted. If the first memory address matches a memory address with relatively high popularity, it means that the cache line that the first memory address needs to occupy is currently occupied by data with relatively high access popularity, and mapping needs to be performed on the first memory address.

[0068] The method proposed in the embodiment of the present application can be implemented in hardware or software or in a combination of software and hardware. For example, in some embodiments, the method proposed in the embodiment of the present application can be implemented by modifying the underlying hardware logic circuit. In other embodiments, it can be implemented in a pure code manner through software improvements without changing the underlying hardware logic circuit. In other embodiments, a portion of the underlying hardware logic circuit can be modified and the corresponding code can be written to implement the method proposed in the embodiment of the present application by combining the code with the underlying hardware.

[0069] The method proposed in the embodiment of the present application can be implemented based on a multi-core processor architecture or a symmetric multi-processor architecture. Alternatively, it is not excluded that the method proposed in the embodiment of the present application can be applied to a non-uniform memory access (NUMA) architecture.

[0070] For example, Figures 1A to 1D An example multi-core processor architecture is shown. Figure 1A In this architecture, the processor (CPU) includes four cores, or computing engines. The main memory is DDR, and the memory controller is a Double Data Rate Synchronous Dynamic Random Access Memory Controller (DDRC). The DDRC is integrated into the CPU motherboard. HBM operates in cache mode, meaning that in this architecture, HBM serves as a cache. The DDRC accesses or manages HBM and DDR using multiple address lines.

[0071] In the method proposed in the embodiment of the present application, operations such as mapping can be performed by Figures 1A to 1D The hardware module 100 shown in FIG is implemented. For example, the hardware module 100 can be integrated into the DDRC as a functional circuit. Alternatively, Figure 1B As shown, the hardware module 100 can also be used as a functional module of HBM and integrated into the HBM. Figure 1C As shown, the hardware module 100 can be used as an independent functional unit and arranged between DDRC and DDR.

[0072] Figures 1A to 1C The architecture examples shown are all using HBM in Cache mode as cache. Obviously, the method proposed in the embodiment of the present application can also be applied to architectures that do not use HBM as cache, such as Figure 1D As shown, HBM can be replaced by Cache. Hardware module 100 can also be set in Cache or between Cache and DDRC.

[0073] The method proposed in the embodiment of the present application can be implemented in a symmetric multi-processor architecture, for example, Figure 1EAs shown, there are two CPUs, each with two cores. Hardware modules 101 and 102 are hardware circuits added to implement the embodiments of the present application, or are modified from existing circuits. Hardware module 101 can be integrated on the motherboard of CPU 1, for example, within DDRC 1, and is symmetrical to hardware module 101. Hardware module 102 can be integrated on the motherboard of CPU 2, for example, within DDRC 2.

[0074] It should be noted that Figures 1A to 1E The structures, number of CPUs, number of cores, main memory type and connection relationships, number of address line bits, etc. shown in the figures are only examples and are not intended to limit the corresponding features of the system architecture in actual applications.

[0075] It should be noted that when the full associative and set associative mapping methods are used between the main memory (such as DDR) and HBM or Cache, the parallel search circuit logic and tag storage area are too large, which makes it difficult to apply in industrial practice. The memory address management method proposed in the embodiment of the present application can be implemented based on a direct mapping method.

[0076] Specifically, the memory address management method provided in the embodiment of the present application may include the following process:

[0077] S10: Determine whether the first memory address satisfies at least one mapping condition.

[0078] The first memory address is the memory address currently reached.

[0079] Not all memory addresses requested for access need to be mapped. Before mapping is performed, it is necessary to first determine whether the currently arrived memory address requires mapping. Specifically, at least one mapping condition can be set. For example, at least a first mapping condition is set. The first mapping condition means that the cache line that the first memory address needs to occupy is already occupied. For ease of description, the cache line that the first memory address needs to occupy is represented by the mth cache line. If the currently arrived first memory address meets at least the first mapping condition, mapping is performed. If the first mapping condition is not met, mapping is not performed.

[0080] In some embodiments, when only the first mapping condition is considered, if the currently arrived first memory address matches the recorded Nth memory address, it is considered that the mth cache line that the first memory address needs to occupy has been occupied.

[0081] For example, Figure 2 As shown, the first memory address includes a tag, an index, and an offset address within the block. The Nth memory address recorded before the current moment includes at least a tag and an index.

[0082] If the index in the first memory address is equal to the index in the Nth memory address already recorded in the status table, it means that the mth cache line that the first memory address needs to occupy is already occupied by the Nth memory address. In this case, according to the original direct mapping method, the data corresponding to the Nth memory address will be kicked out of the mth cache line to store the data corresponding to the currently arrived first memory address. The Nth memory address refers to the memory address corresponding to the data that currently occupies a cache line or the group address corresponding to the data that occupies multiple consecutive cache lines.

[0083] Specifically, in some embodiments of the present application, a state table is used to record and manage information about memory addresses occupying cache lines in an HBM or cache. The state table may include multiple entries, such as one entry per row or one entry per column, each of which records various pieces of information corresponding to a memory address. The state table may be implemented using hardware logic circuits or based on structured data storage.

[0084] The Nth memory address is a memory address recorded in the state table. The following description is for clarity, or the Nth memory address is used as an example for explanation.

[0085] In other embodiments, other forms can be used to record and manage the information of the memory addresses occupying cache lines in the HBM or cache, as long as they can play a recording or management role, and are not limited to the status table. The status table can also be named a record table, a historical access table, a cache table, a matching table, a mapping condition table, etc.

[0086] like Figure 2 As shown, an entry in the state table can record at least the Nth memory address, and the Nth memory address includes a tag and an index.

[0087] In some embodiments of the present application, it is further proposed to distribute hotspot cachelines as much as possible in the HBM (or Cache) through hotspot detection and address mapping, thereby achieving a set-associative effect in a direct-mapped cache mode.

[0088] Specifically, in these embodiments, when it is determined that the currently reached memory address meets the first mapping condition, it is further determined whether it meets the second mapping condition. If both the first mapping condition and the second mapping condition are met, mapping is performed.

[0089] The second mapping condition is whether the access frequency corresponding to the Nth memory address meets the preset requirement.

[0090] Specifically, in the state table, at least one flag bit corresponding to each memory address is recorded. The at least one flag bit includes the access frequency Freq, for example, Figure 2As shown, Freq is a flag used to indicate the access frequency. For example, taking the Nth memory address as an example, an entry in the state table can record the tag and index of the Nth memory address and the access frequency Freq corresponding to the Nth memory address.

[0091] In some embodiments, the value of the Freq field may be recorded or refreshed (updated) in the following manner:

[0092] like Figure 4 As shown, if the third memory address currently reached hits the Nth memory address recorded in the status table, the value of the access frequency Freq corresponding to the Nth memory address is increased by 1.

[0093] It should be noted that we should distinguish between hit and match.

[0094] like Figure 3 As shown, if the indexes of two addresses are equal, then the two addresses are considered to match regardless of whether the tags are equal. For example, if the index of the first memory address is equal to the index of the Nth memory address, and the tags are equal or unequal, then the first memory address is considered to match the Nth memory address recorded in the state table. In the embodiments of the present application, matching can be divided into exact matching and fuzzy matching, which will be explained in detail later.

[0095] like Figure 4 As shown, a hit occurs when the tag and index of the two memory addresses are equal. For example, if the currently reached third memory address has the same tag and index as the recorded Nth memory address, then the third memory address hits the Nth memory address. The Freq value corresponding to the Nth memory address is incremented by 1. For example, before the update, the Freq value was "00000111", and after the increment, it becomes "00001000".

[0096] Or, as Figure 5As shown, if the third memory address currently reached does not hit the memory address recorded in the state table, for example, the third memory address fails to hit any memory address in the state table, that is, the tag in the third memory address is not equal to the tag of each memory address (including the Nth memory address) recorded in the state table, and / or the index in the third memory address is different from the index value of each memory address (including the Nth memory address) recorded in the state table, then, add a record for the third memory address in the state table, for example, record the tag and index of the third memory address and the access frequency as 1. The information of the third memory address can be recorded in an idle table entry. Alternatively, when the state table is full, the information corresponding to the third memory address can be written after removing the data in the state table according to a certain replacement algorithm. The replacement algorithm used when the state table is full will be described in detail in the subsequent content.

[0097] It should be noted that a match may include a hit, and a miss may also include a match.

[0098] In this way, based on the state table, historical access data can be recorded and the access frequency corresponding to each memory address can be counted.

[0099] Specifically, an example of a method for determining whether the second mapping condition is met based on the access frequency is:

[0100] If the first memory address currently reached matches the Nth memory address in the status table, it means that the mth cache line that the first memory address needs to occupy has been occupied by the Nth memory address, then the access frequency value corresponding to the Nth memory address is read in the status table. If the value of the access frequency Freq is greater than or equal to the preset first threshold, it is determined that the second mapping condition is met.

[0101] For example, in some embodiments, the first threshold value may be stored in a register. The first threshold value may be a constant pre-written to the register and cannot be changed; or the first threshold value may be a variable stored in the register, allowing the user to write or modify the value of the variable, thereby enhancing the flexibility and controllability of the mapping mechanism.

[0102] Another example of a method for judging whether the second mapping condition is met based on the access frequency is: Figure 6 As shown, a flag bit "hot" is added to the state table to indicate the heat level. That is, at least one flag bit also includes the heat level. The heat level can be determined based on the access frequency. Specifically, the heat levels corresponding to different memory addresses can be divided into at least two levels based on the access frequency. When the heat level corresponding to the Nth memory address is higher than or equal to the predetermined level, it is determined that the second mapping condition is met.

[0103] For example, it is divided into two levels, "hot" and "cold", and the access frequency is higher than the preset second threshold (the threshold can be equal to the first threshold or another threshold can be set separately), then the value corresponding to hot indicates "hot". For example, set hot to occupy only 1 bit, 0 indicates "cold", and 1 indicates "hot". According to historical access data, the access frequency corresponding to the Nth memory address is less than the second threshold, then the hot value corresponding to the Nth memory address is set to "0". If one row is a table entry, the hot value of the row where the Nth memory address is located is set to "0". If the access frequency corresponding to the Nth memory address is greater than or equal to the second threshold, the hot value corresponding to the Nth memory address in the updated state table is "1". If the third memory address currently reached matches the Nth memory address in the state table, read the hot value corresponding to the Nth memory address in the state table. If the value is 1, the mapping is performed; if the value of hot is 0, the mapping is not performed.

[0104] In other embodiments, the hot field can be divided into more levels, for example, into four levels of "hot", "warm", "normal" and "cold", and the four levels can also be determined based on the value of the Freq field. For example, hot occupies at least 2 bits, for example, "00" means "cold", "01" means "normal", "10" means "warm", and "11" means "hot". If the preset level stored in the register is "10", then mapping is performed when the hot value is "10" or "11". If the preset level stored in the register is "11", mapping is performed only when the hot value is "11", otherwise no mapping is performed. It should be noted that the preset level or the first threshold, the second threshold, etc. may be stored in the register or may not be stored in the register.

[0105] The above description explains how to determine whether the currently reached memory address needs to be mapped. Next, we will continue to explain how to perform the mapping.

[0106] S11: Mapping is performed on the first memory address to obtain a second memory address.

[0107] like Figure 7 As shown, the subject 10 for implementing the method proposed in the embodiment of the present application can be a hardware module 100 or a software module. The specific product form of the subject can be a functional unit or component, device or part implemented by hardware logic circuits, for example, a physical entity that can be inserted into a CPU motherboard, or a plug-in or installation package implemented based on code.

[0108] The main body 10 at least includes a mapping module, which may also be called an address mapping module or an address mapping unit (AddrRemap Unit).

[0109] The mapped second memory address has a first marking bit, and the first marking bit is used to mark that the second memory address is obtained through mapping.

[0110] If the currently reached memory address does not satisfy at least one mapping condition, which can be understood as not satisfying the first mapping condition, it is determined that no mapping is required, and the second flag bit is directly added or set. In other words, the unmapped memory address includes the second flag bit to indicate that the obtained memory address has not been mapped.

[0111] The mark bit (including the first mark bit or the second mark bit) can be an additional bit in the highest bit of the original address, or it can be other unused bits. The specific marking method is not unique.

[0112] For example, a bit can be added before the original address (first memory address), and the value of this bit is 1, which is the first flag bit, and the value of this bit is 0, which is the second flag bit. In other embodiments, "0" can be used to indicate that the mapping has been completed, and "1" can be used to indicate that the mapping has not been completed.

[0113] Alternatively, in other embodiments, the tag bit can also be multiple bits, performing hashing in a higher-dimensional space, adding greater flexibility. That is, the tag bit can occupy two bits or more. For example, the tag bit occupies two bits, and "00" is the second tag bit, indicating that no mapping has been performed. "01," "10," and "11" are all second tag bits. "01" indicates that the mapping is obtained according to the first mapping method, "10" indicates that the mapping is obtained according to the second mapping method, and "11" indicates that the mapping is obtained according to the third mapping method.

[0114] For example, Figure 7 As shown, the second memory address has a first mark bit 10a with a value of "1", indicating that mapping has been performed or obtained through mapping, and the fifth memory address that has not been mapped has a second mark bit 10b with a value of "0", indicating that mapping has not been performed or obtained through mapping.

[0115] Correspondingly, the cacheline address format in HBM or Cache can be as follows Figure 8 As an implementation method, a flag bit can be added to the original address format. Figure 8 The "virtual" shown in is an added flag bit. This flag bit can be the first flag bit or the second flag bit.

[0116] As another possible implementation, instead of adding virtual, one or more unused bits in the tag and index can be selected and set to fixed values ​​to indicate whether mapping has occurred. For example, all "1" bits indicate mapping, and all "0" bits indicate unmapping. Alternatively, all "0" bits indicate mapping, and all "1" bits indicate unmapping, and so on.

[0117] The format of the memory address output by the address mapping unit must be consistent with the address format of the HBM or Cache or be compatible with each other.

[0118] After mapping, the cache line that the obtained second memory address needs to occupy is the nth cache line, where m and n are both integers and m≠n. That is, according to the original direct mapping mechanism, the data in the mth cache line needs to be kicked out. After the mapping operation proposed in the embodiment of the application, the data in the first memory address is actually mapped to the nth cache line corresponding to the second memory address for storage, and the data in the mth cache line does not need to be kicked out.

[0119] Specifically, for example, read the tag and index in the first memory address; assuming that the tag is a binary code of X bits, that is, the tag occupies X bits; the index is a binary code of Y bits, that is, the index occupies Y bits. X≤Y. For example, the following method 1 or method 2 can be used to implement the mapping from the first memory address to the second memory address:

[0120] Method 1:

[0121] When X<Y, swap the value of the X bits of tag in the first memory address with the value of the lowest X bits of index in the first memory address, keep the value of the highest YX bits of index unchanged, and add or set the first tag bit to obtain the mapped second memory address.

[0122] For example, Figure 9 As shown, X=8, Y=12, in the first memory address, the value of tag is " 00100011 ", the value of index is "010111010001", the lowest 8-bit value of index "11010001" is compared with the 8-bit value of tag " 00100011 "Swap, the index value becomes "0101 00100011 ", the value of tag becomes "11010001".

[0123] Alternatively, in the case of X=Y, the value of tag and the value of index are swapped to obtain the mapped second memory address.

[0124] For example, Figure 10 As shown, X=8, Y=8, in the first memory address, the value of tag is " 00100011 ", the value of index is "11010001", compare the value of index "11010001" with the value of tag " 00100011 "Swap, the value of index becomes " 00100011 ", the value of tag becomes "11010001".

[0125] Method 2:

[0126] In some other embodiments, address mapping may also be implemented in the following manner:

[0127] Determine the memory address with the lowest access frequency from the status table, and map the first memory address currently requested to be accessed to the address with the lowest access frequency or the access frequency lower than a predetermined threshold (e.g., a third threshold). For example, one possible implementation method is to determine that the least recently used memory address in the status table is the Yth memory address based on the Least Recently Used (LRU) algorithm. Specifically, the index in the first memory address can be replaced with the index in the Yth memory address. For example, the value of the tag in the first memory address is "00100011", the value of the index is "010111010001", and the value of the tag in the Yth memory address is " 01110011 ", the value of index is " 111011001011 After mapping, the value of tag in the second memory address remains unchanged, still "00100011", and the value of index becomes " 111011001011 ”.

[0128] It should be noted that, in order to map the first memory address to an address with a lower access frequency, it is necessary to maintain a mapping table for recording the mapping relationship between the original address and the mapped address.

[0129] The above method 1 or method 2 is only an example. In other embodiments, other mapping methods can also be used, such as performing a fixed offset based on the index in the first memory address, for example, mapping to index+X rows, where X can be a constant integer.

[0130] Furthermore, embodiments of the present application also propose a masking mechanism that, through the mask in the state table, enables the merging of at least two adjacent cache lines, i.e., multiple consecutive cache lines form a cache group. A cache group can also be referred to as a cache block. Note that in related art, a cache line may be defined as a cache block, but in embodiments of the present application, a cache block represents a group consisting of two or more consecutive cache lines.

[0131] In some embodiments, at least one flag bit also includes a mask, such as Figure 11 As shown, the state table also includes a mask field.

[0132] The mask corresponding to the Nth memory address is used to indicate that the Nth memory address represents 2 q memory addresses, 2 q Memory addresses occupy 2 consecutive q cache lines; q is the mask length, q≥0, and q is an integer.

[0133] For example, a mask can be a binary code that occupies multiple bits. If the values ​​of the lowest q consecutive bits are all 1 and the remaining bits are all 0, the mask length represented by the mask is q. If all bits in the mask are 0, it is considered that q = 0, that is, the mask length is 0. A mask length of 0 means that the memory address corresponding to the mask only occupies one cache line.

[0134] More specifically, for example, the Nth memory address is "0010001101011101", the corresponding mask value is "00000011", and the value of the lowest two bits is 1, then q=2, the Nth memory address is a group address, which actually contains 2 2 memory addresses, 2 2 Memory addresses occupy 4 consecutive cache lines, 2 2 The memory addresses are "0010001101011101", "0010001101011110", "0010001101011111", and "0010001101011100". The group address recorded in the status table can be any of the specific memory addresses contained in the group address. For example, the Nth memory address can also be recorded as "0010001101011100", "0010001101011110", or "0010001101011111".

[0135] Specifically, if Figure 12 As shown, the following methods can be used to refresh or manage the mask value in the status table:

[0136] The first memory address currently reached does not hit a memory address recorded in the status table. A miss includes a mismatch between only the tag, only the index, or both the tag and index. The first memory address is recorded in the status table, and the mask value corresponding to the first memory address is recorded as the first value. The first value, i.e., the initial value, indicates that the mask length q is 0.

[0137] For example, mask occupies 4 bits and supports up to 2 4 The cachelines are merged into one group, and the mask value corresponding to the first memory address currently reached is "0000", and all bits are 0, indicating that the mask length q = 0. It should be noted that in some embodiments, the value of the mask field is not equivalent to the mask length. For example, the value of mask is "0001", which means that the mask length is 1. The value of mask is "0011", which means that the mask length is 2. The value of mask is "0111", which means that the mask length is 3, that is, in this part of the embodiments, the mask length is determined based on the number of bits whose low bit of mask is 1. The design of the value of Mask is related to the operation method in fuzzy matching.

[0138] For example, the currently reached memory address A is compared with the memory addresses recorded in the state table. If address A fails to hit the address in the state table, the mask length corresponding to address A is recorded as 0, indicating that address A only occupies one cacheline.

[0139] Next, if Figure 13 As shown, compare any two memory addresses in the state table to determine that the mask values ​​corresponding to the two memory addresses recorded in the state table are equal, and when the two memory addresses are compared, except for the values ​​of the lowest q bits, the values ​​of other bits are the same, add a group address to the state table, and record the mask value corresponding to the group address as the second value; the second value is used to indicate that the mask length q ≥ 1.

[0140] For example, the currently reached memory address A (the default mask value is 0, indicating a mask length of 0) is compared with each memory address recorded in the state table. If there is a memory address B with a mask length of 0 in the state table, and address A and address B differ only in the lowest bit of the index, in this case, the mask length corresponding to the mask value corresponding to address A and address B is increased by 1, and the mask value is updated from 0000 to 0001. A new merge entry (group address C) is added to the state table. Group address C can be either address A or address B. The mask value corresponding to the first group address is 0001.

[0141] Next, continue to compare group address C with other addresses recorded in the status table. If the mask value corresponding to group address D is equal to the mask value of group address C (what needs to be compared is the mask length. If the mask values ​​are equal, the mask length must be equal), and group address C and group address D only differ in the lowest 2 bits of the index, then group address C and group address D are merged into group address E, the mask length is increased by 1, and the mask value is updated. It should be noted that the mask length plus 1 is not equal to the mask value plus 1. For example, the mask value corresponding to group address C indicates that the mask length is 1, then the mask length plus 1 means that the lowest 2 bits of the mask are both 1, rather than the mask value plus 1. For example, the mask is updated from 0001 to 0011. And so on, repeat the last operation until no table entry that can be merged is found, and the mask in the status table is updated.

[0142] The group address E recorded in the status table can be any of address A, address B, address C or address D. Formally, the third group address is just an ordinary memory address, but combined with the mask, we can know that this address is a group address, which actually occupies 4 (2 2 ) consecutive cache lines, that is, the group of addresses actually includes four specific addresses: address A, address B, address C and address D.

[0143] The mask-based design enables the method provided in the embodiment of the present application to support fuzzy matching.

[0144] Fuzzy matching means that a memory address currently reached can be matched with a group address in the state table.

[0145] Specifically, in some embodiments, the mask is a binary code with the lowest q bits being 1. The following method can be used to determine whether the currently arrived first memory address matches the Nth memory address recorded in the state table based on the mask corresponding to the Nth memory address:

[0146] One fuzzy matching method is: determine the mask length to be q, remove the lowest q bits in the index in the first memory address, and leave multiple bits; remove the lowest q bits in the index in the Nth memory address, and leave multiple bits; perform an XOR operation on the multiple bits remaining in the first memory address and the multiple bits remaining in the Nth memory address, and if the resulting value of all bits is 0, then it can be determined that the first memory address matches the Nth memory address.

[0147] For example, if the value of the mask is "0011," we can determine that, assuming the mask length q = 2, the index of the currently reached memory address F is "00101110." A group address E exists in the state table, and the index of group address E is "00101101." Removing the two lowest-order bits from address F leaves the remaining bits "001011." Removing the two lowest-order bits from group address E leaves the remaining bits "001011." XORing the remaining bits of memory address F (001011) with the remaining bits of memory address E (001011) yields "000000." This confirms that address F and group address E are a fuzzy match.

[0148] Another way is to read the value of mask, determine that the mask length is q, directly perform an XOR operation on the index in the first memory address and the index in the Nth memory address, compare the result with the value of mask, and if the result is less than or equal to the value of mask, then the first memory address can be determined to match the Nth memory address; or, the number of bits with a value of 1 in the lowest q bits of the result obtained by the XOR operation is recorded as q', and q' is compared with q. If q'≤q, then the first memory address can be determined to match the Nth memory address.

[0149] For example, if the mask value is "0011," we can determine that, assuming the mask length q = 2, the index of the currently reached memory address F is "0010100." There is a group address E in the state table with an index of "00101101." By performing an XOR operation on the index value "00101100" in memory address F and the index value "00101101" in group address E, the result is "00000001." Comparing the mask value "0011" with the XOR result of 00000001, 00000001 < 0011, we can determine that address F and group address E are fuzzy matched. Alternatively, if the mask length is 2 and the XOR result is "00000001," then q' = 1, q' < q, and this can be considered a match. For example, if the result of the XOR operation is "00000010", then q'=1, which still satisfies q'<q, and it can be determined as a match; or if the result of the XOR operation is "00000011", then q'=2, q'=q, which can also be determined as a match.

[0150] It should be noted that in the above examples, the number of the lowest q bits of the mask with a value of 1 is mostly used as the mask length. In fact, in other embodiments, the value of the mask can be equal to the mask length. For example, the value of the mask is "0010", which means that the mask length q = 2; or, the value of the mask is "0001", which means that the mask length is 1; the value of the mask is "0000", which means that the mask length is 0.

[0151] If the mask length represented by the mask of the memory address is 0, then the memory address is a memory address occupying a cache line, and the match between the two is an exact match; if the mask length represented by the mask corresponding to the memory address is ≥1, then the Nth memory address is actually a group address, and the match between the first memory address and the Nth memory address is a fuzzy match.

[0152] When it is determined that the first memory address matches the Nth memory address in the state table (including an exact match or a fuzzy match), mapping is performed on the first memory address.

[0153] Optionally, in some embodiments, it can be set to the first memory address currently reached. When it matches the Nth memory address whose level is hot as indicated by the value of hot in the status table and whose mask length is greater than or equal to 1 (or 0) as indicated by the value of mask, it is considered that the cacheline corresponding to the address has a more serious conflict behavior, and the address is mapped.

[0154] It should be noted that, in some embodiments, the tag+index of the two addresses can be XORed after q bits are removed, or the tag+index of the two addresses can be XORed and then compared in the above manner to determine whether the two addresses are fuzzy hits. Based on the setting of the mask field, when counting freq, if the Nth memory address is a group address, the first memory address is compared with the hit Nth memory address (including the tag field), except for the lowest q bits or less than q bits, the other bits are the same, it can be considered that the third memory address hits the Nth memory address (that is, the third memory address hits one of the Nth memory addresses).

[0155] The setting of the Mask field makes the prefetch granularity of the prefetch module adjustable.

[0156] For example, you can interact with the prefetch hint interface to perform the following operations:

[0157] When it is determined that at least one hit occurs at the Nth memory address, a message is sent to the prefetch module. The message includes the Nth memory address and granularity information corresponding to the Nth memory address. The granularity information can be a mask length q or mask.

[0158] When an entry in the state table is added or refreshed, the tag, index, freq, and mask information can be partially or completely output to the prefetch module, which decides whether to prefetch a cacheline or multiple consecutive cachelines (for example, 2 q cacheline).

[0159] In addition, the embodiment of the present application also proposes a maintenance strategy for the state table. If the table is full, the replacement strategy can adopt the LRU strategy, without considering the value of the mask, directly comparing the access frequency corresponding to each address, and deleting the address with the lowest access frequency in the recent period. In some other embodiments, the following strategy can also be adopted:

[0160] When it is determined that the mask length q corresponding to the Nth memory address is ≥ 1, the average access frequency corresponding to the Nth memory address is determined based on the access frequency freq corresponding to the Nth memory address and the mask length q. For example, average access frequency = freq / q. Specifically, freq can be right-shifted by the mask length, i.e., freq is right-shifted by q bits.

[0161] For addresses with a mask length of 0, for example, if it is determined that the mask length q corresponding to the fourth memory address recorded in the state table is 0, at least one memory address is removed from the state table by comparing the access frequency corresponding to the fourth memory address with the average access frequency corresponding to the Nth memory address. In other words, when comparing the access frequencies of addresses with a mask length of 0 with addresses with a non-zero mask length, the group addresses can be averaged to obtain an average access frequency, and then the access frequencies corresponding to the group addresses and ordinary addresses with a mask length of 0 are compared. Based on the comparison result, the address with the lowest recent access frequency is determined to be removed from the state table.

[0162] The following is a complete specific embodiment of the memory address management method provided by the embodiment. Figure 14 The system architecture shown is executed, and the specific process can be referred to Figure 15 :

[0163] S151, an access request to the HBM cache arrives, and the request carries a first memory address Addr 1. The HBM cache is the HBM operating in cache mode.

[0164] S152, refresh the status table.

[0165] Compare Addr 1 with at least one of the tags and indexes of each memory address in the state table. For example, compare the tag field and / or index field in Addr 1 with Addr N. If Addr 1 fails to hit any recorded address in the state table, then write the record of Addr 1 into a blank entry in the state table. For example, Figure 14 As shown, the tag field in Addr 1 is inconsistent with that in AddrN, which means that the Nth memory address is missed. The process continues to traverse other memory addresses until all addresses of the current record in the state table are traversed and no hits are found. Then, the record of Addr 1 is added to a blank entry in the state table (for example, a blank row). Specifically, the tag and index of Addr 1 are written into the state table, and the value of freq of Addr 1 is set to "00001", and the value of mask is set to "0000".

[0166] Compare Addr 1 with the other memory addresses in the state table to see if they meet the merge criteria. Specifically, compare the value of Addr 1 with the mask value of each memory address in the state table. If the mask value of memory address Addr x is also "0000", continue comparing Addr 1 and Addr x to see if the index differs only in the last bit. If so, Addr 1 and Addr x can be merged. Add a merge item (group address) and record the group address as "101000111010". When merging, add the freq values ​​corresponding to Addr 1 and Addr x, respectively, to obtain the access frequency value corresponding to the group address. If no such Addr x exists, do not merge.

[0167] S153: Determine whether Addr 1 needs to be mapped.

[0168] In this embodiment, the first mapping condition is that the index value of the currently reached address Addr 1 is equal to the index value of at least one address in the state table. The second mapping condition is that the freq value corresponding to the memory address matching Addr 1 in the state table exceeds a first threshold. If both the first and second mapping conditions are met, it is considered that mapping is required for Addr 1.

[0169] For example, the value of the tag field in Addr 1 is "00101", and the value of index is "101000111010". Compare the index in Addr1 with the index fields of each memory address recorded in the status table. Through traversal, the value of index in the Nth memory address AddrN is "101000111010", which is consistent with Addr 1, and meets the first mapping condition.

[0170] Read the value of the freq field of Addr N from the state table, read the pre-stored first threshold from the register, compare the value of the freq field with the first threshold, and if the freq value is greater than or equal to the first threshold, the second mapping condition is met.

[0171] For example, Figure 14 In the example, the freq value of Addr N is "01111", and assuming the first threshold is "01110", it meets the second mapping condition.

[0172] This embodiment supports fuzzy matching. For example, the mask value corresponding to Addr N is "0001", which means that Addr N is a group address and the mask length is 2. 1 , which means that Addr N actually occupies two consecutive cache lines. Fuzzy matching can be understood as the current address and the table entry index are the same under the mask.

[0173] It should be noted that some operations in S153 and some operations in S152 can be performed mixedly. The numbers S152 and S153 and the numbers of each item in the embodiment of the present application are only for the purpose of distinction and do not indicate the order of execution.

[0174] S154, perform address mapping.

[0175] For addresses that meet the mapping conditions, proceed to the next step of mapping.

[0176] In other embodiments, other mapping conditions may be added, such as the length of the matching mask needs to be greater than a certain threshold, so as to perform address hashing (ie, address mapping) only on hot group addresses.

[0177] Specifically, the above mapping method 1 is adopted, according to Figure 14 In the addressing format shown, the tag in Addr 1 occupies 5 bits and the index occupies 12 bits. The 5-bit value of the tag is swapped with the value of the lowest 5 bits of the index. The address of Addr 1 is "00101101000111010" (excluding the offset). After mapping, the address of Addr 2 is "11010101000100101" (excluding the offset), where the tag becomes "11010" and the index becomes "101000100101".

[0178] It should be noted that the address mapping in the embodiment of the present application only involves index and tag, not offset. Figure 14 As shown, the offset is concatenated with the swapped tag and index to obtain the mapped Addr 2.

[0179] After being mapped by the mapping module (or address mapping module), the original address will have a 1 added to its highest bit, while the unmapped address will have a 0 added to its highest bit. Alternatively, a 1 can be set (default is 0) at a certain position in the HBM's actual access address (i.e., Address 2). The 1 and 0 can be swapped here, and are only used to distinguish whether the address has been mapped.

[0180] For example, the address format of the address before mapping in HBM is shown in Table 1 below:

[0181] Table 1

[0182] Virtual=0 Tag=1010 Index=00100011 Offset

[0183] Among them, Virtual is a flag bit, and Virtual can have at least two values.

[0184] The address format of the mapped address in HBM is shown in Table 2 below:

[0185] Table 2

[0186] Virtual=1 Tag'=0011 Index'=00101010 Offset

[0187] Access to the HBM Cache is performed using the mapped address Addr 2.

[0188] It should be noted that the embodiment of the present application also supports the expansion of the prefetch granularity. In related technologies, the prefetch granularity is generally not adjustable. However, in this embodiment, data can be prefetched according to a certain granularity, and the granularity is controllable, which can effectively solve the problem that the granularity is too small and the prefetching performance is difficult to utilize the locality of the program, and the problem that the prefetching granularity is too large and occupies bandwidth.

[0189] For example, for merged entries in the state table (with a mask length greater than 0), if the access frequency of these merged entries is increased by 1, the group address and granularity information of the merged entry are output to the prefetch module. The prefetch module can perform a prefetch based on the group address and granularity information. The granularity information can be the mask value or the q value.

[0190] It should be noted that the mapping mechanism proposed in the embodiment of the present application is compatible with reading and writing. For example, assuming that an address that has arrived is address A, address A does not match the address in the status table (the index is not equal and does not meet the fuzzy match), address A has not been mapped, and after adding the mark bit to 0, the data corresponding to address A is stored in the corresponding address in the HBM Cache; after this, there is a currently arrived address that hits address A in the status table, then the hit is that the tag and index are equal, and the index is equal, then it is considered a match, that is, in the embodiment of the present application, a hit is also a match, and mapping can be performed. Therefore, in this access process, the mapping module needs to perform mapping on address A, and after performing mapping on address A, address B is obtained, and the mark bit of address B is 1. The same data may be stored in address A with a mark bit of 0 and address B with a mark bit of 1. If address A is accessed again later, according to the mapping mechanism, it will still be mapped, and then the corresponding data will be read from address B. The advantage of this mechanism is that there is no need to maintain a mapping record table, which is a table used to record the mapping relationship between addresses before and after historical mapping, or a table that records whether each memory address has been mapped before. Under this mechanism, some addresses may occupy one more cache line in individual cases, but the overhead of maintaining the mapping record table is reduced. In comparison, it is a more practical and feasible solution.

[0191] It should be noted that the above Figure 14 and Figure 15 The embodiment shown is only an example. In other embodiments, a simplified solution may also be adopted:

[0192] For example, the tag field in the state table can be deleted, and only the index field is used for state table updates. The mask field does not need to be set in the state table. This eliminates the need for the state table to perform entry merging logic. The prefetch granularity of the prefetch module cannot be adjusted, and only the mapping logic remains.

[0193] In summary, the solution provided by the embodiments of the present application is that when an address in a table entry is identified as "hot," it indicates that the data stored in the cacheline corresponding to the table entry is frequently accessed. If the data in the cacheline is evicted, performance will be degraded. Therefore, the address of the currently requested access that matches the address corresponding to the hot data can be mapped to another cacheline in the HBM to prevent the data in the hot cacheline from being evicted.

[0194] When a new address arrives, the state table is queried. If the new address matches an address with a "hot" value in the state table, the address mapping module performs the mapping. "Hot" can be understood as a level of heat, determined by whether the freq is greater than a certain threshold or other criteria, which are not detailed here.

[0195] An embodiment of the present application also provides a circuit for implementing the method of any of the above embodiments.

[0196] An embodiment of the present application further provides an electronic device, comprising: a processor, wherein the processor is configured to execute a computer program or instruction in a memory to implement the method described in any of the above embodiments.

[0197] It should be noted that a processor can be any chip with computing capabilities, and is not limited to a central processing unit (CPU). For example, a processor can be a chip that includes one or more transistors, resistors, capacitors, and other circuit elements to implement certain functions; or it can be various packaged integrated circuits that can implement the above methods.

[0198] Exemplarily, the processor may include one or more processing units, for example, a neural-network processing unit (NPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a digital signal processor (DSP), a baseband processor, etc. The different processing units may be independent devices or integrated into one or more processors. The controller may generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0199] The memory can be used to store computer executable program code, which includes instructions. The internal memory may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, an application required for at least one function, etc. The data storage area can store data (such as input data, output data) created during the use of the electronic device. In addition, the internal memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory and / or instructions stored in a memory provided in the processor.

[0200] It should be understood that the structure illustrated in the embodiment of the present invention is merely an example and does not limit the electronic device. The electronic device in the embodiment of the present application may include more or fewer components than shown, or combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0201] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed by a processor, the method described in any of the above embodiments is implemented.

[0202] An embodiment of the present application further provides a computer program product, which includes a program. When the program is executed by an electronic device, the electronic device implements the method described in any of the above embodiments.

[0203] An embodiment of the present application also provides a chip system, including: a communication interface for inputting and / or outputting data; and a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any of the above embodiments.

[0204] The above-mentioned computer-readable storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device.

[0205] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0206] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0207] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0208] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0209] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

Claims

1. A memory address management method, characterized in that: The method comprises: Determining that the first memory address satisfies at least one mapping condition; the at least one mapping condition includes that the mth cache line required to be occupied by the first memory address is already occupied; Based on the first memory address, a second memory address is obtained; the second memory address is a memory address that needs to occupy the nth cache line; m and n are both integers, and m≠n.

2. The method according to claim 1, wherein The second memory address includes a first marking bit, and the first marking bit is used to mark that the second memory address is obtained through mapping.

3. The method according to claim 1 or 2, wherein: Before determining that the first memory address satisfies at least one mapping condition, the method further includes: Determining that the first memory address satisfies at least one mapping condition includes: It is determined that the mth cache line required to be occupied by the first memory address is already occupied by the Nth memory address, and the access frequency corresponding to the Nth memory address is greater than or equal to a preset first threshold.

4. The method according to claim 1 or 2, wherein: Determining that the first memory address satisfies at least one mapping condition includes: Determine that the mth cache line that the first memory address needs to occupy is already occupied by the Nth memory address, and the heat level corresponding to the Nth memory address is higher than or equal to a predetermined level; wherein the heat level is determined based on the access frequency.

5. The method according to any one of claims 1 to 4, wherein The first memory address includes an index index; Determining that the mth cache line to be occupied by the first memory address is already occupied by the Nth memory address includes: When it is determined that the index in the first memory address is equal to the index in the Nth memory address recorded in the status table, it is determined that the mth cache line to be occupied by the first memory address is already occupied by the Nth memory address.

6. The method according to claim 3 or 4, wherein: The mask corresponding to the Nth memory address is used to indicate that the Nth memory address represents 2 q memory addresses, the 2 q Memory addresses occupy 2 consecutive q cache lines; q is the mask length, q≥0, and q is an integer.

7. The method according to claim 6, wherein The mask is a binary code with the lowest q bits being 1; Determining that the mth cache line to be occupied by the first memory address is already occupied by the Nth memory address includes: The multiple bits remaining after removing the lowest q bits of the index in the first memory address are XORed with the multiple bits remaining after removing the lowest q bits of the index in the Nth memory address. If the resulting value is 0, it is determined that the mth cache line that the first memory address needs to occupy has been occupied by the Nth memory address.

8. The method according to any one of claims 1 to 7, wherein The first memory address includes a tag and an index; the tag is a binary code of X bits, and the index is a binary code of Y bits; Obtaining a second memory address based on the first memory address includes: When X<Y, swap the value of the X bits of the tag in the first memory address with the value of the lowest X bits of the index in the first memory address, keep the value of the highest YX bits of the index unchanged, add or set the first tag bit, and obtain the mapped second memory address; or, In the case of X=Y, the value of the tag and the value of the index are swapped to obtain the mapped second memory address.

9. The method according to any one of claims 6 to 8, wherein The method further comprises: Determining that at least one hit occurs at the Nth memory address; A message is sent to a prefetch module, where the message includes the Nth memory address and granularity information corresponding to the Nth memory address; the granularity information is a mask or a mask length q.

10. An electronic device, characterized in that: The electronic device comprises: A processor, configured to execute a computer program or instruction in a memory to implement the method according to any one of claims 1 to 9.

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