Data error correction methods, apparatus, electronic devices and computer-readable storage media

Abstract

The data error correction method, apparatus, electronic device, and computer-readable storage medium provided in this invention relate to the field of storage technology. The method involves obtaining the bias read voltage value of a memory cell, performing hard decoding based on the bias read voltage value and a reference read voltage value, and obtaining a reference log-likelihood ratio based on the memory's read voltage characteristic graph, the bias read voltage value, and the reference read voltage value. If hard decoding fails, the reference read voltage value is shifted by the bias read voltage value in the read voltage characteristic graph. The number of cell changes between the shifted reference read voltage value and the reference read voltage value is determined based on the read voltage characteristic graph, and the reference log-likelihood ratio is adjusted based on the number of cell changes. Soft decoding is then performed based on the adjusted reference log-likelihood ratio. By adjusting the log-likelihood ratio using the actual number of cell changes, a more accurate log-likelihood ratio is obtained, improving the error correction performance of LDPC and thus enhancing the reliability and lifespan of the memory.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more specifically, to a data error correction method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] With advancements in NAND Flash manufacturing processes and the increasing demand for higher storage capacities, TLC (Triple-Level Cell) and QLC (Quad-Level Cell) technologies have become increasingly widely used. As the number of bits stored in each cell increases, the stored charge is more susceptible to alteration after data is written, leading to data errors. To address this challenge, a growing number of algorithms are being applied to NAND Flash data error correction.

[0003] The Log-Likelihood Ratio (LLR) is the logarithm of the ratio of likelihood information, which can be understood as the degree of trust in each bit in the data. TLC and QLC chips have high error rates, and traditional error correction methods cannot handle such a high number of flipped bits. To address these issues, the LDPC algorithm is currently more widely used for error correction. In the LDPC decoding process, the correct determination of the soft information LLR is crucial for fully utilizing error correction capabilities. Traditional methods fix the LLR in a table, regardless of the number of erases, reads, high or low temperature environments, or data retention scenarios. However, the LLR values ​​stored in this table are finite and difficult to accurately match the LLR values ​​required for actual error scenarios. This makes it difficult to fully utilize the decoding performance of LDPC, thus affecting the reliability and lifespan of the memory. Summary of the Invention

[0004] The purpose of this invention is to provide a data error correction method, apparatus, electronic device, and computer-readable storage medium to solve the problem of difficulty in fully utilizing the maximum decoding performance of LDPC, which in turn affects the reliability and lifespan of the memory.

[0005] In a first aspect, the present invention provides a data error correction method, the method comprising:

[0006] Obtain the bias read voltage value of the memory cell;

[0007] Hard decoding is performed based on the biased read voltage value and the reference read voltage value, and a reference log-likelihood ratio is obtained based on the read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value.

[0008] If hardware decoding fails, the reference read voltage value is offset by the bias read voltage value in the read voltage characteristic diagram;

[0009] The number of cell changes between the offset reference reading voltage value and the reference reading voltage value is determined based on the reading voltage characteristic diagram, and the reference log-likelihood ratio is adjusted based on the number of cell changes.

[0010] Soft decoding is performed based on the adjusted reference log-likelihood ratio.

[0011] In an optional implementation, determining the number of cell changes between the offset reference read voltage value and the reference read voltage value based on the read voltage characteristic diagram includes:

[0012] The number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value are obtained based on the read voltage characteristic diagram.

[0013] The number of cell changes is obtained based on the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0014] In an optional implementation, after soft decoding based on the adjusted reference log-likelihood ratio, the method further includes:

[0015] If software decoding fails, retrieve the offset count;

[0016] If the number of offsets is less than the preset number of offsets, the adjusted reference log-likelihood ratio is adjusted again until the software decoding is successful.

[0017] If the number of offsets equals the preset number of offsets, then the adjustment of the adjusted reference log-likelihood ratio is stopped.

[0018] In an optional implementation, the hard decoding based on the biased read voltage value and the reference read voltage value includes:

[0019] The voltage state of the memory cell is determined based on the bias read voltage value and the reference read voltage value;

[0020] The voltage state is read and verified. If the voltage state verification fails, the hardware decoding is determined to have failed. If the voltage state verification succeeds, the hardware decoding is determined to have succeeded.

[0021] In an optional implementation, obtaining the reference log-likelihood ratio based on the read voltage characteristic map of the memory, the bias read voltage value, and the reference read voltage value includes:

[0022] The reading voltage characteristic diagram is divided into multiple intervals based on the bias reading voltage value and the reference reading voltage value;

[0023] Obtain the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in the memory within each interval;

[0024] The reference log-likelihood ratio for each interval is obtained based on the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in the memory within each interval.

[0025] In an optional implementation, obtaining the reference log-likelihood ratio for each interval based on the number of memory cells with bit values ​​of 0 and the number of memory cells with bit values ​​of 1 in each interval includes:

[0026] The probability of a storage cell having a bit value of 0 and the probability of having a bit value of 1 in each interval are calculated based on the number of storage cells with a bit value of 0 and the number of storage cells with a bit value of 1 in each interval.

[0027] Calculate the ratio of the probability that a bit in the memory cell is 0 to the probability that a bit is 1 within each interval, and perform a logarithmic calculation on the ratio to obtain the reference log-likelihood ratio for each interval.

[0028] In an optional implementation, adjusting the reference log-likelihood ratio based on the number of CELL changes includes:

[0029] The reference log-likelihood ratio is adjusted based on the number of CELL changes and a preset relationship model to obtain the adjusted reference log-likelihood ratio.

[0030] In a second aspect, the present invention provides a data error correction device, the device comprising:

[0031] Off-balance voltage value acquisition module, used to obtain the off-balance voltage value of the memory cell;

[0032] The hard decoding module is used to perform hard decoding based on the bias read voltage value and the reference read voltage value, and to obtain the reference log-likelihood ratio based on the read voltage characteristic diagram of the memory, the bias read voltage value and the reference read voltage value;

[0033] An offset module is used to offset the reference read voltage value by the bias read voltage value in the read voltage characteristic diagram if hard decoding fails.

[0034] The log-likelihood ratio adjustment module is used to determine the number of CELL changes between the offset reference reading voltage value and the reference reading voltage value based on the reading voltage characteristic diagram, and to adjust the reference log-likelihood ratio based on the number of CELL changes.

[0035] The software decoding module is used for software decoding based on the adjusted reference log-likelihood ratio.

[0036] In an optional implementation, the log-likelihood ratio adjustment module is further configured to obtain the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value based on the read voltage characteristic graph; and to obtain the number of cell changes based on the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0037] Thirdly, the present invention provides an electronic device including a processor and a memory, the memory storing a computer program executable by the processor, the processor executing the computer program to implement the data error correction method described in any of the foregoing embodiments.

[0038] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data error correction method as described in any of the foregoing embodiments.

[0039] The present invention provides a data error correction method, apparatus, electronic device, and computer-readable storage medium. The method includes: obtaining the bias read voltage value of a memory cell; performing hard decoding based on the bias read voltage value and a reference read voltage value; obtaining a reference log-likelihood ratio based on the memory's read voltage characteristic graph, the bias read voltage value, and the reference read voltage value; if hard decoding fails, shifting the reference read voltage value by the bias read voltage value in the read voltage characteristic graph; determining the number of cell changes between the shifted reference read voltage value and the reference read voltage value based on the read voltage characteristic graph; adjusting the reference log-likelihood ratio based on the number of cell changes; and performing soft decoding based on the adjusted reference log-likelihood ratio. By adjusting the log-likelihood ratio using the actual number of cell changes, a more accurate log-likelihood ratio is obtained, improving the error correction performance of LDPC, and thus improving the reliability and lifespan of the memory. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This invention provides a schematic flowchart of a data error correction method according to an embodiment of the present invention.

[0042] Figure 2 This diagram illustrates a read voltage characteristic of a memory provided in an embodiment of the present invention.

[0043] Figure 3 This diagram illustrates yet another schematic representation of the read voltage characteristics of the memory provided in an embodiment of the present invention.

[0044] Figure 4 This diagram illustrates yet another schematic representation of the read voltage characteristics of the memory provided in an embodiment of the present invention.

[0045] Figure 5 A block diagram of a data error correction device provided in an embodiment of the present invention is shown;

[0046] Figure 6 A block diagram of an electronic device provided in an embodiment of the present invention is shown.

[0047] Icons: 100 - Electronic device; 110 - Memory; 120 - Processor; 130 - Communication module; 200 - Data error correction device; 210 - Offset voltage value acquisition module; 220 - Hardware decoding module; 230 - Offset module; 240 - Log-likelihood ratio adjustment module; 250 - Software decoding module. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0050] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0051] Please see Figure 1 , Figure 1 A schematic flowchart of a data error correction method provided in an embodiment of the present invention is shown. This data error correction method can be applied to electronic devices. The specific process of this embodiment is described below using an electronic device as an example. The following section addresses... Figure 1 The process shown is explained in detail. This data error correction method may specifically include the following steps:

[0052] Step 110: Obtain the bias read voltage value of the memory cell.

[0053] The memory can be NAND Flash non-volatile memory, and the memory cells can be SLC (Single Level Cell), MLC (Multi Level Cell), TLC, and QLC, etc.

[0054] In some implementations, the electronic device reads the bias voltage value of the memory cell that needs error correction from the memory, the bias voltage value reflecting the data storage status of the memory cell.

[0055] Step 120: Perform hard decoding based on the bias read voltage value and the reference read voltage value, and obtain the reference log-likelihood ratio based on the memory's read voltage characteristic diagram, the bias read voltage value, and the reference read voltage value.

[0056] It should be noted that hard decoding is a common decoding method in digital communication and storage systems. Hard decoding extracts the most likely original data bits from the bias read voltage. The read voltage characteristic diagram of a memory is used to describe the distribution of memory cells under different read voltages, such as... Figure 2 As shown, the horizontal axis of the reading voltage characteristic graph represents the reading voltage, and the vertical axis represents the number of cells.

[0057] In some implementations, the reference read voltage value can be determined based on Gray code.

[0058] For example, each memory cell can store 2 bits, resulting in 4 states (00, 01, 11, 10). These 4 states are represented using Gray code as shown in Table 1. Three reference read voltage values ​​(R1, R2, R3) are set to distinguish these 4 states. Assuming the voltage ranges corresponding to these 4 states are: State 00: 0.0V-1.0V; State 01: 1.0V-2.0V; State 10: 2.0V-3.0V; State 11: 3.0V-4.0V, R1 is set between the voltage ranges of State 00 and State 01, R2 is set between the voltage ranges of State 01 and State 10, and R3 is set between the voltage ranges of State 10 and State 11. Therefore, the reference read voltage values ​​are R1 = 0.5V, R2 = 1.5V, and R3 = 2.5V, respectively.

[0059] state Graymall 00 00 01 01 10 11 11 10

[0060] Table 1

[0061] It's important to note that only one bit differs between two consecutive states. Even if the voltage reading deviates slightly, it will only result in a single bit error, rather than multiple bits being incorrect simultaneously. For example, if the voltage reading fluctuates around 1.0V, the 01 and 10 states encoded using Gray code will only have one bit change, preventing misreading as completely different states and thus reducing the probability of misreading.

[0062] In some implementations, the number of reference read voltage values ​​can be one or more, depending on the specific circumstances. The reference read voltage value can be set between two peaks in the read voltage characteristic diagram, for example, as shown below. Figure 2 As shown, if there is only one reference reading voltage value, R1 can be used as the reference reading voltage value; if there are two reference reading voltage values, R1 and R5 can be used as the reference reading voltage values.

[0063] Step 130: If hardware decoding fails, the reference read voltage value will be offset by the off-read voltage value in the read voltage characteristic graph.

[0064] The direction of the reference read voltage value's offset in the read voltage characteristic graph depends on the distribution of the graph. For example, if the read window between two peaks is narrow, the reference read voltage value between the two peaks can be shifted to the left to widen the read window. It should be noted that shifting the reference read voltage value to the left will cause more memory cells to be classified as lower data states. When the memory is prone to misclassification under higher read voltage states, shifting the reference read voltage value to the left can reduce the bit error rate under higher read voltage states. Conversely, shifting the reference read voltage value to the right will cause more memory cells to be classified as higher data states. When the memory is prone to misclassification under lower read voltage values, shifting the reference read voltage value to the right can reduce the bit error rate under lower read voltage values.

[0065] For example, such as Figure 3 As shown, the offset reading voltage value is 80mV. If the reference reading voltage values ​​are R1 and R5, then R1 and R5 are both offset to the left by 80mV, and the offset reference reading voltage values ​​are R1a and R5a, respectively.

[0066] Step 140: Determine the number of CELL changes between the offset reference reading voltage value and the reference reading voltage value based on the reading voltage characteristic diagram, and adjust the reference log-likelihood ratio according to the number of CELL changes.

[0067] Step 150: Perform soft decoding based on the adjusted reference log-likelihood ratio.

[0068] It should be noted that software decoding can use the adjusted reference log-likelihood ratio to gradually correct data errors through an iterative algorithm.

[0069] The data error correction method provided in this invention obtains the bias read voltage value of the memory cell, performs hard decoding based on the bias read voltage value and a reference read voltage value, and obtains a reference log-likelihood ratio based on the memory's read voltage characteristic graph, the bias read voltage value, and the reference read voltage value. If hard decoding fails, the reference read voltage value is offset by the bias read voltage value in the read voltage characteristic graph. The number of cell changes between the offset reference read voltage value and the reference read voltage value is determined based on the read voltage characteristic graph, and the reference log-likelihood ratio is adjusted based on the number of cell changes. Soft decoding is then performed based on the adjusted reference log-likelihood ratio. By adjusting the log-likelihood ratio based on the actual number of cell changes, a more accurate log-likelihood ratio is obtained, improving the error correction performance of LDPC, thereby improving the reliability and lifespan of the memory.

[0070] In some implementations, since the log-likelihood ratio represents the reliability of a bit, and the number of cell variations has an explicit relationship with the log-likelihood ratio, a relational model can be established and stored in the electronic device. This relational model characterizes the relationship between the number of cell variations, the reference log-likelihood ratio, and the adjusted reference log-likelihood ratio.

[0071] In this embodiment, the reference log-likelihood ratio can be adjusted according to the number of CELL changes and a preset relationship model to obtain the adjusted reference log-likelihood ratio.

[0072] In one example, assuming the offset read count is 5, the relationship model can be established as follows:

[0073] (LLR4,LLR5,LLR6)=f(B1,B2,B3,B4,LLR1,LLR2,LLR3)

[0074] Where B1, B2, B3, and B4 represent the number of cell variations, LLR4, LLR5, and LLR6 represent the adjusted reference log-likelihood ratios, LLR1, LLR2, and LLR3 represent the reference log-likelihood ratios, and f represents the relational model.

[0075] In some implementations, the relational model can be set based on professional experience and historical data. This could be a functional relational model, a rule-based relational model, or other possible relational models.

[0076] As one implementation method, when the relational model is a regular relational model, it can be represented by a table. For example, as shown in Table 2, LLR1 is the reference log-likelihood ratio, LLR2 is the adjusted reference log-likelihood ratio, d and e are adjustment parameters determined empirically, B2 is the number of cell changes after the current offset, and B1 is the number of cell changes after the previous offset.

[0077] LLR1 LLR2 if B2>B1 -b -llr1+d if B2<B1 -b -llr1-e if B2 == B1 -b -llr1

[0078] Table 2

[0079] As another implementation, when the relational model is a functional relationship, the reference log-likelihood ratio can be adjusted based on the functional relationship and the number of cell changes. For example, the functional relationship can be LLR2 = w1*LLR1 + w2*B1, where LLR1 is the reference log-likelihood ratio, LLR2 is the adjusted reference log-likelihood ratio, B1 is the number of cell changes after the current offset, and w1 and w2 are adjustment parameters, which can be set empirically.

[0080] To reduce error correction time, the following steps are included after step 150: if the soft decoding fails, the number of offsets is obtained; if the number of offsets is less than the preset number of offsets, the adjusted reference log-likelihood ratio is adjusted until the soft decoding is successful; if the number of offsets is equal to the preset number of offsets, the adjustment of the adjusted reference log-likelihood ratio is stopped.

[0081] Understandably, during the data error correction process, the reference read voltage value is gradually increased or decreased. By gradually increasing the reference read voltage value, the reference log-likelihood ratio can be gradually adjusted, allowing the LDPC algorithm to gradually adapt to the reference read voltage value. This can reduce decoding failures caused by excessive increases or decreases at once, thereby reducing the number of offsets and improving the decoding capability of LDPC.

[0082] In some implementations, step 120 further includes the following steps: determining the voltage state of the storage unit based on the biased read voltage value and the reference read voltage value; reading the voltage state and verifying the voltage state; if the voltage state verification fails, determining that the hard decoding has failed; if the voltage state verification succeeds, determining that the hard decoding has succeeded.

[0083] In some implementations, the electronic device can compare the bias read voltage value with the reference read voltage value and determine the voltage state of the memory cell based on the comparison result.

[0084] Understandably, this voltage state refers to whether the logic value stored at the corresponding storage location of the storage cell is logic 1 or logic 0.

[0085] For example, if the reference read voltage value is R1, and the offset read voltage value is greater than or equal to the reference read voltage value, then the memory location corresponding to the memory cell is determined to store a logic "1"; if the offset read voltage value is less than the reference read voltage value, then the memory location corresponding to the memory cell is determined to store a logic "0". Similarly, if the reference read voltage values ​​are R1 and R5, and the offset read voltage value is less than R1 or greater than or equal to R5, then the memory location corresponding to the memory cell is determined to store a logic "1"; if the offset read voltage value is greater than or equal to R1 and less than R5, then the memory location corresponding to the memory cell is determined to store a logic "0".

[0086] It should be noted that if the bias voltage value is inaccurate, the data bits in the memory cell cannot be correctly identified, leading to an error in the voltage state judgment of the memory cell. In this case, the voltage state verification fails, thus confirming the failure of hardware decoding. For example, if the bias voltage value is too high or too low, a data bit that should be a logic "0" will be incorrectly decoded as a logic "1".

[0087] To obtain the reference log-likelihood ratio for each interval, step 120 further includes the following steps: dividing the read voltage characteristic graph into multiple intervals based on the bias read voltage value and the reference read voltage value; obtaining the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in each interval; and obtaining the reference log-likelihood ratio for each interval based on the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in each interval.

[0088] In some implementations, the probability of a memory cell having a bit value of 0 and the probability of a bit value of 1 in each memory cell within each interval are calculated based on the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in each memory interval. The ratio of the probability of a memory cell having a bit value of 0 to the probability of a bit value of 1 in each memory interval is calculated, and the logarithm of the ratio is performed to obtain the reference log-likelihood ratio for each interval.

[0089] For example, such as Figure 4 As shown, the biased read voltage value is V2, and the reference read voltage value is V1. Based on the biased read voltage value V2 and the reference read voltage value V1, the read voltage characteristic graph is divided into three intervals: interval A, interval B, and interval C. Taking the reference log-likelihood ratio corresponding to interval A as an example, in interval A, the number of memory cells with a bit value of 0 is 1000, and the number of memory cells with a bit value of 1 is 500. The probability of a memory cell having a bit value of 0 in interval A is 2 / 3 (1000 / 1500 = 2 / 3), and the probability of a memory cell having a bit value of 1 in interval A is 1 / 3 (500 / 1500 = 1 / 3). The reference log-likelihood ratio corresponding to interval A is 0.3.

[0090] In some implementations, step 140 further includes the following steps: obtaining the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value based on the read voltage characteristic diagram; and obtaining the number of cell changes based on the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0091] In some implementations, the electronic device is equipped with preset calculation rules. Based on these rules, the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value are calculated to obtain the number of cell changes. The preset calculation rules can include addition, subtraction, multiplication, division, XOR, and XNOR, etc.

[0092] For example, the preset operation rule is XOR, such as Figure 4As shown, the number of cells corresponding to the reference read voltage value is 3 (CELL2), and the number of cells corresponding to the offset reference read voltage value is 5 (CELL1). The number of cells corresponding to the reference read voltage value 3 is converted to binary 011, and the number of cells corresponding to the offset reference read voltage value 5 is converted to binary 101. XORing 101 and 011 yields the number of cell changes, 110 (decimal 6).

[0093] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a data error correction device is given below. Further, please refer to... Figure 5 The figure shows a functional block diagram of a data error correction device provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the data error correction device provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. The data error correction device 200 includes: a bias voltage value acquisition module 210, a hard decoding module 220, an offset module 230, a log-likelihood ratio adjustment module 240, and a soft decoding module 250, wherein:

[0094] Off-balance voltage value acquisition module 210 is used to acquire the off-balance voltage value of the memory cell;

[0095] The hardware decoding module 220 is used to perform hardware decoding based on the bias read voltage value and the reference read voltage value, and to obtain the reference log-likelihood ratio based on the read voltage characteristic diagram of the memory, the bias read voltage value and the reference read voltage value.

[0096] Offset module 230 is used to offset the reference read voltage value in the read voltage characteristic diagram by an off-read voltage value if hard decoding fails.

[0097] The log-likelihood ratio adjustment module 240 is used to determine the number of CELL changes between the offset reference reading voltage value and the reference reading voltage value based on the reading voltage characteristic diagram, and to adjust the reference log-likelihood ratio based on the number of CELL changes.

[0098] The software decoding module 250 is used for software decoding based on the adjusted reference log-likelihood ratio.

[0099] Furthermore, the log-likelihood ratio adjustment module 240 is also used to obtain the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value according to the read voltage characteristic diagram; and to obtain the number of cell changes according to the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0100] Furthermore, the offset module 230 is also used to obtain the number of offsets if the soft decoding fails; if the number of offsets is less than the preset number of offsets, the adjusted reference log-likelihood ratio is adjusted until the soft decoding is successful; if the number of offsets is equal to the preset number of offsets, the adjustment of the adjusted reference log-likelihood ratio is stopped.

[0101] Furthermore, the hardware decoding module 220 is also used to determine the voltage state of the storage unit based on the bias read voltage value and the reference read voltage value; read the voltage state and verify the voltage state; if the voltage state verification fails, determine that the hardware decoding has failed; if the voltage state verification succeeds, determine that the hardware decoding has succeeded.

[0102] Furthermore, the hard decoding module 220 is also used to divide the read voltage characteristic graph into multiple intervals according to the bias read voltage value and the reference read voltage value; obtain the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in each interval; and obtain the reference log-likelihood ratio corresponding to each interval according to the number of memory cells with a bit value of 0 and the number of memory cells with a bit value of 1 in each interval.

[0103] Furthermore, the hard decoding module 220 is also used to calculate the probability that a storage cell in each interval has a bit value of 0 and the probability that a bit value is 1, based on the number of storage cells with a bit value of 0 and the number of storage cells with a bit value of 1 in each interval; calculate the ratio of the probability that a storage cell in each interval has a bit value of 0 to the probability that a bit value is 1, and perform logarithmic calculation on the ratio to obtain the reference log-likelihood ratio corresponding to each interval.

[0104] Furthermore, the log-likelihood ratio adjustment module 240 is also used to adjust the reference log-likelihood ratio according to the number of CELL changes and the preset relationship model to obtain the adjusted reference log-likelihood ratio.

[0105] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0106] In several embodiments provided by the present invention, the coupling between modules can be electrical, mechanical or other forms of coupling.

[0107] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0108] Please refer to Figure 6 This is a block diagram of an electronic device 100 provided in an embodiment of the present invention. The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, processor 120, and communication module 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0109] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0110] The processor 120 is used to read / write data or programs stored in the memory and perform corresponding functions. For example, when a computer program stored in the memory 110 is executed by the processor 120, the data error correction method disclosed in the above embodiments can be implemented.

[0111] The communication module 130 is used to establish a communication connection between the electronic device 100 and other devices via a network, and to send and receive data via the network.

[0112] It should be understood that, Figure 6 The structure shown is only a schematic diagram of an electronic device; the electronic device may also include components that are larger than those shown. Figure 6 The number of components shown may be more or less. Figure 6 The components shown can be implemented using hardware, software, or a combination thereof.

[0113] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the data error correction method described in the above method embodiments.

[0114] Computer-readable storage media can be electronic storage devices such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, computer-readable storage media includes non-transitory computer-readable storage medium. The computer-readable storage medium has storage space for program code that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code can be compressed, for example, in a suitable form.

[0115] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0116] If the functionality is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0117] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data error correction method, characterized by, The method comprises: obtaining a bias voltage value of a memory cell of a memory; performing hard decoding according to the bias voltage value and a reference read voltage value, and obtaining a reference log likelihood ratio according to a read voltage characteristic map of the memory, the bias voltage value and the reference read voltage value; if the hard decoding fails, offsetting the reference read voltage value in the read voltage characteristic map by the bias voltage value; determining a number of CELL changes between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic map, and adjusting the reference log likelihood ratio according to the number of CELL changes; performing soft decoding according to the adjusted reference log likelihood ratio.

2. The method of claim 1, wherein, The determining of the number of CELL changes between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic map comprises: obtaining a number of CELLS corresponding to the reference read voltage value and a number of CELLS corresponding to the offset reference read voltage value according to the read voltage characteristic map; obtaining the number of CELL changes according to the number of CELLS corresponding to the reference read voltage value and the number of CELLS corresponding to the offset reference read voltage value.

3. The method of claim 1, wherein, After the soft decoding according to the adjusted reference log likelihood ratio, the method further comprises: if the soft decoding fails, obtaining a number of offset times; if the number of offset times is less than a preset number of offset times, continuing to adjust the adjusted reference log likelihood ratio until the soft decoding succeeds; if the number of offset times is equal to the preset number of offset times, stopping the adjustment of the adjusted reference log likelihood ratio.

4. The method of claim 1, wherein, The hard decoding according to the bias voltage value and the reference read voltage value comprises: determining a voltage state of the memory cell according to the bias voltage value and the reference read voltage value; reading the voltage state and verifying the voltage state, and if the voltage state verification fails, determining that the hard decoding fails, and if the voltage state verification succeeds, determining that the hard decoding succeeds.

5. The method of claim 1, wherein, The obtaining of the reference log likelihood ratio according to the read voltage characteristic map of the memory, the bias voltage value and the reference read voltage value comprises: dividing the read voltage characteristic map into a plurality of intervals according to the bias voltage value and the reference read voltage value; obtaining a number of memory cells with bit value 0 and a number of memory cells with bit value 1 in each interval of the memory; obtaining a reference log likelihood ratio corresponding to each interval according to the number of memory cells with bit value 0 and the number of memory cells with bit value 1 in each interval of the memory.

6. The method of claim 5, wherein, The obtaining of the reference log likelihood ratio corresponding to each interval according to the number of memory cells with bit value 0 and the number of memory cells with bit value 1 in each interval of the memory comprises: calculating a probability of bit value 0 and a probability of bit value 1 of the memory cells in each interval according to the number of memory cells with bit value 0 and the number of memory cells with bit value 1 in each interval of the memory. The probability of the bit value of the storage unit in the memory being 0 and the probability of the bit value being 1 in each of the intervals are calculated, and the ratio of the probabilities is logarithmically calculated to obtain a reference log-likelihood ratio corresponding to each of the intervals.

7. The method of claim 1, wherein, The reference log-likelihood ratio is adjusted according to the number of CELL changes, and the adjusted reference log-likelihood ratio is obtained. The reference log-likelihood ratio is adjusted according to the number of CELL changes and a preset relationship model.

8. A data error correction apparatus, characterized by comprising: The device comprises: a bias voltage value obtaining module configured to obtain a bias voltage value of a storage unit of a memory; a hard decoding module configured to perform hard decoding according to the bias voltage value and a reference read voltage value, and obtain a reference log-likelihood ratio according to a read voltage characteristic map of the memory, the bias voltage value and the reference read voltage value; an offset module configured to offset the reference read voltage value by the bias voltage value in the read voltage characteristic map if the hard decoding fails; a log-likelihood ratio adjusting module configured to determine a number of CELL changes between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic map, and adjust the reference log-likelihood ratio according to the number of CELL changes; a soft decoding module configured to perform soft decoding according to the adjusted reference log-likelihood ratio.

9. An electronic device, comprising: The computer program is executed by the processor to implement the data error correction method of any one of claims 1-7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the data error correction method of any one of claims 1-7.

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