Storage forming method and grinding equipment

Abstract

The invention relates to the related technical field of semiconductors, and provides a memory forming method and grinding device.The memory forming method comprises the steps that a to-be-processed wafer is formed, the to-be-processed wafer comprises a substrate and a device layer located on the surface of the substrate, and the device layer comprises a plurality of device structures and an isolation layer; the isolation layer is located between the device structures and on one side surfaces of the device structures away from the substrate; performing first grinding treatment on the isolation layer until the device structure is exposed; and carrying out second grinding treatment on the exposed device structure and the isolation layer by adopting deionized water. According to the invention, the deionized water is adopted to carry out the second grinding treatment on the device structure and the isolation layer, the concentration of the polishing solution left on the base can be diluted, and the surface temperature of the base can be reduced, so that the generation rate of residues is slowed down, the generation of the residues is effectively reduced and inhibited, and the performance reliability of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor-related technologies, and in particular to a method for forming a memory and a grinding device. Background Art

[0002] Memory with three-dimensional stacking structure (such as 3D XPoint) is widely regarded as a key technology path to achieve high-capacity, high-integration non-volatile memory chips due to its good density expansion potential.

[0003] In device structures with two or more layers, achieving interconnection along the stacking direction and precise alignment of upper and lower device structures often requires precise exposure of the underlying critical structures through chemical mechanical polishing (CMP) during an intermediate manufacturing process. However, this polishing process can easily form difficult-to-remove residues, impacting memory performance and reliability. Summary of the Invention

[0004] The present application provides a method for forming a memory and a grinding device, aiming to improve the problem of difficult-to-remove residues easily produced during the grinding stage of the existing process, thereby improving the performance reliability of the memory.

[0005] To achieve the above objectives, the present application discloses, on the one hand, a method for forming a memory, comprising:

[0006] forming a wafer to be processed, wherein the wafer to be processed comprises a substrate and a device layer located on a surface of the substrate, wherein the device layer comprises a plurality of device structures and an isolation layer, wherein the isolation layer is located between the device structures and on a surface of the device structure away from the substrate;

[0007] performing a first grinding process on the isolation layer until the device structure is exposed;

[0008] The exposed device structure and the isolation layer are subjected to a second grinding process using deionized water.

[0009] Optionally, the material of the isolation layer is different from the material of the device structure, and the second grinding process has a grinding speed for the isolation layer greater than a grinding speed for the device structure.

[0010] Optionally, the device structure includes a storage structure and a mask layer located on a surface of the storage structure away from the substrate, and the sidewall surface of the storage structure, the sidewall surface of the mask layer and the surface of the mask layer away from the substrate are all covered with an outer wall protection layer.

[0011] Optionally, the performing a second grinding process on the exposed device structure and the isolation layer using deionized water includes:

[0012] The exposed device structure and the isolation layer are subjected to a second grinding process using deionized water to remove the outer wall protection layer covering the surface of the mask layer away from the substrate until the mask layer is exposed.

[0013] Optionally, the isolation layer is ground using a polishing liquid in the first grinding process, and the spray coverage of deionized water on the device layer surface in the second grinding process is greater than the spray coverage of the polishing liquid on the device layer surface in the first grinding process.

[0014] Optionally, the spray coverage of the deionized water in the second polishing process is larger than the polishing range of the polishing pad of the polishing equipment on the surface of the device layer.

[0015] Optionally, the isolation layer is ground using a polishing liquid in the first grinding process, and a spray flow rate of deionized water in the second grinding process is greater than a spray flow rate of the polishing liquid in the first grinding process.

[0016] Optionally, the spray flow rate of the polishing liquid in the first grinding process is 200 ml / min to 300 ml / min; the spray flow rate of deionized water in the second grinding process is 8000 ml / min to 10000 ml / min.

[0017] Optionally, the device layer includes a plurality of device regions and spacer regions between the device regions. The device structure is located in the device region, and a distance between adjacent device structures in the device region is smaller than a distance between adjacent device regions.

[0018] On the other hand, the present application discloses a grinding device, which is applied to any of the above-mentioned memory forming methods, and the grinding device includes:

[0019] A base, a polishing pad being fixed to one side surface of the base, and the base being used to drive the polishing pad to rotate;

[0020] a wafer carrier structure movable relative to the base, wherein when the wafer carrier structure is in a working position, the wafer carrier structure is located above the polishing pad, and the wafer carrier structure is configured to contact the wafer to be processed and pressurize the wafer to be processed toward the polishing pad;

[0021] A robotic arm is movable relative to the base, and a dressing disk is provided on a side of the robotic arm opposite to the polishing pad, and the dressing disk is used to rub the surface of the polishing pad; a spray port is also provided on the robotic arm.

[0022] Optionally, there are multiple spray outlets arranged at intervals in the extension direction of the robotic arm.

[0023] Optionally, the spray port can slide on the robotic arm along the extension direction of the robotic arm.

[0024] Through the above technical solution, after the device structure is exposed by the first grinding treatment, the device structure and the isolation layer are subjected to a second grinding treatment using deionized water, which can dilute the concentration of the polishing liquid remaining on the base and simultaneously reduce the surface temperature of the base to slow down the rate of residue generation, effectively reducing and inhibiting the generation of residues, thereby improving the performance reliability of the memory.

[0025] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic flow chart of a method for forming a memory provided in an embodiment of the present application;

[0028] Figures 2 to 4 A cross-sectional view of a memory device during formation provided by an embodiment of the present application;

[0029] Figure 5 A cross-sectional view of the memory provided in an embodiment of the present application during the grinding process;

[0030] Figure 6 Schematic diagram of the structure of the grinding equipment provided in the embodiment of the present application Figure 1 ;

[0031] Figure 7 Schematic diagram of the structure of the grinding equipment provided in the embodiment of the present application Figure 2 ;

[0032] Figure 8 A temperature change curve diagram of the polishing pad provided in an embodiment of the present application;

[0033] Figure 9 A table showing test data of the polishing pad provided in the embodiments of the present application at different polishing cycles;

[0034] Figure 10 Schematic diagram of the structure of the grinding equipment provided in the embodiment of the present application Figure 3 .

[0035] Description of reference numerals:

[0036] 10. Wafer to be processed; 101. Substrate; 102. Device layer; 1021. Device structure; 10211. Storage structure; 10212. Mask layer; 10213. Outer wall protection layer; 10214. Packaging layer;

[0037] 1022, isolation layer; 1023, device area; 1024, spacer area;

[0038] 110, first electrode layer; 111, gating layer; 112, second electrode layer; 113, phase change memory layer; 114, third electrode layer;

[0039] 120, conductive layer;

[0040] 130. polishing liquid; 131. second residue;

[0041] 20. Grinding equipment; 201. Base; 202. Wafer carrier structure; 203. Robotic arm; 2031. Spray port; 204. Fixed arm; 2041. Fixed spray nozzle; 205. Grinding pad; 206. Dressing disk. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0043] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this application.

[0044] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0045] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer that may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers and one or more dielectric layers.

[0046] It should be noted that the illustrations provided in the embodiments of the present application are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0047] As described in the background, three-dimensional stacked memory (such as 3D XPoint) is widely considered a key technology path for achieving high-capacity, high-integration non-volatile memory chips due to its good density expansion potential. In a two-layer or multi-layer stacked device structure, in order to achieve interconnection in the stacking direction and precise docking of the upper and lower device structures, it is often necessary to accurately expose the key structures of the lower layer through a chemical mechanical polishing (CMP) process during the intermediate process stage. However, during this polishing process, residues that are difficult to remove are easily formed, thereby affecting the performance and reliability of the memory.

[0048] Specifically, in the process of forming a multi-layer stacked memory, the wafer to be processed includes a device layer and a substrate. The device layer is located on the substrate surface. The device layer includes multiple device structures and an isolation layer. The isolation layer is located between the device structures and on the side of the device structure away from the substrate.

[0049] During the wafer fabrication process, the device structures are typically etched to form separate, discrete structures. An isolation layer is then deposited, filling the gaps between the device structures and on the surface of the device structures facing away from the substrate. During the device structure etching process, a primary residue is likely to form on the surface of the device structures. This primary residue often contains elements such as fluorine (F) and sulfur (S).

[0050] When preparing a new device layer on the side of the device layer facing away from the substrate, the isolation layer covering the device structure's surface facing away from the substrate needs to be removed to achieve precise alignment between the multiple layers. This process is typically accomplished using a chemical mechanical polishing (CMP) process. In some embodiments, a polishing slurry is first used to polish away the isolation layer covering the device structure's surface facing away from the substrate. Once the device structure is exposed, additional polishing with the polishing slurry is continued.

[0051] However, when the device structure is gradually ground to be exposed, the first residue remaining on the surface of the device structure during the previous etching process will also be exposed. The first residue is rich in elements such as fluorine (F) and sulfur (S). During the supplementary grinding process, the temperature of the wafer and the grinding pad is relatively high, and the concentration of the polishing liquid is also high. The first residue is easily mixed with the grinding by-products formed in the polishing liquid (such as compounds containing carbon C, silicon Si, oxygen O and cerium Ce) and redeposited on the surface of the device structure to form a second residue with a complex structure and a large volume. Due to the complex composition and strong adhesion of the second residue, it is difficult to completely remove it with conventional cleaning processes, which will affect the interface cleanliness, graphic accuracy and electrical performance of subsequent process steps, and may ultimately lead to a decrease in product yield.

[0052] Therefore, in order to improve the performance and reliability of the memory by improving the problem of difficult-to-remove second residues generated by the grinding process during the formation of the memory, an embodiment of the present application provides a method for forming a memory.

[0053] Reference Figure 1 , Figure 1 A flow chart of a method for forming a memory provided in an embodiment of the present application. Figure 1 As shown, a method for forming a memory provided in an embodiment of the present application includes:

[0054] Step S100, forming a wafer to be processed, the wafer to be processed comprising a substrate and a device layer located on a surface of the substrate, the device layer comprising a plurality of device structures and an isolation layer, the isolation layer being located between the device structures and on a surface of the device structures away from the substrate;

[0055] Step S200, performing a first grinding process on the isolation layer until the device structure is exposed;

[0056] Step S300 , performing a second grinding process on the exposed device structure and isolation layer using deionized water.

[0057] refer to Figures 2 to 4 , Figures 2 to 4 This is a cross-sectional view of the memory provided in the embodiment of the present application during the formation process. Figure 1 and Figures 2 to 4 , describing in detail the formation process of the memory provided in the embodiment of the present application.

[0058] Before describing in detail the formation process of the memory provided in the embodiment of the present application, the various directions that may be involved in the embodiment of the present application are first defined. The direction in which the device structures 1021 are arranged at intervals is defined as the intersecting first direction and second direction, and the stacking direction of the device structure 1021 is defined as the third direction. Here, any two of the first direction, the second direction, and the third direction intersect. In some embodiments, any two of the first direction, the second direction, and the third direction are perpendicular to each other. The following description will be based on the example of any two of the first direction, the second direction, and the third direction being perpendicular to each other.

[0059] Please refer to Figure 2 In the embodiment of the present application, a wafer 10 to be processed is formed in step S100. The wafer 10 to be processed includes a substrate 101 and a device layer 102 located on a surface of the substrate 101. The device layer 102 includes a plurality of device structures 1021 and an isolation layer 1022. The isolation layer 1022 is located between the device structures 1021 and on a side of the device structure 1021 away from the substrate 101.

[0060] In some embodiments, the base 101 may be a semiconductor substrate, such as silicon (Si), germanium (Ge), a SiGe substrate, a silicon on insulator (SOI), or a germanium on insulator (GOI).

[0061] In some embodiments, the method for forming the wafer 10 to be processed includes: forming a device structure layer on a substrate 101, etching the device structure layer to form a plurality of device structures 1021 arranged in an array along a first direction and a second direction; forming an isolation layer 1022 between the device structures 1021 and on the side surface of the device structure 1021 facing away from the substrate 101.

[0062] In some embodiments, the device structure 1021 includes a storage structure 10211 and a mask layer 10212 located on a surface of the storage structure 10211 facing away from the substrate 101. Before forming the isolation layer 1022, in some embodiments, an outer wall protection layer 10213 is formed on the sidewall surfaces of the storage structure 10211, the sidewall surfaces of the mask layer 10212, and the surface of the mask layer 10212 facing away from the substrate 101.

[0063] The mask layer 10212 serves as a patterned mask for forming the array of memory structures 10211. In some embodiments, the mask layer 10212 may include, but is not limited to, a silicon nitride hard mask (SiN). The first residue formed during the etching process is typically located on the surface of the mask layer 10212 facing away from the substrate 101, as well as on the sidewalls of the memory structures 10211 and the sidewalls of the mask layer 10212.

[0064] The material of the isolation layer 1022 may include, but is not limited to, a spin-on dielectric (SOD). The outer wall protection layer 10213 may be a single layer or multiple layers, and its material may include, but is not limited to, silicon nitride (SiN), silicon oxide (SiO2), etc. The process for forming the outer wall protection layer 10213 includes, but is not limited to, a pulsed plasma process.

[0065] In some embodiments, before forming the outer wall protection layer 10213, an encapsulation layer 10214 is formed on a surface of the mask layer 10212 facing away from the substrate 101. The material of the encapsulation layer 10214 may include, but is not limited to, silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiON). The process for forming the encapsulation layer 10214 includes, but is not limited to, atomic layer deposition and chemical vapor deposition. Before forming the outer wall protection layer 10213 and the isolation layer 1022, pre-sealing the top of the device structure 1021 protects functional materials (such as GST and TiN) from contamination, corrosion, and thermal damage, thereby ensuring the integrity of the subsequent device structure 1021 and the reliability of its electrical performance.

[0066] Further, refer to Figure 2 Taking a phase-change memory as an example, the memory structure 10211 may include a first electrode layer 110, a gate layer 111, a second electrode layer 112, a phase-change memory layer 113, and a third electrode layer 114 stacked along a third direction. The first electrode layer 110, the second electrode layer 112, and the third electrode layer 114 may be made of the same material, such as carbon electrodes. The gate layer 111 may be made of ZnxTey, GexTey, NbxOy, SixAsy, AsxTey, or the like. The phase-change memory layer 113 may be made of a chalcogenide-based material, such as a chalcogenide containing any of the four elements of Group VIA of the periodic table: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).

[0067] In some embodiments, a conductive layer 120 is connected to the side of the first electrode layer 110 facing away from the substrate 101. The conductive layer 120 extends along the second direction and connects the storage structures arranged at intervals along the second direction.

[0068] 10211, serving as a bit line of the phase change memory. In some embodiments, a conductive layer 120 is connected to the side of the first electrode layer 110 facing away from the substrate 101. The conductive layer 120 extends along a first direction and connects the memory structures 10211 spaced apart along the first direction, serving as a word line of the phase change memory.

[0069] Taking a selection-only memory as an example, the storage structure 10211 may include a first electrode layer 110, a selection layer 111, and a second electrode layer 112 stacked along a third direction.

[0070] Please refer to Figure 3 In the embodiment of the present application, in step S200 , the isolation layer 1022 is subjected to a first grinding process until the device structure 1021 is exposed.

[0071] The purpose of the first grinding process is to remove the isolation layer 1022 located on the side of the device structure 1021 facing away from the substrate 101. The grinding liquid used is a polishing liquid. The polishing liquid may include an oxidizing agent (e.g., hydrogen peroxide H2O2), abrasive particles (e.g., cerium oxide CeO2, aluminum oxide Al2O3, or colloidal silicon dioxide SiO2), a pH adjuster (e.g., ammonium hydroxide NH4OH), and other components.

[0072] Since the material of the isolation layer 1022 is different from the material of the device structure 1021, the removal rate of the isolation layer 1022 in the polishing liquid is generally greater than the removal rate of the device structure 1021 material. Therefore, after the isolation layer 1022 is removed and begins to expose the device structure 1021, the overall material removal efficiency decreases while the grinding equipment removes both materials, resulting in a significant downward trend in the torque of the grinding spindle. By real-time monitoring of the torque of the grinding spindle, the end point of the first grinding process can be identified. During the first grinding process, when the torque value of the grinding spindle shows an inflection point and shows a downward trend, it can be confirmed that this is the end point of the first grinding process, and it is determined that the isolation layer 1022 located on the side of the device structure 1021 away from the substrate 101 has been basically removed, and the device structure 1021 is exposed, thereby controlling the grinding process to automatically switch to the second grinding process stage.

[0073] Please refer to Figure 4 In the embodiment of the present application, step S300 uses deionized water to perform a second grinding process on the exposed device structure 1021 and the isolation layer 1022 .

[0074] The purpose of the second grinding process is to expose the mask layer 10212. In some embodiments, the surface of the mask layer 10212 facing away from the substrate 101 is covered only with the outer wall protection layer 10213, and the second grinding process primarily removes the outer wall protection layer 10213. In some embodiments, the surface of the mask layer 10212 facing away from the substrate 101 is covered with the encapsulation layer 10214, and the surface of the encapsulation layer 10214 facing away from the substrate 101 is covered with the outer wall protection layer 10213. The second grinding process primarily removes both the encapsulation layer 10214 and the outer wall protection layer 10213.

[0075] During the second grinding process, as the outer wall protective layer 10213 is gradually removed, the first residue generated during the previous etching process is gradually exposed. The first residue easily reacts chemically with the polishing liquid remaining on the grinding pad of the grinding equipment, further generating a second residue that is difficult to remove. In the embodiment of the present application, the second grinding process uses deionized water as the grinding liquid. On the one hand, it can dilute the polishing liquid remaining on the grinding pad, reducing its concentration, thereby reducing the probability of reaction between the first residue and the polishing liquid; on the other hand, it can reduce the temperature of the grinding pad, thereby slowing the reaction rate of the first residue and the polishing liquid.

[0076] Furthermore, in some embodiments, in order to efficiently reduce the temperature between the grinding pad and the wafer 10 to be processed, the spray coverage of the deionized water on the surface of the device layer 102 in the second grinding process is greater than the spray coverage of the polishing liquid on the surface of the device layer 102 in the first grinding process. Specifically, in the first grinding process stage, the polishing liquid is usually supplied through one or more fixed nozzles, the position of the nozzle is fixed relative to the base of the grinding equipment, and its spray range is relatively small, mainly concentrated in the central area of ​​the base, with the purpose of maintaining local polishing efficiency at a higher concentration. In the second grinding process stage, in order to achieve cooling over a larger area, the spray range of the deionized water is at least greater than the grinding range of the grinding pad of the grinding equipment on the surface of the device layer. In some embodiments, the spray range of the deionized water even covers the entire surface of the base.

[0077] In some embodiments, reference Figure 7 Deionized water is sprayed through the robotic arm 203, and the robotic arm 203 can move relative to the base 201. When the robotic arm 203 is in the working position, the robotic arm 203 is located above the base 201 and extends from the edge of the base 201 toward the structural center of the base 201. There are multiple spray ports 2031 arranged at intervals in the extension direction of the robotic arm 203.

[0078] Reference Figure 8 , Figure 8This is a temperature change curve diagram of the polishing pad provided in the embodiment of the present application, wherein the ordinate represents the temperature of the polishing pad and the abscissa represents time. Curve A represents the temperature change of the polishing pad over time when the memory formation method disclosed in the embodiment of the present application is adopted; curve B represents the temperature change of the polishing pad over time in the formation method in which polishing liquid is always used during the formation of the memory. It can be seen that in the memory formation method disclosed in the embodiment of the present application, the temperature of the polishing pad can be rapidly reduced from 57.4°C to nearly 30°C at 200 seconds, and this temperature control effect can significantly slow down the reaction rate of the first residue and the polishing liquid.

[0079] It is worth mentioning that the second grinding treatment of the present application uses deionized water for grinding, which can not only effectively reduce the formation of the second residue, but also effectively improve the service life of the grinding pad of the grinding equipment. Experimental data show that when the memory is prepared by the memory formation method disclosed in the embodiment of the present application, the service life of the grinding pad is increased from about 200 wafers to about 450 wafers, which significantly reduces the equipment maintenance frequency and operating costs, and further verifies the superiority of the memory formation method disclosed in the present application in terms of process stability and equipment compatibility.

[0080] And reference Figure 9 , Figure 9 This is a test data table of the polishing pad provided in the embodiment of this application at different polishing cycles, Figure 9 It is shown that no matter at the beginning of the life of the polishing pad (eg, 100 pieces) or at the end of the life of the polishing pad (eg, 450 pieces), the formation method disclosed in the present application does not form large pieces of second residue.

[0081] In some embodiments, the spray flow rate of deionized water in the second grinding process is greater than the spray flow rate of the polishing liquid in the first grinding process. Specifically, the spray flow rate of the polishing liquid in the first grinding process is 200ml / min to 300ml / min; the spray flow rate of deionized water in the second grinding process is 8000ml / min to 10000ml / min. Deionized water with a high flow rate can more effectively dilute the polishing liquid and its reaction by-products remaining on the grinding pad in the first grinding process stage, reduce the second residue generated by the secondary reaction, and at the same time, a large amount of sprayed deionized water can quickly take away the heat generated by friction between the wafer and the grinding pad, thereby slowing down the reaction rate of the first residue and the polishing liquid. Furthermore, a large flow rate of deionized water can also more effectively wash away microparticles, reduce the risk of particle residue, and help improve the final product yield.

[0082] In some embodiments, the device layer 102 of a wafer 10 to be processed includes multiple device areas 1023 and spacing areas 1024 located between the device areas 1023 , the device structure 1021 is located in the device area 1023 , and the distance between adjacent device structures 1021 in the device area 1023 is less than the distance between adjacent device areas 1023 . Figure 5 The disclosed embodiment takes the device layer 102 including two device areas 1023 as an example. Because the material of the isolation layer 1022 is different from the material of the device structure 1021, the grinding speed of the isolation layer 1022 in the second grinding process is greater than the grinding speed of the device structure 1021, and a depression is easily formed between the isolation area and the device structure 1021. The polishing liquid 130 remaining on the grinding pad 205 after the first grinding process is easily accumulated in the depression and reacts with the first residue to generate a second residue 131.

[0083] The embodiment disclosed in this application uses high-flow deionized water polishing in the second polishing process, which can significantly dilute the polishing liquid 130 remaining in the recessed area, reducing the probability of it reacting with the first residue to generate the second residue 131, thereby effectively avoiding the formation of the second residue 131 at the junction of the device area 1023 and the spacer area 1024. It should be noted that Figures 2 to 4 The cross-sectional view of the memory during the formation process is shown with only one device region 1023 as an illustration. In some other embodiments, multiple device regions 1023 may also be included.

[0084] Reference Figure 6 In some embodiments, in the method for forming a memory, the grinding device 20 used in the first grinding process and the second grinding process includes a base 201, a carrier structure 202 movable relative to the base 201, and a fixed arm 204. A grinding pad 205 is fixed to one side surface of the base 201. The base 201 is used to drive the grinding pad 205 to rotate. The carrier structure 202 is used to contact the wafer 10 to be processed and apply pressure to the wafer 10 to be processed toward the grinding pad 205. The fixed arm 204 is located above the base 201. The fixed arm 204 is provided with a fixed spray nozzle 2041. The fixed spray nozzle 2041 is used to spray polishing liquid during the first grinding process and spray deionized water during the second grinding process. The fixed spray nozzle 2041 on the fixed arm 204 is fixed in position, and the landing point of the deionized water during the second grinding process is fixed. The spraying range is small, and it is impossible to efficiently cool and rinse the grinding pad 205. At the same time, since the fixed spray nozzles 2041 are mainly concentrated in the structural center of the base 201, the cooling and cleaning capabilities of the edge of the base 201 are very weak, which can easily lead to the formation of second residues 131 on the edge of the wafer on the grinding pad 205 located at the edge of the base 201.

[0085] Therefore, in order to improve the above problems, the present invention provides a grinding device 20, which is applied to any of the above-mentioned memory forming methods. Figure 7 and Figure 10 The polishing device 20 includes: a base 201, a polishing pad 205 fixed to one side surface of the base 201, and the base 201 is used to drive the polishing pad 205 to rotate; a wafer carrier structure 202 movable relative to the base 201. When the wafer carrier structure 202 is in the working position, the wafer carrier structure 202 is used to contact the wafer 10 to be processed and apply pressure to the polishing pad 205; a robotic arm 203 movable relative to the base 201, and a dressing disk 206 is provided on the side of the robotic arm 203 facing the polishing pad 205. The dressing disk 206 is used to rub the surface of the polishing pad. The robotic arm 203 is also provided with a spray nozzle. When the robotic arm 203 is in the working position, the robotic arm 203 is located above the polishing pad 205 and extends from the edge of the base 201 toward the structural center of the base 201. A plurality of spray nozzles 2031 are spaced apart along the extension direction of the robotic arm 203.

[0086] Specifically, in some embodiments, when the robotic arm 203 is in the working position, the robotic arm 203 swings around its end away from the base 201, so that its end close to the base 201 reciprocates above the polishing pad 205, so that during the second polishing process, the spray range of deionized water can cover the entire structural center of the base 201 to the edge of the base 201, thereby achieving uniform cooling and effective rinsing of the polishing pad 205. In some other embodiments, when the robotic arm 203 is in the working position, the robotic arm 203 is located above the polishing pad 205 and extends from the edge of the base 201 toward the structural center of the base 201, and the spray port 2031 can slide on the robotic arm 203 along the extension direction of the robotic arm 203, so that during the second polishing process, the spray range of deionized water can cover the entire structural center of the base 201 to the edge of the base 201, thereby achieving uniform cooling and effective rinsing of the polishing pad 205.

[0087] It should be noted that in the grinding equipment 20 disclosed in the embodiment of the present application, the fixed arm 204 may exist or be removed. When the fixed arm 204 exists, the polishing liquid may be sprayed from the fixed spray nozzle 2041 or from the spray port 2031 of the robotic arm 203. When the fixed arm 204 does not exist, in the first grinding process, the polishing liquid may be sprayed from the spray port 2031 of the robotic arm 203.

[0088] It is worth mentioning that by preparing the memory through the grinding equipment 20 disclosed in the embodiment of the present application, the service life of the grinding pad 205 is increased from about 200 wafers to about 450 wafers, which significantly reduces the equipment maintenance frequency and operating costs, and further verifies the superiority of the memory formation method disclosed in the present application in terms of process stability and equipment compatibility.

[0089] It should be noted that, during the chemical planarization process, the grinding pad 205 is in contact with the wafer 10 to be processed and the polishing liquid 130 for a long time, and its surface will gradually become smooth, resulting in pore structure blockage or decreased surface flatness, affecting the material removal rate and surface uniformity. The dressing disc 206 is used to regularly dress (cut) the surface of the grinding pad 205, restore and maintain the surface roughness and pore structure of the grinding pad 205. Specifically, the dressing disc 206 and the spray port 2031 reuse the same robotic arm 203, and the dressing disc 206 is provided on the side of the robotic arm 203 relative to the grinding pad 205. The side of the dressing disc 206 facing the grinding pad 205 is covered with diamond particles or other materials with high hardness and high wear resistance to frictionally cut with the surface of the grinding pad 205.

[0090] In the embodiments of this application Figure 6 、 Figure 7 and Figure 10 The present invention is intended only to illustrate the basic configuration and operating principle of the grinding apparatus 20 in the embodiments of the present application, and does not limit the specific structure, size ratio, or component layout of the apparatus in detail. Therefore, those skilled in the art may make appropriate adjustments to the structure of the grinding apparatus 20 based on actual needs without affecting the technical solutions and applicability of the embodiments of the present application.

[0091] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0092] The above are only specific implementation methods of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. The content of this specification should not be understood as limiting the present application.

Claims

1. A method for forming a memory, characterized in that: include: forming a wafer to be processed, wherein the wafer to be processed comprises a substrate and a device layer located on a surface of the substrate, wherein the device layer comprises a plurality of device structures and an isolation layer, wherein the isolation layer is located between the device structures and on a surface of the device structure away from the substrate; performing a first grinding process on the isolation layer until the device structure is exposed; The exposed device structure and the isolation layer are subjected to a second grinding process using deionized water.

2. The method for forming a memory according to claim 1, wherein: The isolation layer is made of a material different from that of the device structure, and a grinding speed of the isolation layer in the second grinding process is greater than a grinding speed of the device structure.

3. The method for forming a memory according to claim 1, wherein: The device structure includes a storage structure and a mask layer located on a surface of the storage structure away from a substrate, wherein the sidewall surface of the storage structure, the sidewall surface of the mask layer, and the surface of the mask layer away from the substrate are all covered with an outer wall protection layer; The second grinding process of the exposed device structure and the isolation layer using deionized water includes: The exposed device structure and the isolation layer are subjected to a second grinding process using deionized water to remove the outer wall protection layer covering the surface of the mask layer away from the substrate until the mask layer is exposed.

4. The method for forming a memory according to claim 1, wherein: The isolation layer is ground using a polishing liquid in the first grinding process, and the spray coverage of deionized water on the device layer surface in the second grinding process is greater than the spray coverage of the polishing liquid on the device layer surface in the first grinding process.

5. The method for forming a memory according to claim 4, wherein: The spray coverage of the deionized water in the second polishing process is larger than the polishing range of the polishing pad of the polishing equipment on the surface of the device layer.

6. The method for forming a memory according to claim 1, wherein: The isolation layer is ground using a polishing liquid in the first grinding process, and a spray flow rate of deionized water in the second grinding process is greater than a spray flow rate of the polishing liquid in the first grinding process.

7. The method for forming a memory according to claim 6, wherein: The spray flow rate of the polishing liquid in the first grinding process is 200ml / min to 300ml / min; the spray flow rate of the deionized water in the second grinding process is 8000ml / min to 10000ml / min.

8. A grinding device, characterized in that: Applied to the method for forming a memory according to any one of claims 1 to 7, the grinding device comprises: A base, a polishing pad being fixed to one side surface of the base, and the base being used to drive the polishing pad to rotate; a wafer carrier structure movable relative to the base, wherein when the wafer carrier structure is in a working position, the wafer carrier structure is located above the polishing pad, and the wafer carrier structure is configured to contact the wafer to be processed and pressurize the wafer to be processed toward the polishing pad; A robotic arm is movable relative to the base, and a dressing disk is provided on a side of the robotic arm opposite to the polishing pad, and the dressing disk is used to rub the surface of the polishing pad; a spray port is also provided on the robotic arm.

9. The grinding device according to claim 8, characterized in that There are multiple spray ports arranged at intervals in the extending direction of the robotic arm.

10. The grinding device according to claim 8, characterized in that The spray port can slide on the robotic arm along the extension direction of the robotic arm.

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