Semiconductor structure, forming method thereof, packaging structure and method

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and a packaging structure and method, and the semiconductor structure comprises a substrate which is provided with a dielectric layer; the metal layer is located in the dielectric layer with partial thickness, the dielectric layer is exposed out of the top surface of the metal layer, and the metal layer comprises a first metal layer and a second metal layer covering the first metal layer; the stress barrier structure protrudes from the first metal layer, the stress barrier structure divides the surface of the first metal layer into a plurality of areas, and the second metal layer covers the stress barrier structure; and the interconnection layer covers the metal layer and the dielectric layer. According to the invention, the device yield is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a forming method thereof, and a packaging structure and method thereof. Background Art

[0002] In semiconductor manufacturing, with the development of ultra-large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to decrease. Consequently, the requirements for integrated circuit packaging are also increasing. Building on the two-dimensional packaging within the X and Y planes of multi-chip modules (MCMs), 3D packaging technology stacked along the Z direction has been fully developed, and this 3D packaging technology has higher density.

[0003] Three-Dimensional Integrated Circuits (3D ICs) utilize the Through Silicon Via (TSV) process to form metal pillars within wafers, coupled with metal bumps. This allows for direct three-dimensional interconnection between wafers (chips) or between a chip and a substrate, overcoming the limitations of traditional two-dimensional wiring for semiconductor chips. Compared to traditional stacking technologies such as bonding, this interconnection method offers advantages such as higher three-dimensional stacking density and smaller packaged dimensions, significantly improving chip speed and reducing power consumption. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and a packaging structure and method, which are beneficial to ensuring the electrical connection performance of the packaging structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, on which a dielectric layer is formed; a metal layer, located in a partial thickness of the dielectric layer, the dielectric layer exposing the top surface of the metal layer, the metal layer including a first metal layer and a second metal layer covering the first metal layer; a stress barrier structure, protruding from the first metal layer, the stress barrier structure dividing the surface of the first metal layer into multiple areas, the second metal layer covering the stress barrier structure; and an interconnect layer, covering the metal layer and the dielectric layer.

[0006] Optionally, the dielectric layer includes a first dielectric layer covering the substrate and a second dielectric layer covering the first dielectric layer. The top surface of the first dielectric layer is flush with the top surface of the first metal layer, and the top surface of the second dielectric layer is flush with the second metal layer.

[0007] Optionally, the stress barrier structure and the second dielectric layer are integrated into one structure.

[0008] Optionally, a top surface of the stress barrier structure is lower than a top surface of the second dielectric layer.

[0009] Optionally, a height difference between a top surface of the stress barrier structure and a top surface of the second dielectric layer is 2 nm to 1000 nm.

[0010] Optionally, the first metal layer includes a central region and an edge region surrounding the central region; the stress barrier structure includes a plurality of discrete substructures, and the substructures extend through the central region and / or the edge region of the first metal layer.

[0011] Optionally, the multiple substructures include mutually perpendicular strip structures and / or multiple arc-shaped structures, and the multiple substructures form a centrally symmetrical figure.

[0012] Optionally, the stress barrier structure includes two groups of mutually perpendicular substructures, each group has two mutually parallel substructures, and the multiple substructures form a "well"-shaped morphology.

[0013] Optionally, in the stress barrier structure, the width of the substructure is 2 nm to 10,000 nm; and the spacing between adjacent parallel substructures is 2 nm to 10,000 nm.

[0014] Optionally, the height of the stress barrier structure is 2 nm to 1000 nm.

[0015] Optionally, the material of the stress barrier structure includes one or more of SiO, SiN, SiCN and SiON.

[0016] Correspondingly, an embodiment of the present invention also provides a packaging structure, including: a first wafer; a second wafer bonded to the first wafer, the second wafer including the semiconductor structure provided by an embodiment of the present invention, the interconnection layer of the second wafer in contact with the first wafer; an interconnection through-hole structure, which passes through the dielectric layer and the substrate on the first metal layer and is electrically connected to the first metal layer.

[0017] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric layer and a metal layer located in a partial thickness of the dielectric layer on the substrate, wherein the dielectric layer exposes the top surface of the metal layer, and the metal layer comprises a first metal layer and a second metal layer covering the first metal layer; forming a stress barrier structure protruding from the first metal layer, wherein the stress barrier structure divides the surface of the first metal layer into multiple regions, and the second metal layer covers the stress barrier structure; and forming an interconnection layer covering the metal layer and the dielectric layer.

[0018] Optionally, the steps of forming a dielectric layer on a substrate and a metal layer located in a partial thickness of the dielectric layer include: forming a first dielectric layer covering the substrate; forming a first metal layer in the partial thickness of the first dielectric layer, with the first dielectric layer exposing a top surface of the first metal layer; forming a second dielectric layer covering the first metal layer and the first dielectric layer; and forming a second metal layer on the first metal layer and penetrating the second dielectric layer, with the second dielectric layer exposing a top surface of the second metal layer.

[0019] Optionally, the step of forming the first metal layer in the partial thickness of the first dielectric layer includes: patterning the first dielectric layer to form a first groove in the first dielectric layer; and forming the first metal layer in the groove.

[0020] Optionally, the step of forming a second metal layer on the first metal layer and penetrating the second dielectric layer includes: patterning the second dielectric layer to form a second groove penetrating the second dielectric layer, the second groove exposing the surface of the first metal layer; and forming the second metal layer in the second groove.

[0021] Optionally, in the same step, the second dielectric layer is patterned to form a second groove penetrating the second dielectric layer, and a stress barrier structure protruding from the first metal layer is formed.

[0022] Optionally, the steps of patterning the second dielectric layer to form a second groove penetrating the second dielectric layer and forming a stress barrier structure protruding from the first metal layer include: removing a portion of the thickness of the second dielectric layer above the first metal layer to form an initial groove, and retaining a portion of the second dielectric layer protruding from the bottom of the initial groove as an initial stress barrier structure, wherein the initial stress barrier structure divides the initial groove into multiple areas; removing the remaining thickness of the second dielectric layer at the bottom of the initial groove above the first metal layer to form a second groove exposing the surface of the first metal layer; removing a portion of the height of the initial stress barrier structure, and retaining the remaining initial stress barrier structure protruding from the first metal layer as the stress barrier structure.

[0023] Optionally, in the same step, the remaining thickness of the second dielectric layer at the bottom of the initial groove above the first metal layer is removed, and a portion of the height of the initial stress barrier structure is removed.

[0024] Optionally, the step of removing a portion of the thickness of the second dielectric layer above the first metal layer to form an initial groove includes: forming a first mask layer on the second dielectric layer, the first mask layer having a first mask opening exposing the surface of the second dielectric layer, the first mask layer protruding from the second dielectric layer in the first mask opening dividing the first mask opening into multiple areas; patterning the second dielectric layer along the first mask opening, removing a portion of the thickness of the second dielectric layer above the first metal layer to form an initial groove; after forming the initial groove, further including: removing the first mask layer.

[0025] Optionally, the steps of removing the second dielectric layer having a remaining thickness at the bottom of the initial groove above the first metal layer and removing a portion of the height of the initial stress barrier structure include: forming a second mask layer on the second dielectric layer, the second mask layer having a second mask opening exposing the initial groove; patterning the second dielectric layer in the initial groove along the second mask opening, removing the wafer having a remaining thickness at the bottom of the initial groove above the first metal layer to form a groove, and removing a portion of the height of the initial stress barrier structure to form a stress barrier structure; after forming the groove, further comprising: removing the second mask layer.

[0026] Optionally, in the step of forming a dielectric layer on a substrate and a metal layer located in the dielectric layer with a partial thickness, the first metal layer includes a central region and an edge region surrounding the central region; in the step of forming a stress barrier structure protruding from the first metal layer, the stress barrier structure includes a plurality of discrete substructures, and the substructures extend through the central region and / or edge region of the first metal layer.

[0027] Optionally, in the step of forming the stress barrier structure protruding from the first metal layer, the multiple substructures include mutually perpendicular strip structures and / or multiple arc structures, and the multiple substructures form a centrally symmetrical pattern.

[0028] Optionally, in the step of forming the stress barrier structure protruding from the first metal layer, the stress barrier structure includes two groups of mutually perpendicular substructures, each group has two mutually parallel substructures, and the multiple substructures form a "well"-shaped morphology.

[0029] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a first wafer; providing a second wafer, the second wafer including the semiconductor structure provided by an embodiment of the present invention; bonding the second wafer to the first wafer, the interconnection layer of the second wafer contacting the first wafer; forming an interconnection opening penetrating the dielectric layer and the substrate on the first metal layer, the interconnection opening exposing the surface of the first metal layer; forming an interconnection through-hole structure in the interconnection opening, the interconnection through-hole structure being electrically connected to the first metal layer.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0031] In a semiconductor structure provided by an embodiment of the present invention, a stress barrier structure protrudes from a first metal layer. The stress barrier structure divides the surface of the first metal layer into multiple regions, a second metal layer covers the stress barrier structure, and an interconnect layer covers the metal layer and the dielectric layer. In the embodiment of the present invention, the stress barrier structure is located in the metal layer and divides the surface of the first metal layer into multiple regions, which helps to disperse the internal stress distribution in the metal layer over a large area, making the metal layer less susceptible to deformation. Moreover, in subsequent manufacturing processes, the interconnect layer is electrically connected to the outside through the metal layer, which requires forming an interconnect opening on the side of the metal layer facing away from the interconnect layer, that is, forming an interconnect opening that exposes the first metal layer. The stress barrier structure has the effect of fixing and restraining the first metal layer away from the interconnect opening, and can generate a force opposite to the deformation force of the metal layer toward the interconnect opening, which helps to balance the stress effects on the upper and lower sides of the metal layer, reduce the stress change of the metal layer on the side of the interconnect opening caused by the formation of the interconnect opening, and thus help alleviate the problem of warping of the metal layer due to stress imbalance between the upper and lower sides, thereby improving device yield.

[0032] In the packaging structure provided by the embodiment of the present invention, the second wafer includes the semiconductor structure of the embodiment of the present invention, and the interconnection through-hole structure penetrates the dielectric layer and the substrate on the first metal layer and is electrically connected to the first metal layer; in the embodiment of the present invention, the stress barrier structure is located in the metal layer, and the surface of the first metal layer is divided into multiple areas, which is beneficial to dispersing the internal stress distribution in the metal layer with a larger area, so that the metal layer is not easily deformed. Moreover, in the process of forming the interconnection through-hole structure, it is necessary to form an interconnection opening on the side of the metal layer facing away from the interconnection layer to expose the first metal layer, and the stress barrier structure has the effect of fixing and restraining the first metal layer away from the interconnection opening, and can generate a force opposite to the deformation force of the metal layer toward the interconnection opening, which is beneficial to balancing the stress effects on the upper and lower sides of the metal layer, reducing the stress change of the metal layer on the side of the interconnection opening due to the formation of the interconnection opening, thereby alleviating the problem of warping of the metal layer due to stress imbalance between the upper and lower sides, thereby improving the device yield.

[0033] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a stress barrier structure is formed protruding from a first metal layer. The stress barrier structure divides the surface of the first metal layer into multiple regions. A second metal layer covers the stress barrier structure, forming an interconnection layer covering the metal layer and the dielectric layer. In this embodiment of the present invention, the stress barrier structure is located within the metal layer and divides the surface of the first metal layer into multiple regions. This facilitates distributing the internal stress distribution within a larger area of ​​the metal layer, thereby reducing deformation of the metal layer. Furthermore, in subsequent manufacturing processes, the interconnection layer is electrically connected to the outside through the metal layer, requiring the formation of an interconnection opening on the side of the metal layer facing away from the interconnection layer, i.e., forming an interconnection opening that exposes the first metal layer. The stress barrier structure has the effect of fixing and restraining the first metal layer away from the interconnection opening, thereby generating a force opposite to the deformation force of the metal layer toward the interconnection opening. This facilitates balancing the stress effects on the upper and lower sides of the metal layer, reducing stress changes in the metal layer on the side of the interconnection opening caused by the formation of the interconnection opening, thereby alleviating warping of the metal layer due to stress imbalance between the upper and lower sides, and thereby improving device yield.

[0034] In the packaging method provided by an embodiment of the present invention, a second wafer is provided, and the second wafer includes the semiconductor structure of the embodiment of the present invention, and an interconnection opening is formed that penetrates the dielectric layer and the substrate on the first metal layer, and the interconnection opening exposes the surface of the first metal layer; in the embodiment of the present invention, the stress barrier structure is located in the metal layer, and the surface of the first metal layer is divided into multiple areas, which is conducive to dispersing the internal stress distribution in the metal layer over a larger area, so that the metal layer is not prone to deformation. Moreover, in the step of forming the interconnection opening, the stress barrier structure has the effect of fixing and restraining the first metal layer away from the interconnection opening, and can generate a force opposite to the deformation force of the metal layer toward the interconnection opening, which is conducive to balancing the stress effects on the upper and lower sides of the metal layer, reducing the stress change of the metal layer on one side of the interconnection opening due to the formation of the interconnection opening, thereby alleviating the problem of warping of the metal layer due to stress imbalance between the upper and lower sides, thereby helping to improve the device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 2 It is a structural schematic diagram corresponding to each step of a packaging method;

[0036] Figures 3 and 4 is a schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0037] Figure 5 is a schematic diagram corresponding to an embodiment of the packaging structure of the present invention;

[0038] Figures 6 to 19 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0039] Figures 20 to 22 It is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present invention. DETAILED DESCRIPTION

[0040] As can be seen from the background technology, it is difficult to improve the device yield of the current packaging structure and to ensure the electrical connection performance. Now, based on a packaging method, we analyze the reasons why it is difficult to improve the device yield of the packaging structure and to ensure the electrical connection performance.

[0041] Figures 1 to 2 It is a structural schematic diagram corresponding to each step of the packaging method.

[0042] refer to Figure 1 A first wafer 10 and a second wafer 20 bonded to each other are provided, wherein the first wafer 10 includes an interconnection layer 11 and a substrate 12 located on the interconnection layer 11, the interconnection layer 11 faces the second wafer 20, and a metal layer 13 is formed on the surface of the interconnection layer 11 facing the substrate 12.

[0043] refer to Figure 2 , patterning the substrate 12 to form interconnection through-holes 31 exposing the metal layer 13.

[0044] The interconnection through hole 31 exposes the upper side of the metal layer 13, causing the stress on the upper side of the metal layer 13 to suddenly decrease, which can easily lead to stress imbalance between the upper and lower sides of the metal layer 13, thereby easily causing the metal layer 13 to warp toward the side of the interconnection through hole 31, affecting the device yield. After the interconnection structure is subsequently formed in the interconnection through hole 31, the electrical connection performance between the interconnection structure and the metal layer 13 is affected.

[0045] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, on which a dielectric layer is formed; a metal layer, located in a partial thickness of the dielectric layer, the dielectric layer exposing the top surface of the metal layer, the metal layer including a first metal layer and a second metal layer covering the first metal layer; a stress barrier structure, protruding from the first metal layer, the stress barrier structure dividing the surface of the first metal layer into multiple areas, the second metal layer covering the stress barrier structure; and an interconnect layer, covering the metal layer and the dielectric layer.

[0046] In an embodiment of the present invention, the stress barrier structure is located in the metal layer, and the surface of the first metal layer is divided into multiple areas, which is beneficial to dispersing the internal stress distribution in the metal layer over a larger area, making the metal layer less likely to deform. Moreover, in the subsequent process, the interconnection layer is electrically connected to the outside through the metal layer, and it is necessary to form an interconnection opening on the side of the metal layer facing away from the interconnection layer, that is, to form an interconnection opening exposing the first metal layer. The stress barrier structure has the effect of fixing and restraining the first metal layer facing away from the interconnection opening, and can generate a force opposite to the deformation force of the metal layer toward the interconnection opening, which is beneficial to balancing the stress effects on the upper and lower sides of the metal layer, reducing the stress change of the metal layer on the side of the interconnection opening due to the formation of the interconnection opening, thereby alleviating the problem of warping of the metal layer due to stress imbalance between the upper and lower sides, and thus improving the device yield.

[0047] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 3 and 4 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention.

[0049] Combined with reference Figure 3 and Figure 4 , Figure 3 (a) Yes Figure 3 (b) A cross-sectional view along the AA direction shows a semiconductor structure comprising: a substrate 100 with a dielectric layer 200 formed thereon; a metal layer 400 located within a portion of the dielectric layer 200, with the dielectric layer 200 exposed on the top surface of the metal layer 400; the metal layer 400 comprising a first metal layer 410 and a second metal layer 420 covering the first metal layer 410; a stress barrier structure 240 protruding from the first metal layer 410. The stress barrier structure 240 divides the surface of the first metal layer 410 into multiple regions; the second metal layer 420 covers the stress barrier structure 240; and an interconnect layer 700 covering the metal layer 400 and the dielectric layer 200.

[0050] It should be noted that for the sake of clarity, Figure 3 (b) shows a top view of the top surface of the dielectric layer 200 .

[0051] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0052] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0053] The dielectric layer 200 is used to provide a process platform for forming the metal layer 400 .

[0054] In this embodiment, the material of the dielectric layer 200 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0055] In this embodiment, the dielectric layer 200 includes a first dielectric layer 210 covering the substrate 100 and a second dielectric layer 220 covering the first dielectric layer 210 .

[0056] The first dielectric layer 210 is used to provide a process platform for forming the first metal layer 410 , and the second dielectric layer 220 is used to provide a process platform for forming the second metal layer 420 .

[0057] The metal layer 400 is used to electrically connect to the outside, thereby realizing electrical connection between the interconnection layer 700 and the outside through the metal layer 400. The first metal layer 410 is used to provide a process platform for the formation of the stress barrier structure 240, and the second metal layer 420 is used to encapsulate the stress barrier structure 240 in the metal layer 400, so that the stress barrier structure 240 will not affect the performance of the metal layer 400.

[0058] The dielectric layer 200 exposes the surface of the metal layer 400 , so that the metal layer 400 and the interconnection layer 700 can be electrically connected.

[0059] In this embodiment, during the semiconductor manufacturing process, after forming the first metal layer 410 within the first dielectric layer 210, the top surface of the first metal layer 410 is exposed. Then, the second dielectric layer 220 is formed, and the second metal layer 420 is formed within the second dielectric layer 220, exposing the top surface of the second metal layer 420. Therefore, in this embodiment, the top surface of the first dielectric layer 210 is flush with the top surface of the first metal layer 410, and the top surface of the second dielectric layer 220 is flush with the second metal layer 420.

[0060] The stress isolation structure 240 is used to balance the stress on the upper and lower sides of the metal layer 400 .

[0061] In this embodiment, the stress barrier structure 240 is located in the metal layer 400 and divides the surface of the first metal layer 410 into multiple regions. This helps disperse the internal stress distribution in the metal layer 400 over a larger area, making the metal layer 400 less susceptible to deformation. Furthermore, in subsequent manufacturing processes, the interconnect layer 700 is electrically connected to the outside through the metal layer 400. This requires forming an interconnect opening on the side of the metal layer 400 facing away from the interconnect layer 700, i.e., forming an interconnect opening that exposes the first metal layer 410. The stress barrier structure 240 has the effect of fixing and restraining the first metal layer 410 away from the interconnect opening, thereby generating a force opposite to the deformation force of the metal layer 400 toward the interconnect opening. This helps balance the stresses on the upper and lower sides of the metal layer 400, reducing the stress variation on the metal layer 400 on one side of the interconnect opening caused by the formation of the interconnect opening, thereby alleviating warping of the metal layer 400 due to stress imbalance between the upper and lower sides, and thereby improving device yield.

[0062] In this embodiment, the first metal layer 410 includes a central region and an edge region surrounding the central region; the stress barrier structure 240 includes a plurality of discrete substructures 250 , and the substructures 250 extend through the central region and / or edge region of the first metal layer 410 .

[0063] The surface area of ​​the metal layer 400 is usually large, and accordingly, the surface area of ​​the first metal layer 410 is large. The substructure in the stress barrier structure 240 passes through the middle area and / or edge area of ​​the first metal layer 410, which indicates that the stress barrier structure 240 is distributed in all areas indicated by the first metal layer 410, which is beneficial to further disperse the internal stress distribution in the metal layer 400. When an interconnection opening is formed to expose the first metal layer 410, the stress barrier structure 240 can make the force generated opposite to the deformation force of the metal layer 400 toward the interconnection opening more uniform, which is beneficial to further balance the stress effects on the upper and lower sides of the metal layer 400, thereby further improving the device yield.

[0064] In this embodiment, the multiple substructures 250 include mutually perpendicular strip structures and / or multiple arc-shaped structures, and the multiple substructures 250 form a centrally symmetrical pattern.

[0065] Multiple substructures 250 form a centrally symmetrical pattern, which is conducive to uniform distribution of the constructed stress barrier structure 240 inside the metal layer 400, and is conducive to uniformly dispersing the internal stress distribution in the metal layer 400. When an interconnection opening is formed to expose the first metal layer 410, the stress barrier structure 240 can make the force generated opposite to the deformation force of the metal layer 400 toward the interconnection opening more uniform, which is conducive to further balancing the stress effects on the upper and lower sides of the metal layer 400, thereby also helping to further improve the device yield.

[0066] In this embodiment, the stress barrier structure 240 includes two groups of mutually perpendicular substructures 250, each group having two mutually parallel substructures 250, and the multiple substructures 250 form a "well" shape (such as Figure 3 (as shown in (b)).

[0067] The “well”-shaped substructures 250 are evenly distributed, and can form a stress barrier structure 240 evenly distributed inside the metal layer 400 .

[0068] In other embodiments, the morphology of the stress barrier structure can also be Figure 4 (a)-(e) show the morphology.

[0069] It should be noted that in this embodiment, the width d5 ​​of the substructure 250 in the stress barrier structure 240 should not be too large or too small. If the width d5 ​​of the substructure 250 is too large, it will easily occupy too much space within the metal layer 400, affecting the performance of the metal layer 400. If the width d5 ​​of the substructure 250 is too small, the stress generated by the stress barrier structure 240 formed by the substructure 250 in the metal layer 400 will be insufficient. When forming the interconnect opening to expose the first metal layer 410, it will be difficult to balance the stress effects on the upper and lower sides of the metal layer 400, thereby making it difficult to improve the device yield. Moreover, if the width d5 ​​of the substructure 250 is too small, it will also make it difficult to form the substructure 250, thereby affecting the formation of the stress barrier structure 240. Therefore, in this embodiment, the width d5 ​​of the substructure 250 in the stress barrier structure 240 is 2nm to 10000nm. As an example, in this embodiment, in the stress barrier structure 240 , the width d5 ​​of the substructure 250 is 200 nm.

[0070] It should also be noted that in this embodiment, the spacing d3 between adjacent parallel substructures 250 should not be too large or too small. If the spacing d3 between adjacent parallel substructures 250 is too large, the width d5 ​​of the substructure 250 may be too small, which may result in insufficient stress generated in the metal layer 400 by the stress barrier structure 240 formed by the substructure 250 and may also cause difficulties in forming the stress barrier structure 240. If the spacing d3 between adjacent parallel substructures 250 is too small, the process difficulty of forming the stress barrier structure 240 is increased. Therefore, in this embodiment, the spacing d3 between adjacent parallel substructures 250 is between 2 nm and 10,000 nm. As an example, in this embodiment, the spacing d3 between adjacent parallel substructures 250 is 1,500 nm.

[0071] It should also be noted that in this embodiment, the height d4 of the stress barrier structure 240 should not be too large or too small. If the height d4 of the stress barrier structure 240 is too large, it is likely to cause unnecessary waste of film layers. If the height d4 of the stress barrier structure 240 is too small, it is likely to cause insufficient stress generated by the stress barrier structure 240 in the metal layer 400. When forming the interconnect opening to expose the first metal layer 410, it is difficult to balance the stress effects on the upper and lower sides of the metal layer 400, thereby making it difficult to improve the device yield. For this reason, in this embodiment, the height d4 of the stress barrier structure 240 is 2nm to 1000nm. As an example, in this embodiment, the height d4 of the stress barrier structure 240 is 24nm.

[0072] In this embodiment, the stress barrier structure 240 and the second dielectric layer 220 are integrated into an integral structure.

[0073] In the semiconductor manufacturing process, a second dielectric layer 220 is first formed to cover the first dielectric layer 210 and the first metal layer 410. The second dielectric layer 220 is then patterned to form a groove that exposes the surface of the first metal layer 410. At the same time, a portion of the second dielectric layer 220 that protrudes above the first metal layer 410 is retained as the stress barrier structure 240. Therefore, in this embodiment, the stress barrier structure 240 and the second dielectric layer 220 are integrated into a structure, which simplifies the process flow and improves process efficiency.

[0074] In this embodiment, the top surface of the stress barrier structure 240 is lower than the top surface of the second dielectric layer 220 .

[0075] The top surface of the stress barrier structure 240 is lower than the top surface of the second dielectric layer 220 , which correspondingly makes the top surface of the stress barrier structure 240 lower than the top surface of the second metal layer 420 , so that the second metal layer 420 is connected through the top of the stress barrier structure 240 , thereby facilitating the electrical connection performance of the second metal layer 420 .

[0076] It should be noted that in this embodiment, the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 should not be too large or too small. If the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is too large, the height d4 of the stress barrier structure 240 may be too small, which may lead to insufficient stress generated by the stress barrier structure 240 in the metal layer 400. When forming an interconnect opening to expose the first metal layer 410, it is difficult to balance the stress effects on the upper and lower sides of the metal layer 400, thereby making it difficult to improve the device yield. If the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is too small, the space above the stress barrier structure 240 that connects to the second metal layer 420 may be too small, which may make it difficult to connect the second metal layer 420 and affect the electrical connection performance of the second metal layer 420. Therefore, in this embodiment, the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is 2 nm to 1000 nm. As an example, in this embodiment, the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is 26 nm.

[0077] In this embodiment, the material of the stress barrier structure 240 includes one or more of SiO, SiN, SiCN and SiON.

[0078] The material of the stress barrier structure 240 includes one or more of SiO, SiN, SiCN and SiON. Accordingly, the material of the stress barrier structure 240 is the same as that of the second dielectric layer 220 .

[0079] The interconnection layer 700 is used to electrically connect to the outside through the metal layer 400 when the semiconductor structure is bonded to the outside.

[0080] Figure 5 It is a schematic diagram corresponding to an embodiment of the packaging structure of the present invention.

[0081] refer to Figure 5 The packaging structure includes: a first wafer 10a; a second wafer 20a bonded to the first wafer 10a, the second wafer 20a including the semiconductor structure provided by an embodiment of the present invention, the interconnection layer 700 of the second wafer 20a in contact with the first wafer 10a; an interconnection through-hole structure 810, which penetrates the dielectric layer 200 and the substrate 100 on the first metal layer 410 and is electrically connected to the first metal layer 410.

[0082] The first wafer 10 a and the second wafer 20 a are used to implement wafer-level packaging.

[0083] In this embodiment, the first wafer 10a is bonded to the second wafer 20a, and the interconnection layer 700 of the second wafer 20a contacts the first wafer 10a, thereby achieving electrical connection between the interconnection layer 700 and the first wafer 10a and realizing the basic function of the packaging structure.

[0084] The interconnection via structure 810 is used to electrically connect the metal layer 400 to the outside, thereby achieving electrical connection of the metal layer 400 in the longitudinal direction.

[0085] In this embodiment, the stress barrier structure 240 is located in the metal layer 400 and divides the surface of the first metal layer 410 into multiple regions. This helps disperse the internal stress distribution in the metal layer 400 over a larger area, making the metal layer 400 less susceptible to deformation. Furthermore, during the formation of the interconnection via structure 810, an interconnection opening is formed on the side of the metal layer 400 facing away from the interconnection layer 700, exposing the first metal layer 410. The stress barrier structure 240 has the effect of fixing and restraining the first metal layer 410 away from the interconnection opening, thereby generating a force opposite to the deformation force of the metal layer 400 toward the interconnection opening. This helps balance the stress effects on the upper and lower sides of the metal layer 400, reduces the stress change on the metal layer 400 on one side of the interconnection opening due to the formation of the interconnection opening, and thus helps alleviate the warping of the metal layer 400 caused by the stress imbalance between the upper and lower sides, thereby improving the device yield.

[0086] Figures 6 to 19 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0087] refer to Figure 6 , providing a substrate 100.

[0088] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0089] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0090] Combined with reference Figures 6 to 18A dielectric layer 200 and a metal layer 400 located in a partial thickness of the dielectric layer 200 are formed on a substrate 100, with the dielectric layer 200 exposing the top surface of the metal layer 400. The metal layer 400 includes a first metal layer 410 and a second metal layer 420 covering the first metal layer 410. A stress barrier structure 240 is formed protruding from the first metal layer 410. The stress barrier structure 240 divides the surface of the first metal layer 410 into multiple regions. The second metal layer 420 covers the stress barrier structure 240.

[0091] The dielectric layer 200 is used to provide a process platform for forming the metal layer 400 .

[0092] In this embodiment, the material of the dielectric layer 200 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0093] The metal layer 400 is used to electrically connect to the outside, thereby realizing electrical connection between the interconnection layer 700 and the outside through the metal layer 400. The first metal layer 410 is used to provide a process platform for the formation of the stress barrier structure 240, and the second metal layer 420 is used to encapsulate the stress barrier structure 240 in the metal layer 400, so that the stress barrier structure 240 will not affect the performance of the metal layer 400.

[0094] The dielectric layer 200 exposes the surface of the metal layer 400 , so that the metal layer 400 and the interconnection layer 700 can be electrically connected.

[0095] refer to Figure 6 The step of forming the dielectric layer 200 on the substrate 100 and the metal layer 400 located in a partial thickness of the dielectric layer 200 includes: forming a first dielectric layer 210 covering the substrate 100 .

[0096] The first dielectric layer 210 is used to provide a process platform for forming the first metal layer 410 .

[0097] Combined with reference Figures 6 to 8 , a first metal layer 410 is formed in a partial thickness of the first dielectric layer 210 , and the top surface of the first metal layer 410 is exposed from the first dielectric layer 210 .

[0098] The first dielectric layer 210 exposes the top surface of the first metal layer 410 , preparing for electrical connection between the second metal layer 420 and the first metal layer 410 .

[0099] Accordingly, in this embodiment, the top surface of the first dielectric layer 210 is flush with the top surface of the first metal layer 410 .

[0100] Continue to refer Figure 6The step of forming the first metal layer 410 in the partial thickness of the first dielectric layer 210 includes: patterning the first dielectric layer 210 to form a first groove 310 in the first dielectric layer 210 .

[0101] The first groove 310 is used to provide a space for forming the first metal layer 410 .

[0102] Combined with reference Figure 7 and Figure 8 , a first metal layer 410 is formed in the first groove 310 .

[0103] Specifically, refer to Figure 7 , forming a first metal material layer 430 filling the first groove 310 and covering the first dielectric layer 210 .

[0104] The first metal material layer 430 is used to form the first metal layer 410 .

[0105] refer to Figure 8 , Figure 8 (a) Yes Figure 8 (b) A cross-sectional view along the AA direction shows that the first metal material layer 430 is planarized, the first metal material layer 430 above the first dielectric layer 210 is removed, and the first metal material layer 430 in the first groove 310 is retained as the first metal layer 410 .

[0106] refer to Figure 9 , Figure 9 (a) Yes Figure 9 (b) A cross-sectional view along the AA direction shows a second dielectric layer 220 covering the first metal layer 410 and the first dielectric layer 210 .

[0107] The second dielectric layer 220 is used to provide a process platform for forming the second metal layer 420 .

[0108] Combined with reference Figures 10 to 18 A second metal layer 420 is formed on the first metal layer 410 and penetrates the second dielectric layer 220 , and the second dielectric layer 220 exposes the top surface of the second metal layer 420 .

[0109] A second metal layer 420 is formed on the first metal layer 410 and penetrates the second dielectric layer 220 , so that the second metal layer 420 is electrically connected to the first metal layer 410 to form a metal layer 400 .

[0110] The second dielectric layer 220 exposes the top surface of the second metal layer 420 , preparing for the subsequent electrical connection between the second metal layer 420 and the interconnection layer.

[0111] Accordingly, in this embodiment, the top surface of the second dielectric layer 220 is flush with the second metal layer 420 .

[0112] Combined with reference Figures 10 to 15 The step of forming the second metal layer 420 penetrating the second dielectric layer 220 on the first metal layer 410 includes: patterning the second dielectric layer 220 to form a second groove 320 penetrating the second dielectric layer 220 , where the second groove 320 exposes the surface of the first metal layer 410 .

[0113] The second groove 320 is used to provide a space for forming the second metal layer 420 .

[0114] Combined with reference Figure 17 and Figure 18 , a second metal layer 420 is formed in the second groove 320 .

[0115] Specifically, refer to Figure 17 , Figure 17 (a) Yes Figure 17 (b) A cross-sectional view along the AA direction shows a second metal material layer 440 filling the second groove 320 and covering the second dielectric layer 220 .

[0116] The second metal material layer 440 is used to form the second metal layer 420 .

[0117] refer to Figure 18 , Figure 18 (a) Yes Figure 18 (b) A cross-sectional view along the AA direction shows that the second metal material layer 440 is planarized, the second metal material layer 440 above the second dielectric layer 220 is removed, and the second metal material layer 440 in the second groove 320 is retained as the second metal layer 420 .

[0118] Figures 10 to 14 Specific steps of forming the stress barrier structure 240 are shown.

[0119] The stress isolation structure 240 is used to balance the stress on the upper and lower sides of the metal layer 400 .

[0120] In this embodiment, the stress barrier structure 240 is located in the metal layer 400 and divides the surface of the first metal layer 410 into multiple regions. This helps disperse the internal stress distribution in the metal layer 400 over a larger area, making the metal layer 400 less susceptible to deformation. Furthermore, in subsequent manufacturing processes, the interconnect layer 700 is electrically connected to the outside through the metal layer 400. This requires forming an interconnect opening on the side of the metal layer 400 facing away from the interconnect layer 700, i.e., forming an interconnect opening that exposes the first metal layer 410. The stress barrier structure 240 has the effect of fixing and restraining the first metal layer 410 away from the interconnect opening, thereby generating a force opposite to the deformation force of the metal layer 400 toward the interconnect opening. This helps balance the stresses on the upper and lower sides of the metal layer 400, reducing the stress variation on the metal layer 400 on one side of the interconnect opening caused by the formation of the interconnect opening, thereby alleviating warping of the metal layer 400 due to stress imbalance between the upper and lower sides, and thereby improving device yield.

[0121] In this embodiment, in the step of forming the dielectric layer 200 on the substrate 100 and the metal layer 400 located in the dielectric layer 200 with a partial thickness, the first metal layer 410 includes a central region and an edge region surrounding the central region; in the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the stress barrier structure 240 includes a plurality of discrete substructures 250, and the substructures 250 extend through the central region and / or edge region of the first metal layer 410.

[0122] The surface area of ​​the metal layer 400 is usually large, and accordingly, the surface area of ​​the first metal layer 410 is large. The substructure in the stress barrier structure 240 passes through the middle area and / or edge area of ​​the first metal layer 410, which indicates that the stress barrier structure 240 is distributed in all areas indicated by the first metal layer 410, which is beneficial to further disperse the internal stress distribution in the metal layer 400. When an interconnection opening is formed to expose the first metal layer 410, the stress barrier structure 240 can make the force generated opposite to the deformation force of the metal layer 400 toward the interconnection opening more uniform, which is beneficial to further balance the stress effects on the upper and lower sides of the metal layer 400, thereby further improving the device yield.

[0123] In this embodiment, in the step of forming the stress barrier structure 240 protruding from the first metal layer 410 , the plurality of substructures 250 include mutually perpendicular strip structures and / or a plurality of arc structures, and the plurality of substructures 250 form a centrally symmetrical pattern.

[0124] Multiple substructures 250 form a centrally symmetrical pattern, which is conducive to uniform distribution of the constructed stress barrier structure 240 inside the metal layer 400, and is conducive to uniformly dispersing the internal stress distribution in the metal layer 400. When an interconnection opening is formed to expose the first metal layer 410, the stress barrier structure 240 can make the force generated opposite to the deformation force of the metal layer 400 toward the interconnection opening more uniform, which is conducive to further balancing the stress effects on the upper and lower sides of the metal layer 400, thereby also helping to further improve the device yield.

[0125] In this embodiment, in the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the stress barrier structure 240 includes two groups of mutually perpendicular substructures 250, each group having two mutually parallel substructures 250, and the multiple substructures 250 form a "well" shape (such as Figure 14 (as shown in (b)).

[0126] The “well”-shaped substructures 250 are evenly distributed, and can form a stress barrier structure 240 evenly distributed inside the metal layer 400 .

[0127] In other embodiments, the morphology of the stress barrier structure can also be Figure 16 (a)-(e) show the morphology.

[0128] It should be noted that in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the width d5 ​​of the substructure 250 in the stress barrier structure 240 should not be too large or too small. If the width d5 ​​of the substructure 250 is too large, it will easily occupy too much space within the metal layer 400, affecting the performance of the metal layer 400. If the width d5 ​​of the substructure 250 is too small, the stress generated in the metal layer 400 by the stress barrier structure 240 formed by the substructure 250 will be insufficient. When forming the interconnect opening exposing the first metal layer 410, it will be difficult to balance the stress effects on the upper and lower sides of the metal layer 400, thereby making it difficult to improve the device yield. Moreover, if the width d5 ​​of the substructure 250 is too small, it will also make it difficult to form the substructure 250, thereby affecting the formation of the stress barrier structure 240. To this end, in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the width d5 ​​of the substructure 250 in the stress barrier structure 240 is 2 nm to 10,000 nm. As an example, in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the width d5 ​​of the substructure 250 in the stress barrier structure 240 is 200 nm.

[0129] It should also be noted that in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the spacing d3 between adjacent parallel substructures 250 should not be too large or too small. If the spacing d3 between adjacent parallel substructures 250 is too large, the width d5 ​​of the substructures 250 may be too small, which may result in insufficient stress generated in the metal layer 400 by the stress barrier structure 240 formed by the substructures 250 and may also hinder the formation of the stress barrier structure 240. If the spacing d3 between adjacent parallel substructures 250 is too small, the process difficulty of forming the stress barrier structure 240 is increased. Therefore, in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the spacing d3 between adjacent parallel substructures 250 is between 2 nm and 10,000 nm. As an example, in this embodiment, in the step of forming the stress barrier structure 240 protruding from the first metal layer 410 , the distance d3 between adjacent parallel substructures 250 is 1500 nm.

[0130] It should also be noted that in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the height d4 of the stress barrier structure 240 should not be too large or too small. If the height d4 of the stress barrier structure 240 is too large, it may easily lead to unnecessary waste of film layers. If the height d4 of the stress barrier structure 240 is too small, it may easily lead to insufficient stress generated by the stress barrier structure 240 in the metal layer 400. When forming the interconnect opening exposing the first metal layer 410, it is difficult to balance the stress effects on the upper and lower sides of the metal layer 400, thereby making it difficult to improve device yield. To this end, in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the height d4 of the stress barrier structure 240 is 2nm to 1000nm. As an example, in this embodiment, during the step of forming the stress barrier structure 240 protruding from the first metal layer 410, the height d4 of the stress barrier structure 240 is 24nm.

[0131] In this embodiment, in the same step, the second dielectric layer 220 is patterned to form a second groove 320 penetrating the second dielectric layer 220 , and a stress barrier structure 240 protruding from the first metal layer 410 is formed.

[0132] In the same step, the second dielectric layer 220 is patterned to form the second groove 320 penetrating the second dielectric layer 220 , and the stress barrier structure 240 protruding from the first metal layer 410 is formed, thereby simplifying the process flow and improving process efficiency.

[0133] Accordingly, in this embodiment, in the step of forming the stress barrier structure 240 protruding from the first metal layer 410 , the stress barrier structure 240 and the second dielectric layer 220 are connected to form an integral structure.

[0134] The stress isolation structure 240 and the second dielectric layer 220 are integrated into one structure, which simplifies the process flow and improves the process efficiency.

[0135] In this embodiment, the stress barrier structure 240 protruding from the first metal layer 410 is formed. However, in the step, the material of the stress barrier structure 240 includes one or more of SiO, SiN, SiCN and SiON.

[0136] The material of the stress barrier structure 240 includes one or more of SiO, SiN, SiCN and SiON. Accordingly, the material of the stress barrier structure 240 is the same as that of the second dielectric layer 220 .

[0137] Combined with reference Figure 10 and Figure 11 The steps of patterning the second dielectric layer 220 to form a second groove 320 penetrating the second dielectric layer 220 and forming a stress barrier structure 240 protruding from the first metal layer 410 include: removing a portion of the second dielectric layer 220 above the first metal layer 410 to form an initial groove 300, and retaining a portion of the second dielectric layer 220 protruding from the bottom of the initial groove 300 as an initial stress barrier structure 230. The initial stress barrier structure 230 divides the initial groove 300 into multiple areas.

[0138] First, an initial groove 300 is formed in the second dielectric layer 220 to prepare for forming the second groove 320 . Furthermore, an initial stress barrier structure 230 is formed to preliminarily obtain the morphology of the stress barrier structure 240 for subsequent etching to obtain the stress barrier structure 240 .

[0139] Specifically, refer to Figure 10 , Figure 10 (a) Yes Figure 10 (b) A cross-sectional view along the AA direction shows the step of removing a portion of the second dielectric layer 220 above the first metal layer 410 to form the initial groove 300, including forming a first mask layer 510 on the second dielectric layer 220, wherein the first mask layer 510 has a first mask opening 610 that exposes the surface of the second dielectric layer 220, and the first mask layer 510 protruding from the second dielectric layer 220 in the first mask opening 610 divides the first mask opening 610 into a plurality of regions.

[0140] The first mask layer 510 is used as an etching mask for patterning the second dielectric layer 220 .

[0141] refer to Figure 11 , Figure 11 (a) Yes Figure 11(b) A cross-sectional view along the AA direction shows that the second dielectric layer 220 is patterned along the first mask opening 610 , and a portion of the second dielectric layer 220 above the first metal layer 410 is removed to form an initial groove 300 .

[0142] A portion of the second dielectric layer 220 above the first metal layer 410 is removed. The second dielectric layer 220 is not initially penetrated, but a portion of the second dielectric layer 220 at the bottom of the initial groove 300 is retained. This allows the initial stress barrier structure 230 to be partially removed when the second dielectric layer 220 remaining at the bottom of the initial groove 300 is subsequently removed.

[0143] refer to Figure 12 , Figure 12 (a) Yes Figure 12 (b) A cross-sectional view along the AA direction, after the initial groove 300 is formed, the process further includes: removing the first mask layer 510 .

[0144] The first mask layer 510 is removed to prepare for the subsequent removal of a portion of the initial stress barrier structure 230 , so that there is a height difference between the stress barrier structure 240 and the top surface of the second dielectric layer 220 .

[0145] Combined with reference Figure 13 and Figure 14 , a portion of the initial stress barrier structure 230 is removed, and the remaining initial stress barrier structure 230 protruding from the first metal layer 410 is retained as the stress barrier structure 240 .

[0146] By removing a portion of the height of the initial stress barrier structure 230, a height difference is formed between the top surface of the formed stress barrier structure 240 and the top surface of the second dielectric layer 220. When the second metal layer 420 is formed in the second groove 320, the second metal layer 420 can be connected to form an integrated structure through the space above the stress barrier structure 240, so that the stress barrier structure 240 has little effect on the electrical connection performance of the metal layer 400.

[0147] Accordingly, in this embodiment, the top surface of the stress barrier structure 240 is lower than the top surface of the second dielectric layer 220 .

[0148] The top surface of the stress barrier structure 240 is lower than the top surface of the second dielectric layer 220 , which correspondingly makes the top surface of the stress barrier structure 240 lower than the top surface of the second metal layer 420 , so that the second metal layer 420 is connected through the top of the stress barrier structure 240 , thereby facilitating the electrical connection performance of the second metal layer 420 .

[0149] It should be noted that in this embodiment, during the step of removing a portion of the initial stress barrier structure 230, the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 should not be too large or too small. If the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is too large, the height d4 of the stress barrier structure 240 may be too small, which may result in insufficient stress generated by the stress barrier structure 240 in the metal layer 400. This may make it difficult to balance the stresses on the upper and lower sides of the metal layer 400 when forming an interconnect opening to expose the first metal layer 410, thereby hindering device yield. If the height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is too small, the space above the stress barrier structure 240 that connects to the second metal layer 420 may be too small, which may make it difficult to connect the second metal layer 420 and affect the electrical connection performance of the second metal layer 420. To this end, in this embodiment, during the step of removing a portion of the initial stress barrier structure 230, a height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is 2 nm to 1000 nm. As an example, in this embodiment, during the step of removing a portion of the initial stress barrier structure 230, a height difference d2 between the top surface of the stress barrier structure 240 and the top surface of the second dielectric layer 220 is 26 nm.

[0150] Continue to combine references Figure 13 and Figure 14 , removing the remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 to form a second groove 320 exposing the surface of the first metal layer 410 .

[0151] The remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 is removed to expose the top surface of the first metal layer 410 in preparation for the subsequent formation of the second metal layer 420 electrically connected to the first metal layer 410 .

[0152] In this embodiment, in the same step, the remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 is removed, and a portion of the height of the initial stress barrier structure 230 is removed.

[0153] In the same step, the remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 and a portion of the height of the initial stress barrier structure 230 are removed, which simplifies the process flow and improves process efficiency.

[0154] Specifically, refer to Figure 13 , Figure 13 (a) Yes Figure 13(b) A cross-sectional view along the AA direction shows the steps of removing the remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 and removing a portion of the height of the initial stress barrier structure 230, including forming a second mask layer 520 on the second dielectric layer 220, the second mask layer 520 having a second mask opening 620 exposing the initial groove 300.

[0155] The second mask layer 520 is used as an etching mask for continuing to pattern the second dielectric layer 220 in the initial groove 300 .

[0156] refer to Figure 14 , Figure 14 (a) Yes Figure 14 (b) A cross-sectional view along the AA direction shows that the second dielectric layer 220 in the initial groove 300 is patterned along the second mask opening 620, the remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 is removed to form the second groove 320, and a portion of the height of the initial stress barrier structure 230 is removed to form the stress barrier structure 240.

[0157] The second mask layer 520 only exposes the initial groove 300. Therefore, when etching the second dielectric layer 220 in the initial groove 300, the initial stress barrier structure 230 and the second dielectric layer 220 at the bottom of the initial groove 300 are simultaneously etched. This allows the remaining thickness of the second dielectric layer 220 at the bottom of the initial groove 300 above the first metal layer 410 and the initial stress barrier structure 230 to be removed simultaneously.

[0158] refer to Figure 15 , Figure 15 (a) Yes Figure 15 (b) A cross-sectional view along the AA direction shows that after the second groove 320 is formed, the process further includes: removing the second mask layer 520 .

[0159] The second mask layer 520 is removed to prepare for forming the second metal layer 420 .

[0160] refer to Figure 19 , forming an interconnection layer 700 covering the metal layer 400 and the dielectric layer 200 .

[0161] The interconnection layer 700 is used to electrically connect to the outside through the metal layer 400 when the semiconductor structure is bonded to the outside.

[0162] Figures 20 to 22 It is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present invention.

[0163] refer to Figure 20 , providing a first wafer 10a; providing a second wafer 20a, the second wafer 20a including the semiconductor structure provided by an embodiment of the present invention.

[0164] The first wafer 10 a and the second wafer 20 a are used to implement wafer-level packaging.

[0165] In this embodiment, the stress barrier structure 240 is located in the metal layer 400 and divides the surface of the first metal layer 410 into multiple areas, which is beneficial to dispersing the internal stress distribution in the metal layer 400 over a larger area, making the metal layer 400 less likely to deform.

[0166] Continue to refer Figure 20 , the second wafer 20 a is bonded to the first wafer 10 a , and the interconnection layer 700 of the second wafer 20 a is in contact with the first wafer 10 a .

[0167] In this embodiment, the first wafer 10a is bonded to the second wafer 20a, and the interconnection layer 700 of the second wafer 20a contacts the first wafer 10a, thereby achieving electrical connection between the interconnection layer 700 and the first wafer 10a and realizing the basic function of the packaging structure.

[0168] refer to Figure 21 , forming an interconnection opening 800 penetrating the dielectric layer 220 on the first metal layer 410 and the substrate 100 , and the interconnection opening 800 exposes the surface of the first metal layer 410 .

[0169] The interconnection opening 800 is used to provide a spatial location for the subsequent formation of an interconnection through-hole structure.

[0170] In this embodiment, in the step of forming the interconnection opening 800, the stress barrier structure 240 has the effect of fixing and restraining the first metal layer 410 toward the interconnection opening, which can generate a force opposite to the deformation force of the metal layer 400 toward the interconnection opening, which is beneficial to balancing the stress effects on the upper and lower sides of the metal layer 400, and reducing the stress changes of the metal layer 400 on the side of the interconnection opening due to the formation of the interconnection opening, thereby alleviating the problem of warping of the metal layer 400 due to the imbalance of stress on the upper and lower sides, thereby helping to improve the device yield.

[0171] refer to Figure 22 , an interconnection via structure 810 is formed in the interconnection opening 800 , and the interconnection via structure 810 is electrically connected to the first metal layer 410 .

[0172] The interconnection via structure 810 is used to electrically connect the metal layer 400 to the outside, thereby achieving electrical connection of the metal layer 400 in the longitudinal direction.

[0173] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a dielectric layer formed thereon; a metal layer located in a portion of the dielectric layer, wherein the dielectric layer exposes a top surface of the metal layer, and the metal layer comprises a first metal layer and a second metal layer covering the first metal layer; a stress barrier structure protruding from the first metal layer, the stress barrier structure dividing the surface of the first metal layer into a plurality of regions, and the second metal layer covering the stress barrier structure; The interconnection layer covers the metal layer and the dielectric layer.

2. The semiconductor structure according to claim 1, wherein The dielectric layer includes a first dielectric layer covering the substrate and a second dielectric layer covering the first dielectric layer. The top surface of the first dielectric layer is flush with the top surface of the first metal layer, and the top surface of the second dielectric layer is flush with the second metal layer.

3. The semiconductor structure according to claim 2, wherein: The stress isolation structure and the second dielectric layer are connected to form an integrated structure.

4. The semiconductor structure according to claim 2, wherein: The top surface of the stress barrier structure is lower than the top surface of the second dielectric layer.

5. The semiconductor structure according to claim 4, wherein: A height difference between a top surface of the stress barrier structure and a top surface of the second dielectric layer is 2 nm to 1000 nm.

6. The semiconductor structure according to claim 1, wherein The first metal layer includes a middle region and an edge region surrounding the middle region; The stress barrier structure includes a plurality of discrete substructures, and the substructures extend through the middle region and / or the edge region of the first metal layer.

7. The semiconductor structure according to claim 6, wherein: The multiple substructures include mutually perpendicular strip structures and / or multiple arc-shaped structures, and the multiple substructures form a centrally symmetrical figure.

8. The semiconductor structure according to claim 7, wherein: The stress barrier structure includes two groups of mutually perpendicular substructures, each group has two mutually parallel substructures, and a plurality of the substructures form a "well"-shaped morphology.

9. The semiconductor structure according to claim 8, wherein: In the stress barrier structure, the width of the substructure is 2 nm to 10,000 nm; and the spacing between adjacent parallel substructures is 2 nm to 10,000 nm.

10. The semiconductor structure according to claim 1, wherein: The stress barrier structure has a height of 2 nm to 1000 nm.

11. The semiconductor structure according to claim 1, wherein: The material of the stress barrier structure includes one or more of SiO, SiN, SiCN and SiON.

12. A packaging structure, characterized in that: include: First wafer; a second wafer bonded to the first wafer, the second wafer comprising the semiconductor structure according to any one of claims 1 to 11, an interconnection layer of the second wafer in contact with the first wafer; The interconnected through-hole structure penetrates the dielectric layer and the substrate on the first metal layer and is electrically connected to the first metal layer.

13. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric layer and a metal layer partially located in the dielectric layer on the substrate, wherein the dielectric layer exposes a top surface of the metal layer, and the metal layer comprises a first metal layer and a second metal layer covering the first metal layer; forming a stress barrier structure protruding from the first metal layer, wherein the stress barrier structure divides the surface of the first metal layer into a plurality of regions, and the second metal layer covers the stress barrier structure; An interconnection layer covering the metal layer and the dielectric layer is formed.

14. The method for forming a semiconductor structure according to claim 13, wherein: The steps of forming a dielectric layer on the substrate and a metal layer located in a partial thickness of the dielectric layer include: forming a first dielectric layer covering the substrate; forming the first metal layer in a partial thickness of the first dielectric layer, wherein the first dielectric layer exposes a top surface of the first metal layer; forming a second dielectric layer covering the first metal layer and the first dielectric layer; A second metal layer is formed on the first metal layer and penetrates the second dielectric layer, and the second dielectric layer exposes a top surface of the second metal layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming the first metal layer in the first dielectric layer of a partial thickness includes: patterning the first dielectric layer to form a first groove in the first dielectric layer; The first metal layer is formed in the first groove.

16. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming the second metal layer on the first metal layer and penetrating the second dielectric layer comprises: patterning the second dielectric layer to form a second groove penetrating the second dielectric layer, wherein the second groove exposes the surface of the first metal layer; The second metal layer is formed in the second groove.

17. The method for forming a semiconductor structure according to claim 16, wherein: In the same step, the second dielectric layer is patterned to form a second groove penetrating the second dielectric layer and a stress barrier structure protruding from the first metal layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The steps of patterning the second dielectric layer to form a second groove penetrating the second dielectric layer and forming a stress barrier structure protruding from the first metal layer include: removing a portion of the second dielectric layer above the first metal layer to form an initial groove, and retaining a portion of the second dielectric layer protruding from the bottom of the initial groove as an initial stress barrier structure, wherein the initial stress barrier structure divides the initial groove into a plurality of regions; removing the remaining thickness of the second dielectric layer at the bottom of the initial groove above the first metal layer to form a second groove exposing the surface of the first metal layer; A portion of the initial stress barrier structure at a height is removed, and the remaining initial stress barrier structure protruding from the first metal layer is retained as the stress barrier structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the same step, the remaining thickness of the second dielectric layer at the bottom of the initial groove above the first metal layer is removed, and a portion of the height of the initial stress barrier structure is removed.

20. The method for forming a semiconductor structure according to claim 18, wherein: The step of removing a portion of the second dielectric layer above the first metal layer to form an initial groove includes: forming a first mask layer on the second dielectric layer, the first mask layer having a first mask opening exposing a surface of the second dielectric layer, the first mask layer protruding from the second dielectric layer in the first mask opening dividing the first mask opening into a plurality of regions; patterning the second dielectric layer along the first mask opening, removing a portion of the second dielectric layer above the first metal layer, and forming the initial groove; After forming the initial groove, the method further includes: removing the first mask layer.

21. The method for forming a semiconductor structure according to claim 18, wherein: The step of removing the remaining thickness of the second dielectric layer at the bottom of the initial groove above the first metal layer and removing a portion of the height of the initial stress barrier structure includes: forming a second mask layer on the second dielectric layer, the second mask layer having a second mask opening exposing the initial groove; patterning the second dielectric layer in the initial groove along the second mask opening, removing the remaining thickness of the second dielectric layer at the bottom of the initial groove above the first metal layer to form the second groove, and removing a portion of the height of the initial stress barrier structure to form the stress barrier structure; After forming the second groove, the method further includes: removing the second mask layer.

22. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a dielectric layer and a metal layer located in a partial thickness of the dielectric layer on the substrate, the first metal layer includes a central region and an edge region surrounding the central region; In the step of forming a stress barrier structure protruding from the first metal layer, the stress barrier structure includes a plurality of discrete substructures, and the substructures extend through the middle region and / or the edge region of the first metal layer.

23. The method for forming a semiconductor structure according to claim 22, wherein: In the step of forming a stress barrier structure protruding from the first metal layer, the plurality of substructures include mutually perpendicular strip structures and / or a plurality of arc-shaped structures, and the plurality of substructures form a centrally symmetrical pattern.

24. The method for forming a semiconductor structure according to claim 22, wherein: In the step of forming a stress barrier structure protruding from the first metal layer, the stress barrier structure includes two groups of mutually perpendicular substructures, each group has two mutually parallel substructures, and the multiple substructures form a "well" shape.

25. A packaging method, characterized in that: include: providing a first wafer; Providing a second wafer, wherein the second wafer comprises the semiconductor structure according to any one of claims 1 to 11; bonding the second wafer to the first wafer, with the interconnect layer of the second wafer in contact with the first wafer; forming an interconnection opening penetrating the dielectric layer and the substrate on the first metal layer, wherein the interconnection opening exposes a surface of the first metal layer; An interconnection via structure is formed in the interconnection opening, the interconnection via structure being electrically connected to the first metal layer.

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