Adaptive ramp compensation circuit system applied to buck-boost circuit

Abstract

This application relates to the field of analog integrated circuit design and discloses an adaptive ramp compensation circuit system applied to buck-boost circuits. The system mainly includes a current sensor and a ramp signal generator. The current sensor mirrors the current of the pull-up power transistor to the pull-up mirror transistor at a specific ratio, converting it into a voltage signal through a sensing resistor. The ramp signal generator reduces the influence of the input voltage on the ramp signal slope through a voltage divider resistor network, and the switching state of the reset switch is controlled by a reset signal controlled by a pulse width modulation signal and a clock signal. By introducing a pulse width modulation control signal, this application ensures that the ramp signal generator operates only when the pull-up power transistor is on, effectively solving the subharmonic oscillation problem that may occur in buck-boost circuits when the duty cycle is greater than 50%. Simultaneously, the resistor voltage divider reduces the influence of the input voltage on the ramp signal, improving the circuit's stability and anti-interference capability.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design, and more particularly to an adaptive ramp compensation technique for buck-boost converters. Background Technology

[0002] In power management systems, buck-boost circuits (step-down to boost converters) are widely used because they can provide stable output over a wide input voltage range. Traditional buck-boost circuits typically employ peak current mode control, such as... Figure 1 As shown, the reference voltage Vref and feedback voltage Vfb are used as inputs to the operational amplifier Gm, generating a voltage error Verr. The voltage error Verr serves as a limit for the current peak value and is compared with Vsen, which represents the peak inductor current. The Vsen signal is obtained by injecting ramp compensation into the inductor current sampling signal. When the clock pulse arrives, the RS flip-flop is set to 1, the main power switch S_HS is turned on, and Vsen increases with the inductor current. When Vsen intersects with Verr, the RS flip-flop is set to 0 and held, the power switch is turned off, and Vsen decreases with the inductor current. The process repeats when the next clock pulse arrives.

[0003] However, under peak current mode control, the BUCK-BOOST circuit is prone to subharmonic oscillations when the duty cycle is greater than 50%, which seriously affects the stability and reliability of the circuit. To solve this problem, ramp compensation is usually introduced into the current sampling signal. However, the ramp signal generator in the traditional ramp compensation circuit system operates continuously throughout the entire operating cycle of the BUCK-BOOST circuit. This not only results in poor anti-interference capability, but also, when the duty cycle exceeds 50%, the falling edge of the ramp signal during the turn-off period may cause the sampling signal to rise instead of fall during the inductor current decrease, further exacerbating the subharmonic oscillation problem.

[0004] Furthermore, the slope of a traditional ramp signal generator is easily affected by changes in the input voltage. When the input voltage is disturbed, the ramp signal will generate large ripples, affecting system stability. At the same time, since the ramp signal generator operates continuously throughout the entire cycle, it also increases the system's static power consumption.

[0005] Therefore, how to design a BUCK-BOOST circuit ramp compensation system that can effectively suppress subharmonic oscillations, improve anti-interference capabilities, and reduce power consumption has become a technical problem that urgently needs to be solved in the field of power management integrated circuit design. Summary of the Invention

[0006] The purpose of this application is to provide an adaptive ramp compensation circuit system for BUCK-BOOST circuits to solve the problems mentioned in the background art.

[0007] This application discloses an adaptive ramp compensation circuit system applied to BUCK-BOOST circuits, comprising:

[0008] The current sensor includes a pull-up power transistor S_HS and a pull-up mirror transistor S_HS_mir, wherein the size ratio of S_HS and S_HS_mir is m:1, and they share the source voltage Vsw and the gate control signal PWM_HS; one end of the sensing resistor Rs is connected to the drain of S_HS_mir, and the other end is grounded, which is used to convert the current of S_HS_mir into a voltage signal Vsen.

[0009] A ramp signal generator includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. One end of R2 is connected to the power supply voltage Vin, and the other end is connected to one end of R1. The other end of R1 is grounded. The inverting input of a second operational amplifier AMP2 is connected to the midpoint between R1 and R2, and the non-inverting input is connected to one end of an adjustable resistor R3 and the drain of a first P-type MOSFET M1. The output of AMP2 is connected to the gates of M1 and the second P-type MOSFET M2. The drain of M2 is connected to one end of a capacitor C and the drain of a reset N-type switch S11. The source of S11 is connected to the other end of C and to Vsen.

[0010] The RST signal generation circuit is used to receive the clock signal Clk and the pulse width modulation signal PWM, generate the reset signal RST and connect it to the gate of S11.

[0011] The comparator COMP has its positive input connected to one end of the C to obtain a superimposed voltage signal VCr, and its inverting input connected to the voltage error signal Verr.

[0012] In a preferred embodiment, the RST signal generation circuit includes a first delay module Delay(T1), a second delay module Delay(T2), three inverters, an OR gate, and a NOR gate. Clk is sequentially passed through Delay(T1) and the first inverter, and then input to the NOR gate along with its inverted signal. The signal of Clk, delayed by Delay(T1), is then passed through Delay(T2) and the second inverter before being input to the NOR gate. The output of the NOR gate is connected to the first input of the OR gate. PWM is connected to the second input of the OR gate after passing through the third inverter. The output of the OR gate is RST. When PWM is high, RST outputs a narrow pulse, controlling S11 to turn off, thus enabling the ramp signal generator to operate. When PWM is low, RST remains low, controlling S11 to turn on, thus turning off the ramp signal generator. The delay time T2 of Delay(T2) is greater than the delay time T1 of Delay(T1).

[0013] In a preferred embodiment, the current sensor further includes a first operational amplifier AMP1, an n-type MOSFET Mn1, a first P-type MOSFET Mp1, and a second P-type MOSFET Mp2; the non-inverting input terminal of AMP1 is connected to the input voltage Vin, the inverting input terminal is connected to the input clamping voltage node Vin_Clp, and the output terminal is connected to the gate of Mn1; the source of Mn1 is connected to Vin_Clp, and the drain is connected to the drain of Mp1; the sources of Mp1 and Mp2 are both connected to the power supply pin Vboot, and their gates are connected to form a current mirror; the drain of Mp2 is connected to Rs.

[0014] In a preferred embodiment, one end of R2 is connected to the power supply voltage, and the other end is connected to one end of R1 to form a voltage divider node, and the other end of R1 is grounded; AMP2, M1 and R3 form a voltage-to-current conversion circuit, wherein the inverting input terminal of AMP2 is connected to the voltage divider node, the non-inverting input terminal is connected to one end of R3 and the drain of M1, and the output terminal controls the gates of M1 and M2 to convert the voltage divider voltage into a charging current.

[0015] In a preferred embodiment, the system controls the BUCK-BOOST circuit in peak current mode, including the following operation: the reference voltage Vref and the feedback voltage Vfb are used as inputs to the transconductance amplifier Gm to generate Verr; when the Clk pulse arrives, the RS flip-flop RS is set to 1, S_HS is turned on, and the inductor current IL rises; when VCr intersects with Verr, RS is set to 0, and S_HS is turned off; when the next clock pulse arrives, the above process is repeated.

[0016] In a preferred embodiment, within one clock cycle T: at time t0, the clock pulse arrives; t0-t2 is the PWM high-level period, during which the current sensor operates and IL rises; during the time period t0-t1, the ramp signal generator operates simultaneously, and VCr rises rapidly; during the time period t1-t2, the ramp signal generator stops operating, and VCr rises slowly only due to the influence of IL; during the time period t2-t0, both the current sensor and the ramp signal generator stop operating, and VCr drops to its initial value.

[0017] In a preferred embodiment, the system is suitable for BUCK-BOOST circuits with operating frequencies ranging from tens of kHz to hundreds of kHz; the Vin input range is 3-20V, and the output voltage Vout range is 1-12V; the size ratio m of S_HS and S_HS_mir ranges from 100 to 1000, and the resistance value of Rs ranges from 0.1 to 1 ohm.

[0018] In a preferred embodiment, the delay time T2 of Delay(T2) is greater than the delay time T1 of Delay(T1), and the difference (T2-T1) determines the narrow pulse width of RST; when PWM is high, RST outputs a narrow pulse to enable the ramp signal generator to work; when PWM is low, RST remains low to turn off the ramp signal generator.

[0019] The adaptive ramp compensation circuit system for BUCK-BOOST circuits provided in this application has the following technical advantages:

[0020] By introducing an adaptive RST signal controlled by a PWM signal, the ramp signal generator operates only during the rise of the inductor current IL, effectively suppressing subharmonic oscillations and improving system stability. Figure 4 As shown, when the duty cycle exceeds 50%, the Vramp signal in a conventional ramp compensation circuit will have a falling edge during the off-time (Toff), causing the VCr signal to rise during the IL falling period, resulting in subharmonic oscillation. This application, however, avoids this problem by controlling the RST signal to ensure that Vramp is only effective during the t0-t1 time period.

[0021] By combining resistor voltage division and adaptive enable, the impact of input ripple is reduced, while the system's static power consumption is decreased, thus improving the system's anti-interference performance. For example... Figure 3 As shown in (a), the voltage divider resistors R1 and R2 divide the input voltage Vin, reducing the impact of Vin variations on the slope of the ramp signal. Simultaneously, since the RST signal shuts off most of the ramp generator's operating time, the impact of Vin ripple on VCr is further reduced.

[0022] The current sensor and ramp signal generator circuits have simple structures and high integration, which helps to reduce costs and improve reliability. For example... Figure 2 As shown, the current sensor achieves efficient current sampling through the proportional configuration of the pull-up power transistor S_HS and the pull-up mirror transistor S_HS_mir. Figure 3 As shown, the ramp signal generator and RST signal generation circuit adopt a simple structural design, which is easy to integrate and implement.

[0023] This application solves the subharmonic oscillation problem that may occur in traditional ramp compensation circuits when the duty cycle is greater than 50% in BUCK-BOOST circuits, improving the stability and reliability of the circuit. At the same time, by reducing the sensitivity to input voltage changes, it enhances the anti-interference capability of the system. It is suitable for BUCK-BOOST circuits with operating frequencies from tens of kHz to hundreds of kHz, with an input voltage range of 3-20V and an output voltage range of 1-12V.

[0024] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the circuit operation scenario of an adaptive ramp compensation circuit system applied to a BUCK-BOOST circuit according to an embodiment of this application.

[0026] Figure 2 This is a schematic diagram of a current sensor for an adaptive ramp compensation circuit system applied to a BUCK-BOOST circuit according to an embodiment of this application.

[0027] Figure 3 This is a schematic diagram of a ramp signal generator for an adaptive ramp compensation circuit system applied to a BUCK-BOOST circuit according to an embodiment of this application, wherein... Figure 3 (a) is the circuit schematic of the ramp signal generator. Figure 3 (b) is the schematic diagram of the RST signal generation circuit.

[0028] Figure 4 This is a waveform diagram of the adaptive ramp compensation circuit system applied to the BUCK-BOOST circuit according to an embodiment of this application. Detailed Implementation

[0029] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Explanation of some concepts:

[0031] BUCK-BOOST circuit: refers to a DC-DC converter that can achieve an output voltage higher or lower than the input voltage by controlling the switching transistor to transfer energy.

[0032] Peak current mode control: refers to a control method for switching power supplies that controls the turn-on and turn-off times of the switching transistor by detecting the peak value of the inductor current and comparing it with a reference value.

[0033] Slope compensation: In peak current mode control, a ramp signal that varies linearly with time is superimposed on the current sampling signal to suppress subharmonic oscillations.

[0034] Subharmonic oscillation: refers to an unstable phenomenon that occurs in switching power supplies, where the oscillation frequency is half or lower than the switching frequency, which can lead to a decrease in system performance.

[0035] Duty cycle: refers to the ratio of the on-time of the switch to the total time of the entire switching cycle, expressed as a percentage.

[0036] PWM: Pulse Width Modulation signal, which controls the turn-on and turn-off of power switching transistors by adjusting the proportion of the high-level duration.

[0037] Current mirror: a circuit structure that replicates a reference current at a specific ratio, used in this application to achieve accurate current detection.

[0038] RST signal: Reset signal, used to control the working state of the ramp signal generator.

[0039] The following is a brief summary of some of the innovative aspects of this application:

[0040] In summary, based on an in-depth analysis of the subharmonic oscillation problem and its causes in BUCK-BOOST circuits under peak current mode control, this application proposes a composite ramp compensation solution integrating adaptive enable and resistor voltage divider technology. By introducing an RST signal generation mechanism modulated by a PWM signal, precise control of the ramp signal generator's operating cycle is achieved, ensuring compensation is only provided during the rising phase of the inductor current IL. This cleverly avoids the subharmonic oscillation problem caused by the asynchronous change of the compensation signal and inductor current when the duty cycle exceeds 50% in traditional ramp compensation. Simultaneously, this application utilizes a voltage divider network constructed by the first and second voltage divider resistors R1 and R2, combined with a voltage-to-current conversion circuit formed by the second operational amplifier AMP2, the first P-type MOSFET M1, and the adjustable resistor R3, to effectively suppress input voltage Vin fluctuations, solving the system stability problem caused by the slope being affected by the input voltage in traditional ramp compensation. Furthermore, the RST signal generation circuit in this application employs a cascaded structure of dual delay modules Delay(T1) and Delay(T2), combined with NOR and OR gates, to achieve precise control over the narrow pulse width, ensuring optimal compensation across different operating frequencies and duty cycles. The synergistic effect of these technical features not only effectively solves the stability problem of the BUCK-BOOST circuit under high duty cycle conditions but also improves the system's anti-interference capability by reducing sensitivity to input voltage fluctuations. Simultaneously, it reduces static power consumption by decreasing the operating time of the ramp generator, forming a technical solution that achieves an optimal balance between performance, stability, and power consumption. This provides strong technical support for the reliable operation of the BUCK-BOOST circuit in complex application environments.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "BUCK-BOOST" and "buck-boost converter BUCK-BOOST" refer to the same technical feature, and "PWM" and "pulse width modulation signal PWM" refer to the same technical feature. Other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0043] Buck-Boost converter;

[0044] Pulse Width Modulation (PWM) signal;

[0045] Pull-up power transistor S_HS;

[0046] Pull up the mirror tube S_HS_mir;

[0047] Sensing resistance Rs;

[0048] Clock signal Clk;

[0049] First operational amplifier AMP1;

[0050] Second operational amplifier AMP2; n-type MOSFET Mn1;

[0051] First P-type MOSFET Mp1;

[0052] The second P-type MOSFET Mp2;

[0053] First P-type MOSFET M1;

[0054] The second P-type MOSFET M2;

[0055] Reset N-type switch S11;

[0056] First voltage divider resistor R1;

[0057] Second voltage divider resistor R2;

[0058] Adjustable resistor R3;

[0059] Capacitor C;

[0060] Reset signal RST;

[0061] Reference voltage Vref;

[0062] Feedback voltage Vfb;

[0063] Transconductance amplifier Gm;

[0064] Voltage error Verr;

[0065] Inductor current sampling signal Vsen; RS flip-flop RS;

[0066] Input voltage Vin;

[0067] Input clamping voltage Vin_Clp; inductor current IL;

[0068] Source voltage Vsw;

[0069] Pull-up transistor control signal PWM_HS;

[0070] The first delay module is Delay(T1);

[0071] The second delay module is Delay(T2);

[0072] The superimposed voltage VCr of current sensing and ramp signal;

[0073] Process, voltage, and temperature variations (PVT);

[0074] Comparator COMP;

[0075] First high-side drive signal HDRV1;

[0076] First low-side drive signal LDRV1;

[0077] Second high-side drive signal HDRV2;

[0078] The second low-side drive signal is LDRV2.

[0079] In this specification, to maintain brevity, the same technical feature is presented in the form of "Chinese name + English code" when it first appears, and may be presented in the form of only its English code when it appears thereafter. These different forms of expression refer to the same technical feature.

[0080] The first embodiment of this application relates to an adaptive ramp compensation circuit system applied to a BUCK-BOOST circuit, such as Figures 1 to 3 As shown, it includes:

[0081] The current sensor includes a pull-up power transistor S_HS and a pull-up mirror transistor S_HS_mir, wherein the size ratio of the pull-up power transistor and the pull-up mirror transistor is m:1, and both share the source voltage Vsw and the gate control signal PWM_HS; one end of the sensing resistor Rs is connected to the drain of the pull-up mirror transistor, and the other end is grounded, which is used to convert the current of the pull-up mirror transistor into a voltage signal Vsen.

[0082] A ramp signal generator includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. One end (the upper end) of the second voltage divider resistor is connected to the power supply voltage Vin, and the other end (the lower end) is connected to one end (the upper end) of the first voltage divider resistor. The other end (the lower end) of the first voltage divider resistor is grounded. The inverting input of a second operational amplifier AMP2 is connected to the midpoint between the first and second voltage divider resistors, and the non-inverting input is connected to one end (the upper end) of an adjustable resistor R3 and the drain of a first P-type MOSFET M1. The output of the second operational amplifier is connected to the gates of the first and second P-type MOSFETs M2, respectively. The drain of the second P-type MOSFET is connected to one end (the upper end) of a capacitor C and the drain of a reset N-type switch S11. The source of the reset N-type switch is connected to the other end (the lower end) of the capacitor and is connected to the voltage signal Vsen.

[0083] The RST signal generation circuit is used to receive the clock signal Clk and the pulse width modulation signal PWM, generate the reset signal RST and connect it to the gate of the reset N-type switch.

[0084] The comparator COMP has its positive input connected to one end (i.e. the upper end) of the capacitor to obtain the superimposed voltage signal VCr, and its inverting input connected to the voltage error signal Verr.

[0085] Optionally, the RST signal generation circuit includes a first delay module DelayT1, a second delay module DelayT2, three inverters, an OR gate, and a NOR gate;

[0086] The clock signal passes through the first delay module and the first inverter in sequence, and is then input to the NOR gate along with the inverted clock signal.

[0087] The clock signal, after being delayed by the first delay module, is then passed through the second delay module and the second inverter before being input to the NOR gate.

[0088] The output of the NOR gate is connected to the first input of the OR gate;

[0089] The pulse width modulation signal is connected to the second input terminal of the OR gate after passing through the third inverter;

[0090] The output of the OR gate is the reset signal. When the pulse width modulation signal is high, the reset signal outputs a narrow pulse, which controls the reset N-type switch to turn off, enabling the ramp signal generator to work. When the pulse width modulation signal is low, the reset signal remains low, which controls the reset N-type switch to turn on, turning off the ramp signal generator.

[0091] The delay time T2 of the second delay module is greater than the delay time T1 of the first delay module.

[0092] Optional, see Figure 2 The current sensor further includes a first operational amplifier AMP1, an n-type MOSFET Mn1, a first P-type MOSFET Mp1, and a second P-type MOSFET Mp2. The non-inverting input terminal of the first operational amplifier is connected to the input voltage Vin, the inverting input terminal is connected to the input clamping voltage node Vin_Clp, and the output terminal is connected to the gate of the n-type MOSFET. The source of the n-type MOSFET is connected to the input clamping voltage node, and the drain is connected to the drain of the first P-type MOSFET. The sources of both the first and second P-type MOSFETs are connected to the power supply pin Vboot, and their gates are connected to form a current mirror. The drain of the second P-type MOSFET is connected to the sensing resistor.

[0093] Optional, see Figure 3 a. One end (i.e., the upper end) of the second voltage divider resistor is connected to the power supply voltage, and the other end (i.e., the lower end) is connected to one end (i.e., the upper end) of the first voltage divider resistor to form a voltage divider node. The other end (i.e., the lower end) of the first voltage divider resistor is grounded. The second operational amplifier, the first P-type MOS transistor, and the adjustable resistor form a voltage-to-current conversion circuit. The inverting input terminal of the second operational amplifier is connected to the voltage divider node, the non-inverting input terminal is connected to one end (i.e., the upper end) of the adjustable resistor and the drain of the first P-type MOS transistor, and the output terminal controls the gates of the first and second P-type MOS transistors to convert the voltage divider voltage into a charging current.

[0094] Optional, see Figure 1 and Figure 4 The system controls the BUCK-BOOST circuit in peak current mode, including the following operation: the reference voltage Vref and the feedback voltage Vfb are used as inputs to the transconductance amplifier Gm to generate a voltage error Verr; when the clock signal pulse arrives, the RS flip-flop RS is set to 1, the pull-up power transistor is turned on, and the inductor current IL rises; when the superimposed voltage signal intersects with the voltage error, the RS flip-flop is set to 0, and the pull-up power transistor is turned off; when the next clock pulse arrives, the above process is repeated.

[0095] Optional, see Figure 4Within one clock cycle T: At time t0, the clock pulse arrives; t0-t2 is the period when the pulse width modulation signal is at a high level, during which the current sensor works and the inductor current rises; during the time period t0-t1, the ramp signal generator works simultaneously, and the superimposed voltage signal rises rapidly; during the time period t1-t2, the ramp signal generator stops working, and the superimposed voltage signal rises slowly only due to the influence of the inductor current; during the time period t2-t0, both the current sensor and the ramp signal generator stop working, and the superimposed voltage signal drops to its initial value.

[0096] Optional, see Figure 1 and Figure 2 The system is suitable for BUCK-BOOST circuits with operating frequencies from tens of kHz to hundreds of kHz; the power supply voltage input range is 3-20V, and the output voltage Vout range is 1-12V; the size ratio m of the pull-up power transistor and the pull-up mirror transistor ranges from 100 to 1000, and the resistance value of the sensing resistor ranges from 0.1 to 1 ohm.

[0097] Optional, see Figure 3 b and Figure 4 The delay time T2 of the second delay module is greater than the delay time T1 of the first delay module, and the difference T2-T1 determines the narrow pulse width of the reset signal. When the pulse width modulation signal is high, the reset signal outputs a narrow pulse to make the ramp signal generator work. When the pulse width modulation signal is low, the reset signal remains low and turns off the ramp signal generator.

[0098] To make the technical solution of this application clearer and more understandable, the following is combined with Figures 1 to 4 Preferred embodiments of this application are described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0099] Figure 1 This is a schematic diagram of the adaptive ramp compensation circuit system proposed in this application.

[0100] like Figure 1 As shown, this application provides an adaptive ramp compensation circuit system for a BUCK-BOOST circuit, wherein a reference voltage (Vref) and a feedback voltage (Vfb) are used as inputs to a transconductance amplifier (Gm) to generate a voltage error (Verr). The voltage error (Verr) serves as a limit for the current peak value and is compared with a signal (Vsen) representing the peak value of the inductor current. The Vsen signal is obtained by injecting ramp compensation into the inductor current sampling signal.

[0101] When the clock pulse (Clk) arrives, the RS flip-flop is set to 1, the main power switch (S_HS) is turned on, and Vsen increases with the inductor current (IL). When Vsen intersects with Verr, the RS flip-flop is set to 0 and held, the power switch is turned off, and Vsen decreases with the inductor current. When the next clock pulse arrives, the above process is repeated.

[0102] The adaptive ramp compensation circuit system of this application mainly consists of two parts: a ramp signal generator and a current sensor. The function of the current sensor is to mirror the current of the pull-up power transistor (S_HS) to the pull-up mirror transistor (S_HS_mir) at an m:1 ratio, and then convert the current into a voltage signal Vsen through the sensing resistor (Rs). The function of the ramp signal generator is to generate a ramp voltage signal Vramp that varies linearly with time, and to control the compensation time of Vramp to Vsen through the reset N-type switch (S11).

[0103] Unlike traditional solutions, this application innovatively introduces a pulse width modulation (PWM) signal to control the enable of the ramp signal generator. The ramp signal generator only operates when the PWM is high, i.e., when the pull-up power transistor is on, and is turned off at other times, thereby effectively suppressing subharmonic oscillations in the BUCK-BOOST circuit and improving the system's anti-interference capability.

[0104] Figure 1 The diagram also shows the drive signals for the BUCK-BOOST circuit, including a first high-side drive signal (HDRV1), a first low-side drive signal (LDRV1), a second high-side drive signal (HDRV2), and a second low-side drive signal (LDRV2).

[0105] Figure 2 This is a schematic diagram of the current sensor in this application.

[0106] like Figure 2 As shown, the current sensor consists of a first operational amplifier (AMP1), a pull-up power transistor (S_HS), a pull-up mirror transistor (S_HS_mir), an n-type MOSFET (Mn1), a first P-type MOSFET (Mp1), a second P-type MOSFET (Mp2), and a sensing resistor (Rs). The size ratio of S_HS to S_HS_mir is m:1, and the resistance value of Rs can be determined according to the current sampling accuracy requirements.

[0107] AMP1 and Mn1 form a clamping circuit that clamps the input clamping voltage (Vin_Clp) to near the input voltage (Vin). The clamping circuit works as follows: when Vin rises, the output voltage of AMP1 rises, and the current through Mn1 also rises, thus pulling up Vin_Clp. Eventually, Vin_Clp will approach Vin, and the degree of approach depends on the gain of AMP1.

[0108] When the PWM signal is high, S_HS is turned on, and S_HS_mir proportionally controls the current in S_HS by 1 / 2.

[0109] The current is mirrored and flows into Mp1. S_HS_mir and S_HS share the same source voltage (Vsw) and gate control signal (PWM_HS), which ensures the accuracy of the current mirror. The current mirror formed by Mp1 and Mp2 replicates the current of S_HS_mir onto Rs, generating a voltage drop Vsen on Rs that is proportional to the current of S_HS. Since the current when S_HS is on in the BUCK circuit is equal to the inductor current IL, Vsen = IL × RS / m, which reflects the magnitude of IL.

[0110] The key design parameter for the current sensor is the selection of the mirror ratio m. A larger m value results in a smaller voltage drop across Rs and lower power consumption, but also a corresponding decrease in sampling accuracy. Determining the m value requires a trade-off between power consumption and accuracy. In this embodiment, m can be between 100 and 1000. The selection of the Rs resistance value also needs to balance the Vsen amplitude and power consumption; too small a value results in a weak Vsen signal, while too large a value results in excessive power consumption. A value between 0.1 and 1 ohm can be selected.

[0111] Figure 3 (a) is a schematic diagram of the ramp signal generator proposed in this application.

[0112] like Figure 3 As shown in (a), the ramp signal generator includes a second operational amplifier (AMP2), a first voltage divider resistor (R1), a second voltage divider resistor (R2), a first P-type MOSFET (M1), a second P-type MOSFET (M2), a reset N-type switch (S11), an adjustable resistor (R3), and a capacitor (C). R1 / R2 is used to divide the input voltage Vin, reducing Vin's influence on the ramp rate; the dimensions of M1 / M2 must ensure that the charging current output by M2 is within a suitable range; the adjustable range of R3 must meet the design margin for the ramp rate; the value of C is determined based on the ramp signal frequency and amplitude range.

[0113] The specific connection method is as follows: the upper terminal of R2 is connected to Vin, the lower terminal of R2 is connected to the inverting input terminal of AMP2 and the upper terminal of R1, and the lower terminal of R1 is grounded; the positive input terminal of AMP2 is connected to the upper terminal of R3 and the drain of M1, and the output terminal of AMP2 is connected to the gates of M1 and M2; the source of M1 is connected to Vin; the lower terminal of R3 is grounded; the drain of M2 is connected to the upper terminal of C and the drain of S11; the lower terminal of C is connected to the source of S11 and Vsen, and the upper terminal of C is connected to the positive input terminal of the comparator (COMP).

[0114] The working principle of the ramp signal generator is as follows: Voltage (Vin) is divided using voltage divider resistors R1 and R2, reducing the impact of Vin changes on the ramp signal slope and thus stabilizing the slope. AMP2, M1, and R3 form a voltage-to-current conversion circuit, where the inverting input is connected to the divided voltage, and the non-inverting input is connected to the drain of M1. When the divided voltage increases, the output of AMP2 decreases, the gate voltage of M1 decreases, and the current of M1 decreases; conversely, the current of M1 increases. This converts the change in the divided voltage into a change in the current of M1.

[0115] The reset signal (RST) is generated by a combinational logic circuit using a PWM wave and a clock signal (Clk). When RST is high, S11 is off, and the current from M2 charges capacitor C, generating an upward ramp. When RST is low, S11 is on, capacitor C is short-circuited, and Vramp quickly drops to its initial value. By adjusting the static operating points of M1 and M2 using R3, the slope and initial value of the ramp signal can be adjusted within a certain range to compensate for the effects of process, voltage, and temperature (PVT) variations.

[0116] Figure 3 (b) is a schematic diagram of the RST signal generation circuit of this application.

[0117] like Figure 3 As shown in (b), the RST signal generation circuit includes two delay modules Delay(T1) and Delay(T2), three inverters, one OR gate and one NOR gate.

[0118] The clock signal Clk is first delayed by T1, then passed through an inverter. The delayed Clk signal and its inverted counterpart are input into a NOR gate. Simultaneously, the Clk signal, after being delayed by T1, is further delayed by T2, then passed through another inverter to obtain a longer-delayed inverted Clk signal, which is also input into the NOR gate. The output of the NOR gate is connected to one input of the OR gate, while the PWM signal, after being invertered, is connected to the other input of the OR gate. Finally, the output of the OR gate is the desired RST signal.

[0119] By appropriately setting the delay times T1 and T2, a narrow pulse of the Clk signal can be extracted using an OR gate, with a pulse width equal to T2-T1. The selection of delay times T1 and T2 directly affects the width of the RST signal and can be adjusted according to the operating frequency and duty cycle range of the BUCK-BOOST circuit to obtain optimal performance. This narrow pulse is then combined with the inverted PWM signal using an OR gate to obtain an RST signal controlled by the PWM signal. When the PWM is high (i.e., the pull-up power transistor is on), the RST outputs a narrow pulse, enabling the ramp signal generator to operate; when the PWM is low, RST remains low, turning off the ramp signal generator.

[0120] Figure 4 The diagram shows the operating waveforms of the adaptive ramp compensation circuit system proposed in this application.

[0121] like Figure 4 As shown, assuming the clock period of the BUCK-BOOST circuit is T and the duty cycle of the PWM signal is 25%, the inductor current IL rises under the control of the PWM signal in the t0-t2 interval and decreases in the t2-t3 interval. The VCr signal is the superposition of Vsen and Vramp. It can be seen that:

[0122] The Vramp signal exhibits two rising edges with equal slopes between t0-t1 and t1-t2, drops rapidly between t2-t3, and remains essentially near its initial value between t3-t0. This is because the RST signal is high between t0-t1 and t1-t2, activating the ramp signal generator; and low during other periods, deactivating the ramp signal generator.

[0123] The Vsen signal rises with IL during the entire pull-up power transistor conduction period from t0 to t2, and remains at its initial value during the falling edge from t2 to t0.

[0124] The VCr signal rises rapidly between t0 and t1 due to the combined effects of Vramp and Vsen, rises slowly between t1 and t2 due to only Vsen, and then falls rapidly after t2, before rising rapidly again at t0. The slow rise between t1 and t2 reduces the intensity of the ramp compensation, preventing overcompensation.

[0125] Specifically, in the t0-t1 interval, both the current sensing circuit and the ramp signal generation circuit are working, and the VCr voltage will continue to rise until it reaches the peak value at time t1. In the t1-t2 interval, the current sensing circuit is working, but the ramp signal generation circuit is not working. At this time, the VCr voltage will decrease slightly and then slowly rise again, with the peak value at time t2 being smaller than that at time t1. After time t2, since neither the current sensing circuit nor the ramp signal generation circuit is working, the VCr voltage will continue to decrease to a DC voltage value and then maintain that voltage until the end of a cycle.

[0126] In traditional ramp compensation circuits, the Vramp signal is always present. When the duty cycle exceeds 50%, the falling edge of the Vramp signal occurs during the off-time (Toff), causing the VCr signal to rise during the IL falling period, resulting in subharmonic oscillations. This application utilizes an adaptive RST signal to apply ramp compensation only during the IL rising period, effectively avoiding this problem.

[0127] Furthermore, in traditional schemes, the Vramp and VCr signals are significantly affected by Vin interference. When Vin is disturbed, Vramp and VCr generate large ripples, affecting system stability. This application compensates for the Vramp slope using R1 / R2, reducing the impact of Vin ripple. Simultaneously, since the RST signal shuts off most of the ramp generator's operating time, the impact of Vin ripple on VCr is further reduced, improving anti-interference capability.

[0128] Working principle:

[0129] like Figure 1 As shown, when the adaptive ramp compensation circuit system of this application is operating, the reference voltage Vref and the feedback voltage Vfb are used as inputs to the transconductance amplifier Gm, generating a voltage error Verr. The voltage error Verr serves as a limit for the current peak value and is compared with the voltage sampling signal Vsen, which represents the peak value of the inductor current.

[0130] In the current sensing circuit, the pull-up power transistor S_HS and the pull-up mirror transistor S_HS_mir are set in an m:1 ratio, sharing the source voltage Vsw and the gate control signal PWM_HS. The current of the pull-up mirror transistor S_HS_mir is replicated to the sensing resistor Rs through the current mirror composed of Mp1 and Mp2, generating a voltage sampling signal Vsen. Since the current when S_HS is on in the BUCK circuit is equal to the inductor current IL, Vsen = IL × RS / m, which reflects the magnitude of IL.

[0131] In the ramp signal generator section, such as Figure 3 As shown in (a), voltage divider resistors R1 and R2 divide the input voltage Vin, reducing the impact of Vin variations on the slope of the ramp signal. The second operational amplifier AMP2, M1, and R3 form a voltage-to-current conversion circuit. The current from M2 charges capacitor C, and the reset N-type switch S11 is controlled by the reset signal RST. Figure 3 As shown in (b), the RST signal is generated by a circuit consisting of two delay modules Delay(T1) and Delay(T2), three inverters, one OR gate, and one NOR gate, based on the PWM signal and the clock signal Clk. When the PWM is high (i.e., the pull-up power transistor is on), RST outputs a narrow pulse, S11 is turned off, and the ramp signal generator works; when the PWM is low, RST remains low, S11 is on, and the ramp signal generator is turned off.

[0132] The overall system operation is as follows: When the clock pulse Clk arrives, the RS flip-flop is set to 1, the main power switch S_HS is turned on, the inductor current IL rises, and the voltage sampling signal Vsen increases accordingly. When the superimposed voltage signal VCr intersects with the voltage error Verr, the RS flip-flop is set to 0 and held, the switch is turned off, and Vsen decreases with the inductor current. When the next clock pulse arrives, the above process is repeated.

[0133] like Figure 4 As shown, within one clock cycle T, the clock pulse arrives at time t0, and t0-t2 is the high-level period of the PWM signal. During this period, the current sensor operates, and the inductor current IL rises. During the time interval t0-t1, the ramp signal generator operates simultaneously, and the superimposed voltage signal VCr rises rapidly. During the time interval t1-t2, the ramp signal generator stops operating, and the superimposed voltage signal VCr rises slowly only due to the influence of the inductor current. During the time interval t2-t0, both the current sensor and the ramp signal generator stop operating, and the superimposed voltage signal VCr drops to its initial value.

[0134] Compared to traditional solutions, this application introduces a PWM control signal, causing the ramp signal generator to operate only during the rise of IL, effectively avoiding subharmonic oscillations caused by the drop in Vramp signal during the turn-off period. Simultaneously, resistor voltage division reduces the influence of the input voltage Vin on the ramp signal slope, improving the system's anti-interference capability.

[0135] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0136] like Figure 1 As shown in the figure, this example provides an adaptive ramp compensation circuit system for BUCK-BOOST circuits, which mainly consists of two parts: a ramp signal generator and a current sensor.

[0137] The current sensor mirrors the current from the pull-up power transistor (S_HS) to the pull-up mirror transistor (S_HS_mir) at an m:1 ratio, and then converts the current into a voltage signal Vsen through the sensing resistor (Rs). The ramp signal generator generates a ramp voltage signal Vramp that varies linearly with time. The compensation time of Vramp to Vsen is controlled by the reset N-type switch (S11). The output signal Vsen of the current sensor is added to the output Vramp of the ramp signal generator to obtain the VCr signal, which serves as the input of the comparator (COMP).

[0138] Traditional ramp signal generators operate continuously throughout the entire duty cycle of a BUCK-BOOST circuit. This example innovatively introduces pulse width modulation (PWM) signals to control the ramp signal generator's enable. The ramp signal generator operates only when the PWM is high, i.e., when the pull-up power transistor is on, and is off at other times. This enable control method effectively suppresses subharmonic oscillations in the BUCK-BOOST circuit, improving the system's anti-interference capability.

[0139] Figure 1 In this circuit, Vref is the reference voltage, Vfb is the feedback voltage, and the difference between them is converted into a current comparison threshold Verr by a transconductance amplifier (Gm), which is then compared with the sampling signal Vsen. The clock signal (Clk) controls the on and off of the power switch S_HS via an RS flip-flop, thereby regulating the inductor current (IL).

[0140] The entire system is designed to be applicable to BUCK-BOOST circuits with operating frequencies ranging from tens of kHz to hundreds of kHz, with an input voltage range of 3-20V and an output voltage range of 1-12V.

[0141] The implementation of the current sensor circuit in this example is explained below. Figure 2 As shown, the current sensor consists of a first operational amplifier (AMP1), a pull-up power transistor (S_HS), a pull-up mirror transistor (S_HS_mir), an n-type MOSFET (Mn1), a first P-type MOSFET (Mp1), a second P-type MOSFET (Mp2), and a sensing resistor (Rs). The size ratio of S_HS to S_HS_mir is m:1, and the resistance value of Rs can be determined according to the current sampling accuracy requirements.

[0142] AMP1 and Mn1 form a clamping circuit that clamps the input clamping voltage (Vin_Clp) to near the input voltage (Vin). The clamping circuit works as follows: when Vin rises, the output voltage of AMP1 rises, and the current through Mn1 also rises, thus pulling up Vin_Clp. Eventually, Vin_Clp will approach Vin, and the degree of approach depends on the gain of AMP1.

[0143] When the PWM signal is high, S_HS is turned on, and S_HS_mir mirrors the current in S_HS at a ratio of 1:m, flowing into Mp1. S_HS_mir and S_HS share the same source voltage (Vsw) and the same gate control signal (PWM_HS), which ensures the accuracy of the current mirror. The current mirror formed by Mp1 and Mp2 replicates the current of S_HS_mir onto Rs, generating a voltage drop Vsen on Rs that is proportional to the current of S_HS. Since the current when S_HS is turned on in the BUCK circuit is equal to the inductor current IL, Vsen = IL × RS / m, which reflects the magnitude of IL.

[0144] The key design parameter for the current sensor is the selection of the mirror ratio m. A larger m value results in a smaller voltage drop across Rs and lower power consumption, but also a corresponding decrease in sampling accuracy. Determining the m value requires a trade-off between power consumption and accuracy. In this embodiment, m can be between 100 and 1000. The selection of the Rs resistance value also needs to balance the Vsen amplitude and power consumption; too small a value results in a weak Vsen signal, while too large a value results in excessive power consumption. A value between 0.1 and 1 ohm can be selected.

[0145] The following describes the implementation of the ramp signal generator circuit in this example. Figure 3 As shown in (a), the ramp signal generator includes a second operational amplifier (AMP2), a first voltage divider resistor (R1), a second voltage divider resistor (R2), a first P-type MOSFET (M1), a second P-type MOSFET (M2), a reset N-type switch (S11), an adjustable resistor (R3), and a capacitor (C). R1 / R2 is used to divide the input voltage Vin, reducing Vin's influence on the ramp rate; the dimensions of M1 / M2 must ensure that the charging current output by M2 is within a suitable range; the adjustable range of R3 must meet the design margin for the ramp rate; the value of C is determined based on the ramp signal frequency and amplitude range.

[0146] The specific connection method is as follows: the upper terminal of R2 is connected to Vin, the lower terminal of R2 is connected to the inverting input terminal of AMP2 and the upper terminal of R1, and the lower terminal of R1 is grounded; the positive input terminal of AMP2 is connected to the upper terminal of R3 and the drain of M1, and the output terminal of AMP2 is connected to the gates of M1 and M2; the source of M1 is connected to Vin; the lower terminal of R3 is grounded; the drain of M2 is connected to the upper terminal of C and the drain of S11; the lower terminal of C is connected to the source of S11 and Vsen, and the upper terminal of C is connected to the positive input terminal of COMP.

[0147] The working principle of the ramp signal generator in this example is explained below.

[0148] Using voltage divider resistors R1 and R2 to divide Vin reduces the impact of Vin variations on the slope of the ramp signal, thus stabilizing the slope.

[0149] AMP2, M1, and R3 form a voltage-to-current conversion circuit, where the inverting input is connected to the divided voltage and the non-inverting input is connected to the drain of M1. When the divided voltage increases, the output of AMP2 decreases, the gate voltage of M1 decreases, and the current of M1 decreases; conversely, the current of M1 increases. This converts the change in the divided voltage into a change in the current of M1.

[0150] The reset signal (RST) is generated by a combinational logic circuit using a PWM wave and a clock signal (Clk). When RST is high, S11 is off, and the current from M2 charges capacitor C, generating an upward ramp. When RST is low, S11 is on, capacitor C is short-circuited, and Vramp quickly drops to its initial value. By adjusting the static operating points of M1 and M2 using R3, the slope and initial value of the ramp signal can be adjusted within a certain range to compensate for the effects of process, voltage, and temperature (PVT) variations.

[0151] The main design specifications for the ramp signal generator are:

[0152] (1) Ramp signal frequency. It needs to match the switching frequency of the BUCK circuit, generally tens to hundreds of kHz. (2) Ramp signal amplitude. It needs to ensure that the peak value of Vramp is greater than the maximum value of Vsen in order to ensure that the comparator can switch in each cycle.

[0153] (3) Adjustable range of ramp slope. A certain adjustment margin should be reserved to adapt to different working conditions.

[0154] The implementation of the RST signal generation circuit in this example is explained below. Figure 3 As shown in (b), the RST signal generation circuit includes two delay modules Delay(T1) and Delay(T2), three inverters, one OR gate and one NOR gate.

[0155] The clock signal Clk is first delayed by T1, then passed through an inverter. The delayed Clk signal and its inverted counterpart are input into a NOR gate. Simultaneously, the Clk signal, after being delayed by T1, is further delayed by T2, then passed through another inverter to obtain a longer-delayed inverted Clk signal, which is also input into the NOR gate. The output of the NOR gate is connected to one input of the OR gate, while the PWM signal, after being invertered, is connected to the other input of the OR gate. Finally, the output of the OR gate is the desired RST signal.

[0156] By appropriately setting the delay times T1 and T2, a narrow pulse of the Clk signal can be extracted using an OR gate, with a pulse width equal to T2-T1. The selection of delay times T1 and T2 directly affects the width of the RST signal and can be adjusted according to the operating frequency and duty cycle range of the BUCK-BOOST circuit to obtain optimal performance. This narrow pulse is then combined with the inverted PWM signal using an OR gate to obtain an RST signal controlled by the PWM signal. When the PWM is high (i.e., the pull-up power transistor is on), the RST outputs a narrow pulse, enabling the ramp signal generator to operate; when the PWM is low, RST remains low, turning off the ramp signal generator.

[0157] The following explains the system's timing and performance analysis.

[0158] like Figure 4 As shown, assuming the clock period of the BUCK-BOOST circuit is T and the duty cycle of the PWM signal is 25%, the inductor current IL rises under the control of the PWM signal in the t0-t2 interval and decreases in the t2-t3 interval. The VCr signal is the superposition of Vsen and Vramp. It can be seen that:

[0159] The Vramp signal exhibits two rising edges with equal slopes between t0-t1 and t1-t2, drops rapidly between t2-t3, and remains essentially near its initial value between t3-t0. This is because the RST signal is high between t0-t1 and t1-t2, activating the ramp signal generator; and low during other periods, deactivating the ramp signal generator.

[0160] The Vsen signal rises with IL during the entire pull-up power transistor conduction period from t0 to t2, and remains at its initial value during the falling edge from t2 to t0.

[0161] The VCr signal rises rapidly between t0 and t1 due to the combined effects of Vramp and Vsen, rises slowly between t1 and t2 due to only Vsen, and then falls rapidly after t2, before rising rapidly again at t0. The slow rise between t1 and t2 reduces the intensity of the ramp compensation, preventing overcompensation.

[0162] Specifically, in the t0-t1 interval, both the current sensing circuit and the ramp signal generation circuit are working, and the VCr voltage will continue to rise until it reaches the peak value at time t1. In the t1-t2 interval, the current sensing circuit is working, but the ramp signal generation circuit is not working. At this time, the VCr voltage will decrease slightly and then slowly rise again, with the peak value at time t2 being smaller than that at time t1. After time t2, since neither the current sensing circuit nor the ramp signal generation circuit is working, the VCr voltage will continue to decrease to a DC voltage value and then maintain that voltage until the end of a cycle.

[0163] In traditional ramp compensation circuits, the Vramp signal is always present. When the duty cycle exceeds 50%, the falling edge of the Vramp occurs during the off-time (Toff), causing the VCr signal to rise during the IL falling period, resulting in subharmonic oscillations. This example, however, utilizes an adaptive RST signal to apply ramp compensation only during the IL rising period, effectively avoiding this problem.

[0164] Furthermore, in traditional schemes, the Vramp and VCr signals are significantly affected by Vin interference. When Vin is disturbed, Vramp and VCr generate large ripples, impacting system stability. This example, however, uses R1 / R2 to compensate for the Vramp slope, reducing the impact of Vin ripple. Simultaneously, since the RST signal shuts off most of the ramp generator's operating time, the impact of Vin ripple on VCr is further reduced, improving anti-interference capability.

[0165] In summary, compared with existing technologies, this example has the following beneficial effects:

[0166] By introducing an adaptive RST signal controlled by a PWM signal, the ramp signal generator operates only during the rise of IL, effectively suppressing subharmonic oscillations and improving system stability.

[0167] By combining resistor voltage division and adaptive enable, the impact of input ripple is reduced, the static power consumption of the system is decreased, and the anti-interference performance of the system is improved.

[0168] The circuit structure of the current sensor and ramp signal generator is simple and highly integrated, which helps to reduce costs and improve reliability.

[0169] The above embodiments have the following technical effects:

[0170] By introducing an adaptive RST signal controlled by a PWM signal, the ramp signal generator operates only during the rise of the inductor current IL, effectively suppressing subharmonic oscillations and improving system stability. Figure 4 As shown, when the duty cycle exceeds 50%, the Vramp signal in a conventional ramp compensation circuit will have a falling edge during the off-time (Toff), causing the VCr signal to rise during the IL falling period, resulting in subharmonic oscillation. This application, however, avoids this problem by controlling the RST signal to ensure that Vramp is only effective during the t0-t1 time period.

[0171] By combining resistor voltage division and adaptive enable, the impact of input ripple is reduced, while the system's static power consumption is decreased, thus improving the system's anti-interference performance. For example... Figure 3As shown in (a), the voltage divider resistors R1 and R2 divide the input voltage Vin, reducing the impact of Vin variations on the slope of the ramp signal. Simultaneously, since the RST signal shuts off most of the ramp generator's operating time, the impact of Vin ripple on VCr is further reduced.

[0172] The current sensor and ramp signal generator circuits have simple structures and high integration, which helps to reduce costs and improve reliability. For example... Figure 2 As shown, the current sensor achieves efficient current sampling through the proportional configuration of the pull-up power transistor S_HS and the pull-up mirror transistor S_HS_mir. Figure 3 As shown, the ramp signal generator and RST signal generation circuit adopt a simple structural design, which is easy to integrate and implement.

[0173] The above embodiments solve the subharmonic oscillation problem that may occur in traditional ramp compensation circuits when the duty cycle is greater than 50% in BUCK-BOOST circuits, improve the stability and reliability of the circuit, and enhance the anti-interference capability of the system by reducing the sensitivity to input voltage changes. It is suitable for BUCK-BOOST circuits with operating frequencies from tens of kHz to hundreds of kHz, with an input voltage range of 3-20V and an output voltage range of 1-12V.

[0174] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0175] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. An adaptive ramp compensation circuit system applied to a BUCK-BOOST circuit, characterized in that, include: The current sensor includes a pull-up power transistor S_HS and a pull-up mirror transistor S_HS_mir, wherein the size ratio of the pull-up power transistor S_HS and the pull-up mirror transistor S_HS_mir is m:1, and both share the source voltage Vsw and the gate control signal PWM_HS; one end of the sensing resistor Rs is connected to the drain of the pull-up mirror transistor S_HS_mir, and the other end is grounded, which is used to convert the current of the pull-up mirror transistor S_HS_mir into a voltage signal Vsen; A ramp signal generator includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. One end of the second voltage divider resistor R2 is connected to the power supply voltage Vin, and the other end is connected to one end of the first voltage divider resistor R1. The other end of the first voltage divider resistor R1 is grounded. The inverting input of a second operational amplifier AMP2 is connected to the midpoint between the first voltage divider resistor R1 and the second voltage divider resistor R2, and the non-inverting input is connected to one end of an adjustable resistor R3 and the drain of a first P-type MOSFET M1. The output of the second operational amplifier AMP2 is connected to the gates of the first P-type MOSFET M1 and the second P-type MOSFET M2. The drain of the second P-type MOSFET M2 is connected to one end of a capacitor C and the drain of a reset N-type switch S11. The source of the reset N-type switch S11 is connected to the other end of the capacitor C and is connected to the voltage signal Vsen. The RST signal generation circuit receives the clock signal Clk and the pulse width modulation signal PWM, generates a reset signal RST, and connects it to the gate of the reset N-type switch S11. The RST signal generation circuit includes a first delay module DelayT1, a second delay module DelayT2, three inverters, an OR gate, and a NOR gate. The clock signal Clk passes through the first delay module DelayT1 and the first inverter sequentially, and is then input to the NOR gate along with its inverted signal. The clock signal Clk, delayed by the first delay module DelayT1, passes through the second delay module DelayT2 and the second inverter again before being input to the NOR gate. The NOR gate; the output of the NOR gate is connected to the first input terminal of the OR gate; the pulse width modulation signal PWM is connected to the second input terminal of the OR gate after passing through the third inverter; the output of the OR gate is the reset signal RST. When the pulse width modulation signal PWM is high, the reset signal RST outputs a narrow pulse, controlling the reset N-type switch S11 to turn off, enabling the ramp signal generator to work; when the pulse width modulation signal PWM is low, the reset signal RST remains low, controlling the reset N-type switch S11 to turn on, turning off the ramp signal generator; wherein, the delay time T2 of the second delay module DelayT2 is greater than the delay time T1 of the first delay module DelayT1; The comparator COMP has its positive input connected to one end of the capacitor C to obtain a superimposed voltage signal VCr, and its inverting input connected to the voltage error signal Verr.

2. The adaptive ramp compensation circuit system according to claim 1, characterized in that: The current sensor further includes a first operational amplifier AMP1, an n-type MOSFET Mn1, a first P-type MOSFET Mp1, and a second P-type MOSFET Mp2. The non-inverting input terminal of the first operational amplifier AMP1 is connected to the input voltage Vin, the inverting input terminal is connected to the input clamping voltage node Vin_Clp, and the output terminal is connected to the gate of the n-type MOSFET Mn1. The source of the n-type MOSFET Mn1 is connected to the input clamping voltage node Vin_Clp, and the drain is connected to the drain of the first P-type MOSFET Mp1. The sources of the first P-type MOSFET Mp1 and the second P-type MOSFET Mp2 are both connected to the power supply pin Vboot, and their gates are connected to form a current mirror. The drain of the second P-type MOSFET Mp2 is connected to the sensing resistor Rs.

3. The adaptive ramp compensation circuit system according to claim 1, characterized in that: One end of the second voltage divider resistor R2 is connected to the power supply voltage Vin, and the other end is connected to one end of the first voltage divider resistor R1 to form a voltage divider node. The other end of the first voltage divider resistor R1 is grounded. The second operational amplifier AMP2, the first P-type MOSFET M1, and the adjustable resistor R3 form a voltage-to-current conversion circuit. The inverting input terminal of the second operational amplifier AMP2 is connected to the voltage divider node, the non-inverting input terminal is connected to one end of the adjustable resistor R3 and the drain of the first P-type MOSFET M1, and the output terminal controls the gates of the first P-type MOSFET M1 and the second P-type MOSFET M2 to convert the voltage divider voltage into a charging current.

4. The adaptive ramp compensation circuit system according to claim 1, characterized in that: The system controls the BUCK-BOOST circuit in peak current mode, including the following operation: the reference voltage Vref and the feedback voltage Vfb are used as inputs to the transconductance amplifier Gm to generate a voltage error signal Verr; when the clock signal Clk pulse arrives, the RS flip-flop RS is set to 1, the pull-up power transistor S_HS is turned on, and the inductor current IL rises; when the superimposed voltage signal VCr intersects with the voltage error signal Verr, the RS flip-flop RS is set to 0, and the pull-up power transistor S_HS is turned off; when the next clock pulse arrives, the above process is repeated.

5. The adaptive ramp compensation circuit system according to claim 1, characterized in that: Within one clock cycle T: At time t0, the clock pulse arrives; from t0 to t2, the pulse width modulation signal (PWM) is at a high level, during which the current sensor operates and the inductor current IL rises; during the time interval t0 to t1, the ramp signal generator operates simultaneously, and the superimposed voltage signal VCr rises rapidly; during the time interval t1 to t2, the ramp signal generator stops operating, and the superimposed voltage signal VCr rises slowly only due to the influence of the inductor current IL; during the time interval t2 to t0, both the current sensor and the ramp signal generator stop operating, and the superimposed voltage signal VCr drops to its initial value.

6. The adaptive ramp compensation circuit system according to claim 1, characterized in that: The system is suitable for BUCK-BOOST circuits with operating frequencies from tens of kHz to hundreds of kHz; the power supply voltage Vin input range is 3-20V, and the output voltage Vout range is 1-12V; the size ratio m of the pull-up power transistor S_HS and the pull-up mirror transistor S_HS_mir ranges from 100 to 1000, and the resistance value of the sensing resistor Rs ranges from 0.1 to 1 ohm.

7. The adaptive ramp compensation circuit system according to claim 1, characterized in that: The delay time T2 of the second delay module DelayT2 is greater than the delay time T1 of the first delay module DelayT1, and the difference T2-T1 determines the narrow pulse width of the reset signal RST. When the pulse width modulation signal PWM is high, the reset signal RST outputs a narrow pulse to enable the ramp signal generator to work. When the pulse width modulation signal PWM is low, the reset signal RST remains low and turns off the ramp signal generator.

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