Filter circuit, method, device and electronic equipment
By designing a filter unit that includes phase processing elements and logic computing elements, the problem of difficulty in removing glitch signals in the prior art is solved, and efficient and low-cost glitch signal filtering is achieved, ensuring signal reliability and circuit stability.
Patent Information
- Application Number
- CN202510587638.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-08-26
AI Technical Summary
Prior art When removing glitch signals during the chip back-end process phase, inserting registers requires readjustment of clock trees to increase design complexity, while inserting delay units can lead to increased chip area and cost.
A filtering unit including phase processing elements and logic computing elements is adopted to design a filter circuit by adjusting the time parameters to ensure the rapid filtering of the glitch signal without affecting the normal signal, and the filtering circuit configuration is optimized through group analysis.
It effectively reduces the difficulty of filtering glitch signals, improves filtering efficiency, ensures signal reliability, and controls circuit area and cost.
Smart Images
Figure CN120546641A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic circuits, and in particular to a filtering circuit, method, device and electronic equipment. Background Art
[0002] In the field of electronic circuit technology, a glitch usually refers to a short-term error or signal instability, which usually manifests as an unexpected short-term high or low level at the moment of signal change. The glitch signal may cause the logic circuit to produce erroneous output.
[0003] However, using registers or delay cells to remove glitch artifacts during the back-end chip manufacturing process has certain limitations. For example, inserting registers requires readjusting the clock tree, increasing the difficulty of digital back-end repairs. Furthermore, inserting delay cells, due to their large size, increases the area required for forced insertion, leading to increased costs.
[0004] Therefore, there is an urgent need for a filtering circuit and method that can effectively reduce the difficulty of burr filtering. Summary of the Invention
[0005] Based on this, embodiments of the present application provide a filtering circuit, method, device, and electronic device.
[0006] According to some embodiments, the present application provides a filtering circuit, comprising a plurality of filter units connected in series, the plurality of filter units configured to output a target output signal based on an initial input signal containing a glitch signal; the filtering unit comprising a phase processing element and a logic operation element; an input end of the phase processing element serving as an input end of the filtering unit; a first input end of the logic operation element connected to an output end of the phase processing element, a second input end of the logic operation element connected to a low level, and an output end of the logic operation element serving as an output end of the filtering unit;
[0007] The first time parameter of the phase processing element is greater than the second time parameter of the phase processing element, and the first time parameter and the second time parameter are different performance parameters of the phase processing element under the same load; the third time parameter of the logic operation element is less than the fourth time parameter of the logic operation element, and the third time parameter and the fourth time parameter are different performance parameters of the logic operation element under the same load.
[0008] In the filter circuit of the above-described embodiment, the filter circuit includes multiple groups of filter units. These groups of filter units can improve signal smoothness, cumulatively filter out glitch effects, and ensure the reliability of the final target output signal. The filter unit includes a phase processing element and a logic operation element. Because the first time parameter of the phase processing element is greater than the second time parameter of the phase processing element, and the third time parameter of the logic operation element is less than the fourth time parameter of the logic operation element, using the filter unit including the phase processing element and the logic operation element for filtering can help reduce the difficulty of filtering, improve filtering efficiency, and ensure that glitch can be quickly removed without affecting normal signals. Furthermore, because the phase processing element and the logic operation element are relatively small in area, they do not impose additional area burden, which helps control costs.
[0009] In some embodiments, the glitch signal is a high-level glitch signal; in the multiple groups of filter units connected in series, the input end of the first filter unit is used to receive the initial input signal containing the high-level glitch signal, and the last filter unit is used to output the target output signal.
[0010] In some embodiments, the glitch signal is a low-level glitch signal; the filtering circuit also includes an initial processing element, which is used to generate a high-level glitch signal based on the low-level glitch signal; the input end of the initial processing element is used to receive the initial input signal containing the low-level glitch signal, and the output end of the initial processing element is connected to the input end of the first filtering unit, and is used to output the signal to be filtered containing the high-level glitch signal; in the multiple groups of filtering units connected in series, the input end of the first filtering unit is used to receive the signal to be filtered containing the high-level glitch signal, and the last filtering unit is used to output the target output signal.
[0011] In some embodiments, the first time parameter is the delay time for the rising edge of the phase processing element to change to the falling edge, and the second time parameter is the delay time for the falling edge of the phase processing element to change to the rising edge.
[0012] In some embodiments, the third time parameter is the delay time for the rising edge of the logic operation element to change to the falling edge, and the fourth time parameter is the delay time for the falling edge of the logic operation element to change to the rising edge.
[0013] In some embodiments, the phase processing element comprises a clocked inverter.
[0014] In some embodiments, the logic operation element includes a NOR gate element.
[0015] In some embodiments, the initial processing element comprises a clocked inverter.
[0016] According to some embodiments, the present application further provides a filtering method, which uses the filtering circuit of any one of the above embodiments to perform filtering, and the method includes:
[0017] Get the width of the glitch signal;
[0018] Obtaining a first time parameter and a second time parameter of the phase processing element, and a third time parameter and a fourth time parameter of the logic operation element, where the first time parameter and the second time parameter are different performance parameters of the phase processing element under the same load, and the third time parameter and the fourth time parameter are different performance parameters of the logic operation element under the same load;
[0019] The number of groups of the filtering units is determined according to the first and second time parameters of the phase processing element, the third and fourth time parameters of the logic operation element, and the width of the glitch signal.
[0020] In the filtering method of the above embodiment, by obtaining the width of the glitch signal, the first and second time parameters of the phase processing element, and the third and fourth time parameters of the logic operation element, the number of filter unit groups can be determined, thereby achieving quantitative analysis of the number of filter unit groups. This facilitates more accurate determination of the filter circuit configuration, avoids unnecessary redundant filter units in the filter circuit, and thus reduces the difficulty of filtering out glitch.
[0021] In some embodiments, the number of groups of filter units is:
[0022] ;
[0023] Where N is the number of filter units, is the width of the glitch signal, is the first time parameter of the phase processing element, is the second time parameter of the phase processing element, is the third time parameter of the logic operation element, It is the fourth time parameter of the logic operation element.
[0024] According to some embodiments, the present application further provides a filtering device, which includes the filtering circuit of any one of the above embodiments.
[0025] In the filtering device of the above-described embodiment, the use of multiple groups of filtering units, including phase processing elements and logic operation elements, for filtering helps reduce the difficulty of filtering, improves filtering efficiency, and ensures that glitches can be quickly removed without affecting normal signals. Furthermore, since the phase processing elements and logic operation elements are relatively small in area, no additional area burden is imposed, which helps control costs. Furthermore, quantitative analysis of the number of filtering unit groups facilitates more accurate determination of the configuration of the filtering circuit, avoids unnecessary redundant filtering units in the filtering circuit, and thus reduces the difficulty of filtering out glitches.
[0026] According to some embodiments, the present application further provides an electronic device, which includes a housing and the filter circuit of any one of the above embodiments, at least partially located in a receiving space of the housing.
[0027] In the electronic device of the above embodiment, the use of multiple groups of filtering units including phase processing elements and logic operation elements for filtering helps reduce the difficulty of filtering, improves filtering efficiency, and ensures that glitches can be quickly removed without affecting normal signals. Furthermore, since the phase processing elements and logic operation elements are relatively small in area, no additional area burden is imposed, which helps control costs. Furthermore, quantitative analysis of the number of filtering unit groups helps more accurately determine the configuration of the filtering circuit, avoids unnecessary redundant filtering units in the filtering circuit, and thus reduces the difficulty of filtering out glitches. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a schematic diagram of a filter circuit;
[0029] Figure 2 for Figure 1 The timing diagram of the filter circuit shown in FIG. 1 for filtering out glitch signals;
[0030] Figure 3 is a schematic top view of another filter circuit;
[0031] Figure 4 for Figure 3 The timing diagram of the filter circuit shown in FIG. 1 for filtering out glitch signals;
[0032] Figure 5 A schematic diagram of a filter circuit provided in one embodiment of the present application;
[0033] Figure 6 A schematic diagram of a filter circuit provided in another embodiment of the present application;
[0034] Figure 7 A timing diagram of a first time parameter, a second time parameter, a third time parameter, and a fourth time parameter in a filter circuit provided in one embodiment of the present application;
[0035] Figure 8 A timing diagram of an initial input signal having a glitch signal during a glitch filtering process performed by a filter circuit according to an embodiment of the present application;
[0036] Figure 9 A timing diagram illustrating a process in which a filter circuit according to an embodiment of the present application performs glitch filtering on an initial input signal, in which the rising edge of a glitch signal obtained after the initial input signal passes through a clock inverter of a first filtering unit is shifted back by a first width;
[0037] Figure 10 A timing diagram showing a process in which a filter circuit according to an embodiment of the present application performs glitch filtering on an initial input signal, in which the falling edge of a glitch signal obtained after the initial input signal passes through a clock inverter of a first filter unit is shifted back by a second width;
[0038] Figure 11 A timing diagram showing a process in which a filter circuit according to an embodiment of the present application performs glitch filtering on an initial input signal, in which the rising edge of a glitch signal obtained after the initial input signal passes through a first filter unit or a NOT gate element is shifted back by a third width;
[0039] Figure 12 A timing diagram showing a process in which a filter circuit according to an embodiment of the present application performs glitch filtering on an initial input signal, in which the falling edge of a glitch signal obtained after the initial input signal passes through a first filter unit or a NOT gate element is shifted back by a fourth width;
[0040] Figure 13 A timing diagram of a filter circuit according to an embodiment of the present application performing glitch filtering on an initial input signal through six groups of filter units;
[0041] Figure 14 A flowchart diagram of a filtering method provided in one embodiment of the present application.
[0042] Explanation of reference numerals: 10, filtering unit; 11, phase processing element; 12, logic operation element; 20, initial processing element; 30, register; 40, delay unit. DETAILED DESCRIPTION
[0043] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0045] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.
[0046] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.
[0047] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to direct connection or indirect connection through an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.
[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.
[0049] In the field of electronic circuit technology, digital signals may pass through multiple gates and different paths to be generated. Input signals, along these various paths, ultimately converge at the output. Due to varying path delays, signals from different paths may not arrive at the output at the same time, resulting in transient errors in the output digital signal. These errors are often referred to as glitches, which manifest as unexpected, brief high or low levels at the moment of a signal transition. Glitches can have serious consequences in logic circuits, causing erroneous outputs and, in turn, impacting the functionality and reliability of the entire system. For example, in sequential logic circuits, glitches can cause triggers to falsely trigger, leading to incorrect data sampling and storage, causing signal integrity issues and ultimately, system crashes. Therefore, to ensure circuit stability and reliability, measures are necessary to eliminate these glitches.
[0050] In the back-end process stage of chip design, registers 30 or delay units 40 are usually used to remove burrs. Figure 1 and Figure 2Inserting register 30 is a common de-glitching strategy. For example, after a digital signal is generated, register 30 samples it before outputting it to remove glitches. The input signal is usually sampled at the rising or falling edge of the clock signal and latched at the output. After timing convergence, the signal state sampled when the clock edge arrives is already stable, effectively filtering out the impact of glitches on the circuit. However, the implementation of inserting register 30 usually requires readjusting the clock tree. The clock tree is an important component responsible for distributing the clock signal to the entire circuit. Readjusting the clock tree not only increases design complexity, but may also introduce new timing issues. Especially in large and complex chips, the difficulty of adjusting the clock tree increases significantly. This will extend the design cycle and increase the burden of subsequent debugging and verification work.
[0051] See also Figure 3 and Figure 4 Another method is to insert a delay unit 40 to delay the change of the signal so that the glitch disappears before the logical judgment. For example, the digital signal passes through multiple groups of delay units 40. If the high-level glitch is filtered, it is output together. If the low-level glitch is filtered, it is output together to remove the glitch. However, the area of the delay unit 40 is usually large, and forcibly inserting it into the design will lead to an increase in the chip area. This increase in area not only means an increase in manufacturing costs, but may also affect the power consumption and heat dissipation characteristics of the chip. In situations where resources are limited, such as high-density integrated circuits, this increase may lead to irrationality in the design and even affect the performance and economic benefits of the chip.
[0052] Based on this, in order to solve the above problems, the embodiments of the present application provide a filtering circuit, method, device and electronic device.
[0053] See also Figure 5 and Figure 6The present application provides a filtering circuit. The filtering circuit includes a plurality of filter units 10 connected in series, the plurality of filter units 10 being configured to output a target output signal based on an initial input signal containing a glitch signal. The filtering unit 10 includes a phase processing element 11 and a logic operation element 12. The input end of the phase processing element 11 serves as the input end of the filtering unit 10. The first input end of the logic operation element 12 is connected to the output end of the phase processing element 11, the second input end of the logic operation element 12 is connected to a low level, and the output end of the logic operation element 12 serves as the output end of the filtering unit 10. The first time parameter of the phase processing element 11 is greater than the second time parameter of the phase processing element 11, and the first time parameter and the second time parameter are different performance parameters of the phase processing element 11 under the same load. The third time parameter of the logic operation element 12 is less than the fourth time parameter of the logic operation element 12, and the third time parameter and the fourth time parameter are different performance parameters of the logic operation element 12 under the same load.
[0054] In the filter circuit of the above embodiment, the filter circuit includes multiple groups of filter units 10. The multiple groups of filter units 10 can improve signal smoothness, cumulatively filter out burrs, and ensure the reliability of the final target output signal. The filter unit 10 includes a phase processing element 11 and a logic operation element 12. Because the first time parameter of the phase processing element 11 is greater than the second time parameter of the phase processing element 11, and the third time parameter of the logic operation element 12 is less than the fourth time parameter of the logic operation element 12, using the filter unit 10 including the phase processing element 11 and the logic operation element 12 for filtering can help reduce the difficulty of filtering, improve filtering efficiency, and ensure that burrs can be quickly removed without affecting normal signals. Furthermore, because the phase processing element 11 and the logic operation element 12 are relatively small in area, no additional area burden is imposed, which helps control costs.
[0055] For example, the second input terminal of the logic operation element 12 is connected to a low level, where the low level can be understood as a logic 0.
[0056] like Figure 5 As shown, in some embodiments, the glitch signal is a high-level glitch signal; in the multiple groups of filter units 10 connected in series, the input end of the first filter unit 10 is used to receive the initial input signal containing the high-level glitch signal, and the last filter unit 10 is used to output the target output signal.
[0057] For example, a high level may be understood as a logic 1.
[0058] like Figure 6As shown, in some embodiments, the glitch signal is a low-level glitch signal; the filtering circuit further includes an initial processing element 20, which is used to generate a high-level glitch signal based on the low-level glitch signal; the input end of the initial processing element 20 is used to receive the initial input signal containing the low-level glitch signal, and the output end of the initial processing element 20 is connected to the input end of the first filtering unit 10, and is used to output the signal to be filtered containing the high-level glitch signal.
[0059] In an embodiment where the glitch signal is a low-level glitch signal, in the multiple groups of filter units 10 connected in series, the input end of the first filter unit 10 is used to receive the signal to be filtered containing the high-level glitch signal, and the last filter unit 10 is used to output the target output signal.
[0060] In some embodiments, the initial processing element 20 includes a clocked inverter.
[0061] In some embodiments, the first time parameter is the delay time for the rising edge of the phase processing element 11 to change to the falling edge, and the second time parameter is the delay time for the falling edge of the phase processing element 11 to change to the rising edge.
[0062] In some embodiments, the third time parameter is the delay time for the rising edge of the logic operation element 12 to change to the falling edge, and the fourth time parameter is the delay time for the falling edge of the logic operation element 12 to change to the rising edge.
[0063] In some embodiments, the phase processing element 11 comprises a clocked inverter.
[0064] Please combine Figure 7 For understanding, in some embodiments, the first time parameter is the delay time cell_fall from the rising edge of the clock inverter to the falling edge, and the second time parameter is the delay time cell_rise from the falling edge of the clock inverter to the rising edge. It can be understood that the delay time cell_rise from the rising edge to the falling edge is the time from the input signal changing to the falling edge of the output signal; correspondingly, the delay time cell_fall from the falling edge to the rising edge is the time from the input signal changing to the rising edge of the output signal.
[0065] Table 1 shows a first time parameter, cell_fall, of a clock inverter. As can be seen from Table 1, because clock inverters typically function in a clock tree and typically have high requirements for the delay of the clock rising edge, when using the same transition time and load, the first time parameter, cell_fall, of the clock inverter is greater than the second time parameter, cell_rise.
[0066] Table 1
[0067]
[0068] In some embodiments, the logic operation element 12 includes a NOR gate element.
[0069] Please combine Figure 7 For better understanding, in some embodiments, the third time parameter is the delay time cell_fall from the rising edge of the NOR gate element to the falling edge, and the fourth time parameter is the delay time cell_rise from the falling edge of the NOR gate element to the rising edge. It can be understood that the delay time cell_rise from the rising edge to the falling edge is the time from the input signal changing to the falling edge of the output signal, and correspondingly, the delay time cell_fall from the falling edge to the rising edge is the time from the input signal changing to the rising edge of the output signal.
[0070] It can be understood that due to the characteristics of the NOR gate, when using the same conversion time and load, the fourth time parameter cell_rise of the NOR gate element is greater than the third time parameter cell_fall, so using the NOR gate element can make the filtering process faster.
[0071] In order to more clearly illustrate the filtering process of the filtering circuit provided by some of the above embodiments, the following is combined with Figures 5 to 13 Understand some embodiments of this application. Figures 8 to 13 As shown, the following is an exemplary description based on a digital signal net_eco_22 containing a 511ps width glitch signal as an initial input signal.
[0072] like Figure 8 As shown, in some embodiments, the glitch signal is a high-level signal.
[0073] Figures 9 to 12 FIG. 1 shows a timing diagram of the digital signal net_eco_22 after passing through the first filtering unit 10. Figure 9 As shown, in some embodiments, after the digital signal net_eco_22 passes through the clock inverter in the first filtering unit 10, the digital signal net_eco_4 is obtained. The digital signal net_eco_4 still includes a glitch signal with a width of 511 ps, but the glitch signal is now converted into a low-level signal, and the rising edge of the glitch signal is shifted back by a first width; illustratively, the first width is approximately 98 ps.
[0074] like Figure 10As shown, in some embodiments, after the digital signal net_eco_22 passes through the clock inverter in the first filter unit 10, it generates the digital signal net_eco_4. At this time, the falling edge of the glitch signal in the digital signal net_eco_4 is delayed by a second width; illustratively, the second width is approximately 66 ps. Therefore, after passing through the clock inverter in the first filter unit 10, the first filter width for filtering out the glitch signal is the difference between the first width and the second width, that is, the first filter width for filtering out the glitch signal is 98 ps - 66 ps = 32 ps.
[0075] like Figure 11 As shown, in some embodiments, after passing through the clock inverter, the digital signal net_eco_4 passes through the NOR gate element in the first filtering unit 10 to obtain the digital signal net_eco_23_15. At this time, the glitch signal is converted into a high-level signal, and the rising edge of the glitch signal is shifted back by a third width; illustratively, the third width is 151 ps.
[0076] like Figure 12 As shown, in some embodiments, after passing through the clock inverter, digital signal net_eco_4 passes through the NOR gate element in the first filter unit 10 to obtain digital signal net_eco_23_15. At this point, the glitch signal is converted to a high-level signal, and the falling edge of the glitch signal is shifted by a fourth width; illustratively, the fourth width is 85 ps. Therefore, after passing through the NOR gate element in the first filter unit 10, the second filter width for filtering out the glitch signal is the difference between the third width and the fourth width, that is, the second filter width for filtering out the glitch signal is 151 ps - 85 ps = 66 ps.
[0077] It can be understood that after passing through the clock inverter and NOR gate element in the first filtering unit 10, the single filtering width of the glitch signal is the sum of the first filtering width and the second filtering width, that is, the single filtering width is 32ps + 66ps = 98ps.
[0078] Furthermore, the number of groups of filtering units 10 in the filtering circuit can be determined according to the width of the glitch signal in the initial input signal and the width of a single filtering.
[0079] For example, the number of groups of filter units 10 in the filter circuit is determined based on the result obtained by dividing the width of the glitch signal in the initial input signal by the width of a single filter. For example, when the result obtained by dividing the width of the glitch signal in the initial input signal by the width of a single filter does not contain a remainder, the number of groups of filter units 10 in the filter circuit is equal to the quotient obtained by dividing the width of the glitch signal in the initial input signal by the width of a single filter; when the result obtained by dividing the width of the glitch signal in the initial input signal by the width of a single filter contains a remainder, the number of groups of filter units 10 in the filter circuit is equal to the quotient obtained by dividing the width of the glitch signal in the initial input signal by the width of a single filter plus one.
[0080] It can be understood that in the above embodiment, the initial input signal, i.e., the digital signal net_eco_22, contains a glitch signal with a width of 511 ps. The single filtering width of the glitch signal is 98 ps. The division operation yields 511 ps / 98 ps = 5.21, which indicates that the number of filter units 10 in the filter circuit is 5 + 1 = 6. In other words, to filter the digital signal net_eco_22 containing a glitch signal with a width of 511 ps, six filter units 10 are required.
[0081] Figure 13 FIG. 1 shows a timing diagram of filtering the digital signal net_eco_22 by six groups of filtering units 10. For example, Figure 13As shown, when the first group of filter units 10 filters the digital signal net_eco_22, it passes through the clock inverter to obtain the digital signal net_eco_4, and passes through the NOR gate element to obtain the digital signal net_eco_23_15; when the second group of filter units 10 filters the digital signal net_eco_23_15 output by the previous group of filter units 10, it passes through the clock inverter to obtain the digital signal net_eco_23_14, and passes through the NOR gate element to obtain the digital signal net_eco_23_13; when the third group of filter units 10 filters the digital signal net_eco_23_13 output by the previous group of filter units 10, it passes through the clock inverter to obtain the digital signal net_eco_23_12, and passes through the NOR gate element to obtain the digital signal net_eco_23_11; when the fourth group of filter units 10 filters the digital signal net_eco_23_11 output by the previous group of filter units 10, After passing through the clocked inverter, digital signal net_eco_23_10 is obtained, which then passes through a NOR gate to obtain digital signal net_eco_23_9. When the fifth filter unit 10 filters the digital signal net_eco_23_9 output by the previous filter unit 10, digital signal net_eco_23_8 is obtained after passing through the clocked inverter, and digital signal net_eco_23_7 is obtained after passing through a NOR gate. When the sixth filter unit 10 filters the digital signal net_eco_23_7 output by the previous filter unit 10, digital signal net_eco_23_6 is obtained after passing through the clocked inverter. At this time, the width of the glitch signal is reduced to 0, but because digital signal net_eco_23_6 is at a high level, digital signal net_eco_23_5 is obtained after passing through the NOR gate. Digital signal net_eco_23_5 is at a low level, and digital signal net_eco_23_5 serves as the target output signal.
[0082] See also Figure 14 According to some embodiments, the present application also provides a filtering method, which uses the filtering circuit of any one of the above embodiments to perform filtering, and the method includes the following steps.
[0083] Step S10, obtaining the width of the glitch signal;
[0084] Step S30: Acquire a first time parameter and a second time parameter of the phase processing element, and a third time parameter and a fourth time parameter of the logic operation element, wherein the first time parameter and the second time parameter are different performance parameters of the phase processing element under the same load, and the third time parameter and the fourth time parameter are different performance parameters of the logic operation element under the same load;
[0085] Step S50 , determining the number of groups of filtering units according to the first and second time parameters of the phase processing element, the third and fourth time parameters of the logic operation element, and the width of the glitch signal.
[0086] In the filtering method of the above embodiment, by obtaining the width of the glitch signal, the first and second time parameters of the phase processing element, and the third and fourth time parameters of the logic operation element, the number of filter unit groups can be determined, thereby achieving quantitative analysis of the number of filter unit groups. This facilitates more accurate determination of the filter circuit configuration, avoids unnecessary redundant filter units in the filter circuit, and thus reduces the difficulty of filtering out glitch.
[0087] In some embodiments, the number of groups of filter units is:
[0088] ;
[0089] Where N is the number of filter units, is the width of the glitch signal, is the first time parameter of the phase processing element, is the second time parameter of the phase processing element, is the third time parameter of the logic operation element, It is the fourth time parameter of the logic operation element.
[0090] In some embodiments, the first time parameter is the delay time for the rising edge of the phase processing element to change to the falling edge, and the second time parameter is the delay time for the falling edge of the phase processing element to change to the rising edge.
[0091] In some embodiments, the third time parameter is the delay time for the rising edge of the logic operation element to change to the falling edge, and the fourth time parameter is the delay time for the falling edge of the logic operation element to change to the rising edge.
[0092] According to some embodiments, the present application further provides a filtering device, which includes the filtering circuit of any one of the above embodiments.
[0093] In the filtering device of the above-described embodiment, the use of multiple groups of filtering units, including phase processing elements and logic operation elements, for filtering helps reduce the difficulty of filtering, improves filtering efficiency, and ensures that glitches can be quickly removed without affecting normal signals. Furthermore, since the phase processing elements and logic operation elements are relatively small in area, no additional area burden is imposed, which helps control costs. Furthermore, quantitative analysis of the number of filtering unit groups facilitates more accurate determination of the configuration of the filtering circuit, avoids unnecessary redundant filtering units in the filtering circuit, and thus reduces the difficulty of filtering out glitches.
[0094] According to some embodiments, the present application further provides an electronic device, which includes a housing and the filter circuit of any one of the above embodiments, at least partially located in a receiving space of the housing.
[0095] In the electronic device of the above embodiment, the use of multiple groups of filtering units including phase processing elements and logic operation elements for filtering helps reduce the difficulty of filtering, improves filtering efficiency, and ensures that glitches can be quickly removed without affecting normal signals. Furthermore, since the phase processing elements and logic operation elements are relatively small in area, no additional area burden is imposed, which helps control costs. Furthermore, quantitative analysis of the number of filtering unit groups helps more accurately determine the configuration of the filtering circuit, avoids unnecessary redundant filtering units in the filtering circuit, and thus reduces the difficulty of filtering out glitches.
[0096] In the above embodiments of the present disclosure, unless otherwise specified herein, there is no strict order restriction on the execution of the steps in the method. These steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
[0097] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.
[0098] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0099] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0100] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.
Claims
1. A filter circuit, characterized in that: The method comprises a plurality of filter units connected in series, wherein the plurality of filter units are used to output a target output signal according to an initial input signal containing a glitch signal; the filter units include: a phase processing element, wherein an input end of the phase processing element is used as an input end of the filtering unit; a logic operation element, wherein a first input terminal of the logic operation element is connected to the output terminal of the phase processing element, a second input terminal of the logic operation element is connected to a low level, and an output terminal of the logic operation element is used as an output terminal of the filtering unit; The first time parameter of the phase processing element is greater than the second time parameter of the phase processing element, and the first time parameter and the second time parameter are different performance parameters of the phase processing element under the same load; the third time parameter of the logic operation element is less than the fourth time parameter of the logic operation element, and the third time parameter and the fourth time parameter are different performance parameters of the logic operation element under the same load.
2. The filter circuit according to claim 1, wherein: The glitch signal is a high-level glitch signal; In the plurality of filter units connected in series, the input end of the first filter unit is used to receive the initial input signal including the high-level glitch signal, and the last filter unit is used to output the target output signal.
3. The filter circuit according to claim 1, wherein: The glitch signal is a low-level glitch signal; the filtering circuit further includes: an initial processing element, configured to generate a high-level glitch signal based on the low-level glitch signal; an input end of the initial processing element being configured to receive an initial input signal including the low-level glitch signal, and an output end of the initial processing element being connected to an input end of the first filtering unit, configured to output a signal to be filtered including the high-level glitch signal; In the plurality of filter units connected in series, the input end of the first filter unit is used to receive the signal to be filtered containing the high-level glitch signal, and the last filter unit is used to output the target output signal.
4. The filter circuit according to claim 2 or 3, characterized in that: The first time parameter is the delay time for the rising edge of the phase processing element to change to the falling edge, and the second time parameter is the delay time for the falling edge of the phase processing element to change to the rising edge; and / or The third time parameter is the delay time for the rising edge of the logic operation element to change to the falling edge, and the fourth time parameter is the delay time for the falling edge of the logic operation element to change to the rising edge.
5. The filter circuit according to claim 4, characterized in that: The phase processing element includes a clock inverter; and / or The logic operation element includes a NOR gate element.
6. The filter circuit according to claim 3, characterized in that: The initial processing element includes a clocked inverter.
7. A filtering method, characterized in that: Filtering is performed using the filter circuit according to any one of claims 1 to 6, the method comprising: Get the width of the glitch signal; Obtaining a first time parameter and a second time parameter of a phase processing element, and a third time parameter and a fourth time parameter of a logic operation element, wherein the first time parameter and the second time parameter are different performance parameters of the phase processing element under the same load, and the third time parameter and the fourth time parameter are different performance parameters of the logic operation element under the same load; The number of groups of the filtering units is determined according to the first time parameter and the second time parameter of the phase processing element, the third time parameter and the fourth time parameter of the logic operation element, and the width of the glitch signal.
8. The filtering method according to claim 7, characterized in that: The number of groups of the filtering units is: ； Where N is the number of filter units, is the width of the glitch signal, is the first time parameter of the phase processing element, is the second time parameter of the phase processing element, is the third time parameter of the logic operation element, is the fourth time parameter of the logic operation element.
9. A filtering device, characterized in that: The filter circuit comprises the filter circuit described in any one of claims 1 to 6.
10. An electronic device, characterized in that: include: case; The filter circuit described in any one of claims 1 to 6 is at least partially located in the accommodating space of the housing.