Circuit board structure

Abstract

The invention provides a circuit board structure. The circuit board structure comprises a substrate, a first layer-adding circuit layer and a second layer-adding circuit layer. The substrate has a first side and a second side opposite to each other. The first layer-adding circuit layer is arranged on the first side of the substrate, the first layer-adding circuit layer is provided with a first wiring area, and the first wiring area comprises a first metal and a first dielectric substance. The second layer-adding circuit layer is arranged on the second side of the substrate, the second layer-adding circuit layer is provided with a second wiring area, and the second wiring area comprises a second metal, a second dielectric substance and a third dielectric substance. The total volume of the second metal is less than the total volume of the first metal. The material of the third dielectric is different from the material of the second dielectric, and the ratio of the total volume of the third dielectric to the total volume of the second dielectric is between 0.45 and 0.55.

Description

Technical Field

[0001] The present invention relates to a circuit board structure, and in particular to a circuit board structure used in high-frequency and high-speed wiring. Background Art

[0002] In the circuit board manufacturing process, a substrate is typically used as a base. A build-up process is used to sequentially stack build-up circuit layers on both sides of the substrate, creating various circuit boards. In some specialized applications, the build-up circuit layers on both sides of the substrate may have an asymmetrical structure. For example, to meet high-frequency and high-speed electrical requirements, the build-up circuit layers on one side of the substrate may have fewer traces (for example, vertical connectors may be provided in specific areas, but horizontal connectors may be omitted) to ensure signal integrity and impedance control.

[0003] However, asymmetric structures can present some challenges. For example, when the wiring volume (i.e., the total volume of metal conductors) in the build-up wiring layers on either side of the substrate differs significantly, unexpected internal stresses (e.g., thermal stress at operating temperatures) may be generated during operation, leading to circuit board warping. Therefore, while existing circuit boards have gradually met their intended uses, they do not meet all requirements. Therefore, there is still a need to develop new circuit board structures. Summary of the Invention

[0004] According to some embodiments, a circuit board structure is provided. The circuit board structure includes a substrate, a first build-up wiring layer, and a second build-up wiring layer. The substrate has a first side and a second side opposite to each other. The first build-up wiring layer is disposed on the first side of the substrate, wherein the first build-up wiring layer has a first wiring area, and the first wiring area includes a first metal and a first dielectric. The second build-up wiring layer is disposed on the second side of the substrate, wherein the second build-up wiring layer has a second wiring area, and the second wiring area includes a second metal, a second dielectric, and a third dielectric. The total volume of the second metal is less than the total volume of the first metal. The material of the third dielectric is different from the material of the second dielectric, and the ratio of the total volume of the third dielectric to the total volume of the second dielectric is between 0.45 and 0.55.

[0005] In some embodiments, the first wiring area and the second wiring area correspond to each other, and a volume of the first wiring area is the same as a volume of the second wiring area.

[0006] In some embodiments, in a top view, the second wiring region has two opposite straight side edges and two opposite curved side edges.

[0007] In some embodiments, in a top view, the third dielectric surrounds the second metal and directly contacts the second metal.

[0008] In some embodiments, in a top view, the second dielectric is separated from the second metal by a third dielectric.

[0009] In some embodiments, the third dielectric has a rectangular shape in a top view.

[0010] In some embodiments, in a top view, the second dielectric surrounds the third dielectric.

[0011] In some embodiments, in a top view, the third dielectric is separated from the first metal by the second dielectric.

[0012] In some embodiments, the second dielectric has a rectangular shape in top view.

[0013] In some embodiments, the third dielectric penetrates the second build-up circuit layer along a vertical direction.

[0014] In some embodiments, the third dielectric has a Young's modulus greater than 1000 MPa at 250° C.

[0015] In some embodiments, the third dielectric has a Young's modulus between 1800 MPa and 2400 MPa at 250°C.

[0016] In some embodiments, the third dielectric has a coefficient of thermal expansion greater than 70 ppm / ° C. at 250° C.

[0017] In some embodiments, at 250° C., the third dielectric has a coefficient of thermal expansion between 75 ppm / ° C. and 95 ppm / ° C.

[0018] In some embodiments, the first dielectric is the same as the second dielectric.

[0019] In some embodiments, at 250° C., the Young's modulus of the first dielectric and the second dielectric is between 100 MPa and 500 MPa.

[0020] In some embodiments, at 250° C., the thermal expansion coefficients of the first dielectric and the second dielectric are between 40 ppm / ° C. and 60 ppm / ° C.

[0021] In some embodiments, the first metal is the same as the second metal.

[0022] In some embodiments, the second metal forms a plurality of vertical connectors, and the vertical connectors are electrically isolated from each other.

[0023] In some embodiments, the second build-up circuit layer further includes horizontal connectors, and the horizontal connectors are located outside the second wiring area, wherein the vertical connectors and the horizontal connectors in the second wiring area are electrically isolated from each other.

[0024] The device disclosed herein can be applied to various types of electronic devices. To make the components and advantages of the present disclosure more clearly understood, various embodiments are given below with accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] When with Figure 1 The present disclosure can be more fully understood from the following detailed description when read together. It is worth noting that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily enlarged or reduced for the sake of clarity.

[0026] Figures 1 to 4 The figures are cross-sectional schematic diagrams showing different steps in a method for forming a circuit board structure according to some embodiments of the present disclosure.

[0027] Figure 5 1 and 2 are schematic top views of circuit board structures according to some embodiments of the present disclosure.

[0028] Figure 6 FIG. 1 is a schematic diagram showing the warping degree of a circuit board structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] The following is a detailed description of the devices of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for a simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations on the present disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements in order to clearly describe the present disclosure. However, the use of these similar and / or corresponding element symbols is only for a simple and clear description of some embodiments of the present disclosure and does not represent any correlation between the different embodiments and / or structures discussed.

[0030] Furthermore, it should be understood that ordinal numbers such as "first," "second," and the like used in the specification and claims to modify an element are not intended to imply any prior ordinal number for the element (or elements), nor do they indicate the order of one element relative to another, or the order of manufacturing methods. The use of ordinal numbers is solely to distinguish one element from another with the same name. The claims and specification may not use the same terms; for example, the first element in the specification may be the second element in the claims.

[0031] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect," "interconnect," and "bond," unless otherwise specified, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with another structure disposed between the two structures. Furthermore, such terms related to joining and bonding may include situations where both structures are movable or both structures are fixed. Furthermore, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0032] As used herein, the terms "approximate," "about," and "substantially" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. A given quantity is an approximate quantity, meaning that even without the specific wording "about," "approximately," or "substantially," the meaning of "approximate," "approximately," or "substantially" is implied. The term "a range between a first value and a second value" means that the range includes the first value, the second value, and any values ​​therebetween. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If a first value is equal to a second value, it implies that the first value and the second value may have an error of approximately 10%, 5%, 3%, 2%, 1%, or 0.5% between them. If a first direction is perpendicular to a second direction, the angle between the first direction and the second direction may be between 80 and 100 degrees. If the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0033] It should be understood that the following embodiments may be implemented by replacing, reorganizing, or combining components from various different embodiments without departing from the spirit of the present disclosure. Components from various embodiments may be combined and used in any manner as long as they do not violate the spirit of the invention or conflict with it.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

[0035] In some embodiments of the circuit board structure, in order to meet the requirements of high frequency and high speed electrical properties, a special circuit layout is required to meet the signal integrity and impedance control. In this case, a cooper-free area can be set to meet the expected differential. It is worth mentioning that the "cooper-free area" used in this article refers to an area in which the number of conductive connectors is low (for example, only vertical connectors are set, but no horizontal connectors are set), resulting in the content of metal conductors (for example, copper or its alloys) in this area being lower than that in other areas of the circuit board structure. Therefore, in some embodiments, this configuration can also be referred to as a "cooper-free structure invertical direction".

[0036] However, while the provision of a hollow copper region addresses electrical requirements, it also introduces mechanical challenges. Because the total amount (e.g., by volume) of metal conductor (e.g., copper or its alloy) in the hollow copper region is lower than in other areas of the circuit board structure, this can lead to stress concentration within the circuit board structure. For example, when the circuit board structure is exposed to operating temperatures (e.g., above 200°C), the strength (e.g., Young's modulus) of the hollow copper region is lower than that of other areas of the circuit board structure, causing the circuit board structure to warp around the hollow copper region.

[0037] To address the aforementioned technical issues, the present disclosure provides a circuit board structure that replaces the dielectric material in the empty copper areas with a high-strength material to prevent warping of the circuit board structure under operating temperatures. Furthermore, the present disclosure adjusts the placement of the high-strength material to more effectively control manufacturing costs and product quality.

[0038] Reference Figures 1 to 4 , which are cross-sectional schematic diagrams showing different steps in the formation method of the circuit board structure according to some embodiments of the present disclosure. It should be understood that for the sake of clarity, some elements of the circuit board structure are omitted in the drawings, and only some elements are schematically illustrated. In some embodiments, additional components may be added to the package carrier described below. In other embodiments, some components of the circuit board structure described below may be replaced or omitted. It should be understood that in some embodiments, additional operation steps may be provided before, during and / or after the formation method of the circuit board structure. In some embodiments, some of the operation steps described may be replaced or omitted, and the order of some of the operation steps described is interchangeable.

[0039] like Figure 1As shown, in some embodiments, a substrate 10 is provided, and the substrate 10 has a first side 10A and a second side 10B opposite to each other. For example, the substrate 10 may be or include a copper foil substrate, but the disclosure is not limited thereto. In some embodiments, the substrate 10 may include a core layer 100, vertical connectors 101, and horizontal connectors 102, but the disclosure is not limited thereto.

[0040] In some embodiments, the core layer 100 can be used to support other components disposed thereon, such as the first build-up circuit layer 11 and the second build-up circuit layer 12 described below. In some embodiments, the core layer 100 can be or include a prepreg containing a polymer material, a fiber material, or other suitable materials, but the present disclosure is not limited thereto. For example, the polymer material can be or include epoxy resin, polyimide (PI), other suitable polymer materials, or combinations thereof, but the present disclosure is not limited thereto. For example, the fiber material can include carbon fiber, glass fiber, other suitable fiber materials, or combinations thereof, but the present disclosure is not limited thereto.

[0041] In some embodiments, the vertical connector 101 is disposed in the core layer 100 and penetrates the core layer 100, and the vertical connector 101 can be used to electrically connect various electronic components located on both sides of the core layer 100. For example, a through hole can be formed on the core layer 100 by a drilling process, and the through hole can be plated, etched, or other suitable processes or combinations thereof to form the vertical connector 101, but the present disclosure is not limited thereto. In some embodiments, the drilling process can be or include laser drilling, mechanical drilling, other suitable drilling processes, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the etching process can be or include dry etching (e.g., reactive-ion etching (RIE)), wet etching, other suitable etching methods, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the plating process can be or include electroplating, electroless plating, other suitable plating processes, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, after forming the through-holes, a seed layer may be formed in the through-holes by chemical vapor deposition (CVD), physical vapor deposition (PVD), other suitable deposition processes, or a combination thereof, and then the vertical connectors 101 may be formed by performing plating, etching, other suitable processes, or a combination thereof.

[0042] In some embodiments, the vertical connector 101 may include a first conductive layer 1010 and a first filling layer 1011. In some embodiments, the first conductive layer 1010 may be or may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), an alloy thereof, or a compound thereof, but the present disclosure is not limited thereto. For example, the alloy or compound of copper may be or may include brass, phosphor bronze, beryllium copper, or oxygen-free copper, but the present disclosure is not limited thereto. In some embodiments, the first filling layer 1011 may be or may include epoxy resin, polyimide (PI), Ajinomoto buildup film (ABF), other suitable polymer materials, or a combination thereof, but the present disclosure is not limited thereto.

[0043] In some embodiments, horizontal connectors 102 are disposed on both sides of the core layer 100 and can be used to electrically connect various electronic components located on the same side of the core layer 100. For example, a conductive material can be disposed on the core layer 100 and patterned using photolithography and etching processes to form the horizontal connectors 102. In some embodiments, the photolithography process can include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the vertical connectors 101 and the horizontal connectors 102 can be formed simultaneously in the same process, or in different process steps.

[0044] In some embodiments, the horizontal connector 102 may be or include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the horizontal connector 102 may be similar or the same as that of the vertical connector 101, but the present disclosure is not limited thereto.

[0045] like Figure 1As shown, following the above process, in some embodiments, a first build-up circuit layer 11 is disposed on the first side 10A of the substrate 10. In some embodiments, the first build-up circuit layer 11 may include a first dielectric layer 110, a first vertical connector 111, and a first horizontal connector 112.

[0046] In some embodiments, the first dielectric layer 110 can be used to support other elements disposed thereon or therein, such as a first vertical connector 111 and a first horizontal connector 112. For example, the first dielectric layer 110 (and the conductive material thereon) can be laminated on the substrate 10 by a lamination process, other suitable processes, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first dielectric layer 110 may include a plurality of sub-layers, and each sub-layer may be formed using similar or identical processes or materials. In some embodiments, the first dielectric layer 110 may be or may include epoxy resin, polyimide (PI), build-up film material (ABF), other suitable polymer materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the first dielectric layer 110 may be similar or the same as that of the core layer 100, but the present disclosure is not limited thereto.

[0047] In some embodiments, the first vertical connector 111 is disposed in the first dielectric layer 110, and the first vertical connector 111 can be used to electrically connect various electronic components located on both sides of the first dielectric layer 110 or various electronic components in the first dielectric layer 110. For example, the first vertical connector 111 can be formed by forming a through hole in the first dielectric layer 110 through a drilling process, and performing plating, etching, other suitable processes, or a combination thereof on the through hole, but the present disclosure is not limited thereto. In some embodiments, the first vertical connector 111 can include multiple sub-vertical connectors, and each sub-vertical connector can be formed using similar or identical processes or materials. In embodiments where the first dielectric layer 110 has multiple sub-layers, the multiple sub-vertical connectors can be used to connect components located on different sub-layers.

[0048] In some embodiments, the first vertical connector 111 may be or include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the first vertical connector 111 may be similar to or the same as that of the vertical connector 101, but the present disclosure is not limited thereto.

[0049] In some embodiments, the first horizontal connector 112 is disposed in the first dielectric layer 110 or on the surface of the first dielectric layer 110 away from the core layer 100, and the first horizontal connector 112 can be used to electrically connect various electronic components located on the same side (or at the same level) of the first dielectric layer 110. For example, a conductive material can be disposed on the first dielectric layer 110 and patterned by a photolithography process and an etching process to form the first horizontal connector 112. In some embodiments, the first vertical connector 111 and the first horizontal connector 112 can be formed simultaneously in the same process, or in different processes. In some embodiments, the first horizontal connector 112 may include a plurality of sub-horizontal connectors, and each sub-horizontal connector may be formed using similar or identical processes or materials. The above-mentioned sub-horizontal connectors can be used to connect components on a single sub-layer.

[0050] In some embodiments, the first horizontal connector 112 may be or include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the first horizontal connector 112 may be similar to or the same as that of the horizontal connector 102, but the present disclosure is not limited thereto.

[0051] like Figure 1 As shown, a first wiring area WA1 may be defined in the first build-up wiring layer 11. In some embodiments, the first wiring area WA1 may include a first metal M1 and a first dielectric D1, wherein the first dielectric D1 surrounds the first metal M1 and directly contacts the first metal M1.

[0052] Herein, "first metal M1" may refer to vertical and horizontal connectors in the first wiring area WA1, such as the first vertical connector 111 and the first horizontal connector 112, but the present disclosure is not limited thereto. For example, in some embodiments, the vertical or horizontal connectors in the first wiring area WA1 may include a metal portion and a dielectric portion. In this case, "first metal M1" may refer to the metal portion of the vertical or horizontal connector in the first wiring area WA1. In some embodiments, the first metal M1 may constitute a plurality of vertical and horizontal connectors, such as the first vertical connector 111 and the first horizontal connector 112 mentioned above.

[0053] Herein, "first dielectric D1" may refer to a dielectric layer in the first wiring area WA1, such as the first dielectric layer 110, but the present disclosure is not limited thereto. Specifically, in order to simplify process complexity and reduce production costs, one dielectric or multiple dielectrics with similar properties may be used to form the first dielectric layer 110, wherein this or these dielectrics may be referred to as "first dielectric D1". In some embodiments, the first dielectric D1 may constitute multiple sublayers in the first dielectric layer 110, and these sublayers may be in direct contact or indirect contact. In some embodiments, the material of the first dielectric D1 is the same as the material of the core layer 100, but the present disclosure is not limited thereto. In some embodiments, the strength of the first dielectric D1 is less than the strength of the first metal M1, and the definition of strength will be further described below.

[0054] like Figure 1 As shown, following the above process, in some embodiments, a second build-up circuit layer 12 is disposed on the second side 10B of the substrate 10. In some embodiments, the second build-up circuit layer 12 may include a second dielectric layer 120, a second vertical connector 121, and a second horizontal connector 122.

[0055] In some embodiments, the second dielectric layer 120 can be used to support other elements disposed thereon or therein, such as a second vertical connector 121 and a second horizontal connector 122. For example, the second dielectric layer 120 (and the conductive material thereon) can be laminated on the substrate 10 by a build-up process, other suitable processes, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second dielectric layer 120 may include multiple sub-layers, and each sub-layer may be formed using similar or identical processes or materials. In some embodiments, the second dielectric layer 120 may be or may include epoxy resin, polyimide (PI), build-up film material (ABF), other suitable polymer materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the second dielectric layer 120 may be similar to or the same as that of the first dielectric layer 110, but the present disclosure is not limited thereto.

[0056] In some embodiments, the second vertical connector 121 is disposed in the second dielectric layer 120, and the second vertical connector 121 can be used to electrically connect various electronic components located on both sides of the second dielectric layer 120 or various electronic components in the second dielectric layer 120. For example, the second vertical connector 121 can be formed by forming a through hole in the second dielectric layer 120 through a drilling process, and then performing plating, etching, other suitable processes, or a combination thereof on the through hole, but the present disclosure is not limited to this. In some embodiments, the second vertical connector 121 can include multiple sub-vertical connectors, and each sub-vertical connector can be formed using similar or identical processes or materials. In embodiments where the second dielectric layer 120 has multiple sub-layers, the multiple sub-vertical connectors can be used to connect components located on different sub-layers.

[0057] In some embodiments, the second vertical connector 121 may be or include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the second vertical connector 121 may be similar or the same as that of the first vertical connector 111, but the present disclosure is not limited thereto.

[0058] In some embodiments, the second horizontal connector 122 is disposed in the second dielectric layer 120 or on the surface of the second dielectric layer 120 away from the core layer 100, and the second horizontal connector 122 can be used to electrically connect various electronic components located on the same side (or at the same level) of the second dielectric layer 120. For example, a conductive material can be disposed on the second dielectric layer 120 and patterned by a photolithography process and an etching process to form the second horizontal connector 122. In some embodiments, the second vertical connector 121 and the second horizontal connector 122 can be formed simultaneously in the same process, or in different process steps. In some embodiments, the second horizontal connector 122 can include a plurality of sub-horizontal connectors, and each sub-horizontal connector can be formed using similar or identical processes or materials. The above-mentioned sub-horizontal connectors can be used to connect components on a single sub-layer.

[0059] In some embodiments, the second horizontal connector 122 may be or include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the second horizontal connector 122 may be similar or the same as that of the first horizontal connector 112, but the present disclosure is not limited thereto.

[0060] like Figure 1 As shown, a second wiring area WA2 can be defined in the second build-up wiring layer 12, where the second wiring area WA2 corresponds to the first wiring area WA1 and has the same volume as the first wiring area WA1. In the present disclosure, the second wiring area WA2 has a special circuit layout that takes signal integrity and impedance control into consideration. Specifically, the second wiring area WA2 includes second vertical connectors 121 but excludes second horizontal connectors 122. For example, the edges of the second horizontal connectors 122 or their sub-horizontal connectors can serve as boundaries to define the scope of the second wiring area WA2. In other words, the horizontal connectors (e.g., second horizontal connectors 122) of the second build-up wiring layer 12 are located outside the second wiring area WA2, and the vertical connectors (e.g., second vertical connectors 121) in the second wiring area WA2 are electrically isolated from the horizontal connectors (e.g., second horizontal connectors 122) outside the second wiring area WA2.

[0061] In some embodiments, the second wiring area WA2 may include a second metal M2 and a second dielectric D2 , wherein the second dielectric D2 surrounds the second metal M2 and directly contacts the second metal M2 .

[0062] Herein, "second metal M2" may refer to a vertical connector in the second wiring area WA2, such as the second vertical connector 121, but the present disclosure is not limited thereto. For example, in some embodiments, the vertical connector in the second wiring area WA2 may include a metal portion and a dielectric portion. In this case, "second metal M2" may refer to the metal portion of the vertical connector in the second wiring area WA2. In some embodiments, the second metal M2 may constitute a plurality of vertical connectors, and these vertical connectors are electrically isolated from each other. For example, the second metal M2 may constitute a plurality of vertical connectors, such as the second vertical connector 121. Figure 1 Two second vertical connectors 121 are shown, and the two second vertical connectors 121 are electrically isolated from each other. In some embodiments, the second metal M2 is the same as the first metal M1, but the disclosure is not limited thereto.

[0063] In this document, the “second dielectric D2” may refer to a dielectric layer in the second wiring area WA2, such as the entire second dielectric layer 120 (eg, Figure 1 ) or a portion of the second dielectric layer 120 (as shown Figure 2 ). Specifically, to enhance the strength of the second wiring area WA2, in subsequent processes, the dielectric layer in the second wiring area WA2 will have two different dielectrics (e.g., with different mechanical properties), one of which is a "second dielectric D2" and the other is a "third dielectric D3." In some embodiments, the second dielectric D2 may constitute multiple sublayers in the second dielectric layer 120, and these sublayers may be in direct or indirect contact. In some embodiments, the second dielectric D2 is the same as the first dielectric D1, but the present disclosure is not limited thereto. In some embodiments, the strength of the second dielectric D2 is less than the strength of the first metal M1 and / or the second metal M2, and the definition of strength will be further described below.

[0064] As described above, to meet design requirements, the first and second wiring areas WA1 and WA2 can have asymmetric structures. Specifically, the second wiring area WA2 has vertical connectors but no horizontal connectors, while the first wiring area WA1 has both vertical and horizontal connectors. In this case, the total volume of the second metal M2 in the second wiring area WA2 is smaller than the total volume of the first metal M1 in the first wiring area WA1. As a result, the first wiring area WA1 can be stronger than the second wiring area WA2.

[0065] To this end, a portion of the second dielectric D2 in the second wiring area WA2 can be removed and replaced with a third dielectric D3, wherein the material of the third dielectric D3 is different from the material of the second dielectric D2. For example, after the step of setting the second dielectric layer 120 on the substrate 10, and before the step of forming the second vertical connection 121 and the second horizontal connection 122, a portion of the second dielectric D2 in the second wiring area WA2 of the second dielectric layer 120 can be removed to form a through hole, and the third dielectric D3 is filled in the through hole. Then, after the second wiring area WA2 of the second dielectric layer 120 includes the second dielectric D2 and the third dielectric D3, the second vertical connection 121 and the second horizontal connection 122 are formed in the second dielectric layer 120. In this way, the second dielectric D2 can be replaced with the third dielectric D3, thereby obtaining the following. Figure 2 However, the present disclosure is not limited to the above-mentioned methods or steps.

[0066] In some embodiments, the third dielectric D3 extends through the second dielectric layer 120 in the second build-up wiring layer 12 along a vertical direction (i.e., the normal direction of the substrate 10). In other words, the third dielectric D3 may be cylindrical, such as a cylinder, an elliptical cylinder, a rectangular cylinder, a triangular cylinder, or a polygonal cylinder. In some embodiments, in a cross-sectional view, the third dielectric D3 may be trapezoidal, funnel-shaped, pear-shaped, or other suitable shapes. In some embodiments, the bottom surface of the third dielectric D3 is coplanar with the bottom surface of the second dielectric D2, but the present disclosure is not limited thereto. In some embodiments, the top surface of the third dielectric D3 is coplanar with the top surface of the second dielectric D2, but the present disclosure is not limited thereto. By replacing a portion of the second dielectric D2 in the second wiring area WA2 with the third dielectric D3, some issues caused by the asymmetry between the first wiring area WA1 and the second wiring area WA2 can be alleviated.

[0067] More specifically, the third dielectric D3 has a higher strength (for example, rigidity) than the second dielectric D2. It is worth mentioning that the term "strength" used in the present disclosure refers to physical properties under specific conditions, such as physical properties at about 250°C. Since the operating temperature of the circuit board structure may be as high as 200°C (for example, 250°C), in order to avoid possible warping under such conditions, the strength of the third dielectric D3 at 250°C needs to be greater than the strength of the second dielectric D2 at 250°C. In some embodiments, since the rigidity of the third dielectric D3 is greater than the rigidity of the second dielectric D2, the third dielectric D3 can also be called a high-rigidity material. In some embodiments, the strength of the third dielectric D3 is less than the strength of the first metal M1 and / or the second metal M2.

[0068] In some embodiments, the Young's modulus can be used to represent rigidity. Specifically, when a material is subjected to a normal stress, a normal strain will be generated. When the strain does not exceed the elastic upper limit of the material, the ratio of the normal stress to the normal strain is defined as the Young's modulus of the material. Therefore, the higher the Young's modulus, the less likely the material is to deform. In some embodiments, at 250°C, the Young's modulus of the third dielectric D3 is greater than 1000 MPa, but the present disclosure is not limited thereto. In some embodiments, at 250°C, the Young's modulus of the third dielectric D3 is between 1800 MPa and 2400 MPa, but the present disclosure is not limited thereto. For example, at 250°C, the Young's modulus of the third dielectric D3 may be 1800 MPa, 1900 MPa, 2000 MPa, 2100 MPa, 2200 MPa, 2300 MPa, 2400 MPa, or any value or any range of values ​​between the above values, but the present disclosure is not limited thereto. In some embodiments, the Young's modulus of the first dielectric D1 and the second dielectric D2 at 250° C. is less than 1000 MPa, but the disclosure is not limited thereto. In some embodiments, the Young's modulus of the first dielectric D1 and the second dielectric D2 at 250° C. is between 100 MPa and 500 MPa, but the disclosure is not limited thereto. For example, the Young's modulus of the first dielectric D1 and the second dielectric D2 at 250° C. may be 100 MPa, 150 MPa, 200 MPa, 250 MPa, 300 MPa, 400 MPa, 500 MPa, or any value or range of values ​​therebetween, but the disclosure is not limited thereto.

[0069] In other embodiments, the coefficient of thermal expansion (CTE) can also be used to represent rigidity. Before filling the third dielectric D3, the strength of the second wiring area WA2 may be lower than the strength of the first wiring area WA1, which causes the two sides of the circuit board structure to apply compressive stress (compressive stress) toward the second wiring area WA2 and warp. Therefore, a third dielectric D3 with a large thermal expansion coefficient can be used to replace the second dielectric D2, so that the second wiring area WA2 can expand outward at the operating temperature to resist the compressive stress. In some embodiments, at 250°C, the thermal expansion coefficient of the third dielectric D3 is greater than 70ppm / °C, but the present disclosure is not limited to this. In some embodiments, at 250°C, the thermal expansion coefficient of the third dielectric D3 is between 75ppm / °C and 95ppm / °C, but the present disclosure is not limited to this. For example, at 250°C, the coefficient of thermal expansion of the third dielectric D3 may be 75 ppm / °C, 77.5 ppm / °C, 80 ppm / °C, 82.5 ppm / °C, 85 ppm / °C, 90 ppm / °C, 95 ppm / °C, or any value or range of values ​​therebetween, but the disclosure is not limited thereto. In some embodiments, at 250°C, the coefficient of thermal expansion of the first dielectric D1 and the second dielectric D2 is less than 70 ppm / °C, but the disclosure is not limited thereto. In some embodiments, at 250°C, the coefficient of thermal expansion of the first dielectric D1 and the second dielectric D2 is between 40 ppm / °C and 60 ppm / °C, but the disclosure is not limited thereto. For example, at 250° C., the thermal expansion coefficients of the first dielectric D1 and the second dielectric D2 may be 40 ppm / ° C., 42.5 ppm / ° C., 45 ppm / ° C., 47.5 ppm / ° C., 50 ppm / ° C., 55 ppm / ° C., 60 ppm / ° C., or any value or range of values ​​therebetween, but the present disclosure is not limited thereto.

[0070] It is worth noting that although Young's modulus and thermal expansion coefficient are used to define strength (or stiffness) above, the present disclosure is not limited thereto. In other embodiments, yield strength, tensile strength, Poisson's ratio, other suitable physical properties, or combinations thereof may be used to represent the strength of the first dielectric D1, the second dielectric D2, and the third dielectric D3.

[0071] Optionally, in some embodiments, build-up circuit layers may be further provided on both sides of the core layer 100, and similar steps as described above may be performed to reduce the warping problem of the resulting circuit board structure. Figure 3As shown, a first build-up wiring layer 13 may be provided on a first build-up wiring layer 11, and a second build-up wiring layer 14 may be provided on a second build-up wiring layer 12. After providing the additional build-up wiring layer, a first wiring area WA1 may be redefined in the first build-up wiring 11 and the first build-up wiring 13, wherein the first wiring area WA1 has vertical connectors and horizontal connectors. Furthermore, after providing the additional build-up wiring layer, a second wiring area WA2 may be redefined in the second build-up wiring 12 and the second build-up wiring 14, wherein the second wiring area WA2 has vertical connectors but no horizontal connectors.

[0072] In some embodiments, the above steps may be repeated until the number of layers and structure of the circuit board structure meet the design requirements. Figure 4 For example, after three build-up circuit layers are respectively provided on both sides of the substrate 10, the following is formed: Figure 4 The structure shown (protective layer 23 will be further described below), but the present disclosure is not limited to the number of layers, thickness, ratio or specific structure of the build-up circuit layer.

[0073] For the sake of simplicity, the build-up wiring layers on the first side 10A are collectively referred to as first build-up wiring layers 21 , wherein the first build-up wiring layer 21 includes a plurality of build-up wiring layers (eg, Figures 1 to 3 The first build-up wiring layer 21 may include a first dielectric layer 210, a first vertical connector 211, and a first horizontal connector 212. Furthermore, the first build-up wiring layer 21 has a first wiring area WA1, and the first wiring area WA1 includes a first metal M1 and a first dielectric D1.

[0074] Likewise, for the sake of simplicity, the build-up wiring layers on the second side 10B are collectively referred to as second build-up wiring layers 22 hereinafter, wherein the second build-up wiring layers 22 include a plurality of build-up wiring layers (eg, Figures 1 to 3 The second build-up wiring layer 22 may include a second dielectric layer 220, a second vertical connector 221, and a second horizontal connector 222. Furthermore, the second build-up wiring layer 22 has a second wiring area WA2, and the second wiring area WA2 includes a second metal M2, a second dielectric D2, and a third dielectric D3.

[0075] In some embodiments, the ratio of the total volume of the third dielectric D3 in the second wiring area WA2 to the total volume of the second dielectric D2 is between 0.45 and 0.55. In other words, approximately half (e.g., approximately 50%) of the second dielectric D2 in the second wiring area WA2 can be removed during the various removal processes described above, and the removed portion can be replaced with the third dielectric D3. It is worth noting that, compared to completely replacing the second dielectric D2 in the second wiring area WA2 with the third dielectric D3, replacing a portion (e.g., 50%) of the second dielectric D2 in the second wiring area WA2 with the third dielectric D3 can effectively improve structural strength while reducing production costs.

[0076] like Figure 4 As shown, following the above process, a protective layer 23 is deposited on the first build-up circuit layer 21 and the second build-up circuit layer 22 to form the circuit board structure 1. In some embodiments, protective layer 23 can be deposited by dip coating, roller coating, curtain coating, spraying, screen printing, or other suitable processes or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the material of protective layer 23 can be or include resin or other suitable materials, but the present disclosure is not limited thereto. For example, protective layer 23 can be solder mask ink.

[0077] Refer to Figures 5 and 6 , which are respectively schematic diagrams showing different top views of the circuit board structure and schematic diagrams showing the warping degree of the circuit board structure according to some embodiments of the present disclosure. It is worth mentioning that for the sake of simplicity, Figure 5 The state (A) to state (D) in FIG. 1 only show the second dielectric D2, the third dielectric D3 and the second metal M2 in the second wiring area WA2, and omit other elements. In addition, in some embodiments, it can be said that Figure 5 It is a bottom view of the circuit board structure, that is, Figure 4 The circuit board structure is observed from the bottom upward Figure 5 Aspect (A) to aspect (D).

[0078] like Figure 5As shown in aspects (A) to (D) of the present disclosure, in some embodiments, in a top view, the second wiring area WA2 has two opposing straight side edges SS and two opposing curved side edges AS, and two second vertical connectors 121 are disposed therein, but the present disclosure is not limited thereto. In other embodiments, the second wiring area WA2 may also have other shapes, such as a circle, an ellipse, a rectangle, a triangle, a polygon, a trapezoid, or other suitable shapes. Alternatively, in other embodiments, the second wiring area WA2 may also have one second vertical connector 221 or more than two second vertical connectors 121, such as four, five, or more second vertical connectors 221.

[0079] In aspect (A), the third dielectric D3 is separated from the second metal M2 by the second dielectric D2. In other words, the third dielectric D3 does not contact the second metal M2. In some embodiments, the second dielectric D2 has a rectangular shape in a top view, but the present disclosure is not limited thereto. In other embodiments, the second dielectric D2 may have other shapes in a top view, such as circular, elliptical, rectangular, triangular, polygonal, trapezoidal, or other suitable shapes.

[0080] In aspect (B), the third dielectric D3 is separated from the second metal M2 by the second dielectric D2, and the third dielectric D3 surrounds the second dielectric D2. In some embodiments, in a top view, the second dielectric D2 has a shape similar to that of the second wiring area WA2. That is, the second dielectric D2 has two opposing straight sides and two opposing curved sides, but the present disclosure is not limited thereto.

[0081] In aspect (C), the second dielectric D2 is separated from the second metal M2 by the third dielectric D3. In other words, the second dielectric D2 does not contact the second metal M2. In some embodiments, the third dielectric D3 has a rectangular shape in a top view, but the present disclosure is not limited thereto. In other embodiments, the third dielectric D3 may have other shapes in a top view, such as a circle, an ellipse, a rectangle, a triangle, a polygon, a trapezoid, or other suitable shapes.

[0082] In aspect (D), the second dielectric D2 is separated from the second metal M2 by a third dielectric D3, and the second dielectric D2 surrounds the third dielectric D3. In some embodiments, in a top view, the third dielectric D3 has a shape similar to that of the second wiring area WA2. That is, the third dielectric D3 has two opposing straight sides and two opposing curved sides, but the present disclosure is not limited thereto.

[0083] like Figure 6As shown, in some embodiments, a detection device can be used to detect the warping and deformation of the circuit board structure in the above application examples based on the principle of optical interference. In the present disclosure, the circuit board structure can be heated from room temperature (e.g., 25°C) to an operating temperature (e.g., 260°C), and then the circuit board structure can be cooled back to room temperature (e.g., 25°C) to measure the warping degree WPG. In the figure, the warping degree WPG is the offset of the circuit board structure after bending, which can be expressed in microns (μm). Compared with the second dielectric layer 120 in the second wiring area WA2 being entirely composed of the second dielectric D2 (Comparative Example 1), replacing part of the second dielectric D2 with the third dielectric D3 can effectively reduce the warping degree. For example, state sample (A) to state sample (D) can reduce the warping degree from 3.5μm to 3μm, 3μm, 2.25μm and 2μm, respectively. On the other hand, compared to the case where the second dielectric layer 120 in the second wiring area WA2 is entirely composed of the third dielectric D3 (Comparative Example 2), partially replacing the second dielectric D2 with the third dielectric D3 can effectively reduce production costs without significantly increasing the warpage WPG. For example, the warpage of Aspect (C) (approximately 2 μm) is close to that of Comparative Example 2 (approximately 1.5 μm), despite using only about half the third dielectric D3.

[0084] In summary, the present disclosure provides a circuit board structure that prevents warping by disposing different dielectric materials in specific areas. Furthermore, the present disclosure further reduces production costs by ensuring that the different dielectric materials have specific shapes and ratios.

[0085] The above summarizes several embodiments so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art will appreciate that other processes and structures can be designed or modified based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present disclosure.

[0086]

Explanation of symbols

[0087] 1: Circuit board structure

[0088] 10:Substrate

[0089] 10A: First side

[0090] 10B: Second side

[0091] 100: Core layer

[0092] 101: Vertical connector

[0093] 1010: first conductive layer

[0094] 1011: first filling layer

[0095] 102: horizontal connector

[0096] 11: First build-up circuit layer

[0097] 110: first dielectric layer

[0098] 111: First vertical connecting member

[0099] 112: first horizontal connecting member

[0100] 12: Second build-up circuit layer

[0101] 120: second dielectric layer

[0102] 121: Second vertical connecting member

[0103] 122: Second horizontal connecting piece

[0104] 13: First build-up circuit layer

[0105] 14: Second build-up circuit layer

[0106] 220: second dielectric layer

[0107] 21: First build-up circuit layer

[0108] 22: Second build-up circuit layer

[0109] 23: Protective layer

[0110] A: Appearance

[0111] AS: Arc side

[0112] B: Attitude

[0113] C: Attitude

[0114] D: Attitude

[0115] D1: First dielectric

[0116] D2: Second dielectric

[0117] D3: The third dielectric

[0118] M1: First Metal

[0119] M2: Second Metal

[0120] SS: Straight side

[0121] WA1: First wiring area

[0122] WA2: Second wiring area

[0123] WPG: Warpage degree.

Claims

1. A circuit board structure, characterized in that: include: a substrate having a first side and a second side opposite to each other; A first build-up circuit layer is disposed on the first side of the substrate, wherein the first build-up circuit layer has a first wiring area, and the first wiring area includes: First Metal; a first dielectric; and A second build-up circuit layer is disposed on the second side of the substrate, wherein the second build-up circuit layer has a second wiring area, and the second wiring area includes: a second metal, wherein the total volume of the second metal is less than the total volume of the first metal; a second dielectric; and A third dielectric, wherein a material of the third dielectric is different from a material of the second dielectric, and a ratio of a total volume of the third dielectric to a total volume of the second dielectric is between 0.45 and 0.

55. 2 . The circuit board structure according to claim 1 , wherein in a top view, the second wiring area has two opposite straight side edges and two opposite curved side edges. 3 . The circuit board structure according to claim 2 , wherein in the top view, the third dielectric surrounds the second metal and directly contacts the second metal. 4 . The circuit board structure according to claim 3 , wherein in the top view, the second dielectric is separated from the first metal by the third dielectric. 5 . The circuit board structure according to claim 4 , wherein in the top view, the third dielectric has a rectangular shape. The circuit board structure according to claim 4 , wherein in the top view, the second dielectric surrounds the third dielectric. 7 . The circuit board structure according to claim 1 , wherein at 250° C., a Young's modulus of the third dielectric is greater than 1000 MPa. 8 . The circuit board structure according to claim 1 , wherein at 250° C., the thermal expansion coefficient of the third dielectric is greater than 70 ppm / ° C. 9 . The circuit board structure according to claim 1 , wherein the second metal forms a plurality of vertical connectors, and the plurality of vertical connectors are electrically isolated from each other.

10. The circuit board structure according to claim 9, wherein the second build-up circuit layer further comprises a horizontal connector, and the horizontal connector is located outside the second wiring area, wherein the plurality of vertical connectors in the second wiring area are electrically isolated from the horizontal connector.

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